US 10771069

US Patent 10771069, titled "Field programmable gate array with internal phase-locked loop," was filed on October 31, 2019, and issued on September 8, 2020. The inventor is Nima Badizadegan, and the current assignee is HFT Solutions LLC.

Abstract:
A field programmable gate array system comprises a field programmable gate array (FPGA) with a first interface. This interface includes a first reference clock pin to receive a first clock signal, a second reference clock pin to receive a second clock signal, first data pins for a first serial data stream, and second data pins for a second serial data stream. A deserializer is connected to the first reference clock pin and the first data pins, converting the first serial data stream into parallel data streams. A phase detector is connected to the deserializer to receive the first receiver side clock signal. A serializer is connected to computational circuitry to receive parallel data streams.

Independent Claims Overview:

• Claim 1 (System Claim): This claim describes an FPGA system including an FPGA with specific interfaces (clock and data pins). It features a deserializer to convert an incoming serial data stream (with a first clock signal) into parallel data, and a serializer to convert parallel data into an outgoing serial data stream. Key to this claim is a phase detector that receives a receiver-side clock signal, and a phase controller that generates adjustment information based on a phase difference between a receiver-side clock and a transmitter-side clock. This adjustment information is used to modify the transmitter-side clock to achieve phase matching.
• Claim 25 (System Claim): Similar to Claim 1, this claim also describes an FPGA system with interfaces, a deserializer, and a serializer. The distinction is that it explicitly includes a transceiver phase-locked loop (PLL) connected to the second reference clock pin, configured to generate a wire rate clock signal for the serializer. This transceiver PLL is adjustable based on adjustment information from the internal phase controller, which in turn uses a phase difference detected between the receiver and transmitter clocks to align them.
• Claim 38 (Method Claim): This claim outlines a method for processing market data (first serial data stream) on an FPGA system to generate order entry data (second serial data stream). The method involves receiving clock and data signals, deserializing the market data, generating a receiver-side clock, performing operations on the parallel data, generating a transmitter-side clock, and serializing the order entry data. Crucially, it includes steps for determining a phase difference between the receiver-side and transmitter-side clocks and adjusting the transmitter-side clock based on this difference to achieve phase alignment.
• Claim 59 (Method Claim): This method claim focuses on generating a transmitter-side clock signal for an FPGA. It involves receiving a second clock signal via a reference pin and processing it using a transceiver phase-locked loop (PLL) that is adjustable. The PLL provides a wire rate clock signal to a serializer. The method integrates a phase detector to compare the receiver-side clock with an interim transmitter-side clock, and a phase controller that generates adjustment information for the adjustable transceiver PLL to align the clocks.
• Claim 75 (System Claim): This claim describes an FPGA system where the second reference clock pin (for the transmitter side) is configured to receive the same first clock signal as the receiver side. It includes a deserializer, computational circuitry, a serializer, a phase detector, and an adjustable phase-locked loop (PLL) within the FPGA to generate the transmitter-side clock. The phase detector compares the receiver-side and transmitter-side clocks, and an internal phase controller uses the phase difference to adjust the PLL for phase matching.
• Claim 96 (Method Claim): This method claim details processing market data on an FPGA system when the second reference clock pin receives the first clock signal. It involves receiving and deserializing the market data, generating a receiver-side clock, performing computations, generating a wire rate clock for serialization using an adjustable phase-locked loop (PLL) within the FPGA, and serializing the output. It emphasizes detecting the phase difference between the receiver-side clock and an interim transmitter-side clock, and then using this information to adjust the PLL to align the phases.

CAFC 2026 Dockets:
A search of the CAFC 2026 dockets did not reveal any cases specifically mentioning US patent 10771069.

As of April 26, 2026, there is no known patent litigation specifically involving US patent 10771069. A search of publicly available litigation databases (including those that cover patent litigation) did not yield any results for this patent number. The search results provided did not relate to patent litigation for US10771069.

Proceedings overview

There is one active AIA trial proceeding on US patent 10771069, currently in the "Pending" status. This means the patent's claims are still being challenged, and the full defensive posture for a defendant will depend on the outcome of this ongoing IPR.

IPR2026-00386 — Optiver US LLC et al. v. HFT Solutions LLC

• Type: Inter Partes Review
• Filed: 2026-06-04
• Status: Pending. The petition has been filed, and the PTAB is currently reviewing it to determine whether to institute a trial.
• Judge panel: Not yet public.
• Petition grounds: Not yet public. The petition was filed too recently for this information to be publicly available.
• Institution decision: Not yet issued. The deadline for the institution decision is typically within six months of the preliminary response or the last due date for such a response.
• Final Written Decision (if issued): Not applicable.
• Settlement / termination: Not applicable.
• Appeal: Not applicable.
• Defensive value: This proceeding indicates that Optiver US LLC et al. are challenging the patent. For a defendant, this means there is an active challenge to the patent's validity, and the outcome of this IPR could significantly impact the strength of any assertion based on US10771069. If the IPR is instituted and claims are invalidated, it could weaken the patent owner's position. Conversely, if institution is denied or claims are upheld, it could strengthen the patent.

Strategic summary

Currently, all claims of US10771069 are legally considered untested in the context of an AIA trial, as the single IPR filed (IPR2026-00386) is still in the pending stage, awaiting an institution decision. No claims have been canceled or sustained through a Final Written Decision. This means that the patent's scope remains as granted by the USPTO.

The estoppel landscape is presently undeveloped. Since no institution decision or FWD has been issued, there are no prior art grounds that are yet barred from being raised by the petitioner (or its privies) under § 315(e)(2) for this specific IPR. For a defendant facing assertion of this patent, all prior art grounds remain potentially available for use in a future IPR or other validity challenges, assuming they are not in privity with Optiver US LLC et al.

The filing of this IPR by Optiver US LLC et al. suggests that they perceive vulnerabilities in the patent's claims. There is no public information at this time to suggest a pattern of multiple IPR filings by the same petitioner, aggressive appeals by the patent owner, or involvement of a defensive aggregator.

Recommended next steps

For a defendant facing assertion of US10771069, monitoring IPR2026-00386 is crucial. The key upcoming milestone is the institution decision. The PTAB has a statutory deadline of one year from institution to issue a Final Written Decision.

To track the progress of this IPR and obtain public documents, you can visit the USPTO PTAB E2E portal for IPR2026-00386. At the current "Pending" status, the relevant document to watch for would be the institution decision, which will detail which claims, if any, the PTAB has decided to review based on the petitioner's grounds.

• USPTO PTAB E2E for IPR2026-00386: https://ptab.uspto.gov/#/proceeding/IPR2026-00386 (Note: This link is illustrative; the actual URL may require navigating the PTAB search interface.)

Inventors

• Nima Badizadegan (Employer: Individual at time of filing)

Unusual patterns: The inventor, Nima Badizadegan, was listed as an "Individual" at the time of filing, rather than being associated with a specific company as an original assignee. This can sometimes precede a direct assignment to a non-practicing entity or a portfolio sale, but it is not inherently an NPE signal without further transfers.

Original assignee

The original assignee on the issued patent is "Individual".

Since the original assignee is an "Individual," it is not possible to determine if "Individual" shipped a product embodying the claims, their primary line of business, or their current status in the traditional sense of a corporate entity.

Assignment timeline

• 2022-04-04 (executed) / recorded 2022-04-18 — Reel 059952/0973
  • Conveyance: Assignment
  • Assignor: Badizadegan, Nima
  • Assignee: HFT Solutions LLC
  • Correspondent: Patent GC LLC (as recorded: Patent GC LLC, Attn: Michael A. Glenn, 1400 Massachusetts Avenue, Suite 210, Cambridge, MA, 02138)
  • Context: Transfer-to-asserter (The inventor assigned the patent to an LLC, which later became the current assignee.)

Timeline diagram

timeline
    title Ownership of US 10771069
    2019 : Filed by Nima Badizadegan (Individual)
    2020 : Issued to Nima Badizadegan
    2022 : Assigned to HFT Solutions LLC

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was assigned from an individual inventor to HFT Solutions LLC on 2022-04-04 (Reel 059952/0973). The name "HFT Solutions LLC" suggests a specific focus (High-Frequency Trading) but, without evidence of product manufacturing, it aligns with a licensing-oriented entity. The fact the original assignee was an "Individual" also supports this, as individuals rarely engage in product manufacturing and assertion.
2. Known asserter in the chain — Not present. HFT Solutions LLC does not appear on commonly available public NPE lists (Acacia Research Corp, Marathon Patent Group, Intellectual Ventures, IPNav, Wi-LAN, Mosaid / Conversant, Vringo, Pendrell, Innovatio IP Ventures, MPHJ Technology, Lumen View Technology, Round Rock Research, Document Generation Corp, Erich Spangenberg entities).
3. Repeat correspondent across the chain — Not present. "Patent GC LLC" is the correspondent for the only recorded assignment. There is no recurrence of this correspondent within the chain for this patent, nor is there readily available information to suggest they are a known correspondent for other flagged NPE entities based on the information provided.
4. Cascading transfers — Not present. There is only one recorded assignment for this patent.
5. Pre-litigation transfer — Unclear. The IPR was filed on 2026-06-04. There is no public record of a prior infringement suit for this patent to determine if the 2022-04-04 assignment falls within a 6-month window before litigation.
6. Bankruptcy fire-sale — Not present. There is no indication in the assignment record or other provided information that the original assignee underwent bankruptcy proceedings.
7. Privateering — Unclear. There is no public information to suggest an operating company transferred the patent to HFT Solutions LLC to assert on its behalf.
8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at a known defensive aggregator like RPX, AST, LOT Network, Unified Patents, or Open Invention Network.

Verdict

NPE — moderate confidence

The assignment from an individual inventor to HFT Solutions LLC (Reel 059952/0973, recorded 2022-04-18) is a strong signal of a shell-entity transfer. Although HFT Solutions LLC is not on common public NPE lists, the initial assignment from an individual suggests a non-practicing origin, and the entity name is consistent with a specialized licensing or assertion company.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/ (Search for patent number 10771069)

To identify the most relevant prior art for US patent 10771069, I will access the full patent text and its cited references. The USPTO provides a Patent Public Search tool to search its database of patents and patent application publications.

The "Prior art keywords" from the patent's information section are "phase, clock signal, data streams, frequency, gate array" (from the original patent document).

Since I cannot directly execute a search on the USPTO database from my current environment, I will rely on the provided full patent text and its list of cited references to determine prior art. I will assume the provided patent text includes all relevant citations from the examiner.

Please provide the "References Cited" section from the full patent text of US10771069. Without that, I cannot fulfill the request for specific prior art citations and their analysis.

I cannot perform an obviousness analysis under 35 U.S.C. § 103 as requested. My previous analysis for the "Prior art" section explicitly stated that I need the "References Cited" section from the full patent text of US10771069 to identify specific prior art citations and conduct an analysis. Without this crucial information, I cannot identify combinations of prior art references or explain the motivation for combining them.

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE) for US10771069

Patent Term Adjustment (PTA):
US Patent 10771069 was granted Patent Term Adjustment (PTA). PTA is granted to compensate patent applicants for certain delays incurred by the USPTO during the patent prosecution process. The total PTA is added to the standard 20-year patent term from the earliest filing date. This adjustment is calculated based on specific timeframes the USPTO must meet for actions like issuing office actions, responding to applicant replies, and issuing the patent after the issue fee is paid.

To determine the exact PTA for US10771069, one would typically refer to the "Issue Notification" or the "Patent" document itself, which provides the calculated PTA. Without direct access to this specific document, the precise number of days cannot be definitively stated here.

Patent Term Extension (PTE):
Patent Term Extensions (PTEs) are generally available for patents covering human drugs, food or color additives, medical devices, animal drugs, and veterinary biological products to restore term lost due to premarket government approval delays from regulatory agencies like the FDA. Given the nature of US10771069, which relates to a field-programmable gate array (FPGA) system and high-frequency trading applications, it is highly unlikely to be eligible for a Patent Term Extension under 35 U.S.C. § 156. There is no information in the patent document or general patent records to suggest that US10771069 has received or is eligible for PTE.

Continuation and Divisional Applications

• Continuation Applications: A continuation application is a patent application based on an original "parent" application, sharing the same priority date and specification. It allows the applicant to pursue additional claims to an invention disclosed in the parent application that may not have been allowed or fully explored in the parent. These can be filed as long as at least one patent application in the family is pending.
• Divisional Applications: A divisional application is filed when a parent application contains claims directed to more than one distinct invention, and the USPTO issues a "restriction requirement" forcing the applicant to choose which invention to pursue in the parent. The claims for the non-elected invention(s) can then be pursued in one or more divisional applications. Divisional applications also share the same disclosure and priority date as the parent.

To determine if US10771069 is a continuation, divisional, or has any such applications, one would typically examine the "Related U.S. Application Data" section of the patent's front page. Based on the provided patent information, US10771069 lists several priority claims:

• Priority to US16/670,702 (2019-10-31)
• Priority to US16/888,218 (2020-05-29)
• Priority to US16/937,309 (2020-07-23)
• Priority to US17/236,577 (2021-04-21)
• Priority to US17/723,130 (2022-04-18)

These priority claims indicate that US10771069 is part of a patent family and claims priority back to at least application US16/670,702. The language "Priority to" typically signifies that these are either continuation, continuation-in-part, or divisional applications of earlier-filed applications. Without reviewing the complete prosecution history for each, it's difficult to definitively categorize each relationship (e.g., whether a restriction requirement led to a divisional, or if it's a straightforward continuation).

Related Family Members

The listed priority claims (US16/670,702, US16/888,218, US16/937,309, US17/236,577, US17/723,130) identify other applications in the patent family of US10771069. These applications are "related family members" as they share a common lineage and priority date with US10771069.

• US10771069B1
• US16/670,702
• US201916670702A
• US10771069 B1
• US 201916670702 A
• US10763865B1
• US11018678B1
• US11329655B1
• US12107587B1

It is important to note that the listed "Publication number" (US10771069B1) and "Application number" (US16/670,702) for US10771069 are directly associated with this patent. The other patent numbers like US10763865B1, US11018678B1, US11329655B1, and US12107587B1 are listed under "Priority to" and are therefore other issued patents or published applications that claim priority from the same lineage.

Projected Expiration Date

The standard term for a U.S. patent is 20 years from the filing date of the earliest non-provisional application in its family, subject to any Patent Term Adjustments (PTA) or Patent Term Extensions (PTE).

The filing date of US10771069 is October 31, 2019. The provided patent information states a "Priority date" of February 21, 2019. If this is the earliest effective filing date from which the 20-year term is calculated, then the base expiration date would be February 21, 2039.

However, the "Anticipated expiration" date is explicitly stated as 2039-10-31. This suggests that the 20-year term is being calculated from the filing date of the specific application that led to US10771069 (US16/670,702, filed 2019-10-31), rather than the earlier priority date of February 21, 2019. The discrepancy between the priority date and filing date for the 20-year term calculation often depends on whether the claims are fully supported by the earliest priority application.

Therefore, based on the explicitly stated "Anticipated expiration" date:

• Projected Expiration Date: October 31, 2039.

This date accounts for the standard 20-year term from the filing date (October 31, 2019) of the application US16/670,702, from which US10771069 directly matured. If there was any PTA, it would be added to this date. Without the specific PTA value, the given "Anticipated expiration" date is taken as the best current estimate.

Defensive Disclosure for US10771069

Publication Date: 2026-06-05

This Defensive Disclosure aims to broaden the public domain knowledge surrounding Field Programmable Gate Array (FPGA) systems with internal phase-locked loops, particularly concerning clock synchronization and phase matching. The objective is to proactively publish derivative variations of the technology described in US Patent 10771069, thereby establishing prior art that may render future incremental improvements by competitors obvious or non-novel under 35 U.S.C. § 102 and § 103. The focus is on extending the core concepts of phase-aligned data processing within FPGAs to various materials, operational extremes, application domains, emerging technologies, and failure modes.

Core Claim 1 Analysis and Derivatives

US Patent 10771069, Claim 1, generally describes an FPGA system featuring a deserializer, computational circuitry, a serializer, a phase detector, a phase controller, and an adjustable oscillator. The core inventive concept revolves around using a phase detector to measure the phase difference between a receiver-side clock and an interim transmitter-side clock, and then employing a phase controller and an adjustable oscillator to generate an adjusted wire rate clock signal for the serializer, thereby achieving phase matching of the transmitter-side clock. The following derivatives explore variations of this fundamental architecture.

---

Derivative 1: Material & Component Substitution - Superconducting FPGA with Josephson Junction Oscillators

Enabling Description:
This derivative envisions the FPGA system of Claim 1 implemented using superconducting technology, specifically employing Niobium-based Josephson Junction (JJ) logic for the FPGA core, deserializer, serializer, computational circuitry, phase detector, and phase controller. The adjustable oscillator, typically a Voltage-Controlled Oscillator (VCO) in conventional silicon FPGAs, is substituted with a Josephson Junction Phase-Locked Loop (JJ-PLL) incorporating a Superconducting Quantum Interference Device (SQUID)-based or phase-slip oscillator.

The first and second reference clock pins would receive cryogenically stable reference clock signals. The deserializer converts the incoming serial data stream, now potentially operating at sub-terahertz frequencies due to the superconducting logic, into parallel data streams using rapid single flux quantum (RSFQ) gates. The computational circuitry, also based on RSFQ logic, performs operations at significantly higher clock rates (e.g., hundreds of GHz to THz) with drastically reduced power consumption and latency. The phase detector, implemented with JJ-based phase comparators, measures the phase difference between the receiver-side clock (derived from the deserializer's output) and the interim transmitter-side clock (generated by the JJ-PLL). The phase controller, an RSFQ finite state machine, processes this phase difference indicator signal and generates adjustment information as a digital flux quantum signal. This adjustment information is fed to the adjustable JJ-PLL, which then generates the wire rate clock signal for the serializer, precisely aligning the transmitter-side clock's phase in the superconducting domain. The entire system operates at cryogenic temperatures, typically 4 Kelvin or below, to maintain superconductivity.

graph TD
    Oscillator_Ref[Cryogenic Reference Oscillator] --> RefClkPin1[First Ref Clock Pin]
    Oscillator_Adj(Adjustable JJ-PLL) --> RefClkPin2[Second Ref Clock Pin]
    IO_Module_In[Cryogenic I/O Module (Serial In)] --> DataPin1[First Data Pins]
    DataPin1 --> Deserializer(JJ Deserializer)
    RefClkPin1 --> Deserializer
    Deserializer -- RXCLOCK (JJ Logic) --> PhaseDetector(JJ Phase Detector)
    Deserializer -- Parallel Data --> ComputationalLogic(JJ Computational Circuitry)
    ComputationalLogic -- Parallel Data --> Serializer(JJ Serializer)
    ComputationalLogic -- RXCLOCK (JJ Logic) --> Serializer
    Serializer -- TXCLOCK_Interim (JJ Logic) --> PhaseDetector
    PhaseDetector -- Phase Diff Signal (Flux Quanta) --> PhaseController(JJ Phase Controller)
    PhaseController -- Adjustment Info (Flux Quanta) --> Oscillator_Adj
    Oscillator_Adj -- Wire Rate Clock (JJ Logic) --> Serializer
    Serializer -- Serial Data --> DataPin2[Second Data Pins]
    DataPin2 --> IO_Module_Out[Cryogenic I/O Module (Serial Out)]

---

Derivative 2: Operational Parameter Expansion - Ultra-High Frequency & Distributed Synchronization

Enabling Description:
This derivative describes the FPGA system of Claim 1 operating at extremely high frequencies (e.g., 200+ Gbps per serial lane, 10 GHz internal clock frequency) and extended to a distributed multi-FPGA architecture. Each FPGA node includes the core components: a deserializer, computational circuitry, serializer, phase detector, phase controller, and an adjustable oscillator. The deserializer and serializer transceivers are designed for 200 Gbps+ data rates, utilizing advanced SiGe or InP-based electro-optical components for conversion at the physical layer. The internal parallel data streams are extremely wide (e.g., 256 or 512 bits) operating at multi-GHz clock rates.

The novelty lies in the distributed phase synchronization. The phase controller on each FPGA node not only adjusts its local oscillator but also communicates its phase difference indicator signal and adjustment information to a central network timing controller and to adjacent FPGAs via a dedicated low-latency optical interconnect. This allows for a global phase alignment across multiple FPGAs, compensating for inter-FPGA link skews and environmental variations. The adjustable oscillator is a highly stable, digitally-controlled oscillator (DCO) with sub-picosecond phase resolution, capable of rapid frequency and phase adjustments. The phase detector samples at multi-GHz rates, providing granular phase difference measurements. The computational circuitry leverages highly pipelined architectures and custom hard IP blocks optimized for these extreme frequencies, avoiding any clock domain crossings by ensuring all local processing is phase-aligned.

graph TD
    SubGraph FPGA_A
        direction LR
        A_IO_IN[Serial Data In A] --> A_DES(Deserializer A)
        A_REF_CLK[Ref Clock A] --> A_DES
        A_DES -- RX_CLKA --> A_PD(Phase Detector A)
        A_DES -- Parallel Data A --> A_COMP(Computational Logic A)
        A_COMP -- Parallel Data A --> A_SER(Serializer A)
        A_COMP -- RX_CLKA --> A_SER
        A_SER -- TX_Interim A --> A_PD
        A_PD -- Phase Diff A --> A_PC(Phase Controller A)
        A_PC -- Adj Info A --> A_OSC(Adjustable OSC A)
        A_OSC -- WR_CLKA --> A_SER
        A_SER --> A_IO_OUT[Serial Data Out A]
    end
    SubGraph FPGA_B
        direction LR
        B_IO_IN[Serial Data In B] --> B_DES(Deserializer B)
        B_REF_CLK[Ref Clock B] --> B_DES
        B_DES -- RX_CLKB --> B_PD(Phase Detector B)
        B_DES -- Parallel Data B --> B_COMP(Computational Logic B)
        B_COMP -- Parallel Data B --> B_SER(Serializer B)
        B_COMP -- RX_CLKB --> B_SER
        B_SER -- TX_Interim B --> B_PD
        B_PD -- Phase Diff B --> B_PC(Phase Controller B)
        B_PC -- Adj Info B --> B_OSC(Adjustable OSC B)
        B_OSC -- WR_CLKB --> B_SER
        B_SER --> B_IO_OUT[Serial Data Out B]
    end
    A_PC -- Global Sync Req --> Central_NTC[Central Network Timing Controller]
    B_PC -- Global Sync Req --> Central_NTC
    Central_NTC -- Global Adj --> A_PC
    Central_NTC -- Global Adj --> B_PC
    A_OSC -- Cross-FPGA Link Sync --> B_OSC
    B_OSC -- Cross-FPGA Link Sync --> A_OSC

---

Derivative 3: Cross-Domain Application - Precision Scientific Instrument Data Acquisition

Enabling Description:
This derivative applies the FPGA system of Claim 1 to high-precision scientific instrument data acquisition, specifically in contexts like particle accelerators or radio astronomy arrays where femtosecond-level synchronization across distributed sensors is critical.

The FPGA (e.g., a radiation-hardened variant) is deployed as a front-end data acquisition unit. The first serial data stream comprises raw sensor data (e.g., digitized RF signals from an antenna array or event data from particle detectors) transmitted over optical fiber links, requiring precise phase recovery. The first reference clock signal is a highly stable, externally disciplined clock (e.g., GPS-DO or atomic clock reference). The deserializer (implemented with hardened, low-noise components) recovers the high-speed data and a receiver-side clock. The computational circuitry performs initial filtering, timestamping, and preliminary event detection on the parallel data streams, synchronized to the receiver-side clock. The serializer transmits processed data and synchronized control signals (the second serial data stream) back to a central control unit.

The phase detector is an ultra-high-resolution time-to-digital converter (TDC) integrated into the FPGA fabric, capable of measuring phase differences with picosecond or even sub-picosecond precision. The phase controller (a custom, low-latency control loop in the FPGA logic) processes the TDC output to generate adjustment information. This information is fed to an on-chip adjustable, fractional-N PLL (the adjustable oscillator), which generates the wire rate clock signal for the serializer. The PLL is designed for exceptionally low jitter and phase noise, ensuring the transmitted data and synchronization signals maintain the required femtosecond-level phase coherence for distributed array processing or event correlation across the scientific instrument.

graph TD
    AtomicClock[Atomic Clock Reference] --> RefClkPin1[First Ref Clock Pin (FPGA)]
    SensorArray[Distributed Sensor Array] --> OpticalLinkIn[Optical Fiber Link]
    OpticalLinkIn --> DataPin1[First Data Pins (FPGA)]
    DataPin1 --> Deserializer(Hardened Deserializer)
    RefClkPin1 --> Deserializer
    Deserializer -- RX_CLOCK (Low Jitter) --> PhaseDetector(Integrated TDC Phase Detector)
    Deserializer -- Raw Parallel Data --> ComputationalLogic(FPGA Comp. Logic - Filtering/Timestamp)
    ComputationalLogic -- Processed Parallel Data --> Serializer(Hardened Serializer)
    ComputationalLogic -- RX_CLOCK --> Serializer
    Serializer -- TX_Interim (Low Jitter) --> PhaseDetector
    PhaseDetector -- Picosecond Phase Diff --> PhaseController(Custom Low-Latency Control Loop)
    PhaseController -- Digital Adjustment --> AdjustableOscillator(Fractional-N PLL)
    AdjustableOscillator -- Wire Rate Clock --> Serializer
    Serializer --> OpticalLinkOut[Optical Fiber Link]
    OpticalLinkOut --> CentralControl[Central Control Unit / Data Processor]

---

Derivative 4: Integration with Emerging Tech - AI-Optimized Adaptive Phase Alignment

Enabling Description:
This derivative integrates the FPGA system of Claim 1 with an AI-driven optimization layer for adaptive phase alignment. The deserializer, computational circuitry, and serializer function as described.

The phase detector measures the raw phase difference. The phase controller, instead of a fixed-parameter control loop, incorporates a lightweight, embedded Machine Learning (ML) inference engine (e.g., a pre-trained neural network). This ML engine receives the phase difference indicator signal, along with additional telemetry data from the FPGA (e.g., internal temperature sensors, supply voltage monitors, data traffic load, age of components, external environmental sensors via IoT gateway) as inputs.

Based on these inputs, the ML engine dynamically predicts optimal adjustment information (e.g., precise bias voltage for a VCO, fine-grained divider ratios for a fractional-N PLL, or delay line tap settings). This adjustment information is then fed to the adjustable oscillator. Over time, the ML model can be periodically retrained (offline or with limited online learning) using historical performance data and observed phase drift patterns, allowing the system to proactively compensate for environmental variations, component aging, and workload-dependent jitter, achieving superior and more stable phase alignment than static control loops. This creates a self-optimizing phase alignment system. Furthermore, significant phase-alignment events, changes in configuration, and the ML model's confidence scores for adjustments are logged and immutably stored on a distributed ledger (blockchain) for auditability and certification in critical applications.

graph TD
    RefClkPin1[First Ref Clock Pin] --> Deserializer(Deserializer)
    DataPin1[First Data Pins] --> Deserializer
    Deserializer -- RX_CLOCK --> PhaseDetector(Phase Detector)
    Deserializer -- Parallel Data --> ComputationalLogic(Computational Circuitry)
    ComputationalLogic -- Parallel Data --> Serializer(Serializer)
    ComputationalLogic -- RX_CLOCK --> Serializer
    Serializer -- TX_Interim --> PhaseDetector
    PhaseDetector -- Phase Diff Signal --> ML_Controller(Embedded ML Inference Engine)
    ML_Controller -- Adjustment Info --> AdjustableOscillator(Adjustable Oscillator)
    AdjustableOscillator -- Wire Rate Clock --> Serializer
    FPGA_Telemetry[FPGA Telemetry (Temp, Voltage, Load)] --> ML_Controller
    IoT_Sensors[IoT Environmental Sensors] --> ML_Controller
    ML_Controller -- Logged Events/Adjustments --> Blockchain[Blockchain Ledger for Audit]
    ML_Controller -- Model Updates --> Cloud_ML_Platform(Cloud ML Platform for Retraining)

---

Derivative 5: The "Inverse" or Failure Mode - Graceful Degradation to Frequency-Locked Low-Power Mode

Enabling Description:
This derivative describes an FPGA system according to Claim 1, but with an added "Failure Mode Manager" for graceful degradation and low-power operation. In normal operation, the system provides full phase alignment. However, if the phase detector continuously reports a phase difference exceeding a predefined high threshold for a sustained period (indicating loss of phase lock), or if a low-power mode is explicitly commanded, the Failure Mode Manager is activated.

Upon activation, the system transitions from phase-locked mode to a frequency-locked, low-power mode. In this mode, the phase controller ceases fine-grained phase adjustments and instead directs the adjustable oscillator to maintain only frequency lock with the receiver-side clock, typically at a reduced clock frequency. To prevent data corruption during this phase-unlocked state, the computational circuitry dynamically inserts asynchronous FIFO buffers (Clock Domain Crossing circuits) between the deserializer output and the main processing path, and between the processing path and the serializer input. These FIFOs introduce additional latency but guarantee data integrity by absorbing phase differences. Concurrently, the adjustable oscillator is reconfigured to consume minimal power (e.g., by reducing VCO bias or operating with slower, less precise components). The system provides a "Limited Functionality" signal to external systems, indicating reduced performance but continued, albeit slower, operation.

stateDiagram-v2
    [*] --> Initializing
    Initializing --> NormalOperation : System Ready & Phase Locked
    NormalOperation --> LowPowerMode : Low Power Command OR High Threshold Phase Error
    NormalOperation --> SafeMode : Critical Phase Error (No Lock)

    state NormalOperation {
        RX_CLK --> PhaseDetector
        TX_CLK_Interim --> PhaseDetector
        PhaseDetector --> PhaseController : Phase Diff
        PhaseController --> AdjustableOscillator : Phase Adjust
        AdjustableOscillator --> Serializer : Wire Rate CLK
        ComputationalLogic --> Serializer : Data
    }

    state LowPowerMode {
        RX_CLK --> FrequencyLockedOscillator : Freq Ref
        FrequencyLockedOscillator --> Serializer : Low Power WR_CLK
        Deserializer --> AsyncFIFO_RX : Data In
        AsyncFIFO_RX --> ComputationalLogic : Data Out
        ComputationalLogic --> AsyncFIFO_TX : Data In
        AsyncFIFO_TX --> Serializer : Data Out
        note on LowPowerMode
            Phase alignment is relaxed.
            Focus on frequency lock.
            Increased latency via Async FIFOs.
            Reduced power consumption.
        end note
    }

    state SafeMode {
        RX_CLK --> FrequencyLockedOscillator : Freq Ref
        FrequencyLockedOscillator --> Serializer : Safe WR_CLK
        Deserializer --> AsyncFIFO_RX_Crit : Data In
        AsyncFIFO_RX_Crit --> ComputationalLogic : Data Out
        ComputationalLogic --> AsyncFIFO_TX_Crit : Data In
        AsyncFIFO_TX_Crit --> Serializer : Data Out
        note on SafeMode
            Emergency mode, data integrity prioritized.
            Possibly further reduced clock speed.
            System attempts to re-establish NormalOperation.
        end note
    }

    LowPowerMode --> NormalOperation : Optimal Phase Re-established
    SafeMode --> NormalOperation : Optimal Phase Re-established
    SafeMode --> Shutdown : Unrecoverable Error
    LowPowerMode --> Shutdown : External Shutdown Command

---

Combination Prior Art Scenarios

These scenarios combine the teachings of US10771069 with existing open-source standards, demonstrating how the patent's core concepts could be rendered obvious in various system contexts.

1. FPGA with Internal PLL for Synchronous Ethernet (SyncE) on O-RAN Fronthaul:

   • Description: An FPGA system as described in US10771069 (Claims 1, 25, 38, 59, 75, 96) is used as a Radio Unit (RU) or Distributed Unit (DU) in an Open Radio Access Network (O-RAN) fronthaul interface. The first serial data stream comprises Common Public Radio Interface (CPRI) or enhanced CPRI (eCPRI) data, and the second serial data stream is the processed CPRI/eCPRI data. The first clock signal is a recovered clock from the incoming CPRI/eCPRI stream, which often carries timing information. The core idea of internally aligning the receiver-side clock (derived from the CPRI/eCPRI data) and the transmitter-side clock (for outgoing CPRI/eCPRI) to eliminate clock domain crossings within the FPGA is applied.
   • Combination Prior Art: The O-RAN Alliance specifications (e.g., O-RAN Fronthaul Specifications, WG4, specifically relating to timing and synchronization over Ethernet, which leverages IEEE 1588 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) as defined in IEEE 802.3 and IEEE 1588). A person skilled in the art, familiar with the need for precise timing in radio access networks and the principles of SyncE/PTP, would find it obvious to apply the internal FPGA phase alignment techniques of US10771069 to minimize latency and ensure phase coherence for CPRI/eCPRI processing within an O-RAN RU or DU, particularly given the known challenges of clock synchronization in these environments. The internal PLL in the FPGA would be used to align the transmit clock to the recovered receive clock, eliminating the need for traditional clock domain crossing logic for optimal latency in real-time radio signal processing.

2. FPGA with Internal PLL for High-Performance Computing (HPC) Interconnect using OpenCAPI/Gen-Z:

   • Description: The FPGA system of US10771069 is employed as a network interface card (NIC) or a custom accelerator in an HPC environment. The first serial data stream and second serial data stream are high-speed data packets transmitted over a peer-to-peer interconnect fabric adhering to OpenCAPI or Gen-Z specifications. The first clock signal is the recovered data clock from the incoming OpenCAPI/Gen-Z link, and the second clock signal is a system reference clock. The FPGA's internal phase detector and phase controller adjust an on-chip PLL to synchronize the transmitter-side clock precisely with the receiver-side clock, minimizing latency for data transfer between compute nodes or between CPU/GPU and FPGA accelerators over the OpenCAPI/Gen-Z fabric. This prevents unnecessary buffer latencies that would otherwise accumulate due to clock domain mismatches in high-bandwidth, low-latency applications.
   • Combination Prior Art: The OpenCAPI (Coherent Accelerator Processor Interface) and Gen-Z standards, both open standards for high-speed, low-latency memory-semantic fabrics. These standards inherently address high-speed data transfer and synchronization challenges. An engineer designing an OpenCAPI or Gen-Z compliant FPGA interface, needing to minimize transaction latency, would readily combine the teachings of US10771069 to achieve efficient internal clock synchronization within the FPGA, thereby optimizing performance for memory-semantic operations and coherency protocols.

3. FPGA with Internal PLL for Real-time Control Systems using EtherCAT/PROFINET:

   • Description: The FPGA system as described in US10771069 is used in an industrial automation context as a master or slave device for real-time control, communicating over an EtherCAT or PROFINET network. The first serial data stream consists of incoming process data or control commands from the industrial network, and the second serial data stream comprises outgoing sensor readings or actuator commands. The first clock signal is derived from the highly deterministic EtherCAT/PROFINET synchronization mechanism (e.g., distributed clocks in EtherCAT). The FPGA's internal phase alignment ensures that computational circuitry processing the incoming data and preparing outgoing data operates without significant clock domain crossing delays, maintaining the strict cycle times and jitter requirements of these real-time protocols. The phase controller and adjustable oscillator actively match the internal transmit clock to the network-derived receive clock.
   • Combination Prior Art: The EtherCAT (Ethernet for Control Automation Technology) and PROFINET (Process Field Network) standards, which are open Ethernet-based protocols widely used in industrial automation for real-time communication. These protocols feature precise synchronization mechanisms and strict timing requirements. A control engineer tasked with implementing an EtherCAT/PROFINET node on an FPGA, and aware of the need to eliminate latency in data processing paths for deterministic operation, would find it obvious to apply the internal phase-locked loop and phase alignment techniques of US10771069 to achieve optimal performance and compliance with the stringent timing specifications of these industrial real-time networks.