US 10771069

US Patent 10771069, titled "Field programmable gate array with internal phase-locked loop," was filed on October 31, 2019, and issued on September 8, 2020. The inventor is Nima Badizadegan, and the current assignee is HFT Solutions LLC.

Abstract:
A field programmable gate array system comprises a field programmable gate array (FPGA) with a first interface. This interface includes a first reference clock pin to receive a first clock signal, a second reference clock pin to receive a second clock signal, first data pins for a first serial data stream, and second data pins for a second serial data stream. A deserializer is connected to the first reference clock pin and the first data pins, converting the first serial data stream into parallel data streams. A phase detector is connected to the deserializer to receive the first receiver side clock signal. A serializer is connected to computational circuitry to receive parallel data streams.

Independent Claims Overview:

• Claim 1 (System Claim): This claim describes an FPGA system including an FPGA with specific interfaces (clock and data pins). It features a deserializer to convert an incoming serial data stream (with a first clock signal) into parallel data, and a serializer to convert parallel data into an outgoing serial data stream. Key to this claim is a phase detector that receives a receiver-side clock signal, and a phase controller that generates adjustment information based on a phase difference between a receiver-side clock and a transmitter-side clock. This adjustment information is used to modify the transmitter-side clock to achieve phase matching.
• Claim 25 (System Claim): Similar to Claim 1, this claim also describes an FPGA system with interfaces, a deserializer, and a serializer. The distinction is that it explicitly includes a transceiver phase-locked loop (PLL) connected to the second reference clock pin, configured to generate a wire rate clock signal for the serializer. This transceiver PLL is adjustable based on adjustment information from the internal phase controller, which in turn uses a phase difference detected between the receiver and transmitter clocks to align them.
• Claim 38 (Method Claim): This claim outlines a method for processing market data (first serial data stream) on an FPGA system to generate order entry data (second serial data stream). The method involves receiving clock and data signals, deserializing the market data, generating a receiver-side clock, performing operations on the parallel data, generating a transmitter-side clock, and serializing the order entry data. Crucially, it includes steps for determining a phase difference between the receiver-side and transmitter-side clocks and adjusting the transmitter-side clock based on this difference to achieve phase alignment.
• Claim 59 (Method Claim): This method claim focuses on generating a transmitter-side clock signal for an FPGA. It involves receiving a second clock signal via a reference pin and processing it using a transceiver phase-locked loop (PLL) that is adjustable. The PLL provides a wire rate clock signal to a serializer. The method integrates a phase detector to compare the receiver-side clock with an interim transmitter-side clock, and a phase controller that generates adjustment information for the adjustable transceiver PLL to align the clocks.
• Claim 75 (System Claim): This claim describes an FPGA system where the second reference clock pin (for the transmitter side) is configured to receive the same first clock signal as the receiver side. It includes a deserializer, computational circuitry, a serializer, a phase detector, and an adjustable phase-locked loop (PLL) within the FPGA to generate the transmitter-side clock. The phase detector compares the receiver-side and transmitter-side clocks, and an internal phase controller uses the phase difference to adjust the PLL for phase matching.
• Claim 96 (Method Claim): This method claim details processing market data on an FPGA system when the second reference clock pin receives the first clock signal. It involves receiving and deserializing the market data, generating a receiver-side clock, performing computations, generating a wire rate clock for serialization using an adjustable phase-locked loop (PLL) within the FPGA, and serializing the output. It emphasizes detecting the phase difference between the receiver-side clock and an interim transmitter-side clock, and then using this information to adjust the PLL to align the phases.

CAFC 2026 Dockets:
A search of the CAFC 2026 dockets did not reveal any cases specifically mentioning US patent 10771069.