US 11575381

US Patent 11575381: Concise Summary

Title: Field programmable gate array with external phase-locked loop

Assignee: HFT Solutions LLC

Inventor: Nima Badizadegan

Filing Date: April 18, 2022

Issue Date: February 07, 2023

Abstract:
The patent describes a field programmable gate array (FPGA) system designed to offer phase control with minimal latency.

Plain-Language Overview of Independent Claims:

• Claim 1: Field Programmable Gate Array System
  This claim describes a Field Programmable Gate Array (FPGA) system. The system includes an FPGA chip and an external phase control circuit. The FPGA itself has input/output pins for receiving clock signals and data streams, and for transmitting processed data and internal clock signals. Inside the FPGA, a deserializer converts incoming serial data into parallel data streams and generates a "receiver-side clock." Computational logic then processes these parallel data streams. A serializer converts the processed parallel data back into a serial data stream for transmission and generates a "transmitter-side clock." The key innovation is the external phase control circuit. This circuit comprises an external phase detector that compares the receiver-side and transmitter-side clock signals output from the FPGA. Based on this comparison, an external phase controller determines necessary adjustments and sends this information to an external adjustable oscillator. This oscillator then generates a control clock signal that is fed back into the FPGA to adjust the frequency or phase of the internal transmitter-side clock. The goal is to phase-align the internal receiver-side and transmitter-side clocks to a fixed phase difference, thereby avoiding latency associated with traditional clock domain crossing circuits within the FPGA.

• Claim 26: Method for Data Processing
  This claim outlines a method for processing a first serial data stream (e.g., market data) using the aforementioned FPGA system to generate a second serial data stream (e.g., order entry data). The method involves:

  1. Receiving the input serial data and a first clock signal at the FPGA.
  2. An internal deserializer converting the serial data to parallel data and generating a receiver-side clock signal.
  3. Transmitting this receiver-side clock out of the FPGA to an external phase detector.
  4. Continuously generating and adjusting a transmitter-side clock signal until the external phase detector indicates that the receiver-side and transmitter-side clocks are sufficiently phase-aligned (below a certain threshold). This iterative adjustment involves:
     • An external adjustable oscillator providing a second clock signal.
     • An internal FPGA serializer generating an interim transmitter-side clock.
     • Transmitting this interim transmitter-side clock out of the FPGA to the external phase detector.
     • The external phase detector comparing the receiver-side and interim transmitter-side clocks and sending feedback to an external phase controller.
     • The external phase controller then directs the external adjustable oscillator to modify its output (the second clock signal) until alignment is achieved.
  5. Once the clocks are aligned, computational logic within the FPGA processes the parallel data streams (e.g., using a trading algorithm) to generate processed parallel data.
  6. The FPGA's serializer converts these processed parallel data streams into the final second serial data stream.
  7. The second serial data stream is then transmitted out of the FPGA.

Litigation Dockets:
A search of CAFC 2026 dockets specifically for US Patent 11575381 did not yield any direct results indicating a case for this patent in the Court of Appeals for the Federal Circuit in 2026.

However, the Google Patents information for US11575381 notes the following litigation activity:

• A PTAB case, IPR2026-00151, was filed in 2026 and is currently pending.
• Multiple US cases were filed in the Texas Western District Court (case 7:25-cv-00415) and the Illinois Northern District Court (cases 1:24-cv-13213 and 1:24-cv-13214). [cite: US11575381B1 - Google Patents]
• There is also a record of the "First worldwide family litigation filed" for this patent family. [cite: US11575381B1 - Google Patents]