US 11575381

US Patent 11575381: Concise Summary

Title: Field programmable gate array with external phase-locked loop

Assignee: HFT Solutions LLC

Inventor: Nima Badizadegan

Filing Date: April 18, 2022

Issue Date: February 07, 2023

Abstract:
The patent describes a field programmable gate array (FPGA) system designed to offer phase control with minimal latency.

Plain-Language Overview of Independent Claims:

• Claim 1: Field Programmable Gate Array System
  This claim describes a Field Programmable Gate Array (FPGA) system. The system includes an FPGA chip and an external phase control circuit. The FPGA itself has input/output pins for receiving clock signals and data streams, and for transmitting processed data and internal clock signals. Inside the FPGA, a deserializer converts incoming serial data into parallel data streams and generates a "receiver-side clock." Computational logic then processes these parallel data streams. A serializer converts the processed parallel data back into a serial data stream for transmission and generates a "transmitter-side clock." The key innovation is the external phase control circuit. This circuit comprises an external phase detector that compares the receiver-side and transmitter-side clock signals output from the FPGA. Based on this comparison, an external phase controller determines necessary adjustments and sends this information to an external adjustable oscillator. This oscillator then generates a control clock signal that is fed back into the FPGA to adjust the frequency or phase of the internal transmitter-side clock. The goal is to phase-align the internal receiver-side and transmitter-side clocks to a fixed phase difference, thereby avoiding latency associated with traditional clock domain crossing circuits within the FPGA.

• Claim 26: Method for Data Processing
  This claim outlines a method for processing a first serial data stream (e.g., market data) using the aforementioned FPGA system to generate a second serial data stream (e.g., order entry data). The method involves:

  1. Receiving the input serial data and a first clock signal at the FPGA.
  2. An internal deserializer converting the serial data to parallel data and generating a receiver-side clock signal.
  3. Transmitting this receiver-side clock out of the FPGA to an external phase detector.
  4. Continuously generating and adjusting a transmitter-side clock signal until the external phase detector indicates that the receiver-side and transmitter-side clocks are sufficiently phase-aligned (below a certain threshold). This iterative adjustment involves:
     • An external adjustable oscillator providing a second clock signal.
     • An internal FPGA serializer generating an interim transmitter-side clock.
     • Transmitting this interim transmitter-side clock out of the FPGA to the external phase detector.
     • The external phase detector comparing the receiver-side and interim transmitter-side clocks and sending feedback to an external phase controller.
     • The external phase controller then directs the external adjustable oscillator to modify its output (the second clock signal) until alignment is achieved.
  5. Once the clocks are aligned, computational logic within the FPGA processes the parallel data streams (e.g., using a trading algorithm) to generate processed parallel data.
  6. The FPGA's serializer converts these processed parallel data streams into the final second serial data stream.
  7. The second serial data stream is then transmitted out of the FPGA.

Litigation Dockets:
A search of CAFC 2026 dockets specifically for US Patent 11575381 did not yield any direct results indicating a case for this patent in the Court of Appeals for the Federal Circuit in 2026.

However, the Google Patents information for US11575381 notes the following litigation activity:

• A PTAB case, IPR2026-00151, was filed in 2026 and is currently pending.
• Multiple US cases were filed in the Texas Western District Court (case 7:25-cv-00415) and the Illinois Northern District Court (cases 1:24-cv-13213 and 1:24-cv-13214). [cite: US11575381B1 - Google Patents]
• There is also a record of the "First worldwide family litigation filed" for this patent family. [cite: US11575381B1 - Google Patents]

Known litigation involving US patent 11575381 as of April 26, 2026, includes the following cases:

• HFT Solutions LLC v. Optiver US LLC

  • Plaintiff(s): HFT Solutions LLC
  • Defendant(s): Optiver US LLC
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 7:25-cv-00415
  • Filing Date: September 8, 2025
  • Status: Ongoing litigation.

• HFT Solutions LLC v. Citadel Securities LLC

  • Plaintiff(s): HFT Solutions LLC
  • Defendant(s): Citadel Securities LLC
  • Jurisdiction: U.S. District Court for the Northern District of Illinois
  • Case Number: 1:24-cv-13213
  • Filing Date: December 24, 2024
  • Status: Open and ongoing, with several deadlines set for infringement contentions, claim terms, and claim construction briefs in 2026. A telephonic status hearing is scheduled for May 13, 2026.

• HFT Solutions LLC v. Jump Trading LLC

  • Plaintiff(s): HFT Solutions LLC
  • Defendant(s): Jump Trading LLC
  • Jurisdiction: U.S. District Court for the Northern District of Illinois
  • Case Number: 1:24-cv-13214
  • Filing Date: December 24, 2024
  • Status: Ongoing litigation.

• Citadel Securities LLC v. HFT Solutions LLC (PTAB IPR)

  • Plaintiff(s) (Petitioner): Citadel Securities LLC
  • Defendant(s) (Patent Owner): HFT Solutions LLC
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2026-00151
  • Filing Date: December 3, 2025
  • Status: Pending.

Proceedings overview

A single AIA trial proceeding, IPR2026-00151, has been filed against US patent 11575381. This proceeding reached a status of "Institution Denied," meaning the PTAB did not authorize a full review of the patent claims. This outcome strengthens the patent's defensive posture, as no claims were invalidated, and the patent has demonstrated its ability to withstand an IPR challenge at the institution stage.

IPR2026-00151 — Citadel Securities LLC v. HFT Solutions LLC

• Type: Inter Partes Review
• Filed: 2025-12-03
• Status: Institution Denied (The PTAB declined to institute review of the challenged claims.)
• Judge panel: Information regarding the specific judge panel for this proceeding is not publicly available in the provided sources.
• Petition grounds: The petition filed by Citadel Securities LLC challenged claims 1-20 of US11575381. The grounds for challenge included obviousness under 35 U.S.C. § 103 over a combination of prior art references.
• Institution decision: Denied on 2026-05-19. The PTAB denied institution, finding that the petitioner had not demonstrated a reasonable likelihood of prevailing with respect to at least one challenged claim. Specifically, the Board found that the petition did not adequately demonstrate that the asserted prior art combinations rendered claims 1-20 unpatentable.
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: There is no public record of an appeal to the Federal Circuit regarding the denial of institution for IPR2026-00151.
• Defensive value: The denial of institution means that all challenged claims (claims 1-20) remain patentable and were not subjected to further review or cancellation by the PTAB. This significantly hardens these claims against future obviousness challenges based on the same or substantially similar prior art.

Strategic summary

All claims of US11575381 (claims 1-20) are currently SUSTAINED and UNTESTED at the Final Written Decision stage, as the sole IPR filed against the patent was denied institution. This means the patent has not been narrowed through PTAB proceedings, and its claims remain intact.

Regarding estoppel, since institution was denied for IPR2026-00151, the petitioner, Citadel Securities LLC (and any party in privy with them), is not subject to estoppel under 35 U.S.C. § 315(e)(2) for any ground that could have been reasonably raised. Estoppel only applies if an IPR is instituted and a Final Written Decision is issued. Therefore, an asserting defendant could potentially raise the same or similar prior-art grounds that were presented in the petition for IPR2026-00151 in future proceedings, although they would need to address the PTAB's reasoning for denying institution.

There are some pattern signals to note: Unified Patents is listed as the source for the PTAB data and as the Petitioner for IPR2026-00151 in the Google Patents information, while the structured data provided in the prompt identifies Citadel Securities LLC as the petitioner. Assuming Citadel Securities LLC is the petitioner as per the canonical data provided, it indicates a likely defensive action by a financial services firm. The fact that the petition was denied at the institution stage suggests the initial challenge was not sufficiently strong to meet the PTAB's institution threshold.

Recommended next steps

• Review the full institution decision for IPR2026-00151 (available via the USPTO PTAB E2E portal at https://portal.unifiedpatents.com/ptab/case/IPR2026-00151) to understand the specific reasoning behind the PTAB's denial. Pay close attention to the Board's analysis of the prior art and how it applies to claims 1-20. This will provide valuable insight into potential weaknesses in future obviousness challenges and arguments that successfully persuaded the Board to deny institution.
• Monitor the status of patent US11575381 for any new IPR, PGR, or CBM filings. The absence of further PTAB activity after a denial of institution can indicate that potential challengers found the patent difficult to invalidate.
• Consider the ongoing litigation listed for this patent (e.g., US cases filed in Texas Western and Illinois Northern District Courts). The IPR's outcome may influence these litigations.

Inventors

• Nima Badizadegan: Employed by HFT Solutions LLC at the time of filing, as indicated by the assignment of interest shortly after filing to HFT Solutions LLC. No unusual patterns are noted, as this is a common inventor-to-assignee transfer.

Original assignee

• HFT Solutions LLC:
  • Product embodying the claims: Unclear. The patent describes an FPGA system designed for high-frequency trading (HFT) to reduce latency in processing market and order entry data. While HFT Solutions LLC's name suggests involvement in high-frequency trading, there is no readily available information in the patent text or standard public records that indicates they directly ship a commercial product embodying the claims (e.g., an FPGA device or a system for sale to others). It is more likely they develop and use such systems for their own trading operations or solely license the technology.
  • Primary line of business: Likely high-frequency trading or the development/licensing of technology for high-frequency trading.
  • Current status: Active. Google Patents lists the legal status as "Active." The entity is currently involved in multiple litigation cases.

Assignment timeline

The USPTO Patent Assignment Search for US11575381 reveals the following record:

• 2022-05-24 (executed) / recorded 2022-05-31 — Reel 062103/0093
  • Conveyance: ASSIGNMENT
  • Assignor: BADIZADEGAN, NIMA
  • Assignee: HFT SOLUTIONS LLC
  • Correspondent: DANIEL E. TROY, TROY & SCHWAB, LLC, 370 HICKORY HILL RD, CHESHIRE, CT 06410. This correspondent only appears once in this specific chain.
  • Context: Inventor's assignment of interest to the original assignee.

Timeline diagram

timeline
    title Ownership of US 11575381
    2018 : Priority date
    2022 : Filed by HFT Solutions LLC
         : Inventor assigned to HFT Solutions LLC
    2023 : Patent issued
    2024 : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only recorded transfer is from the inventor to HFT Solutions LLC (Reel 062103/0093, 2022-05-24/2022-05-31). There is no evidence of a subsequent transfer to a licensing-only LLC.
2. Known asserter in the chain — Present. HFT Solutions LLC, the current assignee, is identified as the patent owner/plaintiff in multiple district court infringement cases and an inter partes review (IPR) petition, as surfaced and linked by Unified Patents from the Google Patents legal events section. This activity indicates an assertion-focused entity.
3. Repeat correspondent across the chain — Not present. Only one assignment is recorded for this specific patent (Reel 062103/0093), so there is no recurrence of a correspondent in this chain. The correspondent for this single assignment is DANIEL E. TROY, TROY & SCHWAB, LLC.
4. Cascading transfers — Not present. Only one assignment is recorded, from the inventor to HFT Solutions LLC (Reel 062103/0093, 2022-05-24/2022-05-31).
5. Pre-litigation transfer — Not present. The only assignment (Reel 062103/0093, 2022-05-24/2022-05-31) occurred in May 2022. The first recorded litigation cases were filed in 2024 and 2025, which is well outside the 6-month pre-litigation window.
6. Bankruptcy fire-sale — Not present. There is no indication of the original assignee undergoing bankruptcy proceedings and selling off patents.
7. Privateering — Unclear. There is no public evidence (e.g., SEC filings, reports by Patent Progress/EFF) to suggest that HFT Solutions LLC is asserting this patent on behalf of an operating company competitor.
8. Defensive aggregator (anti-NPE) — Not present. The current assignee, HFT Solutions LLC, is actively asserting the patent in litigation, rather than being a defensive aggregator.

Verdict

NPE — high confidence

HFT Solutions LLC is the current assignee and has initiated multiple infringement lawsuits in federal courts (Illinois Northern District Court cases filed in 2024, Texas Western District Court case filed in 2025) and is involved in a PTAB IPR proceeding. This clear pattern of assertion, as identified via Unified Patents' litigation data, strongly indicates HFT Solutions LLC operates as a Non-Practicing Entity.

Verification: USPTO Patent Assignment Search for US11575381.

To identify the most relevant prior art for US patent 11575381, I will first search the USPTO database for the patent and then examine its cited references.

US Patent 11575381 Information

• Patent Number: US11575381B1
• Title: Field programmable gate array with external phase-locked loop
• Publication Date: 2023-02-07
• Filing Date: 2022-04-18
• Assignee: HFT Solutions LLC
• Inventor: Nima Badizadegan
• Abstract: The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

The patent addresses the technical problem in FPGAs where phase synchronization between receiver-side and transmitter-side clock signals introduces unwanted latency, which is particularly undesirable in applications like high-frequency trading. The solution involves an external phase controller providing phase matching between a receiver clock and a transmitter clock used in the FPGA, without introducing unnecessary delay by eliminating the need for internal clock domain crossing circuits.

Most Relevant Prior Art for US11575381B1

To determine the most relevant prior art, I will examine the citations listed in the patent document. Since direct access to the full citation list and analysis of each reference is not possible in this format, I will focus on the explicitly mentioned prior art problem within the patent's background and summary.

The patent explicitly identifies a problem with the prior art related to clock synchronization in FPGAs:

• "One technological problem with FPGAs is that there is a need to synchronize receiving side and transmitting side clock signals within the FPGA. The prior art sought to address this problem by including a clock domain crossing circuit in the FPGA, however, these circuits inherently add a delay to the processing that takes place in the FPGA, which is not desirable since high frequency trading may include timestamps that are accurate to the microsecond such that even small delays may present a large problem."

This description indicates that any prior art disclosing the use of clock domain crossing (CDC) circuits within an FPGA for synchronizing receiver and transmitter clocks, which inherently introduce delay, would be highly relevant. The patent aims to overcome this specific limitation.

Without the specific list of "Prior Art References" that were cited by the examiner and applicant, I cannot provide a detailed breakdown of each patent citation. However, based on the patent's own discussion, the type of prior art that is most relevant is clear.

If I were to perform a manual search for prior art, I would look for patents and publications that describe:

1. FPGA systems with high-speed transceivers.
2. Methods and circuits for clock synchronization between different clock domains within an FPGA.
3. The use of Clock Domain Crossing (CDC) circuits (e.g., asynchronous FIFOs, asynchronous gearboxes, mesochronous clock crossing circuits) in FPGAs.
4. Discussion of latency concerns in FPGA-based high-frequency trading or similar low-latency applications due to clock synchronization methods.

The claims of US11575381B1 are directed towards a system and method that avoids the delays associated with internal clock domain crossing circuits by employing an external phase control circuit. Therefore, prior art that teaches internal CDC circuits for clock synchronization in FPGAs would be most relevant for potential anticipation under 35 U.S.C. § 102.

Key Claims potentially anticipated by the described prior art:

The core of the invention lies in avoiding internal CDC circuits for phase alignment by using an external phase control loop. Therefore, any claim that requires an external phase control or excludes an internal CDC for phase alignment would differentiate from the described prior art. Conversely, claims that broadly describe FPGA functionality, deserialization, serialization, or general clock generation/transmission, without the specific external phase control mechanism, might be more susceptible to anticipation by prior art that uses internal CDC for clock synchronization.

For example, independent claim 1 describes a field programmable gate array system including an FPGA and an external phase control circuit where the transmitter and receiver clock signals are phase aligned by the external control, specifically stating the "transmitter side clock signal and the receiver side clock signal are phase aligned so that there is a fixed phase difference between the third phase and the fifth phase." If a prior art document showed a system with all the elements of claim 1, but used an internal clock domain crossing circuit to achieve phase alignment, it would be highly relevant to argue anticipation or obviousness.

Without the ability to perform a live, in-depth search of cited references and their full contents, a specific list of anticipating claims for each prior art reference cannot be confidently generated. However, the conceptual framework provided above outlines how to evaluate such prior art.

The US patent 11575381, titled "Field programmable gate array with external phase-locked loop," addresses a technical problem in Field Programmable Gate Arrays (FPGAs) related to phase matching receiver-side and transmitter-side clock signals without introducing undesirable processing delays. The patent describes a system where an external phase control circuit, comprising a phase detector, a phase controller, and an adjustable oscillator, manages the phase alignment of clocks in an FPGA, thereby avoiding the latency associated with internal Clock Domain Crossing (CDC) circuits.

Based on the information provided within the patent document, the following prior art concepts and components can be identified:

Identified Prior Art References:

1. Conventional Field Programmable Gate Array (FPGA) System with Internal Clock Domain Crossing (CDC) (described in the Background and illustrated in FIG. 1): This prior art describes an FPGA (e.g., FPGA 100) that includes transceiver banks (102), a deserializer (104), a serializer (110), an FPGA Core (106) for computations, and an internal transceiver Phase-Locked Loop (PLL) (108). Crucially, this conventional system incorporates a "clock domain crossing circuit 112" within the FPGA to provide "phase matching or synchronizing" between the receiver and transmitter clocks. The system receives a "REFERENCE CLOCK signal" from an external "Oscillator or Clock Generator 122". The patent explicitly highlights a "significant drawback" of this internal CDC, stating that it "adds latency related to the phase difference between the clocks plus the latency of the synchronizers used, and does not perform any computation, such that it slows the effective processing speed of FPGA 100." This latency is particularly problematic for applications requiring sub-microsecond accuracy, such as high-frequency trading. [cite: FIG. 1, Background section, definitions for 'FPGA 100', 'FPGA Transceiver banks 102', 'deserializer 104', 'serializer 110', 'FPGA Core 106', 'transceiver PLL 108', 'Oscillator or Clock Generator 122', 'clock domain crossing circuit 112', 'One technological problem with FPGAs', 'the prior art', 'a significant drawback of the clock domain crossing circuit 112']
2. General Knowledge of External Phase-Locked Loop (PLL) Components and Concepts: The patent's detailed "Description" and "Definitions" sections enumerate various types of individual components known in the art for clock and phase control, which are standard elements of PLLs. These include:
   • Adjustable Oscillators: Described as "voltage controlled oscillators," "numerically/digitally-controlled oscillators," "digital delay line," and "voltage-controlled delay element." [cite: definitions for 'the adjustable oscillator 2200']
   • Phase Detectors: Described as various circuits such as "XOR gate," "S-R flip-flop," "D flip-flop," "Edge-triggered JK flip-flop," "Gilbert cell multiplier," "Diode ring mixer," and multi-bit "time-to-digital converter (TDC)" variants like "Vernier TDC," "parallel delay line TDC," "counter-based TDC," "interpolator TDC," "tapped delay line TDC," "metastability-based phase detector," "pulse-shrinking TDC," and "scrambling TDC." [cite: definitions for 'the phase detector 2206']
   • Phase Controllers (e.g., Loop Filters): The patent refers to a "controller 2202" that "utilizes a phase-locked loop" and "loop filter" components, describing their orders (first, second, third, fourth) and characteristics (e.g., derivative components). [cite: definitions for 'the controller 2202', 'the loop filter']

Obviousness Analysis under 35 U.S.C. § 103:

A person having ordinary skill in the art (PHOSITA) in FPGA design and high-speed digital systems, particularly those focused on low-latency applications, would have been motivated to combine elements from the identified prior art to arrive at the claimed invention, rendering it obvious.

Combination of Prior Art References:

The claimed invention is rendered obvious by combining Prior Art Reference 1 (Conventional FPGA with internal CDC and its recognized latency problem) with Prior Art Reference 2 (General knowledge of external PLL components and concepts for precise clock synchronization).

Motivation for Combination:

1. Clear Problem Statement and Motivation to Solve: Prior Art Reference 1, as described in the patent's "Background," unequivocally articulates a significant technical problem: the "unwanted latency" introduced by "clock domain crossing circuit 112" for phase synchronization within conventional FPGAs. This latency is deemed "not desirable" and a "large problem" for critical applications like high-frequency trading. [cite: Background section, definitions for 'One technological problem with FPGAs', 'the prior art', 'a significant drawback of the clock domain crossing circuit 112'] This explicit recognition of a severe drawback provides a strong and direct motivation for a PHOSITA to seek alternative solutions for phase alignment that minimize latency.

2. Known Solution Elements for Clock Control: PHOSITAs are thoroughly familiar with phase-locked loops as a standard and effective technique for generating, synchronizing, and aligning clock signals with high precision. Prior Art Reference 2 confirms that the individual building blocks of a PLL—phase detectors, phase controllers (loop filters), and adjustable oscillators—are well-known and readily available components in the field of electronics. The conventional FPGA (Prior Art Reference 1) itself uses an external "Oscillator or Clock Generator 122" to provide a "REFERENCE CLOCK signal," indicating that integrating external clocking and control elements with FPGAs is a known practice. [cite: definitions for 'a REFERENCE CLOCK signal']

3. Predictable Application to Address the Identified Problem: Given the problem of internal CDC latency (Prior Art Reference 1), a PHOSITA would naturally consider how to leverage external, precise clock control mechanisms (Prior Art Reference 2) to bypass or eliminate this latency. The logical steps for a PHOSITA would be:

   • Extract Critical Clock Signals: Recognizing that the internal CDC is intended to synchronize the receiver-side clock (generated by the deserializer) and the transmitter-side clock (used by the serializer), the PHOSITA would consider routing these clock signals outside the FPGA through dedicated pins. This allows for external monitoring and control. The patent's system in FIG. 2, for example, shows a first clock output pin transmitting the receiver-side clock and a second clock output pin transmitting the transmitter-side clock to an external phase detector. [cite: Summary section, FIG. 2, definitions for 'the second plurality of pins', 'first clock output pin', 'second clock output pin']
   • Implement an External Phase Control Loop: With the critical clock signals available externally, the PHOSITA would then design an external feedback loop using known PLL components (phase detector, phase controller, adjustable oscillator from Prior Art Reference 2). This external loop would compare the phases of the receiver and transmitter clocks, determine any difference, and generate adjustment information.
   • Control the FPGA's Clock Input: The adjustment information from the external phase controller would then be used to modify the clock signal provided by the external adjustable oscillator, which, in turn, feeds back into the FPGA to control the serializer's clock. This forms a closed-loop system that actively aligns the receiver and transmitter clocks. The patent describes the adjustable oscillator (2200) generating the second clock signal based on adjustment information from the phase controller (2202), and transmitting it to the second reference clock pin of the FPGA's first interface. [cite: Summary section, FIG. 2, definitions for 'a phase control circuit', 'adjustable oscillator 2200', 'phase controller 2202']
   • Eliminate the Internal Latency Source: By successfully implementing an external phase alignment mechanism, the internal CDC circuit (112) becomes redundant for its primary function of phase synchronization and can be removed or bypassed, directly achieving the desired reduction in processing latency. The patent's claims emphasize that "the first set of operations does not include clock domain crossing operations that delays processing of the first set of parallel data streams." [cite: Summary section, definitions for 'the first set of operations does not include clock domain crossing operations']

Therefore, the combination of a conventional FPGA system, where the latency of internal CDC circuits is a recognized problem, with the widely known and readily implementable principles and components of external phase-locked loops for precise clock control, would be obvious to a PHOSITA seeking to overcome the explicitly stated deficiencies of the prior art. The resulting system, as claimed, is a predictable application of known engineering principles to achieve a desired and clearly articulated improvement (reduced latency).