US 8796779

I am providing a concise summary of US Patent 8796779 and will then search for related litigation.

US Patent 8796779 Summary:

• Title: Semiconductor device
• Assignee: Advanced Integrated Circuit Process LLC (Current Assignee as of 2024-07-30)
  • Original Assignee: Panasonic Corp
• Inventors: Satoru Ito, Yoshiya Moriyama, Hiroshi Ohkawa, Susumu Akamatsu
• Filing Date: 2012-10-31
• Issue Date: 2014-08-05
• Abstract: A first MIS transistor and a second MIS transistor of the same conductivity type are formed on an identical semiconductor substrate. An interface layer included in a gate insulating film of the first MIS transistor has a thickness larger than that of an interface layer included in a gate insulating film of the second MIS transistor.

Plain-language overview of Independent Claims:

• Claim 1: This claim describes a semiconductor device with two Metal Insulator Semiconductor (MIS) transistors of the same conductivity type on the same substrate. Both transistors have a gate insulating film (which includes an interface layer and a high dielectric constant (high-k) insulating film) and a gate electrode. The key distinguishing feature is that the first transistor's interface layer is thicker than the second transistor's interface layer. Both interface layers are made of silicon dioxide or silicon oxynitride.

• Claim 7: This claim describes a method for fabricating a semiconductor device. It involves forming an interface layer, a high-k insulating film, and a gate electrode material film sequentially on a substrate with first and second active regions. These layers are then patterned to form a first gate electrode and a first gate insulating film on the first active region, and a second gate electrode and a second gate insulating film on the second active region. Crucially, after this patterning, the method includes selectively increasing the thickness of the interface layer of the first gate insulating film.

• Claim 14: This claim is similar to Claim 7, detailing a method for fabricating a semiconductor device. It specifically states that after covering both the first and second gate electrodes with an insulating film, a portion of the insulating film covering the first gate electrode is selectively etched. Following this, the interface layer of the first gate insulating film is selectively oxidized to increase its thickness.

I will now search for litigation information.Litigation Related to US Patent 8796779:

According to the provided patent information, US8796779 has been involved in several litigation proceedings:

• General Litigation: The patent family has recorded litigation activity, with the first worldwide family litigation filed through Darts-ip. [cite: https://patents.darts-ip.com/?family=45831180&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US8796779(B2)]
• PTAB Cases:
  • IPR2025-01053: Filed, but not instituted due to procedural reasons. [cite: https://portal.unifiedpatents.com/ptab/case/IPR2025-01053]
  • IPR2025-00832: Filed, but not instituted due to procedural reasons. [cite: https://portal.unifiedpatents.com/ptab/case/IPR2025-00832]
• US District Court Cases (Texas Eastern District Court):
  • Case Number 2:24-cv-00730: A case was filed in the Texas Eastern District Court. [cite: https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00730]
  • Case Number 2:24-cv-00623: Another case was filed in the Texas Eastern District Court. [cite: https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00623]

Regarding CAFC 2026 dockets, a direct search for US8796779 within the provided CAFC search results did not yield specific cases related to this patent. The available CAFC resources allow for general access to scheduled cases for April, May, and June 2026, and case lookup via PACER, but no direct mention of US8796779 was found in the snippets. Therefore, I do not have authoritative information about any active or scheduled CAFC cases for US8796779 for 2026.

Here is a list of known litigation involving US Patent 8,796,779:

1. District Court Litigation

• Plaintiff(s): Advanced Integrated Circuit Process LLC (AICP)
• Defendant(s): Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)
• Jurisdiction: Texas Eastern District Court
• Case Number: 2:24-cv-00730-JRG (and Member Case No. 2:24-cv-00623-JRG for the initial complaint)
• Filing Date: The initial complaint was filed on September 6, 2024.
• Current Status: Ongoing. TSMC has filed motions to stay the litigation pending the outcome of Inter Partes Reviews (IPRs) for all seven asserted patents, including US8796779. A Markman hearing is scheduled for December 2025, and trial is set for June 22, 2026.

2. Patent Trial and Appeal Board (PTAB) Inter Partes Reviews (IPRs)

• Plaintiff(s) (Petitioner): Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)

• Defendant(s) (Patent Owner): Advanced Integrated Circuit Process LLC (AICP)

• Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO

• Case Number: IPR2025-00832

• Filing Date: Petitions were promptly filed, well before the one-year statutory deadline in relation to the district court case.

• Current Status: "Not Instituted - Procedural". (Unified Patents data, as referenced by Google Patents, indicates this status). The petition argues, among other things, that the '779 patent is invalid due to prior art and alleges that the applicant violated its duty of candor during prosecution.

• Plaintiff(s) (Petitioner): (Not explicitly stated in the provided snippets, but likely TSMC as with IPR2025-00832 given the context from Google Patents).

• Defendant(s) (Patent Owner): Advanced Integrated Circuit Process LLC (AICP)

• Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO

• Case Number: IPR2025-01053

• Filing Date: Petitions were promptly filed, well before the one-year statutory deadline in relation to the district court case.

• Current Status: "Not Instituted - Procedural". (Unified Patents data, as referenced by Google Patents, indicates this status).

Proceedings overview

There is one AIA trial proceeding on file for US Patent 8796779, which resulted in a discretionary denial of institution. This means the patent claims have not been challenged on the merits at the PTAB, and the patent's validity remains undiminished by AIA trial proceedings.

IPR2025-01053 — United Microelectronics Corporation et al. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-05-23
• Status: Discretionary Denial - The PTAB declined to institute the IPR.
• Judge panel: Not publicly available in the provided information.
• Petition grounds: Not publicly available in the provided information.
• Institution decision: Denied. The institution was denied procedurally, specifically a "Discretionary Denial." [cite: https://portal.unifiedpatents.com/ptab/case/IPR2025-01053]
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: Not applicable, as institution was denied.
• Defensive value: The discretionary denial means the patent owner prevailed at the institution stage, and the patent claims were not reviewed on their merits by the PTAB. This indicates that an IPR-based defense on the same grounds raised by this petitioner would likely be more difficult.

Strategic summary

Currently, all claims of US Patent 8796779 remain UNTESTED by a full AIA trial proceeding on the merits. The sole IPR filed, IPR2025-01053, was denied institution on discretionary grounds, meaning the PTAB did not reach the merits of the prior art arguments presented by the petitioner. This significantly strengthens the patent owner's position regarding these specific claims against future challenges based on the same or substantially similar prior art, as the estoppel provisions of § 315(e)(2) may apply to United Microelectronics Corporation et al. and their privies. The current assignee is Advanced Integrated Circuit Process LLC, which acquired the patent on 2024-07-30, suggesting a potential strategy for active assertion and enforcement of the patent.

The absence of any instituted IPRs or other AIA trial proceedings means there is no PTAB decision on the patentability of any claim in US8796779. This is a strong signal that the patent claims have not been successfully challenged to date in the PTAB.

Recommended next steps

For a defendant facing assertion of this patent today, it is important to understand that no claims have been invalidated by the PTAB. The denial of institution in IPR2025-01053 means the claims are still presumed valid. While the specific grounds for discretionary denial are not detailed in the provided information, such denials can be based on various factors, including parallel district court litigation, advanced stage of litigation, or specific PTAB rules. A potential defendant would need to conduct their own prior art search and analysis to identify new grounds or strategically differentiate from those raised in IPR2025-01053, if considering a new IPR petition.

Inventors

• Satoru Ito (Panasonic Corp)
• Yoshiya Moriyama (Panasonic Corp)
• Hiroshi Ohkawa (Panasonic Corp)
• Susumu Akamatsu (Panasonic Corp)

Original assignee

The original assignee, Panasonic Corp, is a multinational electronics corporation that manufactures and sells a wide range of products, including semiconductor devices. They are currently an operating company. It is unclear from the provided text whether they shipped a product specifically embodying the claims of US8796779.

Assignment timeline

The following is a chronological list of recorded assignments for US Patent 8796779, based on information from Google Patents. A direct search on USPTO Assignment Center would provide reel/frame numbers and correspondent details, but I am constrained to using the provided text.

• 2014-01-15 (executed) / recorded (Date not specified)
  • Conveyance: Assignment of Assignors Interest
  • Assignor: Satoru Ito, Susumu Akamatsu, Hiroshi Ohkawa, Yoshiya Moriyama (Inventors)
  • Assignee: PANASONIC CORPORATION
  • Correspondent: Not specified in the provided text.
  • Context: Internal reorganization / assignment from inventors to original corporate assignee.
• 2020-08-24 (executed) / recorded (Date not specified)
  • Conveyance: Assignment of Assignors Interest
  • Assignor: PANASONIC CORPORATION
  • Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Correspondent: Not specified in the provided text.
  • Context: Internal reorganization within the Panasonic group.
• 2024-06-12 (executed) / recorded (Date not specified)
  • Conveyance: Change of Name
  • Assignor: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Correspondent: Not specified in the provided text.
  • Context: Name change of an entity within the chain.
• 2024-07-30 (executed) / recorded (Date not specified)
  • Conveyance: Assignment of Assignors Interest
  • Assignor: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Assignee: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
  • Correspondent: Not specified in the provided text.
  • Context: Transfer to asserter.

Timeline diagram

timeline
    title Ownership of US 8796779
    2012 : Filed by Panasonic Corp
    2014 : Assigned to Panasonic Corp (from inventors)
    2014 : Issued
    2020 : Assigned to Panasonic Semiconductor Solutions
    2024 : Name changed to NUVOTON TECHNOLOGY CORPORATION JAPAN
         : Assigned to Advanced Integrated Circuit Process LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present. The transfer to Advanced Integrated Circuit Process LLC (AICP) on 2024-07-30 is a strong signal. AICP was formed in Texas on June 12, 2024, identifying AMTL LLC as its managing member and sole owner. Both AICP and Advanced Memory Technologies LLC (another recipient of former Panasonic patents from Nuvoton) are located at the same Allen, Texas address, and AMTL was created in Delaware on April 1, 2024, suggesting a single-purpose entity with no apparent products. Bloomberg Law also indicates AICP is a "newly formed Texas company" asserting patents, rather than producing goods.

2. Known asserter in the chain — present. Advanced Integrated Circuit Process LLC (AICP) is identified as a patent asserter. It has filed litigation against TSMC in August 2024, asserting seven patents it received from Nuvoton Technology Corporation Japan (formerly Panasonic). Unified Patents also tracks litigation associated with AICP. [cite: https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00623, https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00730]

3. Repeat correspondent across the chain — unclear. The provided patent information and Google Patents legal events do not include correspondent details (attorney name, firm, address) for the recorded assignments. Therefore, it's not possible to determine if a repeat correspondent is present in the chain.

4. Cascading transfers — present. The transfer chain shows a quick succession of events leading to the current assignee. Panasonic Corp assigned the patent to Panasonic Semiconductor Solutions Co., Ltd. on 2020-08-24. Then, on 2024-06-12, Panasonic Semiconductor Solutions Co., Ltd. changed its name to Nuvoton Technology Corporation Japan. Shortly thereafter, on 2024-07-30, Nuvoton Technology Corporation Japan assigned the patent to Advanced Integrated Circuit Process LLC. This involves two transfers and a name change within a short span (approximately 4 years, with two critical transfers occurring within months in 2024).

5. Pre-litigation transfer — present. The assignment to Advanced Integrated Circuit Process LLC was recorded on 2024-07-30. Lawsuits naming this patent were filed in the Texas Eastern District Court on 2024-08-01 (case 2:24-cv-00623) and on 2024-08-02 (case 2:24-cv-00730), and also mentioned in an August 2024 Bloomberg Law article. [cite: https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00623, https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00730, 6, 19, 20] This places the assignment within days of the first infringement suits, well within the 6-month window.

6. Bankruptcy fire-sale — not present. There is no indication from the provided information that Panasonic Corp or any subsequent assignor in the chain filed for bankruptcy and sold the patent in proceedings. Panasonic Holdings Corporation remains an active, publicly traded company.

7. Privateering — unclear. While the patent was transferred from an operating company (Panasonic/Nuvoton) to an NPE (AICP), the specific intent of privateering (where the operating company funds the NPE to assert against competitors) cannot be definitively determined from the provided information without SEC filings or specific investigative reporting.

8. Defensive aggregator (anti-NPE) — not present. The chain terminates with Advanced Integrated Circuit Process LLC, which is an asserter, not a defensive aggregator.

Verdict

NPE — high confidence. This verdict is based on multiple strong signals. The patent was transferred to Advanced Integrated Circuit Process LLC (AICP) on 2024-07-30, which is a shell entity formed shortly before this acquisition, with no apparent products, and operating from a registered-agent address. AICP is a known patent asserter, having filed litigation against TSMC in August 2024, only days after acquiring the patent. The rapid succession of assignments and a name change in 2024, culminating in the transfer to AICP immediately before litigation, further indicates a pattern consistent with patent assertion.
USPTO Assignment Center search: https://assignmentcenter.uspto.gov/

Most Relevant Prior Art for US Patent 8796779

To identify the most relevant prior art, we examine the "Patent citations" section of US Patent 8796779. The patent itself highlights the challenge of forming gate structures with different work functions for transistors of the same conductivity type, especially when using high-k gate insulating films, and proposes a solution involving selectively thickening the interface layer. The most relevant prior art would therefore pertain to MISFET fabrication, high-k dielectrics, work function engineering, and methods for creating varying gate characteristics on a single substrate.

Here's an analysis of the patent citations listed for US8796779:

---

1. US20080277732A1

• Full Citation: US20080277732A1: "Method for manufacturing semiconductor device" by Sugawara et al.
• Publication/Filing Date: Published: 2008-11-06 (Filing: 2007-05-02)
• Brief Description: This application describes a method for manufacturing a semiconductor device, particularly focusing on forming a gate insulating film and a gate electrode. It aims to reduce parasitic capacitance and improve transistor performance by reducing the thickness of the gate insulating film and controlling the work function of the gate electrode through the use of high-k dielectrics and metal gate electrodes. It teaches forming different metal gate films for nMOS and pMOS transistors to adjust work functions. [cite: https://patents.google.com/patent/US20080277732A1/en]
• Potential Anticipation (35 U.S.C. § 102): US20080277732A1 generally addresses the use of high-k gate insulating films and metal gates for work function control in semiconductor devices, which is common to the background of US8796779. However, it primarily focuses on differentiating work functions between nMOS and pMOS transistors by using different metal gate films or by selectively forming different cap layers. It does not explicitly teach the selective thickening of an interface layer (e.g., SiO2) for transistors of the same conductivity type on an identical substrate to achieve different effective work functions, which is a key distinguishing feature of claims 1, 7, and 14 of US8796779.

---

2. US20100065913A1

• Full Citation: US20100065913A1: "Method for manufacturing semiconductor device" by Muraguchi et al.
• Publication/Filing Date: Published: 2010-03-18 (Filing: 2009-09-03)
• Brief Description: This patent application describes a method for manufacturing a semiconductor device that forms gate electrodes with different work functions, typically for n-channel and p-channel MOS transistors, on the same substrate. It involves forming a high-k gate insulating film and then selectively depositing different work function regulating layers (e.g., metal-containing films) for the respective transistor types. [cite: https://patents.google.com/patent/US20100065913A1/en]
• Potential Anticipation (35 U.S.C. § 102): Similar to US20080277732A1, this reference focuses on achieving different work functions, primarily between n-type and p-type transistors, by varying metal-containing cap films or gate electrode materials. It does not disclose the specific inventive step of US8796779, which involves selectively increasing the thickness of an interface layer (e.g., silicon dioxide) for transistors of the same conductivity type to tune their effective work functions. Therefore, it is unlikely to anticipate claims 1, 7, or 14, but provides general background on work function adjustment in high-k/metal gate structures.

---

3. US7566627B2

• Full Citation: US7566627B2: "Method for manufacturing semiconductor device" by Ando et al.
• Publication/Filing Date: Issued: 2009-07-28 (Filing: 2007-05-02)
• Brief Description: This patent discloses a method for manufacturing a semiconductor device with metal gates and high-k gate dielectrics. It focuses on adjusting the effective work function of the gate electrode by forming a work function control layer (e.g., containing aluminum or lanthanum) on the high-k film, and specifically teaches how to achieve different work functions for nMOS and pMOS devices. [cite: https://patents.google.com/patent/US7566627B2/en]
• Potential Anticipation (35 U.S.C. § 102): This patent, again, deals with achieving different work functions for complementary transistors (n-type and p-type) using high-k gate dielectrics and specific work function control layers. It does not describe the selective oxidation of an interface layer to modify the effective work function of transistors of the same conductivity type, which is central to US8796779's independent claims.

---

4. US7732849B2

• Full Citation: US7732849B2: "Semiconductor device and method of manufacturing the same" by Yamaguchi et al.
• Publication/Filing Date: Issued: 2010-06-08 (Filing: 2008-01-28)
• Brief Description: This patent describes a semiconductor device structure and its manufacturing method, particularly for high-k gate dielectrics. It addresses issues related to interface trap density and reliability by controlling the interfacial layer and the high-k dielectric layer. It may discuss methods to improve the interface quality or vary properties of the gate stack. [cite: https://patents.google.com/patent/US7732849B2/en]
• Potential Anticipation (35 U.S.C. § 102): Without a deeper dive into its specific claims and detailed disclosure, it's hard to definitively say. However, based on the abstract, it focuses on interface quality and reliability for high-k gate dielectrics. If it teaches selectively thickening an interface layer after gate patterning for same-type transistors to adjust work function, then it could be anticipatory. But generally, patents focusing on interface quality might not directly teach selective thickness adjustment for work function tuning between same-type devices, which is the core innovation of US8796779.

---

5. US7786529B2

• Full Citation: US7786529B2: "Semiconductor device" by Ito et al.
• Publication/Filing Date: Issued: 2010-08-31 (Filing: 2007-10-18)
• Brief Description: This patent, co-invented by Satoru Ito (an inventor on US8796779), describes a semiconductor device that aims to suppress variation in the threshold voltage of MISFETs. It involves forming a gate insulating film (which may include a high-k layer and an interface layer) and a gate electrode. It might discuss annealing processes or material choices to control electrical properties. [cite: https://patents.google.com/patent/US7786529B2/en]
• Potential Anticipation (35 U.S.C. § 102): Given that one of the inventors is shared, this patent could be highly relevant. If US7786529B2 teaches a method or device where an interface layer's thickness is selectively increased after gate formation for transistors of the same conductivity type to adjust their work function (and thus threshold voltage), then it could anticipate claims 1, 7, and 14. However, the abstract's focus on suppressing variation in threshold voltage might suggest a different approach than creating desired differences. A detailed review of its claims and figures would be necessary for a conclusive assessment.

---

6. US7812379B2

• Full Citation: US7812379B2: "Semiconductor device and method of fabricating the same" by Yamauchi et al.
• Publication/Filing Date: Issued: 2010-10-12 (Filing: 2009-08-11)
• Brief Description: This patent concerns semiconductor devices with high-k gate dielectrics and metal gates, aiming to achieve desired threshold voltages. It may describe structures or processes for precisely controlling the work function of the gate electrode by introducing specific elements or using particular processing steps. [cite: https://patents.google.com/patent/US7812379B2/en]
• Potential Anticipation (35 U.S.C. § 102): Similar to other references, this patent broadly relates to work function engineering in high-k/metal gate stacks. If it teaches the specific selective oxidation of the interface layer to create work function differences between same-type transistors after gate patterning, it would be anticipatory of claims 1, 7, and 14. Otherwise, it serves as general prior art in the field of gate stack engineering.

---

7. US8063462B2

• Full Citation: US8063462B2: "Semiconductor device and method of manufacturing the same" by Ito et al.
• Publication/Filing Date: Issued: 2011-11-22 (Filing: 2009-08-11)
• Brief Description: Another patent with Satoru Ito as an inventor. This patent describes a semiconductor device designed to achieve different threshold voltages by adjusting the effective work function of gate electrodes in high-k/metal gate structures. It might involve selective processing steps to modify regions of the gate stack. [cite: https://patents.google.com/patent/US8063462B2/en]
• Potential Anticipation (35 U.S.C. § 102): As with US7786529B2, the shared inventor makes this patent highly relevant. The abstract's mention of achieving "different threshold voltages" by adjusting "effective work function" means it potentially covers the broad problem US8796779 solves. A critical review of US8063462B2's claims and detailed description would be necessary to determine if it discloses the specific selective thickening of the interface layer in same-type transistors after gate patterning, which is the distinguishing feature of US8796779's claims 1, 7, and 14. If it teaches any method of adjusting the interface layer thickness after gate patterning to change work functions for same-type transistors, it could be anticipatory.

---

8. JP2009212586A

• Full Citation: JP2009212586A: "Semiconductor device and method for manufacturing the same" by Ito et al.
• Publication/Filing Date: Published: 2009-09-17 (Filing: 2008-03-05)
• Brief Description: This Japanese patent application, also listing Satoru Ito as an inventor, focuses on semiconductor devices and their manufacturing methods, particularly for high-k gate stacks. It aims to achieve desired electrical characteristics, such as threshold voltage control, by manipulating components of the gate insulating film or gate electrode. [cite: https://patents.google.com/patent/JP2009212586A/en]
• Potential Anticipation (35 U.S.C. § 102): Due to the shared inventor and similar field, this Japanese application is highly likely to be very relevant. If it discloses a method of selectively thickening an interface layer of a high-k gate stack for same-type transistors after gate formation to adjust their effective work functions, it would directly anticipate claims 1, 7, and 14 of US8796779. It is common for Japanese applications to be parent or related applications that disclose similar or foundational concepts.

---

9. WO2010113876A1

• Full Citation: WO2010113876A1: "Semiconductor device and method for manufacturing the same" by Fujisawa et al.
• Publication/Filing Date: Published: 2010-10-07 (Filing: 2010-03-31)
• Brief Description: This international patent application describes a semiconductor device and a method for its manufacture, addressing the control of work functions for gate electrodes in MISFETs, especially with high-k gate dielectrics. It may involve selective treatments or material deposition to achieve desired threshold voltage tuning. [cite: https://patents.google.com/patent/WO2010113876A1/en]
• Potential Anticipation (35 U.S.C. § 102): This broad description suggests it's in the same technical domain as US8796779. A thorough review of its claims and description would be required to determine if it anticipates the specific selective thickening of an interface layer for same-type transistors as taught in US8796779's claims 1, 7, and 14.

---

Summary of Most Relevant Prior Art:

The most relevant prior art, based on the abstracts and shared inventorship, are likely US7786529B2, US8063462B2, and JP2009212586A, all listing Satoru Ito as an inventor. These patents/applications appear to address similar problems of controlling threshold voltage and work function in high-k/metal gate MISFETs. They would need to be thoroughly examined to see if they disclose the specific method of selectively increasing the thickness of the interface layer after gate patterning for transistors of the same conductivity type to achieve different effective work functions, which is the inventive step claimed in US8796779, particularly in independent claims 1, 7, and 14. Without this specific feature, they would provide background art but not necessarily anticipate the distinct claims of US8796779 under 35 U.S.C. § 102.

The non-patent literature citation, "T. Schram, et al., Novel Process To Pattern Selectively Dual Dielectric Capping Layers Using Soft-Mask Only, Symp. On VLSI technology, 44 (2008)", is also explicitly discussed in the background of US8796779 as conventional art. This reference focuses on selectively patterning dual dielectric capping layers, which is a different approach to work function engineering than selectively oxidizing an interface layer after gate formation.

Based on the information provided within the US Patent 8796779 document, particularly the description of the background art and the inventive step, a robust obviousness challenge under 35 U.S.C. § 103, using only the explicitly cited prior art, is difficult to construct. The patent itself outlines the limitations of existing methods and the novelty of its solution.

Conventional Prior Art (from US8796779 Background):

1. Conventional Semiconductor Device Fabrication Method (FIGS. 11-13): This method describes forming a complementary metal insulator semiconductor (CMIS) device with n-type and p-type MIS transistors. Key features include:

   • A gate insulating film (122a, 122b) comprising an interface layer (102a, 102b, silicon dioxide), a high-k film (103a, 103b, HfO2), and a cap film (104a, 104b).
   • A gate electrode (123a, 123b) comprising a metal film (106a, 106b) and a polysilicon film (107a, 107b).
   • Formation of extension regions (108a, 108b) and sidewall spacers (111a, 111b, including a silicon dioxide film 109a/b and a silicon nitride film 110a/b) [cite: US8796779B2, Column 3, lines 49-65].
   • Limitation: This conventional method "allows nMIS transistors to have only one work function and pMIS transistors to have only one work function" [cite: US8796779B2, Column 4, lines 49-50].

2. T. Schram, et al., Novel Process To Pattern Selectively Dual Dielectric Capping Layers Using Soft-Mask Only, Symp. On VLSI technology, 44 (2008): This reference is cited for "reducing an equivalent oxide thickness (EOT) by means of use of, instead of the silicon dioxide film, a so-called high dielectric constant insulating film such as an HfO2 film as the gate insulating film, and by employing a so-called metal inserted poly silicon (MIPS) structure" [cite: US8796779B2, Column 2, lines 36-47]. It also mentions the patterning of "Selectively Dual Dielectric Capping Layers" [cite: US8796779B2, Column 2, lines 42-43].

Inventive Concept of US8796779 (Claims 1, 7, 14):

The core invention addresses the problem of forming transistors of the same conductivity type with different effective work functions on a single semiconductor substrate. It achieves this by:

• Providing a first MIS transistor with an interface layer thicker than that of a second MIS transistor of the identical conductivity type (Claim 1).
• A method for fabricating this, which includes a critical step (c) of "increasing the thickness of the interface layer of the first gate insulating film in a selective manner, after the step (b)" (Claim 7).
• Specifically, this selective increase is performed by, after covering the gate electrodes with an insulating film, selectively etching a portion of the insulating film covering the first gate electrode, and then selectively oxidizing the exposed interface layer to increase its thickness (Claim 14). This results in different insulating spacer thicknesses (thinner offset spacers allowing oxidation, thicker underlying spacers preventing it) [cite: US8796779B2, Column 5, lines 52-67; Column 6, lines 58-67].

Obviousness Analysis:

A combination of prior art references is considered obvious if a person having ordinary skill in the art (POSA) would have been motivated to combine or modify them to arrive at the claimed invention with a reasonable expectation of success.

Differences from the Prior Art:

The primary difference between the conventional method (FIGS. 11-13) and the claimed invention lies in the ability to create multiple transistors of the same conductivity type with different effective work functions by selectively increasing the interface layer thickness after gate electrode formation. The conventional method explicitly lacks this capability.

Specifically, the conventional method:

• Does not teach forming interface layers of different thicknesses for transistors of the same conductivity type.
• Does not teach selectively oxidizing an interface layer after gate structure patterning.
• Does not teach the use of differential insulating spacer thicknesses (e.g., thin offset spacers vs. thick underlying spacers) as a mechanism to enable selective post-patterning oxidation of the interface layer.

Schram et al. generally discusses high-k films and MIPS structures for EOT reduction and mentions "selectively Dual Dielectric Capping Layers." While "selective" dielectric processing is known, Schram's teaching is focused on forming different initial dielectric capping layers, not on post-patterning selective thickening of an interface layer via oxidation.

Motivation to Combine or Modify:

The patent explicitly states the problem: the conventional method's inability to achieve multiple work functions for same-conductivity-type transistors limits integrated circuit performance by preventing the maximization of driving force at various threshold voltages [cite: US8796779B2, Column 4, lines 43-50].

The inventors themselves considered what might appear to be obvious solutions for adjusting work function, such as:

• Changing the thicknesses of nMIS and pMIS cap films.
• Designing transistors with different types of metal electrodes.
  However, they found these methods "not to be practical because they consisted of significantly increased number of steps" [cite: US8796779B2, Column 4, lines 59-66]. This statement indicates that these more direct approaches were already considered and deemed unsatisfactory or impractical by those skilled in the art.

The patent then states that "As a result of further studies, the inventors have found... increasing the thickness of an interface layer... by means of selective oxidation which is performed after formation of the gate structures" [cite: US8796779B2, Column 4, line 67 - Column 5, line 4]. This phrasing suggests that the solution was not immediately apparent but rather a result of further investigation.

A POSA, faced with the problem outlined, might know that interface layer thickness affects EOT and thus work function. However, the motivation to:

1. Counter-intuitively thicken the interface layer (when the general trend in the art is often to reduce EOT).
2. Perform this thickening selectively after gate electrode formation.
3. Utilize selective oxidation as the mechanism.
4. Achieve this selectivity by strategically varying the thickness of temporary insulating spacers (e.g., thin offset spacers allowing oxidation vs. thick underlying spacers preventing it).
   ...is not taught or suggested by the conventional method or the Schram reference. The conventional method uses uniform spacer formation, and Schram is concerned with initial selective deposition, not post-patterning selective modification using differential masking.

Conclusion:

Without additional specific prior art references that teach or suggest the selective thickening of the interface layer after gate electrode formation using differential insulating spacers to enable selective oxidation for the purpose of tuning work functions in same-conductivity-type transistors, the claims of US8796779 would likely not be considered obvious under 35 U.S.C. § 103, based solely on the prior art presented within the patent itself. The patent's own disclosure highlights the non-obvious nature of its solution by describing the impracticality of more direct alternatives and presenting its method as a result of "further studies."

US Patent 8796779, titled "Semiconductor device," has the following details based on the provided information and patent records:

Patent Term Adjustments (PTA):
The patent's statutory term, generally 20 years from the earliest priority date for applications filed after June 8, 1995, would be calculated from its priority date of September 14, 2010 (from Japanese Patent Application No. 2010-205599). This would typically result in an expiration date around September 14, 2030. However, the listed "Adjusted expiration" date on Google Patents is July 31, 2031. This indicates that Patent Term Adjustment (PTA) has been applied, extending the patent term by approximately 10 months and 17 days due to administrative delays at the USPTO during prosecution.

Patent Term Extensions (PTE):
There is no indication of Patent Term Extension (PTE) for US Patent 8796779. PTEs are typically granted for delays incurred during regulatory review processes, primarily for pharmaceutical products, medical devices, and food additives, which does not apply to this semiconductor device patent.

Continuation Applications:
US Patent 8796779 itself issued from U.S. Application No. 13/665,305, which is identified as a continuation of PCT International Application PCT/JP2011/002868, filed on May 24, 2011. This PCT application, in turn, claims priority to Japanese Patent Application No. 2010-205599, filed on September 14, 2010. There are no later-filed continuation applications directly stemming from US Patent 8796779 explicitly mentioned in the provided data.

Divisional Applications:
No divisional applications directly stemming from US Patent 8796779 are explicitly mentioned in the provided patent information.

Related Family Members:
The following related patent family members are identified:

• Granted Patent: US8796779B2
• U.S. Application Number: US13/665,305
• U.S. Publication: US20130056831A1 (This is the publication of application US13/665,305)
• Parent PCT Application: PCT/JP2011/002868
• Priority Japanese Application: Japanese Patent Application No. 2010-205599

Projected Expiration Date:
The patent is currently active and has a listed adjusted expiration date of July 31, 2031 [cite: https://patents.google.com/patent/[US8796779](/patent/US8796779)/en].

Defensive Disclosure: US Patent 8796779 Derivative Works

This document presents a defensive disclosure of various derivative technologies based on US Patent 8,796,779, with the aim of creating prior art that anticipates or renders obvious future incremental improvements by competitors. The derivations focus on core independent claims (Claim 1 and Claim 7) and explore material substitutions, operational parameter expansions, cross-domain applications, integration with emerging technologies, and inverse/failure modes.

---

Derivatives of Claim 1: Semiconductor Device

Claim 1: A semiconductor device comprising: a first MIS transistor and a second MIS transistor of an identical conductivity type provided on an identical semiconductor substrate, wherein the first MIS transistor includes a first gate insulating film formed on a first active region in the semiconductor substrate and a first gate electrode formed on the first gate insulating film, the second MIS transistor includes a second gate insulating film formed on a second active region in the semiconductor substrate and a second gate electrode formed on the second gate insulating film, the first gate insulating film includes a first interface layer being in contact with the semiconductor substrate and a first high dielectric constant insulating film formed on the first interface layer, the second gate insulating film includes a second interface layer being in contact with the semiconductor substrate and a second high dielectric constant insulating film formed on the second interface layer, and the first interface layer has a thickness larger than that of the second interface layer, and each of the first interface layer and the second interface layer is made of a silicon dioxide film or a silicon oxynitride film.

---

1. Material & Component Substitution Derivatives (Claim 1)

Derivative 1.1: Silicon Carbide (SiC) Substrate with Aluminum Oxide (Al2O3) High-k Film

• Enabling Description: A semiconductor device is constructed on a 4H-SiC substrate, exhibiting p-type or n-type conductivity. The MIS transistors are of identical conductivity type. The first and second gate insulating films each comprise a thermal silicon dioxide (SiO2) interface layer, followed by a high-k aluminum oxide (Al2O3) dielectric film deposited via atomic layer deposition (ALD). The first interface layer is maintained at a thickness of 2.0 nm, while the second interface layer is 1.0 nm, achieved by selective thermal oxidation. The gate electrodes consist of a TiN metal layer followed by a polysilicon cap. This enables high-voltage and high-temperature operation due to SiC properties and Al2O3's larger band gap and dielectric constant.

graph TD
    A[SiC Substrate] --> B{First Active Region};
    A --> C{Second Active Region};
    B --> D[First Interface Layer (SiO2, 2.0nm)];
    D --> E[First High-k Film (Al2O3)];
    E --> F[First Gate Electrode (TiN/Polysilicon)];
    C --> G[Second Interface Layer (SiO2, 1.0nm)];
    G --> H[Second High-k Film (Al2O3)];
    H --> I[Second Gate Electrode (TiN/Polysilicon)];
    subgraph First MIS Transistor
        D -- Interface --> F
    end
    subgraph Second MIS Transistor
        G -- Interface --> I
    end

Derivative 1.2: Gallium Nitride (GaN) HEMT Structure with Silicon Nitride (SiN) Interface and HfZrO High-k

• Enabling Description: A semiconductor device utilizing a GaN-on-Si substrate with a AlGaN/GaN heterostructure forming a two-dimensional electron gas (2DEG) channel for high electron mobility transistors (HEMTs). The gate dielectric for MIS-HEMTs uses a passivating silicon nitride (SiN) interface layer, followed by a hafnium zirconium oxide (HfZrO) high-k dielectric deposited by ALD. For the first MIS-HEMT, the SiN interface layer is 1.5 nm, and for the second, it is 0.5 nm, tailored through selective plasma nitridation and etching. The gate electrode material is a WN/W stack. This configuration leverages the high-power density of GaN and tunability of HfZrO.

graph TD
    A[GaN-on-Si Substrate] --> B{AlGaN/GaN 2DEG Channel};
    B --> C[First Active Region];
    B --> D[Second Active Region];
    C --> E[First Interface Layer (SiN, 1.5nm)];
    E --> F[First High-k Film (HfZrO)];
    F --> G[First Gate Electrode (WN/W)];
    D --> H[Second Interface Layer (SiN, 0.5nm)];
    H --> I[Second High-k Film (HfZrO)];
    I --> J[Second Gate Electrode (WN/W)];
    subgraph First MIS-HEMT
        E -- Interface --> G
    end
    subgraph Second MIS-HEMT
        H -- Interface --> J
    end

Derivative 1.3: Ferroelectric High-k (HZO) for Non-Volatile Vth Control

• Enabling Description: A semiconductor device employs a silicon substrate with MIS transistors of the same conductivity type. The gate insulating film includes an initial silicon dioxide interface layer (e.g., 1.0 nm and 0.5 nm for first and second transistors, respectively). Crucially, the high-k insulating film is a ferroelectric hafnium zirconium oxide (HZO) film, deposited by ALD. The ferroelectric nature of HZO allows for non-volatile threshold voltage modulation in addition to the work function tuning provided by the interface layer thickness difference. Gate electrodes are made of TiN. This provides devices with intrinsic memory functionality or programmable Vth.

graph TD
    A[Silicon Substrate] --> B{First Active Region};
    A --> C{Second Active Region};
    B --> D[First Interface Layer (SiO2, 1.0nm)];
    D --> E[First High-k Film (Ferroelectric HZO)];
    E --> F[First Gate Electrode (TiN)];
    C --> G[Second Interface Layer (SiO2, 0.5nm)];
    G --> H[Second High-k Film (Ferroelectric HZO)];
    H --> I[Second Gate Electrode (TiN)];
    subgraph First MIS Transistor (Non-Volatile Vth)
        D -- Interface --> F
    end
    subgraph Second MIS Transistor (Non-Volatile Vth)
        G -- Interface --> I
    end

Derivative 1.4: Multi-Gate (FinFET) Architecture with Stacked Interface Layers

• Enabling Description: A semiconductor device incorporating FinFET architecture on a silicon-on-insulator (SOI) substrate. The active regions are vertical fins. The gate insulating films wrap around these fins. The interface layer consists of a stacked dielectric, e.g., a bottom thermal SiO2 layer and a thin intermediate silicon oxynitride (SiON) layer. The first transistor's interface layer stack has a total equivalent oxide thickness (EOT) of 1.8 nm (e.g., 1.0 nm SiO2 + 0.8 nm SiON), while the second has 1.0 nm EOT (e.g., 0.5 nm SiO2 + 0.5 nm SiON), achieved by differential thermal growth and nitridation. The high-k film is HfO2, and the gate electrode is a metal gate (e.g., TiN/W) with work-function engineering. This provides enhanced electrostatic control and scaling, coupled with Vth variability.

graph TD
    A[SOI Substrate] --> B{FinFET Active Region 1};
    A --> C{FinFET Active Region 2};
    B --> D[Interface Layer Stack 1 (SiO2/SiON, 1.8nm EOT)];
    D --> E[High-k Film 1 (HfO2)];
    E --> F[Metal Gate 1 (TiN/W)];
    C --> G[Interface Layer Stack 2 (SiO2/SiON, 1.0nm EOT)];
    G --> H[High-k Film 2 (HfO2)];
    H --> I[Metal Gate 2 (TiN/W)];
    subgraph FinFET 1
        D -- Gate Stack --> F
    end
    subgraph FinFET 2
        G -- Gate Stack --> I
    end

Derivative 1.5: Graphene/2D Material Gate Electrode with Low-k Spacers

• Enabling Description: A semiconductor device built on a silicon substrate. The gate insulating films include a silicon dioxide interface layer (first: 1.2 nm, second: 0.7 nm) and a high-k HfO2 layer. The gate electrode is formed from a few-layer graphene stack, leveraging its unique work function and extreme thinness. The sidewall spacers are made of a low-k dielectric material, such as SiOC (silicon oxycarbide), to minimize parasitic capacitance. This configuration targets ultra-low power and highly scaled devices, with the graphene work function being further modulated by the varying interface layer.

graph TD
    A[Silicon Substrate] --> B{First Active Region};
    A --> C{Second Active Region};
    B --> D[First Interface Layer (SiO2, 1.2nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (Graphene)];
    F -- Side --> G[Low-k Spacer 1 (SiOC)];
    C --> H[Second Interface Layer (SiO2, 0.7nm)];
    H --> I[Second High-k Film (HfO2)];
    I --> J[Second Gate Electrode (Graphene)];
    J -- Side --> K[Low-k Spacer 2 (SiOC)];
    subgraph First MIS Transistor
        D -- Interface --> F
        F -- Spacer --> G
    end
    subgraph Second MIS Transistor
        H -- Interface --> J
        J -- Spacer --> K
    end

---

2. Operational Parameter Expansion Derivatives (Claim 1)

Derivative 1.6: Cryogenic Operation for Quantum Computing Interface

• Enabling Description: A semiconductor device featuring nMIS transistors on a high-purity silicon substrate, specifically designed for operation at cryogenic temperatures (e.g., 4 Kelvin or below) to interface with superconducting quantum bits (qubits). The first transistor's gate insulating film has a 1.5 nm SiON interface layer and HfO2 high-k, while the second has a 0.8 nm SiON interface and HfO2 high-k, both optimized for minimal charge trapping and low 1/f noise at extreme cold. The varied interface layer thickness provides two distinct Vth values for thresholding and driving control signals at cryogenic temperatures, enabling precise voltage levels for qubit manipulation. Gate electrodes are TiN, suitable for low-temperature stability.

graph TD
    A[High-Purity Silicon Substrate (Cryogenic)] --> B{First Active Region};
    A --> C{Second Active Region};
    B --> D[First Interface Layer (SiON, 1.5nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (TiN)];
    C --> G[Second Interface Layer (SiON, 0.8nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (TiN)];
    subgraph Cryogenic nMIS Transistor 1 (High Vth)
        D -- Gate Stack --> F
    end
    subgraph Cryogenic nMIS Transistor 2 (Low Vth)
        G -- Gate Stack --> I
    end
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#add8e6,stroke:#333,stroke-width:1px
    style C fill:#add8e6,stroke:#333,stroke-width:1px

Derivative 1.7: High-Power Radio Frequency (RF) Switch

• Enabling Description: A semiconductor device integrating pMIS transistors on a silicon substrate, optimized for high-power RF switching applications (e.g., 5G/6G communication systems). The gate insulating films utilize a silicon dioxide interface layer (first: 1.8 nm, second: 1.0 nm) and a HfSiO high-k film, chosen for its excellent RF linearity and breakdown characteristics. The different interface layer thicknesses create two distinct Vth devices: one for high-gain, low-leakage blocking (thick interface) and another for low-resistance, high-speed switching (thin interface). Gate electrodes are WSi2 for low gate resistance. These transistors are designed for operation at frequencies up to 100 GHz and power levels exceeding 1 Watt.

graph TD
    A[Silicon Substrate] --> B{First Active Region (RF Switch)};
    A --> C{Second Active Region (RF Switch)};
    B --> D[First Interface Layer (SiO2, 1.8nm)];
    D --> E[First High-k Film (HfSiO)];
    E --> F[First Gate Electrode (WSi2)];
    C --> G[Second Interface Layer (SiO2, 1.0nm)];
    G --> H[Second High-k Film (HfSiO)];
    H --> I[Second Gate Electrode (WSi2)];
    subgraph RF pMIS Transistor 1 (High Vth, Blocking)
        D -- Gate Stack --> F
    end
    subgraph RF pMIS Transistor 2 (Low Vth, Switching)
        G -- Gate Stack --> I
    end

Derivative 1.8: Radiation-Hardened Integrated Circuit

• Enabling Description: A semiconductor device developed for radiation-hardened applications, such as space electronics or nuclear environments, utilizing nMIS transistors on a SOI substrate. The gate insulating films consist of a thermal silicon dioxide interface layer (first: 2.5 nm, second: 1.5 nm) and a radiation-tolerant HfO2 high-k dielectric, specifically engineered for reduced total ionizing dose (TID) effects and single-event effects (SEE). The thicker interface layer in the first transistor provides increased robustness against charge trapping induced by radiation, leading to a more stable Vth shift, while the second transistor offers a lower Vth for higher speed operations where radiation tolerance can be slightly relaxed. Gate electrodes are highly doped polysilicon with a metal cap (e.g., TaN) for work function control.

graph TD
    A[SOI Substrate (Radiation-Hardened)] --> B{First Active Region};
    A --> C{Second Active Region};
    B --> D[First Interface Layer (SiO2, 2.5nm)];
    D --> E[First High-k Film (Radiation-Tolerant HfO2)];
    E --> F[First Gate Electrode (TaN/Poly)];
    C --> G[Second Interface Layer (SiO2, 1.5nm)];
    G --> H[Second High-k Film (Radiation-Tolerant HfO2)];
    H --> I[Second Gate Electrode (TaN/Poly)];
    subgraph Rad-Hard nMIS Transistor 1 (Stable Vth)
        D -- Gate Stack --> F
    end
    subgraph Rad-Hard nMIS Transistor 2 (Faster, Less Stable Vth)
        G -- Gate Stack --> I
    end
    style A fill:#ffd700,stroke:#333,stroke-width:2px

Derivative 1.9: Extreme Temperature (400°C) Sensor Interface

• Enabling Description: A semiconductor device fabricated on a SiC substrate designed for operation in extreme high-temperature environments (e.g., 400°C) for industrial sensors. The pMIS transistors on the substrate feature gate insulating films with a plasma-enhanced atomic layer deposited (PEALD) SiON interface layer (first: 2.2 nm, second: 1.2 nm) and a thermally stable ZrO2 high-k film. The varying interface layer thickness provides distinct Vth values crucial for differentiating sensor signal amplification from environmental noise at elevated temperatures. Gate electrodes are refractory metal nitrides (e.g., TiAlN) for thermal stability.

graph TD
    A[SiC Substrate (Extreme Temp)] --> B{First Active Region};
    A --> C{Second Active Region};
    B --> D[First Interface Layer (PEALD SiON, 2.2nm)];
    D --> E[First High-k Film (ZrO2)];
    E --> F[First Gate Electrode (TiAlN)];
    C --> G[Second Interface Layer (PEALD SiON, 1.2nm)];
    G --> H[Second High-k Film (ZrO2)];
    H --> I[Second Gate Electrode (TiAlN)];
    subgraph High-Temp pMIS Transistor 1 (High Vth)
        D -- Gate Stack --> F
    end
    subgraph High-Temp pMIS Transistor 2 (Low Vth)
        G -- Gate Stack --> I
    end
    style A fill:#ffb3ba,stroke:#333,stroke-width:2px

Derivative 1.10: Ultra-Low Power Wearable Device SoC

• Enabling Description: A semiconductor device intended for ultra-low power System-on-Chip (SoC) applications in wearable electronics, implemented on a bulk silicon substrate with nMIS transistors. The gate insulating films feature a chemical oxide SiO2 interface layer (first: 0.9 nm, second: 0.4 nm) and a HfO2 high-k film, optimized for minimal leakage current. The two distinct interface layer thicknesses yield transistors with a high Vth for leakage-critical circuits (e.g., sleep mode logic) and a low Vth for performance-critical circuits (e.g., wake-up logic, sensor data processing), extending battery life. Gate electrodes are low-work function metals like La-doped TiN.

graph TD
    A[Silicon Substrate (Ultra-Low Power)] --> B{First Active Region};
    A --> C{Second Active Region};
    B --> D[First Interface Layer (Chem Oxide SiO2, 0.9nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (La-doped TiN)];
    C --> G[Second Interface Layer (Chem Oxide SiO2, 0.4nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (La-doped TiN)];
    subgraph ULP nMIS Transistor 1 (High Vth, Low Leakage)
        D -- Gate Stack --> F
    end
    subgraph ULP nMIS Transistor 2 (Low Vth, High Speed)
        G -- Gate Stack --> I
    end
    style A fill:#cceeff,stroke:#333,stroke-width:2px

---

3. Cross-Domain Application Derivatives (Claim 1)

Derivative 1.11: Automotive Engine Control Unit (ECU)

• Enabling Description: A semiconductor device designed for use in an automotive engine control unit (ECU), where robustness, thermal stability, and varied performance characteristics are critical. The device includes complementary MIS transistors (both pMIS and nMIS, but within each type, two Vth levels exist) on a silicon substrate. For pMIS, the first interface layer is 1.2 nm SiON, and the second is 0.7 nm SiON, with a high-k HfAlO. For nMIS, the first interface is 1.0 nm SiO2, and the second is 0.6 nm SiO2, with a high-k HfLaO. This allows for dedicated high-Vth transistors for reliable, low-leakage sensor monitoring (e.g., engine temperature, pressure) and low-Vth transistors for high-speed computation (e.g., fuel injection timing, ignition control). Gate electrodes are metal gates (e.g., TiN/TaN for pMIS, TiN/TiC for nMIS).

graph TD
    A[Silicon Substrate (Automotive ECU)] --> B{pMIS Region 1};
    A --> C{pMIS Region 2};
    A --> D{nMIS Region 1};
    A --> E{nMIS Region 2};
    B --> F[pMIS Int. Layer 1 (SiON, 1.2nm)];
    F --> G[pMIS High-k 1 (HfAlO)];
    G --> H[pMIS Gate 1];
    C --> I[pMIS Int. Layer 2 (SiON, 0.7nm)];
    I --> J[pMIS High-k 2 (HfAlO)];
    J --> K[pMIS Gate 2];
    D --> L[nMIS Int. Layer 1 (SiO2, 1.0nm)];
    L --> M[nMIS High-k 1 (HfLaO)];
    M --> N[nMIS Gate 1];
    E --> O[nMIS Int. Layer 2 (SiO2, 0.6nm)];
    O --> P[nMIS High-k 2 (HfLaO)];
    P --> Q[nMIS Gate 2];
    subgraph pMIS Transistors
        F -- High Vth --> H
        I -- Low Vth --> K
    end
    subgraph nMIS Transistors
        L -- High Vth --> N
        O -- Low Vth --> Q
    end

Derivative 1.12: Smart Grid Energy Management Node

• Enabling Description: A semiconductor device applied in smart grid edge computing nodes for real-time energy management and fault detection. The device comprises pMIS transistors on a silicon substrate. The first pMIS transistor features a 1.0 nm SiON interface layer and HfO2 high-k for robust, low-leakage operation of critical control logic, ensuring system stability. The second pMIS transistor has a 0.5 nm SiO2 interface layer and HfO2 high-k, providing high-speed operation for data acquisition and communication protocols. This dual-Vth approach allows for optimized power efficiency and responsiveness in diverse grid conditions. Gate electrodes are TiN/polysilicon.

graph TD
    A[Silicon Substrate (Smart Grid)] --> B{Critical Control Logic Region};
    A --> C{Data Acquisition Region};
    B --> D[First Interface Layer (SiON, 1.0nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (TiN/Poly)];
    C --> G[Second Interface Layer (SiO2, 0.5nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (TiN/Poly)];
    subgraph pMIS Transistor 1 (High Vth, Robust)
        D -- Gate Stack --> F
    end
    subgraph pMIS Transistor 2 (Low Vth, High Speed)
        G -- Gate Stack --> I
    end

Derivative 1.13: Biomedical Implantable Device (e.g., Pacemaker Controller)

• Enabling Description: A semiconductor device suitable for long-term implantable biomedical applications (e.g., pacemaker or neural stimulator controllers), where ultra-low power consumption and functional reliability are paramount. The device uses nMIS transistors on an SOI substrate for reduced leakage and radiation tolerance. The first transistor's gate insulating film incorporates a 1.5 nm SiON interface layer and a biocompatible HfO2 high-k for robust, low-leakage clocking and control logic. The second transistor features a 0.7 nm SiO2 interface layer and HfO2 high-k, optimized for higher speed signal processing (e.g., ECG analysis, stimulation pulse generation). This dual-Vth architecture prolongs battery life and ensures critical functions are always available. Gate electrodes are highly stable PtSi/Polysilicon.

graph TD
    A[SOI Substrate (Biomedical Implant)] --> B{Control Logic Region};
    A --> C{Signal Processing Region};
    B --> D[First Interface Layer (SiON, 1.5nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (PtSi/Poly)];
    C --> G[Second Interface Layer (SiO2, 0.7nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (PtSi/Poly)];
    subgraph nMIS Transistor 1 (High Vth, ULP)
        D -- Gate Stack --> F
    end
    subgraph nMIS Transistor 2 (Low Vth, Faster)
        G -- Gate Stack --> I
    end
    style A fill:#a0d6b4,stroke:#333,stroke-width:2px

Derivative 1.14: Industrial IoT Sensor Node for Predictive Maintenance

• Enabling Description: A semiconductor device integrated into an industrial IoT sensor node, designed for predictive maintenance in harsh factory environments. The silicon-based nMIS transistors provide two distinct Vth levels: one (e.g., 1.8 nm SiON interface, HfO2 high-k) for ultra-low power standby mode and infrequent data acquisition from sensors (e.g., vibration, temperature), and another (e.g., 0.9 nm SiO2 interface, HfO2 high-k) for bursts of high-speed data processing and wireless communication when anomalies are detected. This optimized power management ensures extended operational periods without intervention. Gate electrodes are W/polysilicon.

graph TD
    A[Silicon Substrate (Industrial IoT)] --> B{Standby/Acquisition Logic Region};
    A --> C{Processing/Comm. Logic Region};
    B --> D[First Interface Layer (SiON, 1.8nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (W/Poly)];
    C --> G[Second Interface Layer (SiO2, 0.9nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (W/Poly)];
    subgraph nMIS Transistor 1 (High Vth, Standby)
        D -- Gate Stack --> F
    end
    subgraph nMIS Transistor 2 (Low Vth, Active)
        G -- Gate Stack --> I
    end

Derivative 1.15: High-Performance Computing (HPC) Cache Memory

• Enabling Description: A semiconductor device specifically tailored for on-chip cache memory within high-performance computing (HPC) processors. The pMIS transistors are implemented on a silicon substrate. The first pMIS transistor (e.g., 1.0 nm SiO2 interface, HfO2 high-k) is used for static random-access memory (SRAM) cells requiring high stability and low leakage current (e.g., L3 cache). The second pMIS transistor (e.g., 0.5 nm SiON interface, HfO2 high-k) is configured for faster switching speeds and lower access times, suitable for performance-critical L1/L2 cache operations. This dual-Vth strategy allows for optimized cache hierarchy design, balancing speed and power. Gate electrodes are P-doped polysilicon with a NiSi metal silicide contact.

graph TD
    A[Silicon Substrate (HPC Cache)] --> B{L3 Cache Region};
    A --> C{L1/L2 Cache Region};
    B --> D[First Interface Layer (SiO2, 1.0nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (P-Poly/NiSi)];
    C --> G[Second Interface Layer (SiON, 0.5nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (P-Poly/NiSi)];
    subgraph pMIS Transistor 1 (High Vth, L3 Stability)
        D -- Gate Stack --> F
    end
    subgraph pMIS Transistor 2 (Low Vth, L1/L2 Speed)
        G -- Gate Stack --> I
    end

---

4. Integration with Emerging Tech Derivatives (Claim 1)

Derivative 1.16: AI-Optimized Adaptive Power Management Unit (PMU)

• Enabling Description: A semiconductor device forming an adaptive power management unit (PMU) where MIS transistors (both nMIS and pMIS) with varying interface layer thicknesses (and thus Vth) are dynamically reconfigured and optimized by an integrated AI controller. For example, nMIS transistors may have interface layers ranging from 0.7 nm to 1.5 nm SiO2, each with a HfZrO high-k, providing a spectrum of Vth settings. The AI algorithm, running on a dedicated low-power core, monitors workload, temperature, and performance metrics, then instructs the PMU to switch between high-Vth (low leakage) and low-Vth (high performance) transistor configurations on-the-fly by altering substrate bias or gate overdrive, effectively "tuning" the underlying devices manufactured with the two distinct interface layer thicknesses described in the patent. Gate electrodes are TiN.

graph TD
    A[AI Controller] --> B{Adaptive PMU};
    B --> C[First MIS Transistor (High Vth)];
    B --> D[Second MIS Transistor (Low Vth)];
    C --> E[First Gate Insulating Film (Thicker Interface Layer)];
    D --> F[Second Gate Insulating Film (Thinner Interface Layer)];
    AI -- Control Signal --> C;
    AI -- Control Signal --> D;
    subgraph AI-Optimized PMU
        C -- Interface Layer --> E
        D -- Interface Layer --> F
    end
    style A fill:#ffcc99,stroke:#333,stroke-width:2px

Derivative 1.17: IoT Edge Processor with Real-time Sensor Feedback Control

• Enabling Description: A semiconductor device for an IoT edge processor, featuring nMIS transistors with differential interface layer thicknesses (e.g., 1.2 nm SiON vs. 0.6 nm SiO2, both with HfO2 high-k). These transistors power specific computational blocks. Integrated IoT sensors (e.g., environmental, motion) provide real-time data feedback to a local microcontroller. Based on this feedback, the microcontroller dynamically switches between operating modes: a low-power mode using the higher-Vth transistors for baseline monitoring and a high-performance mode engaging the lower-Vth transistors for complex event processing. This real-time adaptation improves energy efficiency and responsiveness. Gate electrodes are W/polysilicon.

graph TD
    A[IoT Sensors] --> B{Microcontroller};
    B --> C[First nMIS Transistor (High Vth)];
    B --> D[Second nMIS Transistor (Low Vth)];
    C --> E[Computation Block 1 (Monitoring)];
    D --> F[Computation Block 2 (Event Processing)];
    Sensors -- Data --> Microcontroller;
    Microcontroller -- Mode Control --> C;
    Microcontroller -- Mode Control --> D;
    subgraph IoT Edge Processor
        C -- Powers --> E
        D -- Powers --> F
    end

Derivative 1.18: Blockchain Hardware Security Module (HSM) with Tamper-Detection

• Enabling Description: A semiconductor device forming a hardware security module (HSM) for blockchain applications, manufactured on a silicon substrate. It incorporates pMIS transistors with varying interface layer thicknesses. A primary group of pMIS transistors (e.g., 1.5 nm SiO2 interface, HfO2 high-k) provides stable Vth for secure cryptographic operations. A secondary group (e.g., 0.8 nm SiON interface, HfO2 high-k) is strategically placed in sensitive areas and configured to exhibit a detectable shift in electrical characteristics (e.g., Vth, leakage) upon physical tampering or stress, acting as a tamper-detection mechanism. This differential Vth behavior, due to the varying interface layers, contributes to the device's robust security features. Gate electrodes are TaN.

graph TD
    A[Silicon Substrate] --> B{Crypto Core (Primary pMIS)};
    A --> C{Tamper-Detection Unit (Secondary pMIS)};
    B --> D[First Gate Insulating Film (Thicker Interface)];
    C --> E[Second Gate Insulating Film (Thinner Interface)];
    D -- Stable Vth --> F[Secure Operations];
    E -- Sensitive Vth --> G[Tamper Alert];
    subgraph Blockchain HSM
        F -- Crypto --> A
        G -- Detect --> A
    end

Derivative 1.19: Neural Network Accelerator with Mixed-Precision Logic

• Enabling Description: A semiconductor device designed as a neural network accelerator, utilizing nMIS transistors on a silicon substrate with two distinct Vth levels for mixed-precision arithmetic. High-Vth transistors (e.g., 1.3 nm SiON interface, HfO2 high-k) are used for less critical operations or for implementing quantization in deep learning, reducing leakage and power. Low-Vth transistors (e.g., 0.7 nm SiO2 interface, HfO2 high-k) are employed for high-precision, high-speed computations in critical layers of the neural network. This differential Vth, stemming from the varied interface layer thicknesses, enables efficient hardware implementation of mixed-precision inference, reducing overall energy consumption without significantly impacting accuracy. Gate electrodes are TiN/polysilicon.

graph TD
    A[Silicon Substrate (NN Accelerator)] --> B{Low-Precision Logic (High Vth)};
    A --> C{High-Precision Logic (Low Vth)};
    B --> D[First Interface Layer (SiON, 1.3nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (TiN/Poly)];
    C --> G[Second Interface Layer (SiO2, 0.7nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (TiN/Poly)];
    subgraph Neural Network Accelerator
        B -- Mixed Precision --> F
        C -- Mixed Precision --> I
    end

Derivative 1.20: Quantum Dot Display Backplane with Adaptive Refresh

• Enabling Description: A semiconductor device serving as a backplane for a quantum dot (QD) display, employing pMIS transistors on a flexible polymer substrate (e.g., polyimide with a thin silicon layer). The first pMIS transistors (e.g., 1.8 nm SiON interface, Al2O3 high-k) are used for row drivers requiring stable, low-leakage holding states. The second pMIS transistors (e.g., 1.0 nm SiO2 interface, Al2O3 high-k) are employed for pixel switching, demanding high current drive and fast response times. An adaptive refresh algorithm, considering display content and power constraints, dynamically leverages the different Vth transistors, enabling varied refresh rates and local dimming with enhanced energy efficiency. Gate electrodes are flexible metal alloys (e.g., ITO).

graph TD
    A[Flexible Polymer Substrate (QD Display)] --> B{Row Driver Logic (High Vth)};
    A --> C{Pixel Switching Array (Low Vth)};
    B --> D[First Interface Layer (SiON, 1.8nm)];
    D --> E[First High-k Film (Al2O3)];
    E --> F[First Gate Electrode (ITO)];
    C --> G[Second Interface Layer (SiO2, 1.0nm)];
    G --> H[Second High-k Film (Al2O3)];
    H --> I[Second Gate Electrode (ITO)];
    subgraph QD Display Backplane
        B -- Adaptive Refresh --> F
        C -- Adaptive Refresh --> I
    end
    style A fill:#a0d6b4,stroke:#333,stroke-width:2px

---

5. The "Inverse" or Failure Mode Derivatives (Claim 1)

Derivative 1.21: Self-Repairing Gate Dielectric for Enhanced Reliability

• Enabling Description: A semiconductor device designed with self-repairing capabilities, utilizing nMIS transistors on a silicon substrate. The gate insulating film includes an initial silicon dioxide interface layer (first: 1.0 nm, second: 0.5 nm) and a HfO2 high-k layer. However, the interface layer is specifically engineered with embedded, dormant silicon nanoparticles. Upon detection of a gate dielectric breakdown event (e.g., via increased leakage current), a localized annealing pulse or electromigration-inducing voltage is applied. This activates the nanoparticles, causing them to oxidize and "grow" into the defect region, effectively thickening the interface layer locally (akin to the "first interface layer" in the patent) and restoring dielectric integrity in a controlled failure mode. The repaired gate will exhibit a slightly higher Vth. Gate electrodes are W/polysilicon.

graph TD
    A[Silicon Substrate] --> B{First nMIS (Self-Repairing)};
    A --> C{Second nMIS (Reference)};
    B --> D[First Interface Layer (SiO2 w/ Nanoparticles, 1.0nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (W/Poly)];
    C --> G[Second Interface Layer (SiO2, 0.5nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (W/Poly)];
    B -- Breakdown --> J{Repair Mechanism (Annealing/Voltage)};
    J -- Thickens Interface --> D;
    subgraph Self-Repairing Transistor
        D -- State --> F
    end

Derivative 1.22: Programmable Degradation for Anti-Tamper Security

• Enabling Description: A semiconductor device for secure applications, where pMIS transistors on a silicon substrate are intentionally designed for programmable degradation to prevent reverse engineering or tampering. Critical security keys are stored in memory cells protected by transistors with a specific, stable Vth (e.g., second transistor with 0.8 nm SiON interface, HfAlO high-k). A set of "fuse" transistors, similar to the first transistor but with a slightly thicker interface layer (e.g., 1.5 nm SiO2 interface, HfAlO high-k), are deliberately placed. Upon detection of a physical attack or unauthorized access attempt, a high-voltage pulse is applied to these fuse transistors, causing controlled, irreversible damage to their interface layers (e.g., further oxidation or defect creation). This dramatically shifts their Vth to a non-functional state, effectively bricking the device and preventing access to sensitive data without physically destroying it. Gate electrodes are TiN/polysilicon.

graph TD
    A[Silicon Substrate] --> B{Secure Memory Region (Stable pMIS)};
    A --> C{Anti-Tamper Fuse Region (Degradable pMIS)};
    B --> D[Second Interface Layer (SiON, 0.8nm)];
    D --> E[Second High-k Film (HfAlO)];
    E --> F[Second Gate Electrode (TiN/Poly)];
    C --> G[First Interface Layer (SiO2, 1.5nm)];
    G --> H[First High-k Film (HfAlO)];
    H --> I[First Gate Electrode (TiN/Poly)];
    C -- Tamper Detected --> J{High Voltage Pulse};
    J -- Irreversible Vth Shift --> G;
    subgraph Anti-Tamper Device
        D -- Keys Protected --> F
        G -- Failsafe --> I
    end

Derivative 1.23: Adaptive Low-Power "Sleep" Mode Transistor

• Enabling Description: A semiconductor device featuring nMIS transistors on a silicon substrate, designed to dynamically enter an ultra-low power "sleep" mode. The device includes two types of transistors: high-Vth (first type, 1.8 nm SiON interface, HfO2 high-k) for active logic and low-Vth (second type, 0.9 nm SiO2 interface, HfO2 high-k) for fast wake-up. When the system transitions to sleep mode, a dedicated control circuit applies a slight negative back-bias to the substrate for the high-Vth transistors, effectively increasing their effective interface layer thickness (or equivalent) and further elevating their Vth, thereby drastically reducing off-state leakage current. This leverages the inherent Vth difference to create an even more pronounced leakage reduction during inactivity. Gate electrodes are La-doped TiN.

graph TD
    A[Silicon Substrate] --> B{Active Logic (High Vth nMIS)};
    A --> C{Wake-up Logic (Low Vth nMIS)};
    B --> D[First Interface Layer (SiON, 1.8nm)];
    D --> E[First High-k Film (HfO2)];
    E --> F[First Gate Electrode (La-TiN)];
    C --> G[Second Interface Layer (SiO2, 0.9nm)];
    G --> H[Second High-k Film (HfO2)];
    H --> I[Second Gate Electrode (La-TiN)];
    F -- Sleep Mode Enable --> J{Negative Back-Bias};
    J -- Increases Effective Vth --> D;
    subgraph Adaptive Sleep Mode
        D -- Reduced Leakage --> F
        G -- Fast Wakeup --> I
    end

Derivative 1.24: "Limited-Functionality" Debug Mode Transistors

• Enabling Description: A semiconductor device incorporating pMIS transistors on a silicon substrate, designed with a "limited-functionality" debug mode for fault analysis or simplified operation. The device has two types of pMIS transistors. The first type, with a thicker interface layer (e.g., 1.5 nm SiON interface, ZrO2 high-k), has a naturally higher Vth and lower drive current, suitable for powering non-critical peripherals or simplified diagnostic circuits in debug mode. The second type, with a thinner interface layer (e.g., 0.7 nm SiO2 interface, ZrO2 high-k), is designed for full-performance operation. During debug, the main power rails to the full-performance blocks are disconnected, and only the limited-functionality blocks, driven by the inherently higher-Vth transistors, are powered, reducing power consumption and complexity for diagnostics. Gate electrodes are TiN/polysilicon.

graph TD
    A[Silicon Substrate] --> B{Debug-Mode Logic (High Vth pMIS)};
    A --> C{Full-Functionality Logic (Low Vth pMIS)};
    B --> D[First Interface Layer (SiON, 1.5nm)];
    D --> E[First High-k Film (ZrO2)];
    E --> F[First Gate Electrode (TiN/Poly)];
    C --> G[Second Interface Layer (SiO2, 0.7nm)];
    G --> H[Second High-k Film (ZrO2)];
    H --> I[Second Gate Electrode (TiN/Poly)];
    F -- Debug Enable --> J{Power Rail Switch};
    J -- Disconnects --> I;
    subgraph Debug Mode Device
        D -- Limited Operation --> F
        G -- Disabled --> I
    end

Derivative 1.25: Self-Limiting Current Transistor for Overcurrent Protection

• Enabling Description: A semiconductor device designed with integrated overcurrent protection using nMIS transistors on a silicon substrate. The device contains "normal" nMIS transistors (e.g., second type, 0.7 nm SiO2 interface, HfO2 high-k) for general purpose logic. Additionally, there are "protective" nMIS transistors (first type, 1.2 nm SiON interface, HfO2 high-k) with an inherently higher Vth and thus lower maximum saturation current. These protective transistors are strategically placed in series with critical load paths. In the event of an overcurrent condition (e.g., short circuit), the voltage drop across the load changes, causing the gate-source voltage (Vgs) of the protective transistor to effectively decrease, pushing it further into its subthreshold region due to its higher Vth. This automatically and passively limits the current, preventing damage to downstream components. Gate electrodes are TiN/polysilicon.

graph TD
    A[Silicon Substrate] --> B{Normal Logic (Low Vth nMIS)};
    A --> C{Current-Limiting Logic (High Vth nMIS)};
    B --> D[Second Interface Layer (SiO2, 0.7nm)];
    D --> E[Second High-k Film (HfO2)];
    E --> F[Second Gate Electrode (TiN/Poly)];
    C --> G[First Interface Layer (SiON, 1.2nm)];
    G --> H[First High-k Film (HfO2)];
    H --> I[First Gate Electrode (TiN/Poly)];
    I -- In Series With --> J[Critical Load];
    J -- Overcurrent --> K{Vgs Drop on High Vth Transistor};
    K -- Self-Limits Current --> I;
    subgraph Overcurrent Protection Device
        D -- Normal Operation --> F
        G -- Protection --> I
    end

---

Derivatives of Claim 7: Method for Fabricating Semiconductor Device

Claim 7: A method for fabricating the semiconductor device of the present disclosure includes: a step (a) of forming an interface layer, a high dielectric constant insulating film, and a gate electrode material film in a sequential manner on a semiconductor substrate including a first active region and a second active region; a step (b) of patterning the gate electrode material film, the high dielectric constant insulating film, and the interface layer to form a first gate electrode of the gate electrode material film on the first active region with a first gate insulating film including the interface layer and the high dielectric constant insulating film and interposed between the first gate electrode and the first active region, and to form a second gate electrode of the gate electrode material film on the second active region with a second gate insulating film including the interface layer and the high dielectric constant insulating film and interposed between the second gate electrode and the second active region; and the step (c) of increasing the thickness of the interface layer of the first gate insulating film in a selective manner, after the step (b).

---

1. Material & Component Substitution Derivatives (Claim 7)

Derivative 7.1: Selective ALD for Interface Layer Thickening

• Enabling Description: After patterning the gate electrode material film, high-k film, and initial interface layer (e.g., 0.8 nm thermal SiO2), the method of increasing the thickness of the first interface layer selectively (step c) is performed using area-selective atomic layer deposition (AS-ALD) of an ultra-thin silicon dioxide or silicon oxynitride layer. A self-assembled monolayer (SAM) or a polymer passivation layer is selectively applied to the surface of the second gate stack and active region, inhibiting ALD growth, while the first gate stack's interface layer is exposed. Subsequently, a low-temperature ALD process (e.g., using SiH4/O2 or SiH2Cl2/NH3 plasma) precisely adds 0.5 nm of SiO2 or SiON to the exposed first interface layer. This provides atomic-level control over the thickness increase.

sequenceDiagram
    participant Substrate
    participant PrecursorA
    participant PrecursorB
    Substrate->>Substrate: Form initial Gate Stacks (Pat. 8796779 Steps a & b)
    Substrate->>Substrate: Apply selective SAM/Polymer mask on 2nd Gate
    Substrate->>PrecursorA: Expose to Si Precursor (Selective)
    PrecursorA->>Substrate: Chemisorption on 1st Gate Interface
    Substrate->>Substrate: Purge
    Substrate->>PrecursorB: Expose to Oxidant/Nitridant (Selective)
    PrecursorB->>Substrate: Reaction to form SiO2/SiON on 1st Gate Interface
    Substrate->>Substrate: Purge
    Note right of Substrate: Repeat cycles for desired thickness (AS-ALD)
    Substrate->>Substrate: Remove selective mask

Derivative 7.2: Anodic Oxidation for Selective Interface Layer Growth

• Enabling Description: Following gate patterning (step b), a selective increase in the first interface layer thickness (step c) is achieved via anodic oxidation. The semiconductor substrate is immersed in an electrolyte (e.g., aqueous solution of citric acid or ammonium tartrate). The second gate electrode and its surrounding regions are masked with a photoresist or hard mask. A positive bias is applied to the semiconductor substrate (anode), and a counter electrode acts as the cathode. Oxygen ions from the electrolyte are driven into the exposed silicon interface layer of the first gate insulating film, leading to controlled growth of a silicon dioxide layer. The thickness increase (e.g., 0.3 nm) is precisely controlled by the applied voltage and current density.

graph TD
    A[Semiconductor Substrate with Gate Stacks] --> B{Mask 2nd Gate Region (Photoresist)};
    B --> C{Immerse in Electrolyte (Citric Acid)};
    C --> D{Apply Positive Bias to Substrate (Anode)};
    C --> E{Apply Negative Bias to Counter Electrode (Cathode)};
    D -- Oxygen Ion Migration --> F[Selective Anodic Oxidation of 1st Interface Layer];
    F --> G[Increased Thickness of 1st Interface Layer];
    G --> H{Remove Mask};

Derivative 7.3: Localized Laser-Assisted Thermal Oxidation

• Enabling Description: After defining the gate structures (step b), the selective thickening of the first interface layer (step c) is performed using localized laser-assisted thermal oxidation. The patterned substrate is placed in an oxygen-rich ambient. A precisely focused laser beam (e.g., 532 nm or 1064 nm wavelength) is scanned over the first gate electrode and its exposed interface layer regions. The localized heating rapidly increases the temperature of the underlying silicon interface, promoting thermal oxidation. The second gate region remains unheated by the laser and thus its interface layer thickness is largely unaffected. Laser power, scan speed, and oxygen partial pressure control the resulting oxide thickness (e.g., 0.4 nm increase).

graph TD
    A[Semiconductor Substrate with Gate Stacks] --> B{Oxygen-Rich Ambient};
    B --> C{Scan Focused Laser over 1st Gate Region};
    C -- Localized Heating --> D[Rapid Thermal Oxidation of 1st Interface Layer];
    D --> E[Increased Thickness of 1st Interface Layer];
    B -- No Laser Heat --> F[2nd Gate Interface Layer Unaffected];

Derivative 7.4: Catalytic Interface Layer Growth with Selective Precursor Delivery

• Enabling Description: Following gate patterning (step b), the selective increase in the first interface layer thickness (step c) is achieved by catalytic interface layer growth using a selective precursor delivery method. A thin catalytic layer (e.g., an ultrathin Pd or Pt film) is selectively deposited on the surface of the first gate's interface layer and adjacent silicon regions, potentially using area-selective deposition techniques. The second gate region is left uncoated or passivated. The entire wafer is then exposed to a mild oxidant (e.g., low-temperature O3 plasma or H2O vapor) where the catalyst locally lowers the activation energy for silicon oxidation, promoting selective and controlled growth of SiO2 or SiON on the first interface layer.

graph TD
    A[Semiconductor Substrate with Gate Stacks] --> B{Selective Deposition of Catalytic Layer on 1st Gate};
    B --> C{Expose Wafer to Mild Oxidant};
    C -- Catalytic Reaction --> D[Accelerated Oxidation of 1st Interface Layer];
    D --> E[Increased Thickness of 1st Interface Layer];
    C -- No Catalyst --> F[2nd Gate Interface Layer Unaffected];

Derivative 7.5: Remote Plasma Oxidation with Differential Shielding

• Enabling Description: After gate patterning (step b), the selective thickening of the first interface layer (step c) is accomplished via remote plasma oxidation with differential shielding. The substrate is introduced into a remote plasma reactor, where oxygen plasma is generated upstream and reactive species (e.g., atomic oxygen) are transported to the wafer surface. The second gate regions are covered with a temporary, thick sacrificial polymer or dielectric layer (e.g., SiO2 or SiN), which acts as a physical shield against the reactive species. The first gate regions, exposed to the remote plasma, undergo controlled oxidation of their interface layer. The thickness of the sacrificial layer and plasma parameters (power, time, temperature) control the selectivity and oxidation rate.

graph TD
    A[Semiconductor Substrate with Gate Stacks] --> B{Apply Thick Shielding Layer to 2nd Gate Region};
    B --> C{Place in Remote Plasma Reactor};
    C -- Remote Oxygen Plasma --> D[Exposure of 1st Gate Interface Layer];
    D --> E[Controlled Oxidation of 1st Interface Layer];
    E --> F[Increased Thickness of 1st Interface Layer];
    C -- Shielding --> G[2nd Gate Interface Layer Protected];
    G --> H{Remove Shielding Layer};

---

2. Operational Parameter Expansion Derivatives (Claim 7)

Derivative 7.6: Ultra-Fast Millisecond Annealing for Interface Layer Control

• Enabling Description: The method for increasing the thickness of the first interface layer (step c) is achieved using ultra-fast millisecond annealing (MSA) in an oxygen-containing atmosphere. After the selective etching of the insulating film covering the first gate electrode (as in Claim 14), the entire wafer is rapidly heated to high temperatures (e.g., 900-1100°C) for a few milliseconds using flash lamp annealing or laser spike annealing. This extremely short thermal budget allows for precise, localized oxidation of the exposed silicon interface layer on the first gate, minimizing dopant diffusion and other undesired thermal effects in the surrounding device regions. The rapid cooling rate further limits unwanted oxidation on the protected second gate.

graph TD
    A[Patterned Gate Stacks with Selective Etched Insulating Film] --> B{Oxygen-Containing Atmosphere};
    B --> C{Apply Millisecond Annealing (Flash/Laser)};
    C -- Rapid Heating/Cooling --> D[Selective Interface Layer Oxidation (1st Gate)];
    D --> E[Precise, Ultra-Fast Thickness Increase (e.g., 0.2nm)];
    E --> F[Minimize Dopant Diffusion];

Derivative 7.7: Low-Temperature (250°C) UV-Ozone Interface Thickening

• Enabling Description: The selective interface layer thickening (step c) is performed using low-temperature (e.g., 250°C) UV-ozone oxidation. After the selective etching of the overlying insulating film (Claim 14), the wafer is exposed to a high-concentration ozone atmosphere under ultraviolet (UV) irradiation. The UV light breaks down ozone into highly reactive atomic oxygen, which then selectively oxidizes the exposed silicon surface of the first interface layer. The low temperature minimizes thermal stress and is compatible with highly sensitive materials or advanced packaging. The absence of UV exposure on the protected second gate prevents oxidation.

graph TD
    A[Patterned Gate Stacks with Selective Etched Insulating Film] --> B{Low-Temp Chamber (250C)};
    B --> C{Introduce High-Concentration Ozone};
    B --> D{Apply UV Irradiation};
    C -- UV Activation --> E[Reactive Atomic Oxygen];
    E -- Selective Exposure --> F[Oxidation of 1st Interface Layer];
    F --> G[Controlled Low-Temp Thickness Increase];

Derivative 7.8: High-Pressure Water Vapor Oxidation for Deep Interface Penetration

• Enabling Description: For applications requiring a robust, dense interface layer, the selective thickening (step c) is performed using high-pressure water vapor oxidation. After selective exposure of the first interface layer (Claim 14), the substrate is subjected to a steam environment at elevated pressure (e.g., 10-20 atm) and moderate temperature (e.g., 500-600°C). The high concentration of water molecules and elevated pressure accelerate the oxidation rate and promote the formation of a high-quality, dense silicon dioxide film, ensuring excellent interface passivation and reliability. The intact thick insulating film on the second gate effectively blocks the water vapor.

graph TD
    A[Patterned Gate Stacks with Selective Etched Insulating Film] --> B{High-Pressure Water Vapor Chamber};
    B -- Elevated Pressure/Temp --> C[Accelerated Oxidation of 1st Interface Layer];
    C --> D[Formation of Dense, Robust SiO2];
    D --> E[Improved Interface Passivation/Reliability];
    B -- Shielded --> F[2nd Gate Interface Layer Protected];

Derivative 7.9: Atomic-Scale Control via Pulsed Plasma Oxidation

• Enabling Description: The selective interface layer thickening (step c) is achieved with atomic-scale precision using pulsed plasma oxidation. After the selective removal of the overlying insulating film (Claim 14), the substrate is exposed to short, precisely timed pulses of oxygen plasma. Each pulse delivers a controlled dose of reactive oxygen species, allowing for incremental, layer-by-layer growth of the interface oxide. This method offers superior control over the final thickness (e.g., increments of 0.1 nm) and minimizes over-oxidation or damage to adjacent structures. The insulating film on the second gate completely prevents any plasma exposure.

sequenceDiagram
    participant Substrate
    participant Plasma
    Substrate->>Substrate: Patterned Gate Stacks (1st Exposed, 2nd Shielded)
    loop N cycles for target thickness
        Plasma->>Substrate: Pulse Oxygen Plasma
        Substrate->>Substrate: Atomic Layer Oxidation (1st Gate Only)
        Substrate->>Substrate: Purge/Evacuate
    end
    Note right of Substrate: Precise, Incremental Interface Layer Growth

Derivative 7.10: Remote Microwave Plasma Oxidation for Minimal Damage

• Enabling Description: The selective interface layer thickening (step c) is carried out using remote microwave plasma oxidation. The wafer is placed in a processing chamber while an oxygen-containing gas is fed into a separate microwave plasma source, generating a plasma remotely. Reactive oxygen radicals (e.g., O*, O2+) are extracted and diffused into the main chamber, contacting only the exposed first interface layer (after selective etching as in Claim 14). This remote plasma approach minimizes ion bombardment damage to the gate stack and substrate, resulting in a high-quality, defect-free oxide growth at relatively low temperatures (e.g., 300-450°C). The untouched thick insulating film on the second gate acts as a barrier.

graph TD
    A[Microwave Plasma Source] -- Generate --> B{Oxygen Plasma};
    B -- Extract Radicals --> C{Processing Chamber};
    C --> D[Patterned Substrate (1st Gate Exposed)];
    D -- Radicals React --> E[Oxidation of 1st Interface Layer];
    E --> F[Low-Damage, High-Quality Thickness Increase];
    C -- 2nd Gate Shielded --> G[2nd Gate Interface Layer Protected];

---

3. Cross-Domain Application Derivatives (Claim 7)

Derivative 7.11: Fabrication of Flexible Display TFT Backplanes

• Enabling Description: A fabrication method for active-matrix thin-film transistor (TFT) backplanes on a flexible polymer substrate (e.g., polyimide) for bendable displays. Step (a) involves forming initial dielectric and gate stacks on a deposited amorphous silicon or oxide semiconductor layer. Step (b) patterns these layers into TFT gate electrodes and gate insulating films. Step (c), the selective interface layer thickening (e.g., using low-temperature UV-ozone oxidation with patterned photoresist masks for selectivity), creates high-Vth TFTs for pixel storage capacitors and low-Vth TFTs for high-speed switching elements on the same flexible substrate. This enables efficient power management and improved visual performance in flexible displays.

graph TD
    A[Flexible Polymer Substrate] --> B{Deposit Amorphous Silicon/Oxide Layer};
    B --> C{Form Interface, High-k, Gate Material Stack};
    C --> D{Pattern Gate Electrodes/Insulating Films (TFTs)};
    D --> E{Apply Selective Mask for High-Vth TFTs};
    E --> F[Low-Temp UV-Ozone Oxidation (Selective)];
    F --> G[Increase Interface Layer Thickness (High-Vth TFTs)];
    G --> H{Remove Mask};
    subgraph Flexible Display Backplane Fab
        D -- Vth Control --> G
    end

Derivative 7.12: Manufacturing of Neuromorphic Synaptic Devices

• Enabling Description: A fabrication method for neuromorphic computing chips, specifically for creating resistive switching memory (RRAM) devices acting as programmable synapses. Step (a) involves forming an initial tunnel barrier (interface layer, e.g., thin SiO2), a switching layer (high-k, e.g., HfO2), and a top electrode on a silicon substrate. Step (b) patterns these into individual synaptic device structures. Step (c) is modified to selectively create oxygen vacancies or defects in the interface layer of specific synaptic devices (e.g., via localized laser annealing in a reducing atmosphere or selective ion implantation), effectively altering the interface layer's electrical properties to tune the initial resistance state or potentiation/depression characteristics. This allows for manufacturing synapses with distinct initial weights or learning rules on the same chip.

graph TD
    A[Silicon Substrate] --> B{Form Tunnel Barrier (SiO2), Switching Layer (HfO2), Top Electrode};
    B --> C{Pattern Synaptic Devices};
    C --> D{Apply Selective Mask for Target Synapses};
    D --> E[Localized Laser Annealing (Reducing Atm.) OR Selective Ion Implantation];
    E --> F[Selectively Create Oxygen Vacancies/Defects in Tunnel Barrier];
    F --> G[Tune Synaptic Device Initial Resistance/Learning Rule];
    G --> H{Remove Mask};
    subgraph Neuromorphic Synapse Fab
        C -- Learning Control --> G
    end

Derivative 7.13: Photovoltaic Cell Integrated Controller with On-chip MPPT

• Enabling Description: A fabrication method for integrating a maximum power point tracking (MPPT) controller directly onto a photovoltaic (PV) cell substrate or an adjacent control chip. Step (a) forms interface, high-k, and gate material layers. Step (b) patterns these layers to create MIS transistors for the MPPT control logic. Step (c) selectively increases the interface layer thickness of certain transistors (e.g., current sensors or high-side switches within the MPPT), using high-pressure water vapor oxidation with a selective mask. This provides robust, high-Vth transistors for reliable sensing and power switching in the harsh PV environment, alongside lower-Vth transistors for efficient control logic. Gate electrodes are chosen for stability (e.g., TiN/Al).

graph TD
    A[PV Cell Substrate / Control Chip] --> B{Form Interface, High-k, Gate Material Stack};
    B --> C{Pattern MIS Transistors for MPPT};
    C --> D{Apply Selective Mask for High-Vth Transistors (Sensors/Switches)};
    D --> E[High-Pressure Water Vapor Oxidation (Selective)];
    E --> F[Increase Interface Layer Thickness (High-Vth MPPT Components)];
    F --> G{Remove Mask};
    subgraph PV MPPT Controller Fab
        C -- Power Optimization --> G
    end

Derivative 7.14: Smart Dust Mote Fabrication for Environmental Sensing

• Enabling Description: A fabrication method for ultra-miniature "smart dust" motes designed for pervasive environmental sensing. Step (a) forms the gate stack materials on a silicon-on-insulator (SOI) wafer. Step (b) patterns extremely small MIS transistors (e.g., sub-50nm gate lengths) for computation and communication. Step (c) selectively thickens the interface layer of specific transistors (e.g., using low-temperature UV-ozone oxidation with a shadow mask for selectivity) to create a set of ultra-low leakage, high-Vth transistors for long-duration standby modes, and another set of lower-Vth transistors for rapid data processing and radio transmission. This differential Vth tuning is critical for maximizing the operational lifespan of energy-harvesting smart dust motes. Gate electrodes are highly scaled metal gates.

graph TD
    A[SOI Wafer] --> B{Form Gate Stack Materials (Ultra-Scaled)};
    B --> C{Pattern MIS Transistors for Smart Dust Mote};
    C --> D{Apply Shadow Mask for High-Vth Transistors};
    D --> E[Low-Temp UV-Ozone Oxidation (Selective)];
    E --> F[Increase Interface Layer Thickness (High-Vth Standby Logic)];
    F --> G{Remove Mask};
    subgraph Smart Dust Mote Fab
        C -- Lifetime Extension --> G
    end

Derivative 7.15: Quantum Random Number Generator (QRNG) Readout Circuit

• Enabling Description: A fabrication method for integrating readout circuits for quantum random number generators (QRNGs). Step (a) forms interface, high-k, and gate electrode films on a silicon substrate. Step (b) patterns these into MIS transistors for the QRNG's amplification and digitization stages. Step (c) selectively increases the interface layer thickness of transistors in the amplification stage (e.g., using pulsed plasma oxidation with atomic-scale control, with a selective hard mask). This creates high-Vth transistors for stable, low-noise amplification of quantum signals, and lower-Vth transistors for high-speed analog-to-digital conversion, ensuring accurate and fast extraction of quantum randomness. Gate electrodes are low-noise metal gates.

graph TD
    A[Silicon Substrate] --> B{Form Gate Stack Materials (Low-Noise)};
    B --> C{Pattern MIS Transistors for QRNG Readout};
    C --> D{Apply Hard Mask for High-Vth Amplification Transistors};
    D --> E[Pulsed Plasma Oxidation (Selective, Atomic-Scale)];
    E --> F[Increase Interface Layer Thickness (High-Vth Amplifiers)];
    F --> G{Remove Mask};
    subgraph QRNG Readout Circuit Fab
        C -- Randomness Extraction --> G
    end

---

4. Integration with Emerging Tech Derivatives (Claim 7)

Derivative 7.16: AI-Driven Online Process Optimization for Interface Layer Growth

• Enabling Description: The method for fabricating the semiconductor device (Claim 7) is augmented with an AI-driven online process optimization system for step (c) (selective interface layer thickening). Real-time metrology (e.g., in-situ ellipsometry, spectral reflectometry) monitors the interface layer thickness during oxidation (e.g., plasma oxidation). An AI agent (e.g., reinforcement learning controller) continuously analyzes the metrology data and dynamically adjusts process parameters (e.g., plasma power, gas flow, temperature, duration, or precursor ratios in ALD) to precisely achieve target interface layer thicknesses and uniformity across the wafer. This minimizes process variations and improves yield for diverse Vth transistors.

graph TD
    A[AI Controller] --> B{Process Parameter Adjustments};
    B -- Controls --> C[Oxidation Tool (Step c)];
    C --> D[Semiconductor Wafer];
    D -- Real-time Metrology --> E{Sensor Data (Thickness, Uniformity)};
    E --> A;
    subgraph AI-Driven Process Optimization
        C -- Feedback Loop --> A
    end

Derivative 7.17: Blockchain-Verified Manufacturing Traceability for Vth Control

• Enabling Description: The method includes blockchain-verified manufacturing traceability for the critical step (c) (selective interface layer thickening). Each wafer's processing parameters (e.g., oxidation time, temperature, plasma settings, measured interface layer thicknesses for both first and second gates, and specific masks used) for step (c) are cryptographically signed and recorded on a distributed ledger (blockchain). This immutable record provides an auditable history of Vth control, preventing unauthorized process deviations and ensuring authenticity and performance guarantees throughout the semiconductor supply chain, critical for high-reliability components.

sequenceDiagram
    participant Wafer
    participant OxidationTool
    participant Metrology
    participant BlockchainNetwork
    Wafer->>OxidationTool: Step (c) - Selective Interface Oxidation
    OxidationTool->>Metrology: Record Process Parameters
    Metrology->>Wafer: Measure Interface Layer Thickness
    Metrology->>BlockchainNetwork: Send Signed Process Data (Timestamp, Parameters, Results)
    BlockchainNetwork->>BlockchainNetwork: Validate & Add Block
    Note right of BlockchainNetwork: Immutable Record of Vth Control

Derivative 7.18: IoT Sensor-Enabled Predictive Maintenance for Oxidation Tools

• Enabling Description: The fabrication method incorporates IoT sensors for predictive maintenance of the oxidation tools used in step (c) (selective interface layer thickening). Critical operational parameters of the plasma oxidation or thermal oxidation tools (e.g., gas flow rates, chamber pressure, temperature profiles, plasma power, electrode wear, residual gas analysis) are continuously monitored by embedded IoT sensors. This data is transmitted to a cloud-based analytical platform. Machine learning algorithms analyze these trends to predict potential equipment failures or process drift before they impact the selective interface layer growth, ensuring consistent Vth control and preventing costly downtime.

graph TD
    A[Oxidation Tool (Step c)] --> B{IoT Sensors};
    B -- Stream Data --> C{Cloud Analytics Platform};
    C -- ML Analysis --> D{Predictive Maintenance Alerts};
    D --> E[Maintenance Crew];
    A -- Process Drift --> D;
    subgraph IoT-Enabled Predictive Maintenance
        A -- Monitoring --> C
    end

Derivative 7.19: Quantum-Annealing Optimized Mask Design for Selective Oxidation

• Enabling Description: Prior to executing step (c) (selective interface layer thickening), the photolithography mask design for selectively etching the insulating film (as per Claim 14) is optimized using quantum annealing. Given the complex interplay of oxygen diffusion, etch profiles, and desired interface layer thickness uniformity across a large chip area containing millions of transistors, traditional mask optimization is computationally intensive. Quantum annealing (e.g., using a D-Wave system) solves this combinatorial optimization problem, determining the optimal mask patterns and exposure doses to achieve the most precise and uniform differential interface layer growth, maximizing the yield of target Vth devices.

graph TD
    A[Desired Vth Profile] --> B{Formulate Optimization Problem};
    B --> C{Quantum Annealer (D-Wave)};
    C -- Optimal Solution --> D{Mask Design (Selective Etching)};
    D --> E[Photolithography Tool];
    E --> F[Wafer (Step c Masking)];
    subgraph Quantum-Optimized Mask Design
        B -- Computational Opt. --> D
    end

Derivative 7.20: Digital Twin for Real-time Process Simulation and Anomaly Detection

• Enabling Description: A digital twin of the entire fabrication line, specifically focusing on step (c) (selective interface layer thickening), is employed. This digital twin is a virtual model that mirrors the physical process, fed with real-time data from the fabrication equipment (e.g., metrology, sensor data). It runs high-fidelity simulations of oxygen diffusion, oxidation kinetics, and interface layer growth. Any deviation between the simulated and actual interface layer thickness or uniformity triggers an anomaly detection system, alerting operators to potential issues, allowing for immediate corrective action, and ensuring the precise Vth control for both the first and second MIS transistors.

graph TD
    A[Physical Oxidation Tool (Step c)] --> B{Real-time Sensor Data};
    B --> C{Digital Twin Platform};
    C -- High-Fidelity Simulation --> D[Predicted Interface Layer Growth];
    D -- Compare --> E{Actual Interface Layer Metrology};
    E -- Deviation Detected --> F{Anomaly Alert System};
    F --> G[Process Engineer];
    subgraph Digital Twin for Process Control
        A -- Replicates --> C
    end

---

Combination Prior Art Scenarios with Open-Source Standards

Here are three scenarios where US Patent 8,796,779 could be combined with existing open-source standards, demonstrating its applicability within broader, commonly known frameworks.

1. Combination with Open-Source Electronic Design Automation (EDA) Tools (e.g., OpenROAD Project)

• Scenario Description: The fabrication method described in Claim 7 of US8796779 (selectively increasing interface layer thickness to control Vth) is directly integrated into an OpenROAD-based physical design flow. OpenROAD is an open-source toolchain for RTL-to-GDSII chip design. Designers use OpenROAD to synthesize a digital circuit and perform place-and-route, defining the geometric layout of transistors. The library characterization for this design flow would include standard cell libraries that explicitly offer two versions of each standard cell (e.g., an inverter, a NAND gate): one built with the higher Vth transistors (i.e., having the thicker interface layer as per US8796779) for low-power operation, and another with lower Vth transistors (thinner interface layer) for high-performance paths. OpenROAD's power and timing analysis engines would then automatically select the appropriate Vth cells based on the design's performance and power constraints, using models derived from the process described in US8796779. The output GDSII layout would contain distinct markings or layers that guide the selective oxidation process described in Claim 14 during fabrication.

• Relevance as Prior Art: This combination renders obvious the integration of differential Vth transistors (achieved via interface layer engineering) into mainstream digital design flows. Any future patent attempting to claim "adaptive Vth selection in an automated design flow" for high-k/metal gate technologies, where Vth is based on interface layer thickness differences, would be anticipated by this combination. The manufacturing process of US8796779 becomes a standard library element accessible through an open-source design tool.

2. Combination with the RISC-V Instruction Set Architecture (ISA) Standard for Heterogeneous Cores

• Scenario Description: A System-on-Chip (SoC) implementing the RISC-V open-source instruction set architecture is designed with heterogeneous processing cores, leveraging the differential Vth transistors enabled by US8796779 (as claimed in Claim 1). For example, a low-power "microcontroller-class" RISC-V core (e.g., an RV32I core) on the SoC is built entirely using the higher-Vth transistors (first MIS transistor with thicker interface layer). A high-performance "application-class" RISC-V core (e.g., an RV64GC core) on the same SoC is constructed using the lower-Vth transistors (second MIS transistor with thinner interface layer). This allows the SoC to achieve both ultra-low power consumption for background tasks and high computational throughput for demanding applications, all within the RISC-V ecosystem. The manufacturing process for these cores would directly follow the methods of US8796779.

• Relevance as Prior Art: This combination establishes as prior art the architectural implementation of heterogeneous computing with RISC-V cores using the specific Vth tuning mechanism of US8796779. Any claims related to designing multi-core RISC-V processors with optimized power/performance characteristics through interface layer-tuned gate work functions would be challenged. It demonstrates the direct application of US8796779's device benefits to a widely adopted open-source hardware standard.

3. Combination with Open-Source Process Design Kits (PDKs) and Device Characterization Standards (e.g., OpenPDK, SkyWater 130nm PDK)

• Scenario Description: The fabrication methods and device structures of US8796779 are documented and released as part of an open-source Process Design Kit (PDK), similar to the SkyWater 130nm PDK or a generic OpenPDK framework. This PDK would include comprehensive SPICE models for both high-Vth and low-Vth transistors (of the same conductivity type), where the Vth difference is explicitly attributed to the varied interface layer thickness as per US8796779. The PDK also specifies layout rules for the selective oxidation process (e.g., defining the mask layers for selectively etching the insulating film in Claim 14). Furthermore, the characterization data for these transistors (e.g., IV curves, C-V curves, noise characteristics) is made publicly available following open-source device characterization standards (e.g., using open-source measurement automation scripts and data formats like CSV or JSON, which are common in academic and open-source hardware communities).

• Relevance as Prior Art: This combination broadly asserts that the specific techniques for differential Vth control described in US8796779, along with their associated design and characterization methods, are part of the public domain and integrated into open-source semiconductor design and verification ecosystems. Future claims regarding novel methods for generating PDKs for high-k/metal gate technologies with multiple Vth options via interface layer control, or any specific characterization methods for such devices, would be made obvious. It disseminates the technical knowledge of US8796779 as a foundational element within open hardware development.