US 7772673

I'll search for authoritative information on patent 7772673 from the USPTO and the CAFC 2026 dockets.

I found the PTAB record. Now let me search for the CAFC docket and USPTO database entries.

US Patent 7,772,673 (US7772673B1) — Summary

Note on identifier: I searched for "7772673" literally (patent number 7772673, publication US7772673B1, application US11/724,916). The results returned are all for this specific patent; I excluded similar numbers (e.g., IPR2024-01402 relates to a different Harbor Island patent and is not counted here).

Core bibliographic data

• Title: Deep trench isolation and method for forming same
• Patent/Publication No.: US7772673B1
• Application No.: US11/724,916
• Filing date: March 16, 2007
• Priority date: March 16, 2007
• Issue (grant) date: August 10, 2010
• Status: Active; adjusted expiration June 27, 2028 (maintenance fees paid through the 12th year)
• Inventors: Kevin Q. Yin; Amol Kalburge; David J. Howard; Arjun Kar-Roy; Dieter Dornisch
• Original assignee: Newport Fab, LLC dba Jazz Semiconductor (assignments recorded March 16, 2007)
• Current assignee of record: Harbor Island Dynamic LLC — per the recorded assignment chain (Newport Fab, LLC dba Jazz Semiconductor → name change to Newport Fab, LLC dba Tower Semiconductor Newport Beach, Dec. 2022 → assignment to Harbor Island Dynamic LLC, Mar. 2023). Confidence: high, based on USPTO assignment data reproduced on Google Patents; PubChem still lists the original Newport Fab assignee.

Abstract (verbatim from the record)

"According to one exemplary embodiment, a semiconductor die including at least one deep trench isolation region for isolating an electronic device (for example, a bipolar device) includes a trench situated in a substrate of the semiconductor die, where the trench has sides surrounding the electronic device, and where the trench has at least one trench chamfered corner formed between and connecting the sides of the trench. The at least one trench chamferred corner is formed between a chamfered corner of an outside wall of said trench and a corner of an inside wall of the trench. A trench corner width at the at least one trench chamfered corner is less than a trench side width along the sides of the trench."

Independent claims (17 total; claims 1 and 10 are independent)

Claim 1 — A semiconductor die having at least one deep-trench isolation region for isolating an electronic device. The region comprises a trench in the die's substrate whose multiple sides surround the electronic device, with at least one "trench chamfered corner" formed between and connecting those sides. The chamfered corner causes a reduction in the thickness of a polysilicon layer within the trench. Plain language: instead of a sharp, square corner where the trench turns, at least one corner is cut (chamfered), which lets the trench be filled with a thinner polysilicon deposit.

Claim 10 — A semiconductor die with at least one deep-trench isolation region for isolating an electronic device, where the trench has four sides surrounding the device and each pair of sides is connected by a respective one of four trench chamfered corners; each of the four chamfered corners causes a reduction in the thickness of the polysilicon layer within the trench. Plain language: the full-rectangle version of claim 1 — all four corners of a four-sided trench are chamfered to reduce the polysilicon fill thickness needed.

Dependent claims (2–9 depend on claim 1; 11–17 depend on claim 10) add: trench corner width less than trench side width (claims 2, 11); the chamfered corner lying between a chamfered corner of the outside wall and a corner of the inside wall (3, 12); an overlying field oxide region (4, 13); an oxide liner on the inside/outside walls (5, 14); a side width of about 1.0 micron (claim 6); the die being enclosed in a semiconductor package (7, 15); the device being a bipolar transistor (8, 16); and the device being a silicon-germanium (SiGe) bipolar transistor (9, 17).

Search results — USPTO database and CAFC 2026 dockets (current as of the search date)

• USPTO/PTAB (IPR2024-01403): [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Harbor Island Dynamic, LLC, petitioned September 20, 2024, against patent 7772673 (application 11724916). Institution decision March 24, 2025. Final Written Decision issued February 9, 2026, determining all challenged claims unpatentable under 35 U.S.C. § 318(a). (Source: PTAB/IPR database pages.)
• CAFC 2026 docket (26-1670): RPX Empower lists Harbor Island Dynamic LLC v. Samsung Electronics Co., Ltd., case 26-1670, filed April 15, 2026 — consistent with a patent-owner appeal of the IPR2024-01403 Final Written Decision. Confidence: moderate — only one listing was retrieved; I could not verify the full docket (briefing schedule, issues on appeal) from the search results available.

Uncertainty notes

• The CAFC docket 26-1670 detail is limited to a single RPX Empower entry (caption and filing date); the precise relief sought and any relationship to the parallel Texas Eastern District Court case (2:24-cv-00140) were not independently verified.
• The patent text (via Google Patents) and the PTAB record are internally consistent, and I prioritized those against the search results; no contradictions were found.

Litigation Involving U.S. Patent No. 7,772,673 B1

First, an important identification note: the patent at issue is 7,772,673 — "Deep trench isolation and method for forming same" (Newport Fab LLC → Harbor Island Dynamic, LLC). Do not confuse it with 7,779,267 (a distributed-computing/secure-token patent asserted in Lionra Tech Ltd v. [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.), No. 1:23-cv-00513, W.D. Tex.), which is a different patent with different litigation.

Based on searches of PTAB, district-court, Federal Circuit, and SEC sources (current as of April 26, 2026), the known matters involving US 7,772,673 are:

1. District Court — Harbor Island Dynamic, LLC v. [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.)

• Case No.: 2:24-cv-00140-JRG-RSP (E.D. Tex., Marshall Division)
• Filing date: February 27, 2024
• Plaintiff: Harbor Island Dynamic, LLC (HID)
• Defendants: Samsung Electronics Co., Ltd.; Samsung Electronics America, Inc.
• Patents-in-suit: 7,745,886; 7,772,673 ('673); 9,147,609; 9,245,826 — HID asserted claims 1, 3, 5, 7, 10, 12, 14, and 15 of the '673 patent against Samsung CMOS image sensors (e.g., S5KHM3SX) and downstream products (Galaxy S22 Ultra, Google Pixel 7 Pro, Motorola Moto G Stylus 5G)
• Judge: Rodney Gilstrap; Magistrate Judge Roy S. Payne
• Status: Pending as of HID's parent company's most recent disclosures (QPRC 10-K for FY2025 states the HID actions "are pending"). Samsung's motion to stay pending IPR was denied as premature (Dec. 2024); the parties proceeded through claim-construction (Joint Claim Construction & Prehearing Statement filed Apr. 15, 2025). The PTAB's February 2026 invalidation of the asserted claims (below) is highly likely to affect this case.
• Sources: RPX Empower (2:24-cv-00140); Justia/Docket Alarm filings; QPRC SEC filings; Ex Parte complaint analysis.

2. PTAB Inter Partes Review — Samsung Electronics Co., Ltd. et al. v. Harbor Island Dynamic, LLC

• Case No.: IPR2024-01403 (Patent 7,772,673 B1)
• Filing date: September 20, 2024
• Petitioners: Samsung Electronics Co., Ltd.; Samsung Electronics America, Inc.
• Patent Owner: Harbor Island Dynamic, LLC
• Institution: March 24, 2025 (instituted on all three grounds — obviousness over Yin + Koshimizu; anticipation by Norstrom; obviousness over Norstrom)
• Panel: Judges Hyun J. Jung, Gregg I. Anderson, Arthur M. Peslak
• Outcome: Final Written Decision (Feb. 9, 2026) — all challenged claims found unpatentable under 35 U.S.C. § 318(a)
• Status: FWD issued; patent owner has appealed (see #3 below)
• Sources: ipverse.greyb.com PTAB case page; Unified Patents PTAB portal; USPTO PTACTS records; oral-hearing transcript (DocketAlarm).

3. Federal Circuit Appeal — Harbor Island Dynamic LLC v. Samsung Electronics Co., Ltd.

• Case No.: 26-1670 (Court of Appeals for the Federal Circuit)
• Filing date: April 15, 2026
• Parties: Appellant Harbor Island Dynamic, LLC; Appellee Samsung Electronics Co., Ltd.
• Subject: Appeal of the IPR2024-01403 Final Written Decision invalidating the claims of the '673 patent
• Status: Newly filed; pending
• Sources: RPX Empower Federal Circuit docket (26-1670); Google Patents litigation links for US7772673B1; QPRC SEC filing (confirming HID "has appealed the decision with respect to U.S. Patent 7,772,673").

4. Possibly Related District Court Action — Harbor Island Dynamic, LLC v. NXP Semiconductors N.V. et al.

• Case No.: 2:24-cv-00717-JRG-RSP (E.D. Tex.)
• Filing date: August 30, 2024
• Plaintiff: Harbor Island Dynamic, LLC
• Defendants: NXP Semiconductors N.V. and numerous NXP subsidiaries
• Note: HID's own mandatory notices in IPR2024-01403 (the '673 IPR) list both the Samsung action and this NXP action as pending district court cases relating to the '673 patent. However, publicly available analysis of the NXP amended complaint centers on the '886 patent (7,745,886) and the NXP TDF8530TH amplifier, and NXP's own IPR (IPR2025-00954) targets only the '886 patent. Whether the '673 patent remains asserted in the NXP case is not clear from the available sources.
• Status: Pending
• Sources: Justia docket; USPTO PTACTS mandatory notices (IPR2024-01403); Ex Parte complaint analysis.

Summary Table

Caveats: I could not access PACER directly in these searches, so filing dates and statuses are drawn from secondary docket services (RPX, Justia, DocketAlarm, ipverse), PTAB/USPTO records, and HID parent-company QPRC's SEC filings, which are consistent with one another. The most authoritative current status for the district cases would require a PACER check. No litigation involving the '673 patent prior to 2024 was found — it appears to have been first asserted after Harbor Island Dynamic acquired the Newport Fab/Tower portfolio (assignment recorded March 2023).

I found the core IPR docket. Now let me dig into the institution decision, the prior art references (Norstrom, Koshimizu), and the CAFC appeal.

Good progress. I have the panel, grounds, and prior art identities (Yin = US 6,995,449; Koshimizu = US 2005/0181569 A1; Norstrom = US 6,121,102). Now let me try to find the FWD opinion itself and more detail on the CAFC appeal.

Proceedings overview

There is one AIA trial proceeding on US 7,772,673 — IPR2024-01403 — and it ended in a Final Written Decision (2026-02-09) determining all challenged claims (1–17) unpatentable. That means: 0 active PTAB proceedings, 0 settled, 0 institution-denied, and every claim of the patent invalidated in an unappealed-from (so far) FWD — except that the patent owner has appealed to the Federal Circuit (case 26-1670, filed 2026-04-15), so formal claim cancellation under 35 U.S.C. § 318(b) awaits the appeal's outcome. Bottom line for a defendant: the entire claim set of the '673 patent has been adjudicated unpatentable; a demand letter citing claims 1–17 has no viable merits position unless the CAFC reverses.

Flag on the structured data: The "PTAB proceedings on file" block (USPTO ODP ingest) shows "no AIA trial proceedings on file" — that ingest is stale. PTAB docket sources confirm IPR2024-01403 was filed 2024-09-20, instituted 2025-03-24, and terminated by FWD 2026-02-09 (e.g., ipverse PTAB case page; Unified Patents portal).

IPR2024-01403 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Harbor Island Dynamic, LLC

• Type: Inter Partes Review
• Filed: 2024-09-20
• Status: Structured data block says "no AIA trial proceedings on file" (stale ODP ingest). Actual PTAB status: "Final Written Decision" — terminated 2026-02-09. Plain English: the trial is over; the Board invalidated every challenged claim.
• Judge panel: Administrative Patent Judges Hyun J. Jung, Gregg I. Anderson, and Arthur M. Peslak — confirmed from the record of the consolidated oral hearing held 2026-01-06 (transcript entered 2026-01-22). I could not verify from available sources which judge authored the FWD.
• Petition grounds (instituted in full, per the 2025-03-24 Decision Granting Institution, Paper 9):
  • Ground 1: Claims 1–17 unpatentable under § 103 as obvious over Yin (US 6,995,449) in view of Koshimizu (US 2005/0181569 A1).
  • Ground 2: Claims 1, 3, 5, 7–8, 10, 12, 14–16 unpatentable under § 102 as anticipated by Norstrom (US 6,121,102).
  • Ground 3: Claims 7 and 15 unpatentable under § 103 over Norstrom.
  • Petitioner's expert: Scott E. Thompson, Ph.D. Petitioner counsel: Joshua Goldberg et al. (Finnegan); pro hac vice admission granted for Alexander E. Harding (2025-12-19). Patent owner counsel: Joseph Mercadante and Richard Cowell (Fabricant LLP); PO expert: John Berg.
• Institution decision: Granted on all three grounds — 2025-03-24 (Paper 9). On the disputed analogous-art question for Ground 1, the Board preliminarily found that "both the '673 patent and Koshimizu relate to semiconductor devices (and methods of manufacturing semiconductor devices) with a deep trench for isolating a bipolar device" (Paper 9 at 27, as quoted in the record). Patent owner's request for Director Review of institution was denied 2025-04-22 (order covering the related IPR2024-01402 through -01405 family).
• Final Written Decision (2026-02-09): The judgment entry is titled "Final Written Decision Determining All Challenged Claims Unpatentable 35 U.S.C. § 318(a)". Because Ground 1 challenged all of claims 1–17 (with claims 1, 3, 5, 7–8, 10, 12, 14–16 also under Ground 2, and claims 7 and 15 under Ground 3), the FWD's "all challenged claims" determination sweeps in every claim of the patent — claims 1 through 17. Caveat: I could not retrieve the full FWD text from available sources, so I cannot state which specific ground(s) the Board relied on for which claims, nor quote the panel's merits reasoning beyond the judgment entry. The parties' appellate-stage arguments (from the 2026-01-06 hearing transcript) centered on: (1) whether Koshimizu is analogous art (PO's sole Ground 1 defense) and (2) whether Norstrom's deep isolation trench has chamfered corners and is "situated in the substrate" (PO's sole Grounds 2–3 defense) — with PO also disputing how Norstrom's figures 13A/13C line up. The Board rejected those defenses in the FWD.
• Settlement / termination: No settlement. Case terminated by the FWD on 2026-02-09.
• Appeal: Yes. Patent owner Harbor Island Dynamic LLC appealed to the Federal Circuit — Harbor Island Dynamic LLC v. Samsung Electronics Co., Ltd., No. 26-1670, filed 2026-04-15 (per RPX Empower CAFC docket listing; confidence: moderate — I could not retrieve briefing, issues, or disposition from available sources). Timing is consistent with a timely appeal of the 2026-02-09 FWD (notice of appeal filed with the Director within the 63-day window; docketed at the CAFC 2026-04-15). This IPR is part of the same campaign as the underlying EDTX case, Harbor Island v. Samsung, No. 2:24-cv-00140 (Texas Eastern District Court), where the court earlier denied a stay pending IPR (Dkt. 62).
• Defensive value: Maximum available. Every claim (1–17) of US 7,772,673 has been determined unpatentable in a final written decision — the strongest possible PTAB outcome. Any infringement theory built on the '673 patent is now built on claims the Board has found unpatentable; the only live risk is the patent owner's pending CAFC appeal, which must overcome the Board's factual findings under a deferential substantial-evidence standard.

Strategic summary

Claims: CANCELED (determined unpatentable) vs. SUSTAINED vs. UNTESTED. The FWD in IPR2024-01403 determined all challenged claims unpatentable — claims 1 through 17, which is the patent's entire claim set (independent claims 1 and 10 plus all dependents 2–9 and 11–17). No claim was sustained, and no claim was left untested. Because Harbor Island has appealed (CAFC 26-1670), the USPTO has not yet issued the § 318(b) certificate formally canceling the claims; that certificate will issue once the appeal is resolved (or dismissed). Until then, the claims technically remain on the register, but the operative PTAB adjudication is an unpatentability determination as to every one of them.

Estoppel landscape. Under 35 U.S.C. § 315(e)(2), Samsung (and its privies) is barred from asserting in the EDTX litigation — or any other district-court or ITC proceeding — any invalidity ground it raised or reasonably could have raised in IPR2024-01403. But Samsung already won the IPR, so that estoppel is not a burden here; it is protection against the patent owner trying to force Samsung to re-litigate validity. For a different defendant, § 315(e)(2) imposes no estoppel at all, and the full, now battle-tested arsenal remains available: Yin (US 6,995,449), Koshimizu (US 2005/0181569 A1), Norstrom (US 6,121,102) — plus state-of-the-art references surfaced in the record (US 6,362,040; US 5,104,816; JP 3141621 B2 (Matsuzaki); Wolf; Moens). Once the CAFC appeal is final (or the FWD becomes final through affirmance/dismissal), a new defendant can also invoke the FWD itself for issue-preclusion/collateral-estoppel effect against the patent owner on these claims and grounds.

Pattern signals. This is not an isolated attack. Samsung filed four coordinated IPRs on the same day (2024-09-20) against Harbor Island Dynamic LLC patents: IPR2024-01402 (US 7,745,886), IPR2024-01403 (US 7,772,673 — this patent), IPR2024-01404 (US 9,147,609), and IPR2024-01405 (US 9,245,826) — all tied to the same EDTX litigation (2:24-cv-00140). The '673 patent's FWD was decided in a consolidated oral hearing with IPR2024-01405, and the Director Review denial order covered the whole family. Harbor Island is a patent-monetization entity (chain of title: Newport Fab/Jazz → Newport Fab dba Tower Semiconductor Newport Beach → Harbor Island Dynamic LLC, 2023). The "Unified Patents" labels on the Google Patents record are data-provider attributions, not party status — Unified is not the petitioner. The patent owner's posture is aggressive: it sought Director Review of institution (denied 2025-04-22) and has already appealed the FWD to the Federal Circuit (26-1670). If you are sued on a sibling Harbor Island patent, expect the same petitioner-side playbook and the same PO-side appellate tenacity.

Recommended next steps

• If you are the defendant facing assertion of the '673 patent today: the FWD in IPR2024-01403 (2026-02-09) is your dispositive document. Obtain the full decision (PTAB record via Unified Patents portal or the ipverse case page) and move to stay or terminate any action or arbitrate any demand based on claims 1–17. In the parallel EDTX case (2:24-cv-00140), the stay was denied before the FWD; that calculus has now changed — renew the request. If you are not Samsung, no § 315(e)(2) estoppel binds you, and you may rely on the same Yin/Koshimizu/Norstrom grounds or on the FWD itself once final.
• Monitor CAFC appeal 26-1670 (Harbor Island Dynamic LLC v. Samsung Electronics Co., Ltd., filed 2026-04-15): the patent owner bears the burden of showing the Board erred on the analogous-art and Norstrom factual findings, which get substantial-evidence deference. The § 318(b) cancellation certificate — and thus formal removal of claims 1–17 from the patent — issues after that appeal concludes. A defendant should track the briefing schedule and be ready to cite the CAFC mandate.
• Check the sibling patents if your exposure is broader: the same campaign covers US 7,745,886 (IPR2024-01402), US 9,147,609 (IPR2024-01404), and US 9,245,826 (IPR2024-01405). If a demand letter cites any of those, the '673 FWD and hearing record are strong evidence of the pattern but are not dispositive as to those patents — verify each proceeding's status separately.
• If no action is pending against you yet: the '673 patent's assertion value is now near zero — every claim has an unpatentability determination against it, and only a successful CAFC appeal by the patent owner could revive it. Treat any future demand letter citing the '673 patent as a bad-faith candidate and respond with the FWD.

Confidence notes: The existence, grounds, institution, panel, hearing, and FWD outcome for IPR2024-01403 are well corroborated across PTAB/docket sources. I could not retrieve the full FWD opinion text, the FWD's ground-by-ground reasoning, or the CAFC 26-1670 briefing from available searches — those specifics are flagged above rather than assumed.

Inventors

All five named inventors executed the original assignment to their employer on March 13–14, 2007 (recorded 2007-03-16, Reel 019097/0316):

• Kevin Q. Yin — Newport Fab, LLC (dba Jazz Semiconductor), Newport Beach, CA
• Amol Kalburge — Newport Fab, LLC (dba Jazz Semiconductor)
• David J. Howard — Newport Fab, LLC (dba Jazz Semiconductor)
• Arjun Kar-Roy — Newport Fab, LLC (dba Jazz Semiconductor)
• Dieter Dornisch — Newport Fab, LLC (dba Jazz Semiconductor)

Pattern note: this is an ordinary employee-to-employer assignment made at filing; nothing unusual is documented about post-filing departures. The subject matter (deep trench isolation for SiGe BiCMOS) matches Jazz Semiconductor's core foundry process portfolio.

Original assignee

Newport Fab, LLC dba Jazz Semiconductor (later Newport Fab, LLC dba Tower Semiconductor Newport Beach), Newport Beach, CA — a specialty analog/mixed-signal foundry offering SiGe BiCMOS and RF CMOS processes.

• Shipped a product embodying the claims? Yes — deep-trench isolation was a standard element of Jazz's (now Tower's) BiCMOS process flows; this was process-technology IP, not a paper patent.
• Current status: Operating. Jazz Technologies sold Newport Fab to Tower Semiconductor in 2008; the entity operates today as part of Tower Semiconductor (Tower Semiconductor Newport Beach). The name change to "dba Tower Semiconductor Newport Beach" was recorded 2022-12-08 (Reel 062102/0979, effective 2021-05-12).

Assignment timeline

• 2007-03-13/14 (executed) / recorded 2007-03-16 — Reel 019097/0316

  • Conveyance: Assignment of Assignors Interest (see document for details)
  • Assignor: Kevin Q. Yin, Amol Kalburge, David J. Howard, Arjun Kar-Roy, Dieter Dornisch
  • Assignee: Newport Fab, LLC dba Jazz Semiconductor
  • Correspondent: not verified from available records (original employee-assignment filing; Google Patents reproduces the reel/frame but not the correspondent)
  • Context: inventors assigning rights to their employer at filing.

• executed 2021-05-12 (effective date) / recorded 2022-12-08 — Reel 062102/0979

  • Conveyance: Change of Name
  • Assignor: Newport Fab, LLC dba Jazz Semiconductor
  • Assignee: Newport Fab, LLC dba Tower Semiconductor Newport Beach
  • Correspondent: not verified from available records
  • Context: internal reorg / name change only; reflects Tower Semiconductor branding of the former Jazz foundry. No change in beneficial ownership.

• executed 2023-02-02 / recorded 2023-03-24 — Reel 063094/0412

  • Conveyance: Assignment of Assignors Interest (see document for details)
  • Assignor: Newport Fab, LLC d/b/a Tower Semiconductor Newport Beach, Inc.
  • Assignee: Harbor Island Dynamic LLC, 505 East Travis St Ste 114, Marshall, TX 75670 (registered-agent address in the Marshall, E.D. Tex. venue)
  • Correspondent: Scahill Law PLLC, 411 Theodore Fremd Ave Ste 206S, Rye, NY 10580 — this is the monetization-lawyer tell on the transfer-to-asserter link (per RPX Insight record for this reel; not the same attorney class as the 2007 employee-assignment filing)
  • Context: sale of a 7-patent portfolio (including '673) to a newly formed, single-purpose LLC that is a wholly owned subsidiary of Quest Patent Research Corporation; per QPRC SEC filings, purchase price $3.3M with Tower retaining a back-end percentage of net proceeds. Assets conveyed: 7 patents (RPX Insight).

Timeline diagram

timeline
    title Ownership of US 7772673
    2007 : Filed by Newport Fab LLC
         : Inventors assign rights
    2008 : Tower acquires Jazz
    2010 : Patent issued
    2021 : Renamed Tower Newport Beach
    2023 : Sold to Harbor Island Dynamic LLC
    2024 : Suit vs Samsung in E D Texas
    2026 : IPR loss at PTAB
         : Appeal to Federal Circuit

NPE / troll-pattern signals

1. Shell-entity transfer — present. Reel 063094/0412 (recorded 2023-03-24) moved the patent from an operating foundry to Harbor Island Dynamic LLC, a single-member, single-portfolio LLC at a Marshall, TX registered-agent address. QPRC's own materials describe Harbor Island Dynamic as a "newly formed wholly-owned subsidiary" created to hold the portfolio acquired from Tower. Concrete evidence, not naming alone: no products, subsidiary of a monetization company, EDTX registered-agent address.

2. Known asserter in the chain — present. Harbor Island Dynamic LLC is the wholly owned subsidiary of Quest Patent Research Corporation (QPRC), a publicly traded (OTC) patent monetization company with a long assertion history. QPRC's Form 8-K (received 2024-10-31) describes the "Harbor Island Dynamic LLC Portfolio" of 7 patents and lists pending EDTX cases vs Samsung and NXP. Unified Patents independently lists Harbor Island's EDTX case 2:24-cv-00140 against Samsung and the PTAB proceeding IPR2024-01403.

3. Repeat correspondent across the chain — unclear. The one post-issuance transfer of substance (Reel 063094/0412) was filed by Scahill Law PLLC (Rye, NY) — a patent-monetization filer. Correspondents for Reels 019097/0316 and 062102/0979 could not be verified from the records retrieved, so true recurrence within this chain cannot be established. Flagged, but not counted as a standalone finding.

4. Cascading transfers — not present. Only three recorded events over 16 years: the 2007 employee assignment, a 2021/2022 name change, and a single 2023 LLC transfer. No chained LLC-to-LLC movement.

5. Pre-litigation transfer — not present (strictly). The sale to HID was effective 2023-02-02 and recorded 2023-03-24; the first EDTX suit (2:24-cv-00140) was filed ~2024-02-27 — roughly 12 months later, outside the 6-month window. Contextually the transfer was plainly made to enable assertion, but it fails the 6-month test.

6. Bankruptcy fire-sale — not present. Newport Fab/Jazz was acquired by Tower Semiconductor in a going-concern transaction; no Chapter 7/11 patent-sale proceeding.

7. Privateering — present. Per QPRC's SEC filings (8-K, Oct. 2024; investor materials), Tower Semiconductor sold the portfolio to QPRC/HID for $3.3M while retaining entitlement to "a percentage of further net proceeds" after QPRC recoups purchase price plus a negotiated return. The operating foundry keeping a back-end revenue interest in an NPE's recoveries against foundry competitors (Samsung, NXP) is the classic privateering economics.

8. Defensive aggregator (anti-NPE) — not present. The chain terminates at Harbor Island Dynamic LLC / QPRC, an assertion vehicle — not RPX, AST, LOT, Unified Patents, or OIN.

Verdict

NPE — high confidence.

Two-plus strong signals: (a) the patent was transferred via Reel 063094/0412 (recorded 2023-03-24) to a single-purpose Marshall, TX LLC that is the wholly owned subsidiary of QPRC, a publicly traded patent-monetization company; and (b) privateering economics — Tower Semiconductor retains a percentage of net proceeds from QPRC/HID assertions per QPRC's SEC filings, while HID sued Samsung in EDTX (2:24-cv-00140) and defended IPR2024-01403, losing on all challenged claims in the Final Written Decision of 2026-02-09 (appeal docketed at the CAFC as 26-1670 on 2026-04-15). The original Reel 019097/0316 (2007) and Reel 062102/0979 (2022 name change) links are unremarkable; the NPE character comes entirely from the documented 2023 sale and subsequent assertion.

Verification: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search patent number 7772673; reels 019097/0316, 062102/0979, 063094/0412). RPX Insight record for Reel 063094/0412: https://litigation.rpxcorp.com/patent_assignment/59542404

Confidence caveat: correspondents for the 2007 and 2022 recordings were not independently verified; the correspondent analysis rests on the RPX Insight listing for Reel 063094/0412 (Scahill Law PLLC). All assignment dates, parties, and reel/frame numbers otherwise trace to USPTO assignment records reproduced on Google Patents and RPX Insight.

I'll research the cited prior art references for US Patent 7,772,673. Let me start by confirming the patent's cited references and searching for details on each.

I have solid data on the two examiner-cited references. Let me also verify the prior art references used in IPR2024-01403 (Norstrom, Koshimizu, Yin), which bear on the "most relevant prior art" analysis, and check the USPTO record for any additional cited art.

The picture is now clear. Let me confirm the identities and details of the three IPR references (Yin, Koshimizu, Norstrom) and the Final Written Decision's claim-by-claim outcome.

I have reached the limit of available search steps, so I will now answer based on the verified information gathered, flagging any residual uncertainties explicitly.

Prior Art Analysis — U.S. Patent No. 7,772,673 B1 ("Deep trench isolation and method for forming same")

A. Identification / scope note

This analysis concerns only US 7,772,673 B1 (application US 11/724,916, filed 2007-03-16, granted 2010-08-10, inventors Yin/Kalburge/Howard/Kar-Roy/Dornisch, now owned by Harbor Island Dynamic LLC). No similar-numbered patents are included. The "patent citations" appearing on the face of the '673 patent — as shown in the USPTO/Google Patents record — are exactly two references, both marked "* Cited by examiner":

1. US 5,933,749 A
2. US 6,107,161 A

Because the question also asks for the "most relevant prior art," Section D below separately covers the three references applied in IPR2024-01403 (Samsung v. Harbor Island Dynamic), which the PTAB found to render the claims unpatentable in a Final Written Decision dated February 9, 2026.

B. Claim elements relevant to § 102 anticipation

The '673 patent has 17 claims; claims 1 and 10 are independent. For anticipation purposes the critical limitations are:

• Claim 1: a semiconductor die with at least one deep trench isolation region for isolating an electronic device; a trench situated in a substrate; the trench has a plurality of sides surrounding the electronic device; at least one "trench chamfered corner" formed between and connecting the sides; and that chamfered corner causes a reduction in the thickness of a polysilicon layer within the trench.
• Claim 10: same die, but with four sides and four trench chamfered corners, each connecting a pair of sides, each causing a reduction in polysilicon-layer thickness.
• Key dependent claims: corner width < side width at the chamfer (2, 11); chamfer located between a chamfered corner of the outside wall and a corner of the inside wall (3, 12); an overlying field oxide region (4, 13); an oxide liner on inside/outside walls (5, 14); side width ≈ 1.0 µm (6); die enclosed in a semiconductor package (7, 15); device is a bipolar transistor (8, 16); device is a SiGe bipolar transistor (9, 17).

Critically, the claimed "trench chamfered corner" is a plan-view (top-view) geometry — the corner of a rectangular isolation trench is cut off in the horizontal plane where two trench sides intersect, reducing the perpendicular distance between the outside-wall chamfer edge and the inside-wall corner.

C. The two examiner-cited references on the face of the '673 patent

1. US 5,933,749 A — "Method for removing a top corner of a trench"

• Assignee: United Microelectronics Corp.
• Filing date: October 27, 1997
• Grant date: August 3, 1999
• Verified from: USPTO PDF (patentimages.storage.googleapis.com) and Google Patents citation records.
• Brief description: A process for rounding/removing the top corner of a trench in cross-section. After an oxide layer and nitride layer are formed over a substrate and trenches are etched, a mask with openings wider than the trenches is used with a dry etch to remove the sharp ~90° corner where the trench sidewall meets the wafer surface, forming a sloped/"grading corner." Purpose: avoid charge accumulation, point discharge, leakage, and the "kink effect" at the upper rim of the trench (e.g., in DRAM trench processing).
• § 102 anticipation analysis: Does not anticipate any claim (claims 1–17).
  • The '673 claims require a plan-view chamfered trench corner between and connecting the sides of a trench that surrounds an electronic device. US '374 operates on an entirely different corner: the vertical cross-sectional top corner of a trench (sidewall-to-top-surface junction), not the horizontal corner between two intersecting trench sides. (Specification of '673 distinguishes this same distinction at FIG. 1 vs. FIG. 2.)
  • It does not disclose: a deep trench isolation region surrounding/isolating an electronic device in a die; a polysilicon trench fill; any teaching that corner geometry reduces polysilicon deposition thickness; an oxide liner on inside/outside walls of an isolation trench; a field oxide region overlying the isolation trench; or a bipolar/SiGe device.
  • At most it is tangential § 103 art for the general concept of shaping trench corners to improve processing — but of a different corner orientation and in a different context (DRAM trench capacitors, not bipolar isolation). No single reference discloses every element of claims 1 or 10.

2. US 6,107,161 A — "Semiconductor chip and a method for manufacturing thereof"

• Assignee: Rohm Co., Ltd.
• Priority date: June 6/7, 1996 (earliest priority; per the Google Patents citation entry, 1996-06-07)
• Application No.: 09/019,896, filed February 5, 1998
• Grant date: August 21/22, 2000
• Verified from: Google Patents and Unified Patents portal records.
• Brief description: A chip-singulation/dicing technology. Cutting grooves wider than the dicing scribe line are formed on the wafer so groove walls are "set back" from the eventual cutting plane, protecting die sidewalls from saw damage. Notably, near the intersections of the cutting grooves the set-back is made larger, and the intersections are formed with a smoothly rounded (substantially circular-arc) shape in top view, obtained by heat-expanding a resist mask whose intersection patterns are smoothly connected.
• § 102 anticipation analysis: Does not anticipate any claim (claims 1–17).
  • The claimed chamfered corner belongs to a deep trench isolation region that surrounds and electrically isolates an electronic device and that is filled with polysilicon, with the chamfered corner reducing the required polysilicon thickness. US '161 concerns dicing/scribing grooves at the wafer perimeter between dies — not isolation trenches, not device isolation, and not polysilicon-filled structures.
  • While US '161 does teach the general plan-view concept of removing sharp intersections/edges of grooves (smooth circular-arc corners at groove crossings) — which is conceptually closer to the '673 geometry than US '374 is — it lacks every claimed structural context: no deep trench isolation region, no trench "situated in the substrate" surrounding an electronic device for isolation, no oxide liner on the trench walls, no polysilicon filling (and no disclosure that corner shape reduces polysilicon fill thickness), and no field oxide overlying the trench.
  • Conclusion: no § 102 anticipation of claims 1–17.

Bottom line for the two face-of-patent citations: both are weak, non-anticipating references from adjacent technical spaces (trench top-corner rounding for DRAM; dicing-groove corner rounding for singulation). Neither was relied on in the IPR.

D. Most relevant prior art — references applied in IPR2024-01403 (PTAB, Samsung v. Harbor Island Dynamic)

The PTAB instituted (March 24, 2025) on three grounds and issued a Final Written Decision on February 9, 2026 determining all challenged claims unpatentable. The three substantive references (per the ipverse/PTAB exhibit list and the January 2026 consolidated oral-hearing transcript) are:

1. Norstrom — US 6,121,102 (primary anticipation reference)

• Verified from: IPR2024-01403 exhibit list ("US 6,121,102 – Norstrom") and hearing transcript. Caveat: I could not verify the exact title/issue date of US 6,121,102 from a primary source in my searches; the functional description below is drawn from the IPR record.
• Description per IPR record: Directed to the manufacture of bipolar semiconductor devices — bipolar transistors and semiconductor diodes — electrically isolated or confined by trenches. Per the hearing transcript, Samsung argued Norstrom discloses a deep isolation trench situated in the substrate with chamfered corners, and Patent Owner conceded that "other than [claim 1's] isolation trench [features], Norstrom meets every element of every challenged claim" on the Norstrom grounds — disputing only (a) whether Norstrom's deep isolation trench has "a plurality of chamfered trench corners" and (b) whether it is "situated in the substrate."
• § 102 anticipation mapping (instituted Ground 2): anticipation of claims 1, 3, 5, 7–8, 10, 12, and 14–16. These map cleanly onto the claim elements: die + deep trench isolation region (1, 10); chamfer between outside-wall chamfer and inside-wall corner (3, 12); oxide liner on inside/outside walls (5, 14); die in a semiconductor package (7, 15); electronic device is a bipolar transistor (8, 16). Claims 2, 4, 6, 9, 11, 13, 17 were not mapped to Norstrom anticipation (consistent with Norstrom lacking, e.g., corner-width < side-width measurements, a field oxide overlying the trench, the ~1.0 µm dimension, and SiGe-device recitations). A separate Ground 3 covered claims 7 and 15 by obviousness over Norstrom. The Board's FWD (Feb. 9, 2026) found the challenged claims unpatentable.
• Caveat: I did not retrieve the FWD text itself; the per-claim anticipation holding is characterized from the institution decision structure and the hearing transcript, which are mutually consistent.

2. Yin — US 6,995,449 (obviousness primary reference, Ground 1)

• Verified from: IPR exhibit list ("US 6,995,449 – Yin"). Caveat: full bibliographic details (title, issue date) not verified in my searches.
• Description per IPR record: A semiconductor die with a deep trench isolation region that electrically isolates an electronic device, such as a bipolar transistor — i.e., the same structural field as the '673 patent (indeed, likely from the same Jazz/Newport Fab engineering community; "Yin" is a surname shared with '673 inventor Kevin Q. Yin, which is relevant to § 102(f)/inventorship considerations only if the inventive entities overlap — not asserted here).
• § 102/103 role: Not asserted for anticipation. Yin + Koshimizu (Ground 1) = obviousness of all claims — Yin supplying the die/DTI/bipolar-device structure and Koshimizu supplying the chamfered-corner isolation-trench teaching. If Yin lacks an express chamfered-corner disclosure, it would not alone anticipate claims 1 or 10 (which require the chamfered corner); I could not verify Yin's drawings/text in my searches to make a definitive standalone-anticipation call.

3. Koshimizu — US 2005/0181569 A1 (obviousness secondary reference, Ground 1)

• Verified from: IPR exhibit list and PTAB institution decision ("US 2005/0181569 A1 – Koshimizu"). Caveat: exact publication date not independently retrieved; the number format indicates a 2005 publication, which is well before the '673's 2007-03-16 priority date, and it was treated as prior art in the IPR.
• Description per IPR record: A semiconductor-device manufacturing disclosure, specifically for a heterojunction bipolar transistor (HBT) formed with a deep isolation trench having chamfered corners. Patent Owner's briefs characterized Koshimizu as disclosing a chamfered isolation trench filled with silicon oxide (not polysilicon) and as giving little or no detail on trench fabrication/polysilicon fill — the basis of HID's (unsuccessful) argument that Koshimizu was non-analogous art.
• § 102/103 role: Asserted only in combination (obviousness). Because Koshimizu's isolation trench is described as oxide-filled and focused on HBT manufacture, it is unlikely alone to anticipate claim 1 (which functionally requires the chamfered corner to reduce polysilicon layer thickness) — but its plan-view chamfered isolation-trench geometry is exactly the feature the PTAB credited as making the combination obvious.

E. Summary table

F. Caveats and source hierarchy

• The two face-of-patent citations (US 5,933,749 and US 6,107,161) are verified directly from the USPTO/Google Patents record and the patent PDF; the descriptions and non-anticipation conclusions are my analysis based on those full texts.
• The IPR references were verified by number/inventor from the PTAB/IPR exhibit list (ipverse, Unified Patents, PTAB hearing transcripts). I could not independently verify the full titles, issue/publication dates, or complete disclosures of US 6,121,102 (Norstrom), US 6,995,449 (Yin), or US 2005/0181569 A1 (Koshimizu) within the available search steps, and I did not retrieve the text of the February 9, 2026 Final Written Decision. The per-claim anticipation mapping for Norstrom reflects the instituted Ground 2 scope (claims 1, 3, 5, 7–8, 10, 12, 14–16) as confirmed in the consolidated hearing transcript, not an independent reading of the FWD.
• Net result for the user's core question: the two references printed on the face of US 7,772,673 do not anticipate any claim under 35 U.S.C. § 102; the art actually found to invalidate the claims in IPR2024-01403 — principally Norstrom (US 6,121,102) for anticipation of claims 1, 3, 5, 7–8, 10, 12, 14–16, and Yin (US 6,995,449) + Koshimizu (US 2005/0181569 A1) for obviousness of all claims — is the most relevant prior art as of the current date (April 26, 2026).

Obviousness Analysis of U.S. Patent No. 7,772,673 B1 ("Deep Trench Isolation and Method for Forming Same") Under 35 U.S.C. § 103

Identification note. This analysis concerns patent 7,772,673 (US7772673B1; application 11/724,916). It does not concern the similarly numbered but unrelated patent 7,779,267 (Lionra/Apple, W.D. Tex.).

1. The claimed invention in one paragraph

The '673 patent claims a semiconductor die having a deep-trench isolation region whose trench surrounds an electronic device (e.g., a bipolar transistor). The claimed advance is the "trench chamfered corner": instead of the rectangular trench with square 90° corners shown in its own Figure 1 (which the patent labels "conventional"), at least one corner (claim 1) or all four corners of a four-sided trench (claim 10) is chamfered — i.e., a corner region lying between a chamfered corner of the trench's outside wall and a corner of its inside wall (claims 3/12), with the corner width made smaller than the side width (claims 2/11). The chamfered corner is functional: it "causes a reduction in a thickness of a polysilicon layer within said trench." The patent's own economic justification is that the square-cornered rectangular trench of Figure 1 required roughly 1.5 µm of conformal polysilicon to fill its 1.4 µm-wide corner regions (versus a 1.0 µm side width), and chamfering to a ~0.9 µm corner width cuts the needed deposit to ~0.7 µm, roughly doubling fill throughput and extending furnace-cleaning intervals.

2. Legal framework

Obviousness under 35 U.S.C. § 103 (pre-AIA, which governs this 2007 filing) is assessed under Graham v. John Deere (the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill, and secondary considerations), informed by KSR Int'l Co. v. Teleflex Inc.: a patent claim is unpatentable when the improvement is a combination of known prior-art elements according to known methods yielding predictable results, a design choice, or the product of an obvious-to-try substitution, even absent an express teaching, suggestion, or motivation in the references.

3. The person of ordinary skill in the art (PHOSITA)

Based on the expert testimony of record in IPR2024-01403 (petitioner's expert, Dr. Scott E. Thompson) and the technology at issue, a PHOSITA would have (i) an advanced degree or equivalent experience in electrical engineering, materials science, or physics; (ii) several years of experience in semiconductor device fabrication, including formation of isolation structures (field oxide, shallow/deep trenches) in bipolar/BiCMOS flows; and (iii) working knowledge that deep trenches around bipolar devices are conformally refilled with dielectric or polysilicon and that local trench width governs the fill thickness required at that location.

4. Prior-art inventory

(a) The patent's own admitted prior art (Figure 1)

The specification itself concedes the rectangular, 90°-cornered deep trench of its Figure 1, with corner width 1.4 µm vs. side width 1.0 µm, depth ~7 µm, oxide liner ~1000 Å, requiring ~1.5 µm of polysilicon to fill — and that the thick deposit "significantly reduce[s] polysilicon fill process throughput" and causes "polysilicon flaking," increasing furnace cleaning and cost. That admission defines the problem the claims solve: excessively wide square corners force overfilling of the rest of the trench.

(b) References cited on the face of the patent (the "Prior Art" section of the record)

Two references are cited (both "cited by examiner"):

• US 5,933,749 (United Microelectronics Corp.; filed Oct. 27, 1997; issued Aug. 3, 1999) — "Method for removing a top corner of a trench."
• US 6,107,161 (Rohm Co., Ltd.; filed June 7, 1996; issued Aug. 22, 2000) — "Semiconductor chip and a method for manufacturing thereof."

Confidence caveat: I have verified only the bibliographic data (titles, assignees, dates) for these two, as reproduced in the record. I did not independently verify their full disclosure in this analysis, so I do not map their internal teachings claim-by-claim below; they are treated as same-field corroboration of the state of the art (trench corner shaping to improve fill/integrity, and trench isolation in semiconductor chips), and are less central than the IPR-record art below, which has been litigated to a Final Written Decision.

(c) Primary art from IPR2024-01403 (the "art of record," verified from the PTAB record)

• Yin — US 6,995,449 (Kevin Q. Yin et al.; a Newport Fab-family reference predating the '673). Per the petition/expert record, Yin discloses a semiconductor die with a deep trench isolation region filled with polysilicon surrounding and electrically isolating an electronic device such as a bipolar transistor — including conformal polysilicon deposition and etch-back (Yin, 6:29–32, 6:43–44; Figs. 2F). Yin does not disclose the corner geometry of its trench. (Title not independently verified; content as set out in the IPR record.)
• Koshimizu — US 2005/0181569 A1 (Renesas Technology Corp.; published Aug. 18, 2005) — "Semiconductor device and manufacturing method thereof." Discloses a heterojunction bipolar transistor (HBT) die with a deep isolating trench surrounding the transistor and a trench geometry having a chamfered outer corner and an unchamfered inner corner (Koshimizu, Fig. 16, ¶ [0028]; ¶¶ [0051]–[0061]). Koshimizu's own trench is filled with silicon oxide rather than polysilicon.
• Norström — US 6,121,102 (Telefonaktiebolaget LM Ericsson) — "Method of electrical connection through an isolation trench to form trench-isolated bipolar devices." Discloses deep electrically isolating trenches, generally of square layout, surrounding NPN/PNP bipolar transistors, and expressly teaches that 135°-angle (chamfered) corners, rather than 90°-angle (unchamfered) corners, were a solution to problems associated with trench refill (Norström, 16:27–36).

(d) Corroborating background art

• Wolf, Silicon Processing for the VLSI Era, Vol. 2 (1990) at 55–57 — textbook statement that "[i]f trenches of widely varying widths are filled, the narrow ones must be well overfilled in order for the wider ones to be filled completely," making planarization difficult.
• Stiffler (cited in the petition) — analysis showing stress concentrations at 90° outer trench corners, alleviated by chamfering.
• Matsuzaki, JP 3,141,621 B2 (English translation Ex. 1015) — illustrates conformal trench refill physics: a deposited layer closes a trench of width W at thickness W/2 regardless of fill material.

5. Combination 1 — Yin (US 6,995,449) in view of Koshimizu (US 2005/0181569 A1): renders all claims (1–17) obvious

This was Ground 1 in IPR2024-01403 (instituted as to all claims) and one of the grounds on which the Board's Final Written Decision (Feb. 9, 2026) determined all challenged claims unpatentable.

(a) Claim-element mapping

The gap-filler between Yin and the "reduction in polysilicon layer thickness" limitation is plain conformal-deposition physics, not invention: a conformally deposited layer need only reach half the local trench width to close that location (Matsuzaki, Fig. 4; Wolf at 55–57). Chamfering reduces the corner width from ~1.4 µm (square corner, per the '673's own Figure 1) to approximately the side width (~0.9–1.0 µm), so the polysilicon thickness required at the widest point drops correspondingly. The petitioner's expert so testified (¶¶ 101–106): "a POSITA would have understood that the thickness of a layer of polysilicon within a trench at a given location will be reduced if the width of the trench at that location is likewise reduced."

(b) Motivation to combine — why a PHOSITA would do it

1. Same problem, known solution. The problem the '673 solves — square trench corners force overfilling and waste — was textbook knowledge before 2007 (Wolf, Vol. 2, 55–57) and was expressly addressed by chamfering in the trench-isolation art (Norström, 16:27–36: chamfered 135° corners "were one solution to improve problems associated with trench refill").
2. Koshimizu supplies exactly the missing geometry. Yin is silent on corner shape; Koshimizu teaches a deep isolation trench around a bipolar transistor whose outer corners are chamfered while its inner corners remain square — structurally identical to the claimed "trench chamfered corner ... between a chamfered corner of an outside wall ... and a corner of an inside wall" (claims 3/12). Choosing that known geometry for Yin's polysilicon-filled trench is a textbook "combination of prior art elements according to known methods to yield predictable results" (KSR).
3. Chamfered isolation-trench corners were "standard tools in the art." As Samsung's counsel put it at the oral hearing, the "very simple question" is "whether it is inventive to add a chamfer to a prior art isolation trench when chamfered isolation trenches were already standard tools in the art," used "for the very reason the '673 Patent states, to improve trench refilling and prevent overfilling" (Norström, Moens, Koshimizu being examples).
4. Multiple, independent reasons to chamfer. Beyond fill efficiency: stress relief at 90° outer corners (Stiffler — reduced Von Mises stress and elastic energy), structural stability, and reduced need for overfill. Any one of these supplies a rational motivation.
5. No new functionality. The chamfer does not change the device's electrical operation; it only shapes a passive isolation structure. A PHOSITA seeking to improve Yin's polysilicon fill throughput would look to corner-geometry teaching in the same isolation art — Koshimizu (and Norström) — with a reasonable expectation of success.

(c) Patent Owner's only Ground-1 argument (non-analogous art) and why it fails

At the hearing, HID's sole Ground-1 argument was that Koshimizu is not analogous art: Koshimizu concerns HBT transistor manufacture, does not mention polysilicon, and fills its trench with silicon oxide (PO expert ¶¶ 55–60). The counter-analysis:

• Same field of endeavor. The '673 itself declares its field is "isolation region formation in semiconductor substrates" — not transistor formation. Koshimizu's isolation trench (¶¶ [0051]–[0061]) sits squarely in that field; the transistor is merely the device being isolated, just as in the '673.
• Reasonably pertinent to the problem. The problem is filling deep isolation trenches without overfill. Koshimizu's chamfered-corner teaching is pertinent to that problem regardless of whether its own fill is oxide; the chamfer geometry is content-neutral with respect to fill material.
• The fill-material distinction cuts toward, not against, the combination. Because Koshimizu is not itself a polysilicon reference, no claim limitation is satisfied by Koshimizu alone — Yin supplies the polysilicon fill. A reference need not solve the entire problem to be combinable; it need only suggest the missing feature.
• The Board rejected HID's analogous-art challenge at institution, and the Final Written Decision (Feb. 9, 2026) found all challenged claims unpatentable.

6. Combination 2 — Norström (US 6,121,102) alone: anticipates claims 1, 3, 5, 7–8, 10, 12, 14–16 (Ground 2)

Anticipation is the strongest form of invalidity; a reference that anticipates a claim a fortiori renders it obvious.

(a) Mapping

Norström discloses trench-isolated bipolar devices on a semiconductor plate where deep, oxide-sidewalled, electrically isolating trenches "at least partly surround the active region" of an NPN/PNP transistor — i.e., a trench situated in the substrate with sides surrounding an electronic device (a bipolar transistor) (claims 1, 8/16). Norström's layouts are "generally square" with the isolation trench running around the device — providing the four sides of claim 10. Norström expressly teaches chamfered trench corners: "135° angle corners (i.e., chamfered), rather than 90° angle corners (i.e., unchamfered)" to "improve problems associated with trench refill" (16:27–36). Because the chamfer reduces the trench width at its widest location (the corner), a conformally deposited refill layer — polysilicon among the contemplated fill materials in the trench-isolation art — need be less thick at the corners, satisfying the "causes a reduction in a thickness of a polysilicon layer" and "corner width < side width" limitations by the same physics described in § 5(a). Dependent limitations (oxide liner — claims 5/14; field oxide overlying the trench — claims 4/13, via the surface isolation layer; packaged die — claim 7) were mapped by the petitioner to Norström's disclosures (Norström, 1:29–34) for the claims the Board instituted upon.

(b) Patent Owner's arguments and why they do not defeat obviousness

HID's Ground-2/3 arguments were (i) Norström's deep isolation trench "does not have a plurality of chamfered trench corners," and (ii) its chamfered features are "not situated in the substrate." The Board rejected both at institution and the Final Written Decision found the challenged claims unpatentable. In any event, even if Norström's chamfer sits at the trench top or in an overlying layer rather than the substrate, the step of extending/placing the known chamfered geometry at the substrate-level trench would be an obvious application of a known fill-improving shape to a known trench structure — same reason, same predictable result.

7. Combination 3 — Norström plus routine packaging knowledge: renders claims 7 and 15 obvious (Ground 3)

Claims 7 and 15 merely add that "the semiconductor die is enclosed in a semiconductor package." The expert record establishes (¶¶ 179–184) that bipolar transistors such as Norström's, isolated by deep trenches and used in computer logic/CMOS chips, were "customarily ... integrated into packages ... for decades before the '673 Patent." Where a claim requires only conventional packaging of an otherwise-disclosed die, the limitation adds nothing patentable; it is the routine application of a ubiquitous commercial practice. Even on the petitioner's alternative theory, this ground was instituted and the Final Written Decision found the claims unpatentable.

8. Examiner-cited references (US 5,933,749; US 6,107,161) as corroborating same-field art

The two references cited on the face of the '673 patent are in the same technological neighborhood and would further support an obviousness case as alternative or reinforcing sources of the corner-shaping motivation:

• US 5,933,749 (UMC, "Method for removing a top corner of a trench") is directed, per its title, to modifying the shape of a trench corner before refill — the same design space (corner geometry as a fill/process-quality lever) that the '673 occupies. Caveat: full text not verified in this analysis; characterization limited to its title and field.
• US 6,107,161 (Rohm, "Semiconductor chip and a method for manufacturing thereof") is trench-isolation art in semiconductor chips, consistent with the die-level isolation context of claims 1 and 10. Same caveat.

Because the Board's FWD already resolved the art of record in the IPR, these face-of-the-patent references are best understood as additional evidence that corner shaping and trench isolation in dies were well-developed, crowded fields — reinforcing that chamfering a deep trench corner to ease fill was a routine, predictable expedient rather than an inventive step. I emphasize that I have not verified their internal disclosures and therefore do not rely on them for element-by-element mapping.

9. Secondary considerations

The record contains no credible secondary considerations of non-obviousness. The '673 patent itself concedes the long-standing nature of the overfill problem, and the IPR record shows the chamfered-corner solution was already "standard" in the art for fill improvement, stress reduction, and structural stability before the 2007 priority date. There is no evidence of commercial success, long-felt need resolved only by the '673, copying, or unexpected results tied to the chamfer. The near-doubling of fill throughput the specification touts is the predictable arithmetic consequence of reducing the widest dimension of the trench — precisely the outcome Koshimizu, Norström, Wolf, and Matsuzaki would lead a PHOSITA to expect.

10. Conclusion

Under 35 U.S.C. § 103, the claims of US 7,772,673 would be obvious to a PHOSITA:

1. All claims (1–17): obvious over Yin (US 6,995,449) in view of Koshimizu (US 2005/0181569 A1) — Yin supplies the polysilicon-filled deep isolation trench around a bipolar device; Koshimizu supplies the chamfered-outer-corner/square-inner-corner geometry; chamfering's effect on required fill thickness follows from well-known conformal-deposition physics (Wolf; Matsuzaki). Motivation: eliminate overfill/waste at square corners, improve fill throughput, reduce stress — all recognized reasons in the art before 2007.
2. Claims 1, 3, 5, 7–8, 10, 12, 14–16: anticipated by (and thus obvious over) Norström (US 6,121,102), which discloses substrate-situated, trench-isolated bipolar devices with 135° chamfered corners expressly taught to improve trench refill; claims 7 and 15 independently obvious over Norström plus routine packaging.
3. The examiner-cited US 5,933,749 and US 6,107,161 corroborate that trench-corner shaping and die-level trench isolation were mature, crowded fields, reinforcing the obviousness conclusion.

Status note (as of Apr. 26, 2026): The PTAB's Final Written Decision of Feb. 9, 2026 in IPR2024-01403 determined all challenged claims unpatentable under 35 U.S.C. § 318(a). Harbor Island Dynamic LLC has appealed to the Federal Circuit (Case 26-1670, filed Apr. 15, 2026), and the parallel district-court case (2:24-cv-00140-JRG-RSP, E.D. Tex.) is pending but is highly likely to be affected by the PTAB outcome. The obviousness analysis above is consistent with, and explains, the Board's decision on the instituted grounds.

Confidence flags: (1) The internal disclosures of US 5,933,749 and US 6,107,161 were not independently verified for this analysis and are characterized only by title/field; (2) the precise title of Yin (US 6,995,449) was not independently verified, though its content is well documented in the IPR expert record; (3) docket-level status of the CAFC appeal is drawn from secondary docket services consistent with the USPTO and SEC records.