US 6774000

I'll search for information on US Patent 6,774,000 specifically, including any CAFC docket activity.

The CAFC search returned no results. Let me run a few more targeted searches to confirm the claim structure, assignment chain, and any litigation/docket activity.

Summary — U.S. Patent 6,774,000 B2 (US6774000)

I searched for U.S. Patent No. 6,774,000 specifically and did not include similar-numbered documents (e.g., Japanese patent JP6774000 and Australian application AU6774000A, which are unrelated — a battery-charging patent and a color-capture application respectively).

Bibliographic data (verified against the USPTO Official Gazette entry and Google Patents)

• Title: Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures
• Patent / Publication No.: US 6,774,000 B2
• Application No.: 10/300,239
• Filing date: November 20, 2002
• Issue (grant) date: August 10, 2004
• Prior publication: US 2004/0097047 A1 (published May 20, 2004)
• Inventors: Wesley C. Natzle (New Paltz, NY); Marc W. Cantell (Sheldon, VT); Louis D. Lanzerotti (Charlotte, VT); Effendi Leobandung (Wappingers Falls, NY); Brian L. Tessier (Poughkeepsie, NY); Ryan W. Wuthrich (Burlington, VT)
• Original assignee: International Business Machines Corporation (Armonk, NY)
• Current assignee (per Google Patents assignment records): Auriga Innovations Inc., via the chain IBM → GlobalFoundries U.S. 2 LLC (2015-09-03) → GlobalFoundries Inc. (2015-10-05) → Auriga Innovations, Inc. (2017-02-17)
• Classifications: Int. Cl.⁷ H01L 21/336; U.S. Cl. 438/300; 17 claims
• Related filings: US 6,858,903 B2 is a division of Application 10/300,239; Chinese counterpart CN1263108C (CNB2003101180785A) also claims priority to it
• Legal status: "Expired – Lifetime" per Google Patents, with anticipated expiration noted as November 20, 2022

Abstract (verbatim)

"A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric."

Independent claims — plain-language overview

The Official Gazette entry confirms the patent has 17 claims and reproduces claim 1 verbatim (with minor OCR artifacts in the OG scan):

• Claim 1 (method): Forming an FET by (a) providing a device having a gate dielectric layer on a semiconductor substrate and a conductive gate electrode with sidewalls formed over the gate dielectric with an interface between the sidewall edges; (b) forming the gate dielectric with rounded surfaces at the base of the gate electrode; (c) depositing a silicon layer covering the device to form raised source and drain regions protruding beyond the exterior surface level of the gate dielectric; and (d) forming doped source/drain regions in the substrate with a channel region below the gate electrode.

The patent is a method patent (the companion device claims are in the division, US 6,858,903 B2, whose claim 1 mirrors the rounded-corner/raised-S/D structure in apparatus form). The specification describes multiple claimed-method embodiments: selective low-temperature epitaxy (LTE) with in-situ doping (FIGS. 1A–1F); non-selective blanket epitaxy followed by an isotropic etch-back/oxidation to remove shorting silicon segments (FIGS. 2A–2F); a no-reoxidation flow suited to metal gates (FIGS. 3A–3F); double-laminated raised source/drain structures (FIGS. 4A–4C, 5A–5C); a silicon-nitride collar embodiment (FIGS. 6A–6I); recessed/undercut source-drain embodiments (FIGS. 7A–7B, 8); and a high-K dielectric with deposited-oxide triangular spacer (FIG. 9).

CAFC 2026 docket search

My search of CAFC/2026 docket records for this patent number returned no results. I did not find any Federal Circuit appeal, Hatch-Waxman/ANDA action, or other district-court litigation tied to US 6,774,000. This is consistent with the patent being expired (November 20, 2022), but absence from search results is not definitive proof that no proceeding exists — I could not fully verify all docket sources within this session.

Uncertainty notes

• I have verbatim text only for claim 1 (from the USPTO Official Gazette). I could not authoritatively retrieve the full text of the remaining 16 claims (including whether claims beyond claim 1 are independent) from the sources available in this session, so I have not enumerated them to avoid fabrication.
• The current-assignee chain (Auriga Innovations) comes from Google Patents' assignment summary; the "Auriga Innovations Inc" listing carries Google's caveat that its assignment data may be inaccurate.