US 6593197

I'll search for the specific patent number and any CAFC 2026 docket references.

Let me run a few more targeted searches to verify USPTO records and any CAFC litigation.

Let me verify the official USPTO bibliographic data and check for any litigation or appeal activity.

Search Results Summary

USPTO / patent databases: Confirmed for the exact number 6593197 — Google Patents record US6593197B2 and a Patent Leaderboard entry both match. No similar-number ambiguity arose.

CAFC 2026 dockets: My searches for CAFC 2026 docket activity involving patent 6593197 returned no results (queries for CAFC docket 2026 patent 6593197, "US6593197" CAFC appeal, and "6593197" litigation/PTAB/Fed Cir all came back empty). Note this is an absence-of-results finding, not a definitive certification that no docket exists; however, the patent's expired status (below) makes 2026 litigation/appeal highly unlikely.

US Patent 6,593,197 B2 — Summary

Abstract: "This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process."

Plain-Language Overview of Independent Claims

The patent has 29 claims; the independent claims are 1, 7, 8, 11, 13, 15, 18, 22, and 26. All share one core idea: the active region and shallow-trench isolation (STI) are positioned self-aligned to the gate electrode using sidewall spacers as a mask, eliminating photolithographic overlay-alignment steps.

• Claim 1 — Base method: form a gate electrode (with sidewalls along its width) over a substrate; form first sidewall spacers alongside the gate; etch the substrate using those spacers as a mask to define trenches and the active region; fill the trenches with insulation (overfill → polish back until a pre-formed gate cover layer is exposed → isotropic etch-back); remove the first sidewall spacers; then ion-implant source/drain regions between the gate and the insulation.
• Claim 7 — Fuller embodiment: adds a thin gate-insulation layer and a gate cover layer; trims away the spacers along the gate-length direction (keeping them along the gate-width direction); etches trenches using both the spacers and cover layer as a mask; grows a thermal oxide for trench-corner rounding; fills, polishes, and isotropic-etches the insulation; removes the cover layer and first spacers; forms second, narrower spacers; then forms source/drain regions.
• Claim 8 — Spacer-trimming variant: same trench/active-region definition as claim 1, but the source/drain formation step works by trimming the first spacers down to narrower second spacers (rather than removing them first).
• Claim 11 — Replacement-spacer variant: same trench definition, but source/drain formation proceeds by removing the first spacers and then forming new, narrower second spacers.
• Claim 13 — Gate-cover variant: uses both the gate cover layer and the first spacers as the mask for trench/active-region definition (source/drain formation not specified in the claim; dependent claim 14 has the cover layer removed after source/drain formation).
• Claim 15 — Method claim (no "integrated circuit" preamble): gate + gate cover + spacers; etch substrate using the cover and spacers as a mask to define trenches; fill trenches with insulation; remove spacers; ion-implant source/drain between gate and insulation.
• Claim 18 — Trim-to-form-second-spacers method: trenches defined using the first spacers as a mask; insulation formed; first spacers are etched/trimmed into narrower second spacers; ion implantation for source/drain occurs while the trimmed spacers are still in place.
• Claim 22 — Length-direction trim method: after forming spacers around the gate, etch away substantially all spacers except the portions along the gate width; then etch the substrate using the cover layer plus those remaining width-side spacer portions as a mask to define trenches; fill with insulation.
• Claim 26 — Insulation-processing method: trenches defined using the cover layer and spacers as a mask; insulation formed by overfilling → polishing until the cover layer is exposed → etching to thin the insulation (dependent claim 29 clarifies the etch lowers the insulation surface to a level above the gate insulation layer, to reduce shorting risk).

Common theme across all independent claims: replace mechanical overlay alignment with a spacer-defined, self-aligned active region/STI so the source/drain lengths track the gate length and can be scaled down to reduce parasitic capacitance and increase circuit density.

Uncertainties / Caveats

• CAFC 2026 dockets: I found no CAFC 2026 docket entries for this patent. Because the patent expired in April 2021, post-expiration appeal activity in 2026 would be unusual; treat the "no docket" result as unverified absence rather than confirmed non-existence.
• I did not independently pull the USPTO Patent Public Search/Patent Center record in this session; bibliographic data above is sourced from the Google Patents record (provided as authoritative text) and corroborated by a secondary database search.
• The third-party leaderboard entry omits inventor Michael Raab; the official patent record (assignment document) includes him, and I've relied on the patent record.