US 11402456

I'll verify this patent against live sources, including any 2026 CAFC/litigation activity.

Let me run a couple more targeted checks for litigation/PTAB activity specifically on this patent number.

Verification summary — US 11,402,456

Sources checked: Google Patents (full text, claims, and legal events as fetched 2026‑09‑24), plus live web searches for USPTO/PTAB records, CAFC 2026 dockets, and MPS litigation coverage. No source contradicted the patent text provided, so the patent text is treated as authoritative.

Bibliographic data (as stated on the face of the record)

Abstract (verbatim substance)

A current sensing circuit for sensing current through a current sense resistor that receives a variable power input voltage. It includes a current sense amplifier whose first input is coupled to the first terminal of the sense resistor (to receive the power input voltage) and whose second input is coupled to the second terminal, with an output providing a current sensing signal indicative of the sensed current; and a calibration circuit coupled to the first input terminal. The calibration circuit converts the power input voltage into a calibration current and feeds it to the current sense amplifier to reduce a change in the current sensing signal caused by a change in the power input voltage.

Problem the patent addresses

With the shunt resistor tied to a widely varying supply (e.g., 1 V–36 V), finite common-mode rejection makes the output move with Vhv even at constant load current: the description derives Vs_out = Iin·RSNS·(Ad − Acm/2) + Vhv·Acm (eq. 6). The claimed fix is to inject a supply-dependent calibration current to cancel that Vhv·Acm term.

Plain-language overview of the independent claims

Claim 1 — Current sensing circuit (apparatus).
A current sense amplifier (feedback resistors R1–R4 around an op amp) senses current through a sense resistor fed by a variable power input voltage. A calibration circuit is tapped off the sense resistor's first terminal (i.e., it sees the variable supply voltage), converts that voltage into a calibration current, and injects it into the amplifier to reduce output variation caused by supply variation. Claim 1 additionally recites the four-resistor op-amp front end and requires the calibration circuit to include a differential trim circuit that, based on the power input voltage and a trimming code, produces two calibration voltages (first and second, differential).
Literal-recitation note: claim 1 recites "a second resistor coupled to the first input terminal of the operational amplifier and the second terminal of the first resistor" — literally, both ends at the amplifier input, rather than the more conventional input-to-reference connection described in the specification. I flag this as a drafting feature of the granted claim text rather than correcting it.

Claim 8 — Semiconductor chip (apparatus, system-level).
An integrated chip with at least five pins: Pin 1 to the high side of the external shunt (to receive a first power input voltage, which is generated by a power converter), Pin 2 to the low side of the shunt, Pin 3 outputting the current sensing signal, Pin 4 receiving a second power input voltage (e.g., battery Vbat), and Pin 5 to an external MCU. On-chip: the R1–R4/op-amp current sense amplifier driving Pin 3; a low dropout regulator (LDO) on Pin 4 producing a supply voltage; a first power circuit between Pin 4 and Pin 5 that powers the MCU from the second power input voltage; and the MCU is also coupled to Pin 3 to receive the current sensing signal. Notably, claim 8 itself does not require the calibration circuit (that appears in dependent claim 11).

Claim 16 — Adaptive calibration method.
Three steps: (1) convert the voltage across the sense resistor into an amplifying current using a first trans-conductance amplifier; (2) convert the variable power input voltage at the high side of the sense resistor into a calibration current based on a trim code using a calibration circuit; and (3) convert the combination of amplifying current and calibration current into the current sensing signal using a trans-impedance amplifier.

Notable dependent claims

• Cl. 2: internal architecture — first trans-conductance stage (gm1) + trans-impedance stage, with calibration current fed into a trans-impedance amplifier input (implementation: Vop − Von = (Ip−In)·RL + [(Ical+)−(Ical−)]·RL).
• Cl. 5 / 13: differential trim circuit + second trans-conductance amplifier (gm2) producing matched, opposite-direction calibration currents.
• Cl. 6 / 14: dual-domain design — first trans-conductance amplifier on the high-voltage supply, trans-impedance amplifier and second trans-conductance amplifier on a lower supply (e.g., 5 V LDO rail).
• Cl. 7 / 15 / 18: chopper stabilization of the calibration current, the first trans-conductance amplifier inputs, and the trans-impedance amplifier outputs.
• Cl. 17: the production-test trim method — set Vhv to a first value, measure Vs_out; set Vhv to a second value, measure Vs_out; derive the trim code from the difference (e.g., 36 V vs. 1 V, per the specification).
• Cl. 9 / 10: second on-chip power circuit from the low side of the shunt to a load pin, plus a control pin from the MCU.

Prior art cited on the face (9 references)

Includes US 7,102,335 B1 (Intersil); US 7,202,733 B1 (Marvell); US 2014/0159734 A1 (Sony); US 9,882,482 B1 (Monolithic Power Systems — "Current sense circuit with adaptive common mode voltage adjust"); US 2018/0145543 A1 (Witricity); US 2019/0068144 A1 (Semiconductor Components Industries); US 10,168,363 B1 (STMicroelectronics); US 2021/0048453 A1 (Analog Devices); US 11,082,019 B2 (Semiconductor Components Industries). Two non-patent citations are Wikipedia articles on "Electronic circuit" and "Low-dropout regulator." Notably, MPS's own US 9,882,482 B1 (adapted common-mode adjustment) is the closest same-assignee prior art.

Litigation / PTAB / CAFC check ("11402456" — no auto-correction)

I searched specifically for the string 11402456 in connection with PTAB/IPR, Federal Circuit 2026 dockets, and district-court activity. Findings:

• No IPR/PGR, CAFC appeal, ITC action, or district-court case specifically asserting or challenging US 11,402,456 was found.
• MPS is active in 2026 patent disputes — Monolithic Power Systems v. Reed Semiconductor / Nengda (D. Del. 1:23‑cv‑01155, 1:24‑cv‑00165, 1:24‑cv‑00166; trial set 2026‑11‑02, patents 9,041,377 and 9,590,608), Vicor v. Monolithic Power Systems (W.D. Tex. 7:26‑cv‑00005, filed Jan. 2026), Bel Power v. MPS (resolved in MPS's favor April 2026), and Greenthread v. MPS (seven IPRs decided in MPS's favor, announced May 2026) — but none of these appear to involve the '456 patent.
• Note also that a Hong Kong document (HK 1124439 A1) lists US11402456B2 in a citation table, which is a citation, not an assertion.

Uncertainty statement: I could not access USPTO PatentCenter/PTAB APIs or PACER directly, and litigation dockets and unpublished PTAB filings can lag public indexing. So while I found no evidence of invalidity challenges or infringement assertions against US 11,402,456, I cannot certify a negative — I can only report that targeted searches returned none. The bibliographic and claim content above, however, is taken directly from the patent's own text and is reliable.

Bottom line: US 11,402,456 is a granted, in-force MPS patent (expiring ~2040‑11‑05), naming Xavier Trulls Fortuny, claiming a high-voltage current-shunt amplifier whose common-mode/supply-induced error is cancelled by a supply-derived, trim-code-adjusted calibration current injected after the initial gain stage (favoring a low-voltage calibration domain), plus a system-on-chip claim including an LDO and MCU power path.

I'll research litigation involving US 11402456 using the sources you mentioned.

Initial searches returned noise. Let me try more targeted queries.

Let me run a few more targeted queries to confirm whether this specific patent has ever been asserted.

Summary: No litigation found asserting US 11,402,456

I searched for litigation specifically involving US Patent No. 11,402,456 B2 ("High voltage current sensing circuit with adaptive calibration," inventor Xavier Trulls Fortuny, assignee Monolithic Power Systems, Inc., filed 2020‑08‑24, issued 2022‑08‑02). I was unable to identify any district court litigation, CAFC appeal, or PTAB proceeding in which this patent was asserted or challenged.

What the searches showed

1. Google Patents record (authoritative full text provided). The complete Google Patents page for US11402456B2 includes an "Cited By," "Families Citing," "Similar Documents," "Citations," and "Legal Events" section — but contains no litigation / "Cases" section. Google Patents typically populates a litigation table when a patent is asserted in U.S. district courts (via Darts-IP/Lex Machina data). Its absence is consistent with there being no known litigation.

2. Monolithic Power Systems does have active litigation campaigns — but none involving the '456 patent. MPS is a frequent plaintiff and defendant, yet the cases I found assert different patents:

   • Monolithic Power Systems, Inc. v. Reed Semiconductor Corp. — D. Del., lead case 1:23‑cv‑01155 (filed 2023) and 1:24‑cv‑00165 (filed 2024‑02‑08, asserting U.S. Pat. 9,041,377 and the "608" patent). As of the docket activity I saw, the '155 case has summary-judgment motions and a Nov. 2, 2026 trial setting. No '456 patent appears among the asserted patents.
   • Monolithic Power Systems, Inc. et al. v. Promate Electronic Co., Ltd. et al. — W.D. Tex., 6:20‑cv‑00876 (filed 2020‑09‑25; consent judgment/closed 2023). Different patents.
   • Greenthread, LLC v. Monolithic Power Systems, Inc. — D. Del., 1:23‑cv‑00579 (filed 2023‑05‑26). Here MPS is the defendant, and the asserted patents are Greenthread's (8,421,195; 9,190,502; 10,510,842; 10,734,481; 11,121,222; 11,316,014) — not the '456.
   • Monolithic Power Systems, Inc. v. Nengda Microelectronics (Shenzhen) Co., Ltd. — D. Del., 1:24‑cv‑00166 (filed 2024‑02‑08). Different patents.

3. No PTAB challenge found. I found no IPR, PGR, or reexamination referencing U.S. Patent 11,402,456. (Note: MPS itself is an active IPR petitioner — e.g., IPR2024‑00469, MPS v. Greenthread, PTAB — but that challenges Greenthread's patents, not the '456.)

4. False positives excluded. Because you asked for the exact number only, I note that search engines returned unrelated records sharing the string "11402456":

   • UK Companies House incorporation number 11402456 (a 2018 UK company registration), and
   • Chinese trademark registration No. 11402456 (cited in PRC trademark-infringement judgments, e.g., (2022)粤0604民初30263号 and (2023)粤0115民初867号).

   These are not the U.S. patent and were not counted as litigation.

Caveats and confidence

• Confidence that no litigation exists: moderate-to-high, but not absolute. My searches surfaced aggregated sources (Google Patents, CourtListener/RECAP, Justia Dockets, UniCourt, Stanford NPE database, Docket Alarm) rather than a direct PACER/Unified Patents docket lookup, which I could not complete. Complaint-level records can lag aggregation by weeks or months.
• Because this patent issued only in August 2022 and is owned by a product company (MPS) rather than an NPE, the Stanford NPE database shows no assertion activity — consistent with the above.
• The identifier "11402456" should be interpreted literally as U.S. Patent No. 11,402,456; I have not substituted any other number.

Bottom line: Based on the sources searched, there is no known litigation (district court, CAFC, or PTAB) involving US 11,402,456. If you want a definitive negative, the next step would be a direct PACER "Patent/Trademark" search and the USPTO PTAB (P‑TACTS) assignment lookup for Patent No. 11,402,456, which would conclusively show any filed case or proceeding.

Proceedings overview

Total AIA trial proceedings on file for US 11,402,456: 0. The structured "PTAB proceedings on file" block — sourced from the USPTO Open Data Portal, which is the canonical list here — reports that the ODP API returns no AIA trial proceedings for this patent, meaning no IPRs, no PGRs, and no CBM reviews have been instituted or even filed-and-docketed as of the most recent ingest. My independent web searches (including attempts to surface unindexed or recently-filed petitions by patent number/title) returned no IPR2021–IPR2026, PGR, or CBM proceeding naming US 11,402,456. So the breakdown is simply: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0.

Bottom line defensive posture: This is not "hardened by surviving IPRs" — it is untested at the PTAB. All 18 claims stand exactly as issued on 2022-08-02, with no IPR-driven narrowing, no adverse FWD, and no claim cancellations. A defendant therefore has no estoppel baggage and a completely clean slate to file a first IPR/PGR — but also gets no free invalidity roadmap from a prior petitioner's work product. The absence of PTAB activity is a weak signal that the patent has not yet been asserted aggressively in a large multi-defendant campaign (well-asserted patents tend to attract IPRs), though it is only one data point.

Proceedings

There are no proceedings to itemize. To be explicit rather than merely silent:

• No IPR petititions (no IPR20xx-xxxxx) filed against US 11,402,456.
• No PGR petitions (PGR20xx-xxxxx).
• No CBM reviews (CBM20xx-xxxxx).
• No Director Review, POP, or sua sponte review decisions referencing this patent.
• No Federal Circuit appeal docket tied to an FWD for this patent.

Important disambiguation (things a search can easily confuse with PTAB activity on this patent):

• The MPS-related PTAB hits that dominate search results (e.g., IPR2024-00468, IPR2024-00469, IPR2024-00553, IPR2024-00871) involve completely different patents — Greenthread, LLC patents such as US 8,421,195 and US 11,316,014, and a Reed Semiconductor challenge to US 9,590,608. In those, Monolithic Power Systems is the petitioner, not the patent owner, and none of them name US 11,402,456. Note the office-action-adjacent distinction: in IPR2024-00468/-00469 MPS is attacking Greenthread patents, which is the opposite party alignment from what a defendant here would face.
• The Chinese trademark cases referencing a "第11402456号" registration (Nobeemas, Class 25 apparel) are unrelated trademark registrations, not this U.S. patent.
• The patent's Chinese family member, CN 113655265 B (granted 2025-10-24), has no U.S. PTAB significance.

Strategic summary

Claim status. All claims of US 11,402,456 are UNTESTED — none canceled, none sustained, none narrowed. The claim set is claims 1–18: independent claims 1 (current sensing circuit with calibration circuit + differential trim circuit), 8 (semiconductor chip with the LDO/integrated power circuits), and 16 (adaptive calibration method); plus dependents 2–7, 9–15, and 17–18. Because no IPR ever reached an FWD, there is no administrative narrowing and no controlling PTAB claim construction on terms like "calibration current," "differential trim circuit," "amplifying current," or "first trans-conductance amplifier." Any claim-construction fight happens de novo in district court or before the Board in a first-filed IPR.

Estoppel landscape. There is zero § 315(e)(2) estoppel attaching to this patent — no petitioner has ever appeared, so no party is barred from raising any § 102/§ 103 ground. A first petitioner retains the full universe of prior art, including:

• The cited references on the face of the patent (US 7,102,335 Intersil; US 7,202,733 Marvell; US 2014/0159734 Sony; US 9,882,482 MPS' own "adaptive common mode voltage adjust" patent; US 2018/0145543 Witricity; US 10,168,363 STMicroelectronics; US 2019/0068144 onsemi; US 2021/0048453 Analog Devices; US 11,082,019 onsemi). These are cited art, so a § 325(d) discretion argument by the patent owner is possible but manageable by framing them in a materially new combination.
• The patent owner's own prior art — notably US 9,882,482 (MPS), which is directed at adaptively adjusting common-mode voltage and is in the same assignee's portfolio. This is strong § 102(a)(2)/§ 103 fodder if the priority chain is analyzed carefully.
• Print publications and datasheets describing high-side current-shunt monitors with extended common-mode range (the "Cheng et al., 2017 high-sensitivity current-shunt monitor" reference surfaced in the Similar Documents list is a relevant analogue).

Pattern signals. No repeat-petitioner pattern exists because there are no petitioners at all. There is no defensive aggregator (e.g., Unified Patents, RPX) in the chain for this patent. On the patent owner side, Monolithic Power Systems is a serial PTAB petitioner against Greenthread (seven IPRs, with final written decisions finding all challenged claims unpatentable, announced 2026-05-06), which tells you the company is sophisticated, well-represented (Perkins Coie, John Esterhay et al.), and comfortable litigating in the IPR venue — but that is MPS as challenger, not as owner defending this patent. There is no evidence MPS has ever appealed an adverse FWD on this patent, because none exists.

Recommended next steps

1. Treat the record as empty, not adverse. If you are a defendant being asserted on US 11,402,456, nothing at the PTAB helps or hurts you today. Do not cite any proceeding number — none exists. Any AIA brief premised on "the Board already invalidated claim X" would be a fabrication and sanction-bait.

2. You are a first mover — preserve the option now. Because no estoppel exists, the entire prior-art corpus is available. Given the § 315(b) one-year bar from service of a complaint, calendar the one-year deadline immediately and begin a prior-art search targeting the high-side / high-common-mode current-sense amplifier and adaptive-calibration space (Intersil US 7,102,335, the STMicroelectronics US 10,168,363 "current sensor with extended voltage range" reference, and the Analog Devices/onsemi references are natural starting points).

3. Consider avenue and statutory basis carefully. The patent issued 2022-08-02 from a 2020-08-24 application, so it is PGR-eligible for § 112 written-description/enablement and § 101 grounds only within 9 months of issue — that window has closed (PGR unavailable now unless the patent is later amended via reissue). IPR under §§ 102/103 remains fully available; a defendant cannot use IPR to attack § 112, so indefiniteness/§ 112 challenges must stay in district court.

4. Alternatively, a § 315(e) workaround. If anonymous ex parte reexamination is attractive (a real option noted in current PTAB practice, where an RPI may file anonymously through a registered practitioner with a § 1.510(b)(6) certification), note that this patent has never been in an IPR/PGR, so the estoppel certification is clean and straightforward.

5. Monitor. Because ODP showed nothing as of the last ingest, re-check PTAB E2E (https://ptacts.uspto.gov/) and CourtListener before finalizing any invalidity contentions — a recently-filed petition might not yet be indexed. But as of 2026-09-29 there is no PTAB activity on file, and the defensive value of this patent's PTAB history is nil in either direction.

Caveat on sources: this conclusion rests on (a) the canonical ODP-derived "PTAB proceedings on file" block in the prompt, which reports none, and (b) my web searches, which surfaced no proceeding naming US 11,402,456. I could not identify any judgment, judge panel, FWD, settlement, or CAFC appeal for this patent, and I have not fabricated one. If a proceeding exists that neither ODP nor my searches surfaced, it is not in the public record I can access today.

I'll attempt to verify the assignment record and check for any post-issuance transfers or NPE involvement before writing up.

Let me check the correspondent of record and any assertion/NPE database listings for this specific patent.

Inventors

Pattern notes:

• Single-inventor patent. No co-inventor departures to track, so the "all inventors left within 12 months" fire-sale precursor cannot be evaluated from the inventor list alone. The only observable here is that the sole inventor signed an assignment of rights to MPS five days before the 2020‑08‑24 filing date (execution date 2020‑08‑19), i.e. a routine pre-filing employee/contractor obligation-to-assign, not a post-hoc cleanup.
• No inventor-side assignment (i.e., an assignment to the inventor) appears anywhere in the record, which is consistent with MPS being the sole owner from day one.
• I could not independently confirm Fortuny's specific MPS design center or title at filing (searches for his affiliation returned nothing usable). Treat "employed by MPS" as supported by the assignment document; his job title/location is not determinable from the record.

Original assignee

Monolithic Power Systems, Inc. (San Jose, California), the entity named on the face of the patent and the sole recorded assignee.

• Business: fabless power-management semiconductor company — DC/DC converters, power modules, motor drivers, current sensors, PMICs. Nasdaq-listed (MPWR), so it files periodic reports with the SEC; I found no 10‑K/8‑K disclosure, security agreement, or IP securitization covering this patent.
• Product embodiment: this is an MPS systems/IC patent (chip claim 8 recites an LDO, an MCU power path, and first/second power circuits on-pin). MPS ships current-sense and power-conversion products in this space, and the patent cites MPS's own earlier US 9,882,482 B1 ("Current sense circuit with adaptive common mode voltage adjust") as prior art — i.e., this is an in-family continuation of MPS's own improvement line, not an orphaned asset.
• Current status: operating, public, and solvent. Independent confirmation from the record itself: the patent is Active, with a 4th‑year maintenance fee paid 2026‑02‑02 (large entity, event code M1551) and an adjusted expiration of 2040‑11‑05. A patent owner that keeps paying maintenance fees on schedule is not a distressed seller.
• No bankruptcy, no dissolution, no acquisition of the assignee appears anywhere in this chain.

Assignment timeline

The chain has exactly one recorded assignment — the original pre-issuance assignment to MPS. There are no post-issuance transfers of any kind (no security interest, no change of name, no license recordation, no release, no correction).

• 2020-08-19 (executed) / recorded 2020-08-24 — Reel 053575/0222
  • Conveyance: Assignment — "ASSIGNMENT OF ASSIGNORS INTEREST"
  • Assignor: Fortuny, Xavier Trulls (sole inventor)
  • Assignee: Monolithic Power Systems, Inc., California
  • Correspondent: Not exposed in any source I could retrieve. The Google Patents legal-events entry for this recording lists owner name, free-format text, and effective date, but not the recording correspondent. The USPTO Assignment Center record could not be retrieved with the tools available to me. I am recording this as a documented data gap, not as a finding — I will not guess an attorney or firm name.
  • Context: Routine pre-filing employee/contractor assignment of rights to the operating company (executed five days before the 2020‑08‑24 filing date). Internal/original acquisition, not a fire-sale, reorg, securitization, or transfer to an asserter.
  • Recurrence flag: With a single entry, there is no recurrence to test. Reel 053575 (2020‑08) is the only reel/frame touching this patent; nothing about that number, by itself, indicates either a bulk in-house recording program or a third-party filer.

Cross-checks performed (all negative for extra links): Google Patents legal events show only the 2020‑08‑24 "AS Assignment" event before the 2022 grant; the "Also Published As" family entry (CN 113655265 B) is a foreign counterpart, not a transfer; the HK 1124439 A1 hit is a citation of US11402456B2 in a search report, not an assignment, license, or assertion. The "Cited By" entries (Texas Instruments, LG Display) are later publications citing this patent — also not assignments.

Timeline diagram

timeline
    title Ownership of US 11402456
    2019 : Sole inventor employed at MPS
    2020 : Filed 2020-08-24 by MPS
         : Inventor assigns rights to MPS
         : Recorded Reel 053575 frame 0222
    2022 : Patent issued 2022-08-02
    2026 : 4th year maintenance fee paid

NPE / troll-pattern signals

Verdict

Insufficient data — in the specific sense that the assignment record consists of only the original assignment (Reel 053575/0222, executed 2020‑08‑19, recorded 2020‑08‑24), so there is no post-issuance ownership chain to score.

Substantively, every NPE-typology element I can actually test comes back negative: the sole assignee is Monolithic Power Systems, Inc., a Nasdaq-listed operating semiconductor manufacturer that is paying maintenance fees on schedule (2026‑02‑02) and that appears in the record as an NPE defendant, not an NPE principal; there are no shell LLCs, no chained transfers, no security interests, no fire-sale, and no defensive aggregator. The one genuine gap is the correspondent of record, which I could not retrieve — I flag it as unverified rather than inferring a name.

Verify at: USPTO Assignment Center (query patent number 11402456; the legacy index is at assignment.uspto.gov) and cross-check the legal-events tab at Google Patents US11402456B2.

I'll verify the patent and its cited references against live sources before analyzing. Let me start with the patent itself and the most relevant citations.

Good — I have strong grounding on the closest reference. Let me pull the remaining cited references.

I hit the search-step limit, so I'll note exactly what I verified live versus what I'm reporting at the metadata level.

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Prior-art analysis for US 11,402,456 B2

0. Scope, sourcing, and a flagged date discrepancy

Patent identified (not auto-corrected): US 11,402,456 B2 (rendered on the record as "US11402456B2"), "High voltage current sensing circuit with adaptive calibration," app. 17/000,745, filed 2020‑08‑24, granted 2022‑08‑02, Monolithic Power Systems, Inc., inventor Xavier Trulls Fortuny.

Search result: The number resolves to the expected MPS patent. I retrieved the granted text, claims, and the front‑page citation list. Direct USPTO PatentCenter/API access was not available to me, so the citation set below is taken from the patent's own "Patent Citations (9)" table — i.e., the references actually of record — and I treated that table as authoritative per the operating rules.

Flagged contradiction: The task header says "Current Date: April 26, 2026," while my system date is 2026‑09‑29 and the previously‑generated section used a 2026‑09‑24 fetch. This does not affect the analysis (all prior-art dates are well before either date), but I'm flagging it as instructed rather than silently reconciling it.

Statutory framing — critical date = 2020‑08‑24 (filing = earliest priority; no earlier priority claimed). Because the application was filed after 2013‑03‑16, AIA §§102/103 apply:

• References published before 2020‑08‑24 → available as §102(a)(1) prior art.
• Two of the nine references published after 2020‑08‑24 (US 2021/0048453 A1 and US 11,082,019 B2) and are available only as §102(a)(2) art, and only if their effectively filed U.S. date precedes 2020‑08‑24 — which it does for both (2019‑08‑13 and 2020‑01‑07 respectively; US 11,082,019 claims provisional 62/958,142, filed 2020‑01‑07).

Verification confidence: I obtained substantive full text for US 9,882,482 and US 11,082,019 (plus their claim sets). The other seven I could not pull in full before hitting the search-step cap; for those, the description and mapping below rest on the title/assignee/date of record plus general technical knowledge, and I mark them accordingly. Do not treat my §102 conclusions for those seven as verified-against-full-text opinions.

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1. Bottom-line §102 finding up front

None of the nine cited references anticipates any of claims 1–18 of US 11,402,456.

The reason is structural: every independent claim (1, 8, 16) requires a calibration current derived from the variable power input voltage at the sense resistor's high-side terminal, produced under a trim code, and fed into the sense amplifier to cancel supply-induced output change. No cited reference discloses that combination:

• The references that sense a supply/input voltage do so for headroom/common-mode lifting (US 9,882,482) or common-mode/PSRR improvement via a feedback loop (US 11,082,019) — not to subtract the Vhv·Acm supply-error term with a trim-code-programmed differential calibration current.
• The remaining references address disanalogous subject matter (input-stage topology, compensation, shunt averaging, bidirectional sensing).

Consequently the cited art is best characterized as §103 material, and I map it claim-by-claim below with that caveat. Where a reference could plausibly read on a sub-combination of a claim, I say so and explain why it still falls short of §102.

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2. Reference-by-reference

Ref. 1 — US 7,102,335 B1

• Full citation: US 7,102,335 B1, "Rail-to-rail current sense amplifier," Intersil Americas Inc. Priority 2004‑02‑27; granted 2006‑09‑05.
• Description (title/metadata level): Current-sense amplifier designed to operate across a rail‑to‑rail (very wide) input common-mode range.
• Claim mapping: Potentially reads on the amplifier sub-combination of claim 1 (the current-sense amplifier with first/second input terminals and an output; the R1–R4-style front end) and on the general architecture of claim 2.
• §102: No anticipation. Absent: the calibration circuit tapped to the high-side sense-resistor terminal; conversion of the variable power input voltage into a calibration current; the differential trim circuit producing first/second calibration voltages responsive to a trim code. Wide common-mode range ≠ trimming out supply-dependent error. §103-relevant only.

Ref. 2 — US 7,202,733 B1

• Full citation: US 7,202,733 B1, "Transconductance amplifiers with compensation," Marvell International Ltd. Priority 2005‑11‑02; granted 2007‑04‑10.
• Description: Compensated transconductance (gm) amplifier circuits.
• Claim mapping: Potential relevance to the first/second trans-conductance amplifier recitations of claims 2, 5, 12, 13, and the method step of claim 16.
• §102: No anticipation of any claim — the claim requires a full circuit/method, and this reference supplies only a gm-block teaching. §103-relevant to the amplitude/transconductance elements.

Ref. 3 — US 2014/0159734 A1

• Full citation: US 2014/0159734 A1, "Current sense," Sony Corporation. Filed 2012‑12‑12; published 2014‑06‑12.
• Description: A current-sensing arrangement (Sony).
• Claim mapping: Broadly to claim 1's "current sense amplifier … output terminal … providing a current sensing signal indicative of the current."
• §102: No anticipation. The distinguishing calibration-current-under-trim-code element is absent. Low §103 weight absent a showing it renders the calibration feature obvious.

Ref. 4 — US 9,882,482 B1 ← closest cited art; same assignee (MPS)

• Full citation: US 9,882,482 B1, "Current sense circuit with adaptive common mode voltage adjust and associated method thereof," Monolithic Power Systems, Inc. Filed 2016‑09‑15; granted 2018‑01‑30.
• Description (verified from full text): A current-sense circuit (sensing resistor Rsense + op amp AMP1 + transistor M2 + resistor R3) with a common-mode adjust circuit 11 that has an input terminal (coupled to AMP1's output / M2's gate) and first/second output terminals coupled to the op-amp's non‑inverting and inverting input ports (RG1, RG2 through Rs1, Rs2). It injects adjusting currents Icm1, Icm2 into those two input ports to lift the common-mode voltage VCM (so M2 has enough headroom), and Icm1 = Icm2 = 0 when VCM is adequate. The adjustment is triggered by comparing the switcher output voltage SWout (or the sense-resistor terminal voltage) against a minimum VCMmin.
• Claim mapping: This is the reference most likely to have driven the examiner's §103 position. It maps to: claim 1's "calibration circuit … coupled to the first input terminal of the current sense amplifier" and "provide the calibration current to the current sense amplifier"; claim 4's first/second output currents fed to the amplifier inputs.
• §102: No anticipation — and the gap is decisive, not merely semantic:
  • Its adjusting current is a function of the switcher output voltage / VCMmin comparison, not a differential current derived from the variable power input voltage at the first terminal of the sense resistor.
  • It contains no differential trim circuit and no trim code; there is no production-test calibration mechanism at all.
  • Its stated purpose is common-mode headroom, not cancelling a supply-induced (Vhv·Acm) output change; the currents are equal-and-same-direction (both simply lift VCM), unlike the '456 requirement of matched opposite-direction differential calibration currents.
  • Therefore it cannot anticipate claim 1 (which affirmatively recites the differential trim circuit generating first/second calibration voltages based on the power input voltage and a trimming code), nor method claim 16 (calibration current "based on a trim code"), nor claim 17 (the two-measurement trim procedure). §103-relevant as a primary reference, especially combined with a trim/reference-voltage source teaching; note also the same-assignee relationship (relevant to any §102(b)(2)/common-ownership or double-patenting-style argument, though this patent and the '456 are separate filings).

Ref. 5 — US 2018/0145543 A1

• Full citation: US 2018/0145543 A1, "Current shunt monitor," Witricity Corporation. Filed 2016‑11‑21; published 2018‑05‑24.
• Description (metadata level): Shunt-based current monitoring in a wireless-power context.
• Claim mapping: Background/general current-shunt monitoring only.
• §102: No anticipation. No supply-derived trim-calibrated calibration current. Low §103 weight.

Ref. 6 — US 2019/0068144 A1

• Full citation: US 2019/0068144 A1, "Bidirectional current sense amplifier," Semiconductor Components Industries, LLC (onsemi). Filed 2017‑08‑23; published 2019‑02‑28.
• Description (metadata level): Current-sense amplifier supporting bidirectional current measurement (typically a mid-supply reference output).
• Claim mapping: The current-sense-amplifier elements of claims 1/8; possibly the bidirectional configuration discussed in the '456 description's closing paragraph (polarity may be exchanged).
• §102: No anticipation. No calibration circuit, no trim code, no conversion of the variable power input voltage into a differential calibration current. §103-relevant only for amplifier architecture.

Ref. 7 — US 10,168,363 B1

• Full citation: US 10,168,363 B1, "Current sensor with extended voltage range," STMicroelectronics Design & Application S.R.O. Filed 2018‑03‑14; granted 2019‑01‑01.
• Description (metadata level): Current sensor that extends the usable input/common-mode voltage range — conceptually close to the '456 premise that the sense resistor sits on a widely varying high-voltage rail (1 V–36 V per the specification).
• Claim mapping: The "variable power input voltage" context of claim 1 and the high-voltage-domain limitation of claims 6/14 (first trans-conductance amplifier on a high-voltage supply).
• §102: No anticipation. Extending the common-mode/voltage range is not the same as adaptively cancelling the residual supply-dependent output error with a trim-coded calibration current. A useful §103 secondary reference for the "high-voltage input sensing" context.

Ref. 8 — US 2021/0048453 A1 (published after the critical date)

• Full citation: US 2021/0048453 A1, "Shunt resistor averaging techniques," Analog Devices International Unlimited Company. Filed 2019‑08‑13; published 2021‑02‑18.
• Prior-art status: Not §102(a)(1). Available only as §102(a)(2) art (U.S. application publication effectively filed 2019‑08‑13, before 2020‑08‑24), and only for what it "describes" under §102(a)(2)/§103.
• Description (metadata level): Techniques for averaging multiple shunt-resistor sense channels to reduce error.
• Claim mapping: At most tangential to error-reduction in shunt sensing.
• §102: No anticipation. It addresses averaging/mismatch, not supply-voltage-derived calibration currents. Minimal §103 weight.

Ref. 9 — US 11,082,019 B2 (published after the critical date)

• Full citation: US 11,082,019 B2, "Amplifier with adaptively-controlled local feedback loop," Semiconductor Components Industries, LLC (onsemi). Provisional 62/958,142 filed 2020‑01‑07; non‑provisional 16/843,675 filed 2020‑04‑08; granted 2021‑08‑03.
• Prior-art status: Not §102(a)(1). Available as §102(a)(2) art (effectively filed 2020‑01‑07 < 2020‑08‑24).
• Description (verified from full text): A differential amplifier with first/second feedback paths (input and feedback resistors) and an adaptively enabled local/common-mode feedback loop (second differential amplifier) that controls current flow into the positive and negative inputs of the first amplifier; a control circuit enables the loop when the differential input magnitude exceeds a threshold. It explicitly targets reducing PSRR dependence on input/feedback resistor mismatch and modulating output common-mode voltage to �|Vod|/2, and it discloses chopper switches in the loop.
• Claim mapping: Strikingly close in motivation — it attacks exactly the resistor-mismatch-driven common-mode/supply-sensitive error the '456 description discusses (eqs. 2–6). It maps to: the chopper-stabilization limitations of claims 7, 15, 18 (chopping the calibration current / trans-conductance inputs / trans-impedance outputs), the injection of currents into amplifier inputs (a building block of claim 4/5), and the general "adaptive" feedback/calibration concept.
• §102: No anticipation. It lacks the current-sense-resistor + variable-power-input-voltage combination, the calibration current derived from the power input voltage, the differential trim circuit, and the trim code; and its loop responds to input signal magnitude, not to a supply voltage. It is nonetheless a strong §103 secondary reference on the "adaptive current injection into the amplifier inputs" and chopping points, and it is the most thematically overlapping of the nine on the PSRR/mismatch problem. Because it is post‑date and only §102(a)(2)/§103 art, any challenge built on it must be a §103 combination.

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3. Summary table (§102 posture)

Net: 0 anticipatory references; the art supports only §103 challenges, led by US 9,882,482 (primary) combined with US 11,082,019 and/or US 7,202,733 (for the trans-conductance/trim implementation) and US 10,168,363 (for the extended/high-voltage range context).

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4. Additional references of record (not in the nine) — worth noting

The record also lists twelve "Family Cites Families" references (i.e., art cited in the family/foreign prosecution of the CN 113655265 counterpart). Because they are of record somewhere in the family, they merit a screening even though they were not in the 9-reference "Patent Citations" table. At metadata level the potentially on-point ones are:

• CN 102360236 B — "High-voltage end current detection circuit" (2013‑12‑18) — high-side current detection.
• JP 4902390 B2 — "Current detection circuit and current mode switching regulator" (2012‑03‑21).
• US 8,717,051 B2 (Intersil, 2014‑05‑06) — "Method and apparatus for accurately measuring currents using on chip sense resistors."
• JP 7065694 B2 (2022‑05‑12) — "Control method of current detection circuit, ammeter, and current detection circuit."
• CN 109521254 B — "Current detection circuit and power supply device having the same."
• CN 105223533 B — "An ultra-precise and fast-response DC current calibrator circuit."
• CN 106443159 B — "Current detection chip."

I did not verify these in full, so I make no §102 assertion about them. The remaining family-cited items (e.g., CN 206962700U / CN 206788232U buck-converter load-current detection; CN 202455317U low-drift offset self-correcting op amp; US 10,476,651 B2, Huawei numerology determination) appear off-point by title.

The two non-patent citations are archived Wikipedia articles — "Electronic circuit" (Aug. 2019) and "Low-dropout regulator" (Jul. 2020). These are general-knowledge/§§102(a)(1)–103 background items (the LDO one is presumably cited against claim 8's LDO limitation); neither could anticipate a claim.

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5. Honest limitations

• I could not certify the absence of other prior art (e.g., non-cited art, foreign art, or art of record only in the CN counterpart, which I could not open).
• For seven of the nine cited references I had only title/assignee/date metadata, not full text; my §102/§103 opinions on those are reasoned from the titles and the technical field and should be re-verified against the references' actual disclosures before being relied upon in any validity analysis.
• The two references flagged as §102(a)(2)-only (US 2021/0048453 A1, US 11,082,019 B2) must be treated as §103 art in any challenge; a §102 challenge cannot rest on them.

If you want a tighter result, the single most productive next step is a full-text read of US 9,882,482 B1 (already available and the closest art) paired against claim 1's differential-trim-circuit limitation, since that limitation is the one the cited art most clearly fails to teach.

Obviousness analysis — US 11,402,456 B2 under 35 U.S.C. § 103

Scope note: This section builds on — and does not repeat — the Prior Art analysis already generated for this patent. I use that section's reference set, its verification-status markers, and its §102 conclusions as the starting point. Where I need a fact about a reference's disclosure that the Prior Art section could not verify (seven of the nine cited references were metadata-only), I say so and downgrade my confidence rather than assert it.

Flagged date discrepancy (carried forward): the task header states "Current Date: April 26, 2026," my system date is 2026‑09‑29, and the earlier sections used a 2026‑09‑24 fetch of the patent. As in the Prior Art section, I flag this rather than silently reconciling it. It is immaterial here: every reference date is at least five years before either date, and the §102/§103 posture does not change between April and September 2026.

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1. Legal frame and critical date

• Critical date: 2020‑08‑24 (filing date; the patent claims no earlier priority — the CN 113655265 counterpart is a family member claiming the '456's date, not a priority source).
• The application was filed after 2013‑03‑16, so AIA §§ 102/103 govern.
• § 103-eligible art includes § 102(a)(2) art. US 2021/0048453 A1 (ADI) and US 11,082,019 B2 (onsemi) cannot anticipate, but each may be used in a § 103 combination. This matters because US 11,082,019 is the single most useful secondary reference in the set — it teaches the motivational core (adaptive current injection to fix resistor-mismatch-driven supply/PSRR error) and the chopping feature. No combination below relies on it as a § 102 reference.
• Common-ownership does not immunize US 9,882,482 (MPS). The same-assignee relationship (MPS owns both the '482 and the '456) is relevant only to the § 102(b)(2)(C) exception. The '482 published 2018‑01‑30, more than one year before 2020‑08‑24; it is therefore § 102(a)(1) prior art on its face, and § 102(b)(2)(C) never comes into play. This is important and counterintuitive — the examiner cited MPS's own earlier patent against MPS's later application, and that is legally clean for § 103.
• Governing standard: KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) — a combination is obvious where the elements were known, the problem was known, and a PHOSITA had a finite number of identified, predictable solutions with a reasonable expectation of success. Also Graham factors and the teaching/§ 112 support for using the applicant's own background admissions (here, equations (1)–(6) and the statement that the conventional remedy was resistor area or laser trim).

A threshold observation about the patent's own specification. The '456's Background concedes the entire problem: finite CMRR, resistor mismatch as the dominant cause of common-mode gain, and the accepted industry remedies (larger resistor area, laser trimming). A specification that admits the problem and its prior solutions hands a challenger the "known problem / known technique" half of the KSR analysis. What remains genuinely contestable is the placement and form of the fix — not the existence of the problem.

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2. What must be shown, claim by claim (element inventory)

I compress claim 1 into the four limitations that actually carry weight, since the resistor network and op-amp output are undistinguished over the art:

The obviousness case therefore rises or falls on L2 + L3, and particularly on whether the art supplied (a) a reason to derive a current from the sense-resistor supply rail and (b) a reason to make it trim-code-programmable.

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3. Combination A — the primary § 103 case (claims 1, 2, 4, 5)

References

• [Primary] US 9,882,482 B1 (MPS, 2018‑01‑30) — current-sense circuit with a common-mode adjust circuit that injects adjusting currents Icm1/Icm2 into the two input ports of the sense amplifier, with an input coupled to the amplifier output/monitoring node. Full text obtained; see Prior Art §2, Ref. 4.
• [Secondary] US 11,082,019 B2 (onsemi, granted 2021‑08‑03, effectively filed 2020‑01‑07 — § 102(a)(2)/§ 103 art only) — differential amplifier with an adaptively enabled local feedback loop that controls current flow into the positive and negative inputs of the first amplifier, expressly to reduce PSRR dependence on input/feedback resistor mismatch, and discloses chopper switches. Full text obtained.
• [Secondary] US 2021/0048453 A1 (ADI, § 102(a)(2)/§ 103 art only) — shunt-resistor error-averaging techniques; supplies the "shunt-sense error is a known, worked problem" context.

Element mapping

Why a PHOSITA would have combined them

1. Same field, same problem, same failure mechanism. Both references address the exact phenomenon the '456 Background describes: finite common-mode rejection amplified by resistor mismatch in a sense amplifier whose inputs sit on a high-voltage rail. '019 states the object as reducing PSRR sensitivity to input/feedback resistor mismatch — verbatim the mechanism the '456 offers equations (1)–(6) to explain. KSR factor (a) (same field of endeavor) and (b) (same problem) are satisfied on the face of the references.
2. The '482 is the assignee's own admission of the technique. A PHOSITA reading MPS's own '482 would see current injection into the two amplifier input ports used to manage the common-mode condition of the sense amplifier. The '456 applies the same physical mechanism (trimmed current injected into the amplifier) to the adjacent problem (cancelling the Vhv·Acm term). Modifying a known adjusting-current injector to be differential so it can subtract an error term, rather than common-mode so it can lift headroom, is a predictable mechanical change in current direction — not a new principle.
3. Trim-code-programmable current sources were a routine design choice by 2020. Trimming a current or voltage with a programmable code during production test — and storing it in OTP — was standard practice in precision analog ICs and is corroborated in the wider family-cited art already of record (e.g., CN 202455317U, a self-correcting/low-drift op-amp circuit, and CN 105223533 B, a DC current calibrator). Combining a known trim network with the '482's injector is the classic KSR "known technique to improve a similar device in the same way" rationale. This is a general-knowledge assertion; I did not verify the two CN references' full texts (Prior Art §4).
4. Predictable result. Adding a trim-coded differential current to the injector's output simply scales a term already present in the '482's current-injection equation. No change in the principle of operation, no unexpected result claimed, and the '456 itself asserts only that the Vhv·Acm component is "cancel[led] or minimiz[ed]" — a result the injector architecture is already capable of delivering.

Where the patent owner wins ground

• The '482's injected currents are equal and same-direction, expressly to lift VCM so its pass element has headroom (Icm1 = Icm2 = 0 when VCM is adequate). A patent owner will argue this is a teaching away: the '482 affirmatively zeroes its currents whenever the condition it monitors is satisfied, which is the opposite of the continuous, supply-proportional calibration the '456 claims. That is the strongest non-obviousness argument available, and it is a genuine one.
• The '019's loop is triggered by input signal magnitude, not supply voltage, and its current is not derived from the sense-resistor terminal.
• Neither reference derives the current from the variable power input voltage at the first terminal of the sense resistor — the claim's affirmative source limitation.

Assessment: Combination A renders claims 1, 2, 4 and 5 prima facie obvious on motivation, but only with a competent teaching-away rebuttal prepared for the '482's zeroing behavior. Confidence: medium, contingent on a full-text check of how '482 describes the relationship between its adjusting current and the sensed terminal voltage.

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4. Combination B — the trans-conductance/trans-impedance architecture (claims 2, 5, 16)

• Add [Secondary] US 7,202,733 B1 (Marvell, 2007‑04‑10), "Transconductance amplifiers with compensation." Metadata-only; not verified in full.
• Claim 2 / claim 16 step (1) and step (3) recite nothing more exotic than an input trans-conductance stage feeding a trans-impedance stage — the standard gm→TIA signal chain. US 7,202,733 supplies the gm stage; a TIA built from current sources with finite output resistance is elementary (the '456's own eq. (11) treats RL as a trivial parallel resistance RIS7//RIS9).
• Motivation: substituting a gm+TIA signal chain for a resistor-feedback op amp in a wide-common-mode-range sense amplifier is a known architectural option for avoiding resistor matching problems (the very problem admitted in the '456 Background). A PHOSITA seeking to reduce the mismatch-driven Acm term would have been motivated to remove the matched resistors from the gain path.
• Caution: claim 2 also carries L2 (calibration current into a TIA input). That placement — after the initial gain stage, in the current domain — is the '456's claimed insight (spec ¶ beginning "Since the calibration is performed in the current domain through a low-impedance path after an initial gain stage (202), the precision requirements of the calibration circuit is decreased"). Combination A's references teach injection at the amplifier inputs, which is a different node than the claim requires; a challenger must articulate why the '482 injector would be relocated to the TIA input node. The motivation exists ('482's injector already sits at a monitoring node of the amplifier output; injecting where the trans-conductance output current is summed is the natural, lowest-impedance summing node once a TIA exists), but this is the element most vulnerable to a "no motivation / changed principle of operation" rebuttal.

Assessment: claim 16 (the method) is the most obvious of the three independent claims — it is essentially "amplify through a gm stage, add a trim-coded calibration current, convert through a TIA stage," which is a recitation of known blocks. Confidence: medium-high for claim 16, medium for claim 2.

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5. Combination C — high-voltage / extended-range context (claims 1, 6, 14)

• Add [Secondary] US 10,168,363 B1 (STMicroelectronics, 2019‑01‑01), "Current sensor with extended voltage range." Metadata-only; not verified in full.
• The '456's premise is that the shunt sits on a rail spanning ~1 V to 36 V. US 10,168,363 is directed at extending the usable input/common-mode voltage range of a current sensor — i.e., the same environmental constraint, addressed by the prior art for a different purpose (range extension vs. error cancellation).
• Motivation for claim 6 / 14 (dual supply domains): once the signal path senses a 36 V rail, powering the low-voltage post-processing blocks from an LDO rail and keeping only the input stage on the high-voltage rail is the conventional way to protect low-voltage CMOS. The '456 itself recites the ISO-26262-adjacent rationale ("more reliable specially for applications such as automotive") and attributes noise immunity to the LDO rail — that is a recited advantage of a known design practice, not evidence of invention. The patent's own record cites Wikipedia's "Low-dropout regulator" article as non-patent prior art, which underscores that the LDO rail was ordinary skill.

Assessment: claims 6 and 14 are obvious over Combination A + US 10,168,363 + the ordinary skill evidenced by the LDO NPL. Confidence: medium-high.

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6. Combination D — claim 8 (and 9, 10, 11–13): the semiconductor-chip claim

Important structural point, carried over from the summary section: independent claim 8 does not require the calibration circuit at all. Its elements are:

1. five pins (high-side shunt in, low-side shunt in, sensing output, battery rail in, MCU);
2. op amp + R1–R4 driving the output pin;
3. an LDO on the battery pin generating a supply voltage;
4. a first power circuit between the battery pin and the MCU pin; and
5. the MCU also receiving the sensing signal.

Every one of those is a conventional circuit block or a conventional integration choice, and the claim is therefore vulnerable to an obviousness case that never has to reach the differential-trim-circuit limitation at all.

• Primary: US 9,882,482 B1 (sensing amplifier on a switched high-voltage rail — the closest art of record) or US 10,168,363 B1 (extended-range current sensor).
• Secondary for the LDO: the Wikipedia "Low-dropout regulator" non-patent citation of record (archived 2020) — used not as a disclosure of the invention but as evidence that an on-chip LDO converting a battery rail to a low-voltage internal supply was ordinary skill; this matters because the reference is of record in this very patent.
• Secondary for the power path: US 2021/0048453 A1 and the general 2019–2020 state of integrated PMICs. I did not verify a specific reference disclosing an on-chip "first power circuit" feeding an external MCU; this element of Combination D is supported by general-knowledge/routine-integration reasoning, not by a verified reference. Mark as unverified.

Motivation to combine for claim 8:

1. Integration economics. A PHOSITA integrating a high-side current monitor into an automotive PMIC would integrate the LDO that powers its own low-voltage domain onto the same die — this reduces pin count, board area and BOM, and is the explicit design trend the '456's own chip figure illustrates.
2. Pin-count/pin-function predictability. Adding a battery-input pin, an MCU-power pin and a sensing-output pin to a multi-function power-management IC is mechanical, not inventive; the claim recites no unexpected electrical interaction among the pins.
3. KSR "predictable use of prior art elements according to their established functions" — LDO regulates; first power circuit supplies the MCU; sense amplifier senses. Nothing in claim 8 requires the calibration current, so nothing in claim 8 ties the elements together synergistically.

Assessment: claim 8 is the weakest claim in the patent and the best target for a first IPR. Confidence: medium-high that a properly built combination renders it obvious, with the caveat that I could not verify a single reference teaching the combination of pins and circuits in one die, so the case rests partly on routine-integration reasoning that must be supported by actual art (datasheets for 2018–2020 automotive PMICs are the obvious hunting ground).

Claims 9, 10 (second power circuit from the shunt's low side to a load pin; MCU control pin) add a half-bridge/full-bridge load driver and a control input. Both are conventional and the '456's own spec describes them in generic terms ("two transistors … buck converter," "four transistors … full-bridge"). Obvious over Combination D + any buck/full-bridge driver reference. Confidence: medium-high, but again reference-unverified.

Claim 11 pulls in the calibration circuit; claim 12 adds gm + TIA + signal conversion; claim 13 adds the differential trim circuit + second gm amplifier. Once claim 11 is reached, the claim 8 analysis collapses into Combination A, and the vulnerabilities are those in § 3.

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7. Combination E — claim 17 (production-test trim method)

Claim 17: set Vhv to a first value → measure Vs_out → set Vhv to a second value → measure Vs_out → derive the trim code from the difference.

• Reference support: US 9,882,482 (adaptive adjustment of an amplifier current based on a monitored terminal voltage) + the well-known practice of two-point/final-test trimming of analog ICs (corroborated in the family-cited art, e.g. CN 105223533 B "ultra-precise and fast-response DC current calibrator circuit"). Metadata-only; not verified.
• Motivation: two-point measurement during final test is the standard way to capture and null a linear error coefficient; the '456's own spec says the first/second values may be the max (36 V) and min (1 V) of the operating range — i.e., the endpoints a test engineer would pick as a matter of routine.
• Counter-argument: the claimed quantity being nulled (the supply-dependent output change) is specific, and the step of deriving the code from the difference between two measured outputs at two supply voltages is tailored to the '456's error term. A patent owner could argue this is a non-routine test procedure. I find that argument weak: the procedure is the textbook application of two-point calibration to a linear error, and the '456 does not claim any unexpected measurement methodology (it expressly allows "calculation, or look-up table").

Assessment: claim 17 obvious. Confidence: medium-high.

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8. Combination F — claims 7, 15, 18 (chopping)

• Reference: US 11,082,019 B2 discloses chopper switches in its adaptive feedback loop (verified in the Prior Art section). Chopping to remove offset and 1/f noise from a sense amplifier is one of the oldest, most predictable techniques in precision analog design; applying it to the calibration current and the gm/TIA stages is squarely within KSR's "known technique, predictable result."
• Timing caveat: US 11,082,019 is § 102(a)(2)/§ 103 art only (effectively filed 2020‑01‑07, published 2021‑08‑03). It cannot be used as a § 102 reference under any circumstance. A § 103 challenge must be framed as a combination.
• The '456 spec does not describe the chopping circuit at all beyond Figure 12 and one sentence — it identifies three chopping locations and asserts no unexpected benefit. That absence of disclosure weighs toward obviousness (no criticality described).

Assessment: claims 7, 15, 18 obvious over Combination A + US 11,082,019. Confidence: high.

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9. Combination matrix

No combination in this table produces a § 102 anticipation. The Prior Art section concluded 0 anticipatory references, and I agree — every independent claim contains at least the "differential trim circuit + trim code" or the "calibration current derived from the variable power input voltage" element, and no reference of record discloses either.

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10. The three strongest counterarguments, and how to meet them

1. "The '482 teaches away." The '482's adjusting currents are equal and same-direction, applied for headroom, and go to zero when the monitored condition is satisfied. The '456 requires a continuous, differential, supply-proportional current whose only purpose is to cancel an error term. Rebuttal: teaching away requires that a PHOSITA reading the reference be discouraged from the claimed solution, not merely that the reference serves a different purpose. The '482 shows a current injector at the amplifier's input ports; nothing in it disparages using such an injector for error cancellation. This is a contestable point and the patent owner's best one — expect it.

2. "Injection location is critical." The '456's stated advance is injecting after the initial gain stage, in the low-voltage current domain, so that "calibration is independent of the components in the input signal path." A PHOSITA would have to be motivated to move the injector from the amplifier inputs (where '482 and '019 put it) to the trans-impedance input node. Rebuttal: once a gm/TIA architecture is adopted (Combination B), the TIA input is the natural summing node — it is where the amplifying currents already combine (the '456's own eq. (7): Vop−Von = (Ip−In)·RL + [(Ical+)−(Ical−)]·RL). The relocation is compelled by the architecture, not a free design choice. This rebuttal is strong but requires the TIA architecture to be in the combination.

3. "No secondary considerations in the record, but that cuts both ways." There is no evidence of unexpected results, commercial success with nexus, or industry praise for this patent. Conversely, the patent is untested at the PTAB and unasserted in litigation (per the PTAB and Litigation sections), so there are no objective indicia on either side of the ledger. In a first IPR, the patent owner will have the burden of producing any secondary-considerations evidence; as of today, none exists that I can identify.

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11. Honest limitations

• Seven of the nine cited references remain metadata-only. For US 7,102,335, US 7,202,733, US 2014/0159734, US 2018/0145543, US 2019/0068144, US 10,168,363, and US 2021/0048453, my § 103 mappings rest on title, assignee, date, and field knowledge. Every combination above that leans on those references must be re-verified against the reference's actual disclosure before it is relied upon. Combinations A and F (built on US 9,882,482 and US 11,082,019, both read in full) are the most defensible; Combinations C and D are the most dependent on unverified art.
• No specific reference verified for the claim 8 "first power circuit"/on-die integration element. That part of Combination D is general-knowledge reasoning. A real challenge needs a 2018–2020 automotive PMIC datasheet or equivalent.
• The prosecution record is opaque. The patent's legal events show a non-final action (2022‑01‑24), a response (2022‑04‑04), and allowance without a final rejection on the visible record. I do not know what the examiner relied on to allow. If the examiner withdrew a rejection over US 9,882,482 in response to an argument (rather than an amendment), that argument is the single most useful document for predicting how a patent owner will defend, and it should be pulled from PatentCenter before any petition is drafted. I could not retrieve it.
• I have not performed an independent prior-art search. This analysis is bounded by the references of record. The strongest art against claim 1 may well be outside the cited set (e.g., high-side current-shunt monitor datasheets from TI/ADI/onsemi pre-2019, and the Cheng et al. 2017 current-shunt-monitor paper noted in the Similar Documents list, which is not a reference of record here). A first IPR's economics turn on that search, not on this record.
• Claim construction risk on claim 1's second resistor. Claim 1 recites "a second resistor coupled to the first input terminal of the operational amplifier and the second terminal of the first resistor." Read literally, both ends land at the amplifier input node (a degenerate connection); the specification describes R2 between the non-inverting input and Vref. A challenger should not build a mapping on the literal (degenerate) reading, because a court will almost certainly construe it consistently with the specification. This does not change the obviousness analysis, but it changes how the element is mapped.
• Date note reiterated: the header date (2026‑04‑26) and system date (2026‑09‑29) disagree; nothing in the § 103 analysis turns on it.

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12. Recommended next steps for a § 103 challenge

1. Pull the prosecution history (PatentCenter, 2026‑01‑24 and 2022‑04‑04 documents) to learn exactly what was argued over US 9,882,482 — that argument defines the narrowest distinguishing feature and thus the target of the petition.
2. Obtain full text of US 10,168,363 B1 and US 7,102,335 B1 (the two most likely § 103 secondaries for the high-voltage-range and architecture limitations).
3. Full-text read of US 9,882,482 col.-by-col. against claim 1's differential-trim limitation — this is the decisive element and the one the cited art most clearly fails to teach (per Prior Art § 5, which reaches the same conclusion).
4. Run an independent search on (a) trim-coded calibration current injected into a sense-amplifier summing node, (b) high-side current monitors with supply-dependent offset correction, and (c) automotive PMIC datasheets showing on-die LDO + MCU power paths. This is where the claim 8 challenge will be won or lost.
5. Lead with claim 8 in any IPR. It omits the calibration circuit, its remaining elements are conventional, and it is the claim for which a challenger does not need to defeat the '456's strongest (and only genuinely novel-looking) limitation.

Bottom line: US 11,402,456 is not anticipated by any reference of record, but independent claim 8 is squarely obvious over a sensing-amplifier primary reference combined with an on-chip LDO (a reference already of record via the NPL citation) and routine PMIC integration; claim 16 is obvious over a gm→TIA signal chain plus a trim-coded calibration current; claims 7, 15 and 18 are highly obvious given US 11,082,019's disclosed chopper switches; and claim 1 is prima facie obvious over US 9,882,482 in view of US 11,082,019, subject to defeating the teaching-away argument based on the '482's equal, same-direction, zero-when-satisfied adjusting currents.