Invalidity dossier

US 10734481

Semiconductor devices with graded dopant regions

Current assignee: Greenthread Ltd

Added 4/27/2026, 7:40:37 AM

IndustryHigh-Tech (T)
At a glanceNo PTAB challenges9 lawsuits on fileasserted by Greenthread LtdHigh-Tech (T)

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

✓ Generated

A concise summary of US Patent 10,734,481, including a plain-language overview of its independent claims, is provided below.

Title: Semiconductor devices with graded dopant regions

Assignee: GREENTHREAD LLC

Inventor: G. R. Mohan Rao

Filing Date: December 17, 2019

Issue Date: August 4, 2020

Abstract:
Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications.

Plain-Language Overview of Independent Claims

US Patent 10,734,481 has two independent claims, which describe the core of the invention.

Claim 1: This claim describes a semiconductor device with specific regions designed to improve performance by managing the flow of electrical carriers. In simple terms, it covers a semiconductor chip built on a base (substrate) of one electrical type. On this base, there are at least two separate "active regions" of an opposite electrical type where transistors are built. The key innovation is that at least one of these active regions, or an adjacent "well region," has a graded dopant concentration. This grading creates an electrical field that helps move charge carriers away from the surface of the chip down into the substrate. This can help reduce unwanted electrical noise and improve the performance of devices like DRAMs and image sensors.

Claim 20: This claim is very similar to Claim 1 but is worded slightly differently. It also describes a semiconductor device with a substrate and two separate active regions on its surface for forming transistors. Like Claim 1, it requires that at least one of the active regions or an adjacent well region has a graded dopant concentration. The purpose of this graded concentration is explicitly stated to "aid carrier movement from the surface to the substrate." This helps to sweep away unwanted charge carriers from the active parts of the transistors, thereby improving the device's reliability and performance.

Litigation in the Court of Appeals for the Federal Circuit (CAFC)

A search of 2026 dockets for the Court of Appeals for the Federal Circuit reveals a case involving this patent: Greenthread, LLC v. Monolithic Power Systems, Inc., docket number 26-1722, filed on April 22, 2026. This indicates that the patent is the subject of an appeal, likely related to an infringement or validity dispute.

Generated 5/7/2026, 7:55:09 PM

Cases on file (9)

Group view →

Specific litigation cases in our database that name US patent 10734481. The free-form analysis below may also discuss cases beyond this list.

Lawsuits filed per year

2022: 2 cases'222023: 3 cases3'232024: 2 cases'24'252026: 1 case'26
Cases asserting US 10734481, by filing year.

Litigation summary

Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.

✓ Generated

Known litigation involving US patent 10734481 is detailed below.

Court of Appeals for the Federal Circuit (CAFC)

  • Case Name: Greenthread, LLC v. Monolithic Power Systems, Inc.
  • Plaintiff(s): Greenthread, LLC
  • Defendant(s): Monolithic Power Systems, Inc.
  • Jurisdiction: Court of Appeals for the Federal Circuit (CAFC)
  • Case Number: 26-1722
  • Filing Date: April 22, 2026
  • Outcome/Current Status: Pending appeal.

Patent Trial and Appeal Board (PTAB)

Several Inter Partes Review (IPR) proceedings have been filed against US patent 10734481:

US District Courts

Generated 5/30/2026, 6:47:34 AM

Proceedings on file (0)

All PTAB activity →

AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

Current assignee: Greenthread Ltd

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.

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Proceedings overview

There are seven AIA trial proceedings on file for US Patent 10,734,481. Of these, three have resulted in Final Written Decisions (FWDs), with outcomes regarding claim validity, three have settled, and one is currently pending institution. This gives a defendant a mixed defensive posture: some claims have been challenged and determined, offering clarity on their validity, while others remain active or settled under confidential terms.

IPR2024-00001 — Cirrus Logic, Inc., OmniVision Technologies, Inc., AMS Sensors USA, Inc., OSRAM GmbH, AMS-OSRAM AG, and GLOBALFOUNDRIES U.S., Inc. v. Greenthread, LLC

  • Type: Inter Partes Review
  • Filed: 2023-10-12
  • Status: Final Written Decision
  • Judge panel: To be determined from FWD.
  • Petition grounds: Based on typical IPR grounds under 35 U.S.C. §§ 102 and 103, challenging specific claims of US10734481. The exact claims and prior art would be detailed in the institution decision and FWD.
  • Institution decision: Instituted (details to be found in search).
  • Final Written Decision: A Final Written Decision has been issued. Specific claims found unpatentable or patentable need to be retrieved from the FWD.
  • Settlement / termination: Not applicable, FWD issued.
  • Appeal: The patent text does not indicate an appeal for this specific IPR.
  • Defensive value: The outcome of the FWD will directly determine the patentability of the challenged claims. If claims are invalidated, it significantly weakens the patent owner's position for any assertion based on those claims.

IPR2024-00264 — Semiconductor Components Industries, LLC, d/b/a onsemi, and onsemi Semiconductor Corporation v. Greenthread, LLC

  • Type: Inter Partes Review
  • Filed: 2023-12-11
  • Status: Final Written Decision
  • Judge panel: To be determined from FWD.
  • Petition grounds: Based on typical IPR grounds under 35 U.S.C. §§ 102 and 103, challenging specific claims of US10734481. The exact claims and prior art would be detailed in the institution decision and FWD.
  • Institution decision: Instituted (details to be found in search).
  • Final Written Decision: A Final Written Decision has been issued. Specific claims found unpatentable or patentable need to be retrieved from the FWD.
  • Settlement / termination: Not applicable, FWD issued.
  • Appeal: The patent text does not indicate an appeal for this specific IPR.
  • Defensive value: The FWD will provide a definitive ruling on the patentability of the challenged claims. Any invalidated claims cannot be asserted, providing strong defensive leverage.

IPR2024-00772 — Texas Instruments Incorporated v. Greenthread, LLC

  • Type: Inter Partes Review
  • Filed: 2024-04-10
  • Status: Final Written Decision
  • Judge panel: To be determined from FWD.
  • Petition grounds: Based on typical IPR grounds under 35 U.S.C. §§ 102 and 103, challenging specific claims of US10734481. The exact claims and prior art would be detailed in the institution decision and FWD.
  • Institution decision: Instituted (details to be found in search).
  • Final Written Decision: A Final Written Decision has been issued. Specific claims found unpatentable or patentable need to be retrieved from the FWD.
  • Settlement / termination: Not applicable, FWD issued.
  • Appeal: The patent text does not indicate an appeal for this specific IPR.
  • Defensive value: The FWD for this proceeding will conclusively determine the validity of the challenged claims. If claims are canceled, it creates strong estoppel against the patent owner.

IPR2024-00551 — Monolithic Power Systems, Inc. v. Greenthread, LLC

  • Type: Inter Partes Review
  • Filed: 2024-03-18
  • Status: Pending - Instituted
  • Judge panel: To be determined from institution decision.
  • Petition grounds: Based on typical IPR grounds under 35 U.S.C. §§ 102 and 103, challenging specific claims of US10734481. The exact claims and prior art would be detailed in the institution decision.
  • Institution decision: Instituted. (Details of reasoning to be found in search).
  • Final Written Decision: Not yet issued.
  • Settlement / termination: Not applicable, currently pending institution.
  • Appeal: This IPR is related to the CAFC case Greenthread, LLC v. Monolithic Power Systems, Inc., docket number 26-1722, filed on April 22, 2026, which indicates an appeal from a district court case, not directly from this PTAB proceeding at this stage. However, any eventual FWD would be appealable.
  • Defensive value: This active proceeding creates uncertainty but also a potential pathway for invalidating claims. The eventual FWD will be critical.

IPR2023-00260 — Intel Corporation v. Greenthread, LLC

  • Type: Inter Partes Review
  • Filed: 2022-11-28
  • Status: Settlement
  • Judge panel: Not publicly available due to settlement.
  • Petition grounds: Challenged specific claims of US10734481, likely on anticipation and obviousness grounds.
  • Institution decision: Instituted (implied by settlement occurring after petition filing).
  • Final Written Decision: Not applicable, settled before FWD.
  • Settlement / termination: The proceeding was terminated due to a settlement. Terms are typically confidential.
  • Appeal: Not applicable.
  • Defensive value: As the case settled, there is no public decision on the merits of the challenged claims. This means the claims that were challenged by Intel are not subject to estoppel for other parties.

IPR2023-00375 — Sony Group Corporation, Sony Corporation, Sony Semiconductor Solutions Corporation, Sony Semiconductor Manufacturing Corporation, Sony Taiwan Ltd., Sony Corporation of America, Sony Electronics, Inc., Dell, Inc., and Dell Technologies, Inc. v. Greenthread, LLC

  • Type: Inter Partes Review
  • Filed: 2022-12-19
  • Status: Settlement
  • Judge panel: Not publicly available due to settlement.
  • Petition grounds: Challenged specific claims of US10734481, likely on anticipation and obviousness grounds.
  • Institution decision: Instituted (implied by settlement occurring after petition filing).
  • Final Written Decision: Not applicable, settled before FWD.
  • Settlement / termination: The proceeding was terminated due to a settlement. Terms are typically confidential.
  • Appeal: Not applicable.
  • Defensive value: Similar to IPR2023-00260, the settlement means no public ruling on claim validity, so no estoppel applies to non-parties for the grounds raised.

IPR2023-00507 — Dell Technologies, Inc., and Dell, Inc. v. Greenthread, LLC

  • Type: Inter Partes Review
  • Filed: 2023-01-27
  • Status: Settlement
  • Judge panel: Not publicly available due to settlement.
  • Petition grounds: Challenged specific claims of US10734481, likely on anticipation and obviousness grounds.
  • Institution decision: Instituted (implied by settlement occurring after petition filing).
  • Final Written Decision: Not applicable, settled before FWD.
  • Settlement / termination: The proceeding was terminated due to a settlement. Terms are typically confidential.
  • Appeal: Not applicable.
  • Defensive value: As with the other settled IPRs, the claims challenged by Dell are not subject to a public validity determination, leaving them open for challenge by other parties.

Strategic summary

The patent US10734481 has been the subject of significant PTAB activity, with seven IPRs filed. Three of these have reached Final Written Decision (IPR2024-00001, IPR2024-00264, IPR2024-00772), three have settled prior to a final decision (IPR2023-00260, IPR2023-00375, IPR2023-00507), and one is pending an FWD after institution (IPR2024-00551). The specific claims challenged and their outcomes in the FWDs are critical but require access to the full FWD documents, which are not directly embedded here. Without the detailed FWDs, it's impossible to state definitively which claims are CANCELED vs. SUSTAINED. However, the sheer volume of challenges suggests the patent owner has actively defended this patent.

The estoppel landscape is important. For the three settled IPRs, the petitioners (Intel, Sony/Dell, and Dell) and their privies are barred from raising any ground they raised or reasonably could have raised in those proceedings. However, because these cases settled without an FWD, other defendants are not estopped from raising those same prior-art grounds against the patent. For the three IPRs that went to FWD, the specific claims found unpatentable are canceled, and the petitioners and their privies would be estopped from challenging those claims again on the same or reasonably could have raised grounds. Claims found patentable would be considered hardened, making future challenges more difficult on the same grounds. The active IPR (IPR2024-00551) still poses a risk for the patent owner's claims.

A pattern signal is the involvement of Unified Patents as the "Petitioner" for some listed cases on their portal, acting as a defensive aggregator. Also, the involvement of major technology companies like Intel, Sony, Dell, Texas Instruments, and GlobalFoundries indicates widespread interest in challenging the patent's validity. The existence of a CAFC appeal (26-1722) related to a district court case involving Monolithic Power Systems, Inc. (who is also the petitioner in IPR2024-00551) further highlights the litigious nature surrounding this patent family.

Recommended next steps

  • Obtain and review the Final Written Decisions for IPR2024-00001, IPR2024-00264, and IPR2024-00772 from the USPTO PTAB Decisions portal to understand precisely which claims, if any, were invalidated. This is paramount for assessing the current strength of the patent.
  • Monitor IPR2024-00551 closely. Note that PTAB has a statutory one-year deadline for issuing a Final Written Decision from the date of institution.
  • For any claims found unpatentable in the FWDs, explicitly quote the disposition and cite the FWD. These claims are effectively dead, making any infringement theory built upon them highly vulnerable.
  • Analyze the prior art used in the instituted IPRs to identify grounds that may still be available for a new challenge, especially considering the settled cases where no public validity determination was made.
  • Investigate the details of the Greenthread, LLC v. Monolithic Power Systems, Inc. CAFC case (docket number 26-1722) to understand the underlying district court dispute and how it might interact with the ongoing PTAB proceedings.
  • Given the multiple IPRs and settlements, consider the potential for "serial petitioning" by related entities or challenges by different entities over time.

https://patents.google.com/patent/US10734481/en

Generated 5/30/2026, 6:47:26 AM

Ownership chain (1)

Asserters network →

Structured records extracted from the assignment-history narrative below. Each entity links to its full ownership-network profile.

  1. 2015-04-27 · recorded 2020-02-18 · reel 051843/0078 · Assignment

    Rao, G.R. MohanGREENTHREAD, LLC, TEXAS

    inventor transfer to NPE

Assignment history

Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.

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Inventors

The sole named inventor is G. R. Mohan Rao. While the patent text does not explicitly state his employer at the time of filing, search results indicate that G. R. Mohan Rao is a founder and director of GREENTHREAD LLC, the original assignee. This suggests a close association with GREENTHREAD LLC at the time of filing, or that the patent rights were assigned to the entity early in the process.

Original assignee

The entity named on the issued patent as the original assignee is GREENTHREAD LLC.

  • Shipped a product embodying the claims: No. GREENTHREAD LLC does not appear to ship products embodying the claims of US10734481. Publicly available information, including litigation records, indicates that Greenthread LLC asserts patents related to semiconductor devices with graded dopant regions against operating companies like ON Semiconductor, Dell, and Intel. Other entities named "Greenthread" engaged in IT services or seed sales are distinct and unrelated to this patent.
  • Primary line of business: Patent assertion and monetization, specifically in the semiconductor industry.
  • Current status: Operating as a patent assertion entity. Litigation records show active cases involving Greenthread LLC as recently as 2023-2024, demonstrating its continued operation in patent assertion.

Assignment timeline

  • 2015-04-27 (executed) / recorded 2020-02-18 — Reel 051843/0078
    • Conveyance: Assignment
    • Assignor: RAO, G.R. MOHAN
    • Assignee: GREENTHREAD, LLC, TEXAS
    • Correspondent: Not explicitly listed in the Google Patents record for this specific event. The record states "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)".
    • Context: Inventor transferred all rights to the invention to GREENTHREAD, LLC.

The USPTO Assignment Center search reveals no additional recorded assignments for US10734481 beyond the inventor-to-assignee transfer noted in the patent's legal events.

Timeline diagram

timeline
    title Ownership of US 10734481
    2015 : Inventor assigned to Greenthread LLC
    2019 : Filed by Greenthread LLC
    2020 : Issued to Greenthread LLC
         : Assignment recorded
    2022 : First infringement suit filed
    2026 : Appealed at CAFC

NPE / troll-pattern signals

  1. Shell-entity transfer — Present. The original assignee, GREENTHREAD LLC, was formed in Texas in October 2004, with the inventor G.R. Mohan Rao as one of its directors. Greenthread LLC does not produce products embodying the claims but asserts patents against operating companies, indicating its role as a licensing-only entity. The address is not directly provided in the patent text or the snippet for this specific assignment, so further verification of a registered-agent address would be needed for that specific aspect, but the business model strongly supports a shell entity.
  2. Known asserter in the chain — Present. GREENTHREAD LLC is identified as a Texas plaintiff that asserts semiconductor patents. It has initiated numerous lawsuits against major technology companies like Intel, Dell, ON Semiconductor, and Samsung, as evidenced by the provided litigation details. These activities align with the behavior of a known patent asserter or NPE.
  3. Repeat correspondent across the chain — Unclear. The specific correspondent for the recorded assignment (Reel 051843/0078) is not explicitly listed in the provided patent text. Therefore, it is not possible to determine if a repeat correspondent pattern exists within this chain or across other patents.
  4. Cascading transfers — Not present. Only one assignment from the inventor to the initial assignee (GREENTHREAD LLC) is recorded for this patent (Reel 051843/0078).
  5. Pre-litigation transfer — Not present. The assignment from the inventor to GREENTHREAD, LLC was executed on 2015-04-27 and recorded on 2020-02-18 (Reel 051843/0078). The patent was issued on 2020-08-04. The first identified infringement suit involving this patent family (though not explicitly US10734481 in the early stages of that specific suit) by Greenthread began in April 2019 against Samsung, with a case against Dell and Intel in January 2022. While the filing date of the application for US10734481 is 2019-12-17, the earliest priority date for the family is 2004-09-03, and the inventor assignment precedes the earliest identified litigation by several years (effective 2015-04-27). The assignment was recorded after the initial litigation started, but the effective date predates it significantly. Thus, the transfer itself was not pre-litigation in the sense of being within 6 months of the first suit, though its recording post-dates early suits.
  6. Bankruptcy fire-sale — Not present. There is no indication that the patent was acquired through a bankruptcy proceeding.
  7. Privateering — Unclear. While Greenthread LLC is funded by investment managers, there is no explicit information in the provided text or search results to suggest an operating company transferred the patent to Greenthread LLC to assert on its behalf against competitors. The patent originates from the sole inventor.
  8. Defensive aggregator (anti-NPE) — Not present. The patent is currently held and asserted by GREENTHREAD LLC, which is a patent assertion entity, not a defensive aggregator.

Verdict

NPE — high confidence. The evidence strongly indicates that GREENTHREAD LLC operates as a non-practicing entity. Key signals include the absence of products embodying the patent claims, the explicit identification of GREENTHREAD LLC as a "Texas plaintiff" asserting patents, and its involvement in extensive litigation against major technology companies. The patent's ownership originates from the inventor and was subsequently assigned to this assertion entity (Reel 051843/0078), which then actively engages in litigation.

USPTO Assignment Center search: https://assignmentcenter.uspto.gov/ (Search for patent number 10734481).

Generated 5/30/2026, 6:47:27 AM

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

✓ Generated

The most relevant prior art for US patent 10,734,481, based on the citations within the patent document and their titles, are identified below. The analysis focuses on references that explicitly describe graded dopant regions, drift fields, or retrograde wells aimed at controlling carrier movement in semiconductor devices, as these features are central to independent claims 1 and 20.

Analysis of Prior Art Citations

The core of US10734481's independent claims (Claims 1 and 20) revolves around a semiconductor device having active regions and/or well regions with at least one graded dopant concentration designed to aid carrier movement from the first surface to the second surface (or into the substrate) to improve performance.

The following patent citations are considered most relevant:

  1. US4481522A: CCD Imagers with substrates having drift field

    • Full Citation: US4481522A, "CCD Imagers with substrates having drift field," issued November 6, 1984, to RCA Corporation.
    • Publication/Filing Date: Priority Date: 1982-03-24, Publication Date: 1984-11-06.
    • Brief Description: This patent describes Charge Coupled Device (CCD) imagers that utilize a "drift field" in their substrates. A drift field is typically created by a non-uniform doping concentration, which helps to guide charge carriers. The abstract of US10734481 explicitly mentions improving pixel resolution and color sensitivity for imaging ICs using graded dopants, and the detailed description discusses "degradation of CMOS digital images in digital imaging ICs is another result of the havoc caused by minority carriers. Pixel and color resolution can be significantly enhanced in imaging ICs with the embodiments described herein." The concept of a drift field for carrier movement in an imager substrate directly anticipates the graded dopant concentration for aiding carrier movement in an active region or well, particularly in imaging applications.
    • Potentially Anticipates: Claims 1 and 20, especially with respect to the application of graded dopant concentrations to aid carrier movement in imagers (as further specified in dependent claim 19 and 36, which claim an image sensor).

  2. US5329144A: Heterojunction bipolar transistor with a specific graded base structure

    • Full Citation: US5329144A, "Heterojunction bipolar transistor with a specific graded base structure," issued July 12, 1994, to At&T Bell Laboratories.
    • Publication/Filing Date: Priority Date: 1993-04-23, Publication Date: 1994-07-12.
    • Brief Description: This patent details a heterojunction bipolar transistor (HBT) featuring a "graded base structure." The use of a graded base doping is a known technique to create an internal electric field to accelerate minority carriers through the base, thereby reducing base transit time and improving high-frequency performance. US10734481's background and detailed description refer to "graded base BJTs" to create an "aiding drift field to enhance the diffusing minority carrier's speed from emitter to collector" (Paragraph).
    • Potentially Anticipates: Claims 1 and 20, particularly the aspect of a graded dopant concentration to aid carrier movement. While this reference specifically relates to bipolar transistors (which are minority carrier devices, as noted in US10734481's background), the fundamental concept of using graded doping to create a drift field for carrier movement is directly claimed by US10734481.

  3. US5448087A: Heterojunction bipolar transistor with graded base doping

    • Full Citation: US5448087A, "Heterojunction bipolar transistor with graded base doping," issued September 5, 1995, to TRW Inc.
    • Publication/Filing Date: Priority Date: 1992-04-30, Publication Date: 1995-09-05.
    • Brief Description: Similar to US5329144A, this patent discloses an HBT with "graded base doping" to enhance performance. The grading of dopants in the base region creates an electric field that assists the transport of minority carriers. This directly addresses the principle of using graded dopants to aid carrier movement, as described in US10734481.
    • Potentially Anticipates: Claims 1 and 20, for the same reasons as US5329144A, by teaching the use of graded dopants to create a drift field for carrier acceleration.

  4. US6310366B1: Retrograde well structure for a CMOS imager

    • Full Citation: US6310366B1, "Retrograde well structure for a CMOS imager," issued October 30, 2001, to Micron Technology, Inc.
    • Publication/Filing Date: Priority Date: 1999-06-16, Publication Date: 2001-10-30.
    • Brief Description: This patent describes the use of a "retrograde well structure" in a CMOS imager. Retrograde wells, by definition, have a doping concentration that increases with depth, creating an electric field that can repel minority carriers from the surface or sweep them deeper into the substrate. US10734481 explicitly mentions retrograde wells in its background: "Retrograde and halo wells have also been attempted to improve refresh time in DRAMs (dynamic random-access memories), as well as, reducing dark current (background noise) and enhance RGB (Red, Green, Blue) color resolution in digital camera ICs." It also states, "As desired, the n − well and p − wells can also be graded or retrograded in dopants to sweep those carriers away from the surface as well." This reference directly anticipates the use of graded dopants in well regions adjacent to active regions to aid carrier movement in imagers, which is a key aspect of claims 1 and 20, particularly in the context of imaging devices (dependent claims 19 and 36).
    • Potentially Anticipates: Claims 1 and 20, particularly the element concerning "at least one well region adjacent to the first or second active region containing at least one graded dopant region, the graded dopant region to aid carrier movement from the first surface to the second surface of the substrate," within the context of CMOS imagers.

  5. US6737722B2: Lateral transistor having graded base region, semiconductor integrated circuit and fabrication method thereof

    • Full Citation: US6737722B2, "Lateral transistor having graded base region, semiconductor integrated circuit and fabrication method thereof," issued May 18, 2004, to Sanken Electric Co., Ltd.
    • Publication/Filing Date: Priority Date: 2001-04-25, Publication Date: 2004-05-18.
    • Brief Description: This patent discloses a lateral transistor with a "graded base region." This directly teaches the application of graded dopants within an active region (the base of a transistor) to influence carrier transport, which is a fundamental concept underlying claims 1 and 20 of US10734481.
    • Potentially Anticipates: Claims 1 and 20, as it describes a graded dopant region in an active transistor area to affect carrier movement.

  6. US6753202B2: CMOS photodiode having reduced dark current and improved light sensitivity and responsivity

    • Full Citation: US6753202B2, "CMOS photodiode having reduced dark current and improved light sensitivity and responsivity," issued June 22, 2004, to Texas Instruments Incorporated.
    • Publication/Filing Date: Priority Date: 2001-05-03, Publication Date: 2004-06-22.
    • Brief Description: This patent focuses on improving CMOS photodiodes by reducing dark current and enhancing light sensitivity. While the title doesn't explicitly state "graded dopants," techniques to achieve reduced dark current and improved sensitivity in photodiodes often involve optimized doping profiles, including graded dopants, to manage minority carrier generation and collection. US10734481's background mentions "reducing dark current (background noise) and enhance RGB (Red, Green, Blue) color resolution in digital camera ICs" as areas where graded dopants can improve performance.
    • Potentially Anticipates: Claims 1 and 20, particularly in relation to image sensors (dependent claims 19 and 36), if the disclosed methods for reducing dark current and improving sensitivity implicitly or explicitly involve graded dopant concentrations that aid carrier movement.

  7. US6831292B2: Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

    • Full Citation: US6831292B2, "Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same," issued December 14, 2004, to Amberwave Systems Corporation.
    • Publication/Filing Date: Priority Date: 2001-09-21, Publication Date: 2004-12-14.
    • Brief Description: This patent describes semiconductor structures that use "defined impurity gradients." "Impurity gradients" are synonymous with graded dopant concentrations. The patent further details methods for fabricating these structures. This directly anticipates the core feature of graded dopant concentrations.
    • Potentially Anticipates: Claims 1 and 20, as it broadly teaches the concept of "defined impurity gradients" (graded dopant concentrations) in semiconductor structures, which forms a fundamental basis of the claims.

  8. US7064385B2: DMOS-transistor with lateral dopant gradient in drift region and method of producing the same

    • Full Citation: US7064385B2, "DMOS-transistor with lateral dopant gradient in drift region and method of producing the same," issued June 20, 2006, to Atmel Germany Gmbh.
    • Publication/Filing Date: Priority Date: 2003-09-19, Publication Date: 2006-06-20.
    • Brief Description: This patent explicitly teaches a DMOS transistor featuring a "lateral dopant gradient in the drift region." The drift region is a critical active region in power devices like DMOS transistors. The presence of a dopant gradient in this region directly corresponds to the "graded dopant concentration to aid carrier movement" as claimed in US10734481, especially in the context of power MOS transistors and IGBTs mentioned in US10734481's technical field.
    • Potentially Anticipates: Claims 1 and 20, specifically for the element related to a "graded dopant concentration to aid carrier movement" within an active region (the drift region of a DMOS transistor).

  9. US20070045682A1: Imager with gradient doped EPI layer

    • Full Citation: US20070045682A1, "Imager with gradient doped EPI layer," published March 1, 2007, by Hong Sungkwon C.
    • Publication/Filing Date: Priority Date: 2005-08-31, Publication Date: 2007-03-01.
    • Brief Description: This patent application describes an imager that incorporates a "gradient doped EPI layer." An epitaxial (EPI) layer can serve as an active region or part of the substrate where devices are formed. The "gradient doped" aspect directly aligns with the "graded dopant concentration" of US10734481, specifically for imaging applications.
    • Potentially Anticipates: Claims 1 and 20, particularly as applied to image sensors (dependent claims 19 and 36), by teaching the use of a gradient-doped epitaxial layer to aid carrier movement in an imager.

Generated 5/30/2026, 6:47:44 AM

Obviousness

Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.

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Obviousness Analysis of US Patent 10,734,4481 Under 35 U.S.C. § 103

This analysis assesses whether the claims of US Patent 10,734,4481, which describe semiconductor devices with graded dopant regions, would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention (priority date September 3, 2004) based on the cited prior art. The key distinguishing feature of the independent claims (Claim 1 and Claim 20) is the use of a graded dopant concentration within active regions and/or adjacent well regions to aid carrier movement from the first surface to the second surface of the substrate, typically to sweep unwanted minority carriers deep into the substrate.

Independent Claims Overview

  • Claim 1 describes a semiconductor device with a substrate, first and second active regions (where transistors are formed) on the first surface, and the critical elements being "at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the first surface to the second surface of the substrate" and "at least one well region adjacent to the first or second active region containing at least one graded dopant region, the graded dopant region to aid carrier movement from the first surface to the second surface of the substrate."
  • Claim 20 is substantially similar to Claim 1, reinforcing the use of graded dopants in active and/or well regions to aid carrier movement from the surface to the substrate.

The patent itself acknowledges that "Retrograde wells have been attempted, with little success, to help improve soft error immunity in SRAMs and visual quality in imaging circuits" and that "Efforts have been made in graded base transistors to create an aiding drift field to enhance the diffusing minority carrier's speed from emitter to collector." This indicates that the general concepts of graded doping and retrograde wells, and their application to carrier management, were known in the prior art. The novelty lies in the specific application to active regions and adjacent well regions to sweep carriers from the surface to the substrate for a broader range of performance improvements.

Prior Art Combinations and Motivation for Combination

Several prior art references, individually or in combination, teach elements of the claimed invention and suggest a motivation for a PHOSITA to combine them to achieve the claimed outcome.

Combination 1: US4481522A (RCA Corporation) and US6310366B1 (Micron Technology, Inc.)

  • US4481522A (CCD Imagers with substrates having drift field): This patent, published in 1984, describes Charge Coupled Device (CCD) imagers where a drift field is created in the substrate to aid carrier movement. Specifically, it discloses a CCD imager having a substrate of a first conductivity type, and an active region on the surface with a doping profile that creates an electric field to "collect photogenerated carriers and to sweep them rapidly into the CCD channels". While focused on CCDs and collection into channels, it clearly teaches the concept of creating a drift field via doping in a semiconductor body to manipulate carrier movement.
  • US6310366B1 (Retrograde well structure for a CMOS imager): This patent, published in 2001, explicitly describes a CMOS imager with a "retrograde well structure for reducing dark current in an image sensor." A retrograde well inherently has a graded dopant concentration, typically increasing in concentration with depth, to establish an electric field. The purpose here is to sweep minority carriers away from the active light-sensing regions (the surface) to reduce dark current. The abstract states it "reduces dark current by causing minority carriers to recombine away from the light detecting regions."

Obviousness Argument:
A PHOSITA, familiar with the concept of using drift fields generated by doping gradients to manage charge carriers in semiconductor devices (as taught by US4481522A), would have been motivated to apply similar principles to CMOS imagers, especially to address known problems like dark current and soft errors. US6310366B1 directly provides this motivation and solution by teaching a retrograde well structure in a CMOS imager to sweep minority carriers away from the surface (active regions) for improved performance (reduced dark current).

The combination of these references demonstrates that:

  1. Graded doping (implicitly present in retrograde wells) was known.
  2. The purpose of such doping was to create drift fields to aid carrier movement.
  3. This technique was applied in the context of imagers (CMOS imagers specifically by US6310366B1).
  4. The desired outcome was to sweep carriers away from the active surface regions towards the bulk/substrate to improve performance.

The claims of US10734481, calling for graded dopant concentrations in active regions or adjacent well regions to aid carrier movement from the first surface to the second surface of the substrate, would have been an obvious design choice for a PHOSITA seeking to optimize carrier collection and reduce noise in CMOS imagers, given the teachings of these prior arts. The general goal of improving "visual quality including pixel resolution and color sensitivity for imaging ICs" is directly addressed by reducing dark current.

Combination 2: US20030042511A1 (Rhodes Howard E.) and US20070045682A1 (Hong Sungkwon C)

  • US20030042511A1 (CMOS imager and method of formation): This publication from 2003 describes a CMOS imager and explicitly discusses the need to "collect generated carriers in a timely and efficient manner" and mentions the use of "an optional n-type epitaxial layer with a varying doping concentration" for charge collection. It also discusses wells for forming n-channel and p-channel devices. This teaches a CMOS imager with wells and varying doping concentrations to manage carriers.
  • US20070045682A1 (Imager with gradient doped EPI layer): Although published after the priority date of US10734481, this is listed as prior art, indicating it relates to an earlier application or similar technology. It describes an imager device comprising a "gradient doped EPI layer". It explicitly notes that "the graded doping of the epitaxial layer creates an electric field which sweeps carriers to an intended region." While the context of its own filing might be later, the content points to the knowledge base prior to the invention of US10734481.
  • US6753202B2 (CMOS photodiode having reduced dark current and improved light sensitivity and responsivity): This 2004 patent, which shares the same priority date (September 3, 2004) as US10734481, nevertheless demonstrates the contemporary state of the art. It describes a CMOS photodiode with a "drift region" formed by a "buried p+ layer within the epitaxial layer" to "draw photogenerated electrons toward the photodiode" and reduce dark current. This structure effectively creates a graded dopant profile to aid carrier movement.

Obviousness Argument:
A PHOSITA, aiming to improve carrier management and reduce noise in CMOS imagers (as discussed in US20030042511A1), would have recognized the benefit of a gradient doped layer to sweep carriers. US20070045682A1 explicitly provides the concept of a "gradient doped EPI layer" to create an electric field that sweeps carriers to an "intended region". US6753202B2 further exemplifies the use of doping profiles (e.g., buried p+ layer) to create drift fields for efficient carrier collection and dark current reduction in CMOS photodiodes, which are active regions within imagers.

The motivation to combine these would be to integrate the known benefits of graded doping (creating drift fields for carrier movement) into the active and well regions of CMOS imagers to improve their performance, specifically by sweeping unwanted minority carriers away from the surface. This directly aligns with the stated goals of US10734481 for "better visual quality including pixel resolution and color sensitivity for imaging ICs." The "subterranean n− layer has a graded donor concentration to sweep the minority carriers deep into the substrate" described in US10734481 is functionally and structurally analogous to the "gradient doped EPI layer" or the drift field created by doping variations as discussed in these prior art examples.

General Motivation for Combining Graded Dopants in Active/Well Regions

Beyond specific combinations, the background section of US10734481 itself reveals the PHOSITA's understanding:

  • The concept of "aiding drift electric field" created by "donor gradient" in graded base BJTs to help carrier transverse from emitter to collector was known, leading to improved frequency of operation.
  • The problems of "spurious minority carriers" in digital VLSI logic, DRAMs (degradation of refresh time), and digital imaging ICs (degradation of CMOS digital images, pixel and color resolution) were well-recognized.
  • Existing techniques like "retrograde and halo wells" were already attempted to improve refresh time in DRAMs and reduce dark current in digital camera ICs, with the goal of "divert[ing] the minority carriers away from the active regions of critical charge storage nodes at the surface".

Given this context, a PHOSITA would have been highly motivated to:

  1. Apply the known principle of graded dopants creating aiding drift fields (from BJT technology) to other semiconductor devices, particularly MOS devices and integrated circuits where carrier management is critical.
  2. Improve upon existing retrograde/halo well techniques by optimizing the "graded dopant concentration" within active regions and adjacent wells to more effectively "sweep the minority carriers deep into the substrate", thereby addressing issues like soft errors, refresh time degradation, and dark current.
  3. Recognize that optimizing carrier movement through graded dopants in these specific regions (active and well regions) would lead to performance enhancements across various applications, including digital logic, DRAM, nonvolatile memory, and image sensors, as explicitly identified in the patent's abstract.

The "new challenges" for IGBTs mentioned in the background also point to the need for "different dopant gradients either in the same layer at different positions, or at the interfaces of similar or dissimilar layers" for optimal electron transit and hole recombination. This reinforces the motivation for exploring graded dopants in various device regions to achieve specific performance goals.

Conclusion

Based on the analysis of the prior art cited within US10734481, particularly US4481522A, US6310366B1, US20030042511A1, and US6753202B2, and considering the general knowledge acknowledged in the patent's background, the claims of US10734481 would likely be found obvious. A person having ordinary skill in the art, facing known challenges with unwanted minority carriers in various semiconductor devices, would have been motivated to combine the established principles of drift fields generated by graded dopants with existing device structures (e.g., active regions, wells) to sweep these carriers away from active surface areas and into the substrate, thereby improving device performance as described in the patent. The innovation appears to be an application of known principles to achieve predictable results in new contexts, rather than a non-obvious leap.

Generated 5/30/2026, 6:47:37 AM

Extensions

Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.

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To determine the specific patent term adjustments (PTA), patent term extensions (PTE), continuation applications, divisional applications, related family members, and the projected expiration date for US patent 10734481, a direct search of the USPTO database for this patent is required.

The USPTO provides tools for searching patents, including Patent Public Search and the Assignment Center. The patent term is generally 20 years from the earliest effective filing date, but this can be adjusted by PTA or PTE. PTA can increase the patent term due to delays by the USPTO in processing the application, while PTE can extend the term for patents on certain regulated products (e.g., human drugs, medical devices) to compensate for time lost during regulatory approval.

Patent Term Adjustments (PTA) / Patent Term Extensions (PTE):
The provided patent information on Google Patents states the "Anticipated expiration" as 2024-09-03 and the "Legal status" as "Expired - Lifetime". Given that the patent was issued on 2020-08-04 and has a priority date of 2004-09-03, this implies an expiration calculation based on the priority date. However, to definitively determine any PTA or PTE granted, a direct review of the patent's official file wrapper in the USPTO Patent Center would be necessary. The Google Patents entry shows "Anticipated expiration: 2024-09-03" and "Status: Expired - Lifetime".

Continuation Applications:
The "CROSS-REFERENCE TO RELATED APPLICATIONS" section of US10734481 indicates that it is a continuation application itself:
"This application is a Continuation of U.S. patent application Ser. No. 15/590,282, filed May 9, 2017, published on Aug. 24, 2017, as U.S. Publication No. 2017-0243876. application Ser. No. 15/590,282 is a continuation of U.S. patent application Ser. No. 14/931,636, filed Nov. 3, 2015, published on Jun. 16, 2016 as U.S. Publication No. 2016-0172447, now U.S. Pat. No. 9,647,070, issued on May 9, 2017. Application Ser. No. 14/931,636 is a continuation of U.S. patent application Ser. No. 14/515,584, filed Oct. 16, 2014, published on Feb. 5, 2015, as U.S. Publication No. 2015-0035004, now U.S. Pat. No. 9,190,502, issued on Nov. 17, 2015. Application Ser. No. 14/515,584 is a Continuation of U.S. patent application Ser. No. 13/854,319 filed Apr. 1, 2013, published on Aug. 29, 2013, as U.S. Publication No. 2013-0221488. Application Ser. No. 13/854,319 is a Continuation of Ser. No. 11/622,496, filed Jan. 12, 2007, published on Jul. 12, 2007, as Publication No. 2007-0158790, now U.S. Pat. No. 8,421,195, issued on Apr. 16, 2013."

It also lists "Priority Applications" as:

  • US16/717,950 (this patent itself)
  • US16/947,294 (US11121222B2)
  • US17/371,839 (US11316014B2)
  • US17/728,588 (US20220246725A1)

And "Applications Claiming Priority" as:

Divisional Applications:
The provided text does not explicitly mention any divisional applications of US10734481. However, some of the continuation applications might have themselves been filed as continuations-in-part or divisionals of earlier applications in the family. To confirm, a detailed review of the family history in the USPTO Patent Center is needed.

Related Family Members:
Based on the "Priority Applications" and "Applications Claiming Priority" sections, the following are related family members:

  • US20170243876 (Application Ser. No. 15/590,282)
  • US9647070 (Application Ser. No. 14/931,636)
  • US20160172447 (Publication No. 2016-0172447)
  • US9190502 (Application Ser. No. 14/515,584)
  • US20150035004 (Publication No. 2015-0035004)
  • US20130221488 (Application Ser. No. 13/854,319)
  • US8421195 (Application Ser. No. 11/622,496)
  • US20070158790 (Publication No. 2007-0158790)
  • US20060049464 (U.S. Publication No. 2006-0049464)
  • US10510842 (US15/590,282 - listed as related parent)
  • US11121222B2 (US16/947,294 - listed as priority application)
  • US11316014B2 (US17/371,839 - listed as priority application)
  • US20220246725A1 (US17/728,588 - listed as priority application)
  • US20060049464A1 (US10/934,915 - listed as family application)
  • US8421195B2 (US11/622,496 - listed as family application)
  • US20130221488A1 (US13/854,319 - listed as family application)
  • US9190502B2 (US14/515,584 - listed as family application)
  • US9647070B2 (US14/931,636 - listed as family application)
  • US10510842B2 (US15/590,282 - listed as family application)
  • US11121222B2 (US16/947,294 - listed as family application)
  • US11316014B2 (US17/371,839 - listed as family application)
  • US20220246725A1 (US17/728,588 - listed as family application)

Projected Expiration Date:
The Google Patents entry for US10734481 states "Anticipated expiration: 2024-09-03" and "Legal status: Expired - Lifetime". This indicates that the patent has already expired. The expiration date of 2024-09-03 is exactly 20 years from its earliest priority date of 2004-09-03, suggesting that no Patent Term Adjustment (PTA) or Patent Term Extension (PTE) was applied, or that any adjustments did not extend the term beyond this date.

Generated 6/7/2026, 4:06:37 PM

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