US 11121222

A detailed analysis of U.S. Patent 11,121,222 reveals a focus on enhancing semiconductor performance by manipulating dopant concentrations. Below is a summary of the patent's key details and a simplified explanation of its independent claims. A search of the CAFC 2026 dockets for this patent number yielded no results.

Summary of U.S. Patent 11,121,222

Title: Semiconductor devices with graded dopant regions

Assignee: GREENTHREAD LLC

Inventor: G.R. Mohan Rao

Filing Date: July 27, 2020

Issue Date: September 14, 2021

Abstract:
Most semiconductor devices manufactured today have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application-specific areas like an increase in the frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications.

Plain-Language Overview of Independent Claims

The independent claims of a patent define the core of the invention. For U.S. Patent 11,121,222, these can be understood as follows:

• Claim 1: This claim outlines a Very Large Scale Integration (VLSI) semiconductor device, which is a complex integrated circuit. The innovation lies in creating a "graded dopant concentration" within the active areas where transistors are built. This graded doping profile creates an electrical field that actively pushes charge carriers away from the sensitive transistor regions towards an unused part of the substrate. The claim also specifies a "well region" with a similar graded doping to further assist in clearing unwanted charge carriers from the device's surface. The transistors in this device are intended to be used for digital logic.

• Claim 21: This claim is also directed at a VLSI semiconductor device with a similar structure to that described in Claim 1. Its unique aspect is the specific definition of the graded dopant profile. It states that the concentration gradient can follow several mathematical patterns, such as linear, quasi-linear, or error function distributions.

• Claim 39: This claim describes a broader semiconductor device, not limited to VLSI. It focuses on the fundamental concept of having two separate active regions for transistors where at least one has a graded dopant concentration. The purpose of this gradient is to facilitate the movement of charge carriers away from the active region to an inactive area of the substrate.

• Claim 41: This claim narrows the scope of the general semiconductor device by specifying that the graded dopant concentration is composed of "acceptor" dopants, which are used to create p-type semiconductor material.

• Claim 42: Similar to the above, this claim specifies the use of "donor" dopants for the graded concentration, which are used to create n-type semiconductor material.

• Claim 43: This claim combines the concepts of the previous two, describing a semiconductor device that utilizes both graded acceptor and graded donor dopant concentrations to help steer charge carriers away from the active transistor areas.

• Claim 44: This claim is specific to a Complementary Metal-Oxide-Semiconductor (CMOS) device. It describes a structure featuring a "single drift layer" with a graded dopant concentration situated between the device's surface and the underlying substrate. This layer is designed to create a built-in, one-way electric field that pushes charge carriers away from the surface. The claim also includes a "well region" within this drift layer that has its own graded doping and associated electric field to further enhance this effect.