US 11121222

A detailed analysis of U.S. Patent 11,121,222 reveals a focus on enhancing semiconductor performance by manipulating dopant concentrations. Below is a summary of the patent's key details and a simplified explanation of its independent claims. A search of the CAFC 2026 dockets for this patent number yielded no results.

Summary of U.S. Patent 11,121,222

Title: Semiconductor devices with graded dopant regions

Assignee: GREENTHREAD LLC

Inventor: G.R. Mohan Rao

Filing Date: July 27, 2020

Issue Date: September 14, 2021

Abstract:
Most semiconductor devices manufactured today have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application-specific areas like an increase in the frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications.

Plain-Language Overview of Independent Claims

The independent claims of a patent define the core of the invention. For U.S. Patent 11,121,222, these can be understood as follows:

• Claim 1: This claim outlines a Very Large Scale Integration (VLSI) semiconductor device, which is a complex integrated circuit. The innovation lies in creating a "graded dopant concentration" within the active areas where transistors are built. This graded doping profile creates an electrical field that actively pushes charge carriers away from the sensitive transistor regions towards an unused part of the substrate. The claim also specifies a "well region" with a similar graded doping to further assist in clearing unwanted charge carriers from the device's surface. The transistors in this device are intended to be used for digital logic.

• Claim 21: This claim is also directed at a VLSI semiconductor device with a similar structure to that described in Claim 1. Its unique aspect is the specific definition of the graded dopant profile. It states that the concentration gradient can follow several mathematical patterns, such as linear, quasi-linear, or error function distributions.

• Claim 39: This claim describes a broader semiconductor device, not limited to VLSI. It focuses on the fundamental concept of having two separate active regions for transistors where at least one has a graded dopant concentration. The purpose of this gradient is to facilitate the movement of charge carriers away from the active region to an inactive area of the substrate.

• Claim 41: This claim narrows the scope of the general semiconductor device by specifying that the graded dopant concentration is composed of "acceptor" dopants, which are used to create p-type semiconductor material.

• Claim 42: Similar to the above, this claim specifies the use of "donor" dopants for the graded concentration, which are used to create n-type semiconductor material.

• Claim 43: This claim combines the concepts of the previous two, describing a semiconductor device that utilizes both graded acceptor and graded donor dopant concentrations to help steer charge carriers away from the active transistor areas.

• Claim 44: This claim is specific to a Complementary Metal-Oxide-Semiconductor (CMOS) device. It describes a structure featuring a "single drift layer" with a graded dopant concentration situated between the device's surface and the underlying substrate. This layer is designed to create a built-in, one-way electric field that pushes charge carriers away from the surface. The claim also includes a "well region" within this drift layer that has its own graded doping and associated electric field to further enhance this effect.

Litigation History

U.S. Patent No. 11,121,222 ('222 patent), assigned to Greenthread, LLC, has been subject to extensive litigation, including numerous district court filings and inter partes review (IPR) proceedings before the Patent Trial and Appeal Board (PTAB). Greenthread, LLC has been the plaintiff in all identified district court cases, asserting the '222 patent and other related patents against a wide array of major technology and automotive companies. The patent's legal status is currently listed as "Expired - Fee Related," which may impact the resolution of any ongoing matters.

District Court Litigation

Greenthread has initiated multiple infringement lawsuits across various U.S. District Courts. A common pattern in these cases involves co-defendants from the semiconductor and electronics manufacturing sectors. Many of these district court cases have been stayed pending the outcome of the PTAB proceedings challenging the validity of the asserted patents.

• Plaintiff: Greenthread, LLC
  Defendants: Intel Corporation, Dell Inc., and Dell Technologies Inc.
  Jurisdiction: U.S. District Court for the Western District of Texas
  Case Number: 6:22-cv-00105
  Filing Date: January 27, 2022
  Status: Active, with various motions and claim construction proceedings having taken place.

• Plaintiff: Greenthread, LLC
  Defendant: NXP USA, Inc.
  Jurisdiction: U.S. District Court for the Western District of Texas
  Case Number: 6:22-cv-01293
  Status: The case is related to other actions filed by Greenthread.

• Plaintiff: Greenthread, LLC
  Defendant: General Motors Company
  Jurisdiction: U.S. District Court for the Western District of Texas
  Case Number: 1:23-cv-00369
  Status: Active.

• Plaintiff: Greenthread, LLC
  Defendant: Continental Automotive Systems, Inc.
  Jurisdiction: U.S. District Court for the District of Delaware
  Case Number: 1:23-cv-00326
  Status: The case is related to other actions filed by Greenthread.

• Plaintiff: Greenthread, LLC
  Defendant: Robert Bosch LLC
  Jurisdiction: U.S. District Court for the District of Delaware
  Case Number: 1:23-cv-00333
  Status: The case is related to other actions filed by Greenthread.

• Plaintiff: Greenthread, LLC
  Defendants: ON Semiconductor Corporation and Semiconductor Components Industries, LLC
  Jurisdiction: U.S. District Court for the District of Delaware
  Case Number: 1:23-cv-00443
  Filing Date: April 21, 2023
  Status: The case was stayed pending IPR proceedings and administratively closed on April 22, 2024.

• Plaintiff: Greenthread, LLC
  Defendant: Monolithic Power Systems, Inc.
  Jurisdiction: U.S. District Court for the District of Delaware
  Case Number: 1:23-cv-00579
  Filing Date: May 26, 2023
  Status: The case is related to ongoing IPR proceedings.

• Plaintiff: Greenthread, LLC
  Defendant: STMicroelectronics, Inc.
  Jurisdiction: U.S. District Court for the Eastern District of Texas
  Case Number: 2:23-cv-00157
  Status: This case is related to other infringement suits initiated by Greenthread.

• Plaintiff: Greenthread, LLC
  Defendant: Renesas Electronics America, Inc.
  Jurisdiction: U.S. District Court for the Eastern District of Texas
  Case Number: 2:23-cv-00179
  Status: This case involves allegations against a major semiconductor manufacturer.

• Plaintiff: Greenthread, LLC
  Defendant: OmniVision Technologies, Inc.
  Jurisdiction: U.S. District Court for the Eastern District of Texas
  Case Number: 2:23-cv-00212
  Filing Date: May 10, 2023
  Status: Active litigation with related IPR challenges.

Patent Trial and Appeal Board (PTAB) Litigation

Numerous IPR petitions have been filed against the '222 patent, challenging the validity of its claims. These proceedings are central to the overall litigation strategy, with district courts often waiting for the PTAB's decisions on patentability.

• IPR Number: IPR2023-00324
  Petitioner(s): Sony Group Corporation, Dell, Inc., et al.
  Status: Terminated - Settlement.

• IPR Number: IPR2023-00420
  Petitioner(s): Intel Corporation
  Status: Terminated - Settlement.

• IPR Number: IPR2023-00509
  Petitioner(s): Dell Technologies, Inc., and Dell, Inc.
  Status: Terminated - Settlement.

• IPR Number: IPR2023-00552
  Petitioner(s): Intel Corporation
  Status: Terminated - Settlement.

• IPR Numbers: IPR2023-01242, IPR2023-01244
  Petitioner(s): Semiconductor Components Industries, LLC (d/b/a onsemi), and ON Semiconductor Corporation. Texas Instruments Inc. was later joined as a petitioner.
  Status: A Final Written Decision was issued, but this was subsequently vacated by the Director, and the case was remanded to the Board for further proceedings as of April 2025. A request for rehearing of the Director's review was denied in May 2025.

• IPR Numbers: IPR2024-00020, IPR2024-00021
  Petitioner(s): Cirrus Logic, Inc., Omnivision Technologies, Inc., AMS Sensors USA, Inc., et al.
  Filing Date: October 27, 2023
  Status: A Final Written Decision found claim 44 unpatentable. Greenthread indicated it would file for Director Review. The broader case appears to have resulted in a settlement.

• IPR Number: IPR2024-00470
  Petitioner(s): Monolithic Power Systems Inc.
  Filing Date: February 3, 2024
  Status: Pending - Instituted.

• IPR Number: IPR2024-00552
  Petitioner(s): Monolithic Power Systems, Inc.
  Status: Pending - Instituted.

• IPR Numbers: IPR2024-00673, IPR2024-00674
  Petitioner(s): Texas Instruments Incorporated
  Filing Date: March 12, 2024
  Status: Texas Instruments filed these petitions and moved to be joined with the pending IPRs filed by onsemi (IPR2023-01242 and IPR2023-01244). The proceedings are ongoing.

The USPTO's Open Data Portal API did not return any AIA trial proceedings for US Patent 11,121,222 during the most recent ingest, as stated in the "PTAB proceedings on file" section. However, the "Litigation summary" section of the provided patent analysis explicitly lists multiple inter partes review (IPR) proceedings. This analysis will proceed using the detailed IPR information from the "Litigation summary," as it appears to be more current and comprehensive.

Proceedings overview

There have been a total of twelve identified AIA trial proceedings challenging US Patent 11,121,222. Four of these IPRs (IPR2023-00324, IPR2023-00420, IPR2023-00509, IPR2023-00552, IPR2024-00021) were terminated due to settlement. One IPR (IPR2024-00020) resulted in a Final Written Decision finding claim 44 unpatentable, though it also appears to have settled. Two IPRs (IPR2023-01242, IPR2023-01244) had Final Written Decisions that were subsequently vacated by the Director and remanded for further proceedings. Two IPRs (IPR2024-00470, IPR2024-00552) are pending after institution. The remaining two IPRs (IPR2024-00673, IPR2024-00674) are ongoing, with institution decisions pending or recently made. The defensive posture for a defendant is mixed: claim 44 has been found unpatentable in one proceeding (though settled), and the status of claims in the vacated FWDs is uncertain. Several claims remain untested or are currently subject to ongoing PTAB review.

IPR2024-00020 — Cirrus Logic, Inc., Omnivision Technologies, Inc., AMS Sensors USA, Inc., et al. v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2023-10-27
• Status: Final Written Decision issued finding claim 44 unpatentable. The broader case appears to have resulted in a settlement.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: The Final Written Decision found claim 44 unpatentable.
• Settlement / termination: The broader case appears to have resulted in a settlement, and Patent Owner indicated it would file for Director Review of the FWD.
• Appeal: Not publicly available from provided text.
• Defensive value: Claim 44, a CMOS-specific claim, was found unpatentable by the PTAB. While the case settled, this FWD provides a strong indicator of invalidity for claim 44, potentially rendering infringement theories built solely on this claim vulnerable.

IPR2023-01242 — Semiconductor Components Industries, LLC, d/b/a onsemi, and ON Semiconductor Corporation. Texas Instruments Inc. joined. v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2023-07-27
• Status: A Final Written Decision was issued, but this was subsequently vacated by the Director, and the case was remanded to the Board for further proceedings as of April 2025. A request for rehearing of the Director's review was denied in May 2025.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: An FWD was issued, but its contents regarding specific claims are not detailed in the provided text. This FWD was subsequently vacated by the Director.
• Settlement / termination: The proceeding was remanded after the Director vacated the FWD.
• Appeal: Not publicly available from provided text.
• Defensive value: The vacating of the FWD by the Director means that the prior determination of patentability/unpatentability for claims challenged in this IPR is no longer valid. The outcome of this proceeding is uncertain until the remanded proceedings conclude.

IPR2023-01244 — Semiconductor Components Industries, LLC, d/b/a onsemi, and ON Semiconductor Corporation. Texas Instruments Inc. joined. v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2023-07-27
• Status: A Final Written Decision was issued, but this was subsequently vacated by the Director, and the case was remanded to the Board for further proceedings as of April 2025. A request for rehearing of the Director's review was denied in May 2025.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: An FWD was issued, but its contents regarding specific claims are not detailed in the provided text. This FWD was subsequently vacated by the Director.
• Settlement / termination: The proceeding was remanded after the Director vacated the FWD.
• Appeal: Not publicly available from provided text.
• Defensive value: Similar to IPR2023-01242, the vacating of the FWD means the prior determination of patentability/unpatentability for claims challenged in this IPR is no longer valid. The outcome is uncertain until the remanded proceedings conclude.

IPR2024-00470 — Monolithic Power Systems Inc. v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2024-02-03
• Status: Pending - Instituted.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: The petition was instituted. Specific details on the claims challenged and grounds are not publicly available from provided text.
• Final Written Decision: Not yet issued.
• Settlement / termination: Not terminated.
• Appeal: Not applicable at this stage.
• Defensive value: This proceeding is active and could potentially lead to the invalidation of claims. Its outcome will impact the patent's strength.

IPR2024-00552 — Monolithic Power Systems, Inc. v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2024-03-18
• Status: Pending - Instituted.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: The petition was instituted. Specific details on the claims challenged and grounds are not publicly available from provided text.
• Final Written Decision: Not yet issued.
• Settlement / termination: Not terminated.
• Appeal: Not applicable at this stage.
• Defensive value: This is an active proceeding that could lead to claim invalidation. Its eventual decision will be crucial for assessing the patent's scope and validity.

IPR2023-00324 — Sony Group Corporation, Dell, Inc., et al. v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2022-12-12
• Status: Terminated - Settlement.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated due to settlement.
• Appeal: Not applicable.
• Defensive value: The settlement means no final determination of patentability was reached, so the challenged claims remain patentable as far as this IPR is concerned.

IPR2023-00420 — Intel Corporation v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2022-12-28
• Status: Terminated - Settlement.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated due to settlement.
• Appeal: Not applicable.
• Defensive value: The settlement means no final determination of patentability was reached, so the challenged claims remain patentable as far as this IPR is concerned.

IPR2023-00509 — Dell Technologies, Inc., and Dell, Inc. v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2023-01-27
• Status: Terminated - Settlement.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated due to settlement.
• Appeal: Not applicable.
• Defensive value: The settlement means no final determination of patentability was reached, so the challenged claims remain patentable as far as this IPR is concerned.

IPR2023-00552 — Intel Corporation v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2023-02-01
• Status: Terminated - Settlement.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated due to settlement.
• Appeal: Not applicable.
• Defensive value: The settlement means no final determination of patentability was reached, so the challenged claims remain patentable as far as this IPR is concerned.

IPR2024-00021 — Cirrus Logic, Inc., Omnivision Technologies, Inc., AMS Sensors USA, Inc., et al. v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2023-10-27
• Status: Terminated - Settlement.
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated due to settlement.
• Appeal: Not applicable.
• Defensive value: The settlement means no final determination of patentability was reached, so the challenged claims remain patentable as far as this IPR is concerned.

IPR2024-00673 — Texas Instruments Incorporated v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2024-03-12
• Status: Ongoing. Texas Instruments moved to be joined with pending IPRs filed by onsemi (IPR2023-01242 and IPR2023-01244).
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: Not yet issued.
• Settlement / termination: Not terminated.
• Appeal: Not applicable at this stage.
• Defensive value: This proceeding is ongoing, with potential impact on the claims challenged. Its current status means no definitive validity determination has been made.

IPR2024-00674 — Texas Instruments Incorporated v. Greenthread, LLC

• Type: Inter Partes Review
• Filed: 2024-03-12
• Status: Ongoing. Texas Instruments moved to be joined with pending IPRs filed by onsemi (IPR2023-01242 and IPR2023-01244).
• Judge panel: Not publicly available from provided text.
• Petition grounds: Not publicly available from provided text.
• Institution decision: Not publicly available from provided text.
• Final Written Decision: Not yet issued.
• Settlement / termination: Not terminated.
• Appeal: Not applicable at this stage.
• Defensive value: This proceeding is ongoing, with potential impact on the claims challenged. Its current status means no definitive validity determination has been made.

Strategic summary

Of the independent claims, claim 44 was found unpatentable in IPR2024-00020. The status of claims challenged in IPR2023-01242 and IPR2023-01244 is currently uncertain due to the Director's decision to vacate the Final Written Decisions and remand the cases. The remaining independent claims (1, 21, 39, 41, 42, 43, and the dependent claims not tied to claim 44) have either been subject to IPRs that settled before a final decision, or they are currently being challenged in active, instituted IPRs (IPR2024-00470, IPR2024-00552) or pending IPRs (IPR2024-00673, IPR2024-00674). Therefore, while claim 44 faces a strong challenge to its validity, other claims are either presumed patentable (due to settlement) or their validity is still under review.

The estoppel landscape is complex due to the numerous settlements. For petitioners who settled (Sony, Dell, Intel, Cirrus Logic, Omnivision, AMS Sensors, et al.), 35 U.S.C. § 315(e)(2) bars them (and their privies) from raising any ground that was raised or reasonably could have been raised in their respective IPRs. This means these parties would face estoppel in subsequent litigation on those grounds. For a defendant not involved in these settlements, or not in privity with the petitioners, a wider range of prior-art grounds may still be available for challenges, provided they have not been litigated to a final judgment on the merits. Given the vacated FWDs in IPR2023-01242 and IPR2023-01244, the estoppel effect from those proceedings is also currently unclear.

A clear pattern signal is the high volume of IPR filings, particularly from major technology companies like Sony, Dell, Intel, onsemi, and Texas Instruments. This indicates that the patent is being widely asserted, leading to concerted efforts to challenge its validity at the PTAB. The repeated settlements suggest a strategy by Greenthread, LLC, to monetize the patent through licensing agreements, possibly using the threat of ongoing litigation, while avoiding a definitive PTAB decision on all claims. The Director's review and remand of the onsemi IPRs also highlights the active and often unpredictable nature of PTAB proceedings for this patent family.

Recommended next steps

• If you are a defendant facing assertion of US Patent 11,121,222, note that claim 44 has been found unpatentable in IPR2024-00020. Any infringement theory built on claim 44 is significantly weakened by this finding.
• For claims challenged in IPR2023-01242 and IPR2023-01244, monitor the remanded proceedings closely. The previous FWDs were vacated, so the patentability of those claims is once again in question.
• For claims challenged in IPR2024-00470 and IPR2024-00552, these proceedings are instituted and pending. Track their progress, including oral hearings and the statutory one-year deadline for Final Written Decisions (which would be around February 2025 and March 2025, respectively, from the institution dates).
• For claims challenged in IPR2024-00673 and IPR2024-00674, these are ongoing. Keep an eye on institution decisions and any subsequent trial stages.
• Given the history of settlements, consider the potential for settlement negotiations. However, the existing FWD against claim 44, and the ongoing/remanded proceedings, provide leverage for defendants.

Inventors

• G.R. Mohan Rao: The patent text does not explicitly state an employer for G.R. Mohan Rao at the time of filing. The original assignee on the patent is GREENTHREAD LLC. The assignment record indicates G.R. Mohan Rao assigned his interest to GREENTHREAD, LLC.

Original assignee

The original assignee listed on the issued patent is GREENTHREAD LLC. Based on the provided patent analysis, there is no indication that GREENTHREAD LLC manufactures or ships products embodying the claims. Their primary line of business appears to be patent licensing and assertion, as evidenced by the extensive litigation history detailed in the "Litigation summary" section. GREENTHREAD LLC is currently operating, as it is actively involved in numerous district court and PTAB proceedings concerning this patent and its family members.

Assignment timeline

• 2015-04-27 (executed) / recorded 2020-09-25 — Reel 053886/0863
  • Conveyance: Assignment of Assignors Interest
  • Assignor: Rao, G.R. Mohan
  • Assignee: Greenthread, LLC
  • Correspondent: Robert J. Stanczyk, Esq., Stanczyk Law Firm, PLLC, PO BOX 29806, Dallas, TX 75229-0806.
  • Context: Transfer from inventor to assignee.

Timeline diagram

timeline
    title Ownership of US 11121222
    2004 : Priority date
    2015 : Inventor assigns to Greenthread LLC
    2020 : Filed by Greenthread LLC
         : Assignment recorded by USPTO
    2021 : Patent issued
    2022 : First infringement suit filed
    2025 : Anticipated expiration (fee related)

NPE / troll-pattern signals

1. Shell-entity transfer — Present. GREENTHREAD LLC is the original and current assignee. The provided information does not indicate that GREENTHREAD LLC produces any products embodying the claims. The extensive litigation history suggests its primary business is patent licensing and assertion.
2. Known asserter in the chain — Present. GREENTHREAD LLC is identified as a high-frequency plaintiff, having initiated numerous district court and PTAB proceedings against a wide array of technology and automotive companies, as detailed in the "Litigation summary" section. This aligns with the characteristics of a known patent asserter (NPE).
3. Repeat correspondent across the chain — Not present. There is only one recorded assignment for US11121222 (Reel 053886/0863). Therefore, the correspondent, Robert J. Stanczyk, Esq., does not recur within this specific assignment chain.
4. Cascading transfers — Not present. There is only one assignment from the inventor to Greenthread, LLC.
5. Pre-litigation transfer — Not present. The assignment from G.R. Mohan Rao to Greenthread, LLC was executed on April 27, 2015, and recorded on September 25, 2020 (Reel 053886/0863). The earliest identified district court litigation (Case Number: 6:22-cv-00105) was filed on January 27, 2022, which is more than six months after both the execution and recording dates of the assignment.
6. Bankruptcy fire-sale — Not present. There is no information to suggest the original assignee filed for bankruptcy.
7. Privateering — Unclear. While Greenthread, LLC functions as an asserting entity, the provided information does not contain details about any operating company transferring the patent to Greenthread specifically to assert on its behalf against competitors.
8. Defensive aggregator (anti-NPE) — Not present. The patent is owned by GREENTHREAD, LLC, which is an asserting entity, not a defensive aggregator.

Verdict

NPE — high confidence

GREENTHREAD LLC, the current and original assignee, exhibits strong signals of being an NPE. The "Litigation summary" clearly indicates a pattern of aggressive patent assertion against numerous defendants, without any public record of product manufacturing or sales. This consistent behavior, combined with the assignment from the inventor to this entity (Reel 053886/0863), supports a high-confidence determination of NPE status.

Verification: https://assignmentcenter.uspto.gov/

Analysis of Prior Art Cited in U.S. Patent 11,121,222

An analysis of the prior art cited during the examination of U.S. Patent 11,121,222, "Semiconductor devices with graded dopant regions," provides insight into the patent landscape at the time of invention and the specific documents considered by the USPTO examiner. Under 35 U.S.C. § 102, a patent claim is anticipated if every element and limitation of the claim is found, either explicitly or inherently, in a single prior art reference. The following is an evaluation of the most relevant cited references and their potential to anticipate the independent claims of the '222 patent.

Key Cited Prior Art References

The following patents and patent applications were cited by the examiner and are considered relevant to the core concepts of the '222 patent.

1. U.S. Patent No. 6,310,366 B1

• Full Citation: Rhodes, Howard E. Retrograde well structure for a CMOS imager. Micron Technology, Inc., assignee. 30 Oct. 2001.
• Filing Date: June 16, 1999.
• Brief Description: This patent describes a CMOS active pixel sensor that utilizes a retrograde well to reduce dark current generation. The retrograde well has a higher dopant concentration at the bottom than at the surface. This creates an electric field that directs minority charge carriers (which contribute to dark current) away from the charge collection region of the photodiode, thereby improving image quality.
• Potential Anticipation of Claims:
  • Claims 1, 21, 39, and 44: The '366 patent discloses a CMOS device (relevant to claims 1, 21, and 44) with a specific type of graded dopant region—a retrograde well. This well is designed to aid carrier movement away from an active region (the photodiode's charge collection node) toward the substrate, which aligns with the core concept of these claims. The '366 patent's well could be interpreted as anticipating the "graded dopant concentration to aid carrier movement" and the "well region adjacent to the... active region containing at least one graded dopant region" recited in these claims. Specifically for claim 44, the retrograde well acts as a "drift field" to move carriers.

2. U.S. Patent No. 6,696,314 B2

• Full Citation: Rhodes, Howard E. CMOS imager and method of formation. Micron Technology, Inc., assignee. 24 Feb. 2004.
• Filing Date: Aug. 30, 2001.
• Brief Description: A continuation of the '366 patent, this reference further details CMOS imager cells with retrograde wells to suppress dark current. It elaborates on forming a p-n-p structure where a p-type substrate contains an n-type retrograde well and a p-type photodiode region. The graded concentration of the n-well creates a potential barrier that repels electrons from the surface.
• Potential Anticipation of Claims:
  • Claims 1, 21, 39, 41, and 43: Similar to its parent patent, the '314 patent discloses a graded dopant region (the retrograde n-well) in a CMOS device to direct unwanted carriers. It specifies the use of both p-type (substrate, photodiode) and n-type (well) regions, making it relevant to claims specifying acceptor dopants (claim 41) and a combination of acceptor and donor dopants (claim 43). The fundamental principle of using a graded dopant profile to sweep carriers away from an active surface region is clearly taught.

3. U.S. Patent Application Publication No. 2003/0183856 A1

• Full Citation: Wieczorek, Karsten, et al. Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same. Infineon Technologies AG, assignee. 2 Oct. 2003.
• Filing Date: Mar. 28, 2002.
• Brief Description: This application describes a MOS transistor with a retrograde dopant profile directly in the channel region. The concentration of dopants is higher deeper in the substrate and lower near the surface. This is designed to improve the transistor's electrical characteristics, such as reducing short-channel effects and improving threshold voltage control, rather than sweeping minority carriers away from active regions for purposes like refresh time or dark current reduction.
• Potential Anticipation of Claims:
  • Claims 39, 41, 42, 43: While focused on the channel itself, the '856 application teaches a "graded dopant concentration" in an active region (the channel) of a semiconductor device. It could be argued that this anticipates the broader independent claims (39, 41, 42, 43) which do not strictly limit the purpose of the graded region to sweeping spurious carriers. The reference discloses grading both acceptor and donor dopants. However, it may not anticipate claims 1, 21, and 44, as its stated purpose is not to move carriers "towards an area of the substrate where there are no active regions" but rather to control transistor behavior within the channel.

4. U.S. Patent No. 6,831,292 B2

• Full Citation: Currie, Marc T., et al. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same. AmberWave Systems Corporation, assignee. 14 Dec. 2004.
• Filing Date: Sep. 21, 2001.
• Brief Description: This patent focuses on creating high-performance transistors by using strained silicon layers. A key aspect of the invention is the creation of defined impurity (dopant) gradients within these strained layers. These gradients are used to form a built-in electric field that can enhance carrier mobility and thus transistor speed.
• Potential Anticipation of Claims:
  • Claims 39, 41, 42, 43: The '292 patent explicitly teaches "defined impurity gradients" (i.e., graded dopant concentrations) within active regions of a semiconductor device to aid carrier movement (enhance mobility). This directly maps to the language of the broader independent claims. It describes grading both n-type and p-type dopants. The motivation is to improve performance by accelerating majority carriers, which is one of the applications mentioned in the '222 patent's specification. This reference presents a strong case for anticipating the more general claims. It is less likely to anticipate claims 1, 21, and 44 because its focus is on accelerating carriers within the channel to improve transistor speed, not sweeping spurious minority carriers away from active regions into an inactive substrate area.

5. U.S. Patent No. 4,481,522 A

• Full Citation: Savoye, Eugene D., et al. CCD Imagers with substrates having drift field. RCA Corporation, assignee. 6 Nov. 1984.
• Filing Date: Mar. 24, 1982.
• Brief Description: This older patent describes a Charge-Coupled Device (CCD) imager built on a substrate that has a graded dopant concentration, such as a lightly doped epitaxial layer on a heavily doped substrate. This grading creates a "drift field" that accelerates charge carriers generated deep within the substrate towards the charge collection wells at the surface. This enhances the quantum efficiency of the sensor, particularly for longer-wavelength light.
• Potential Anticipation of Claims:
  • Claims 39, 42, and 44: The '522 patent clearly discloses a semiconductor device with a graded dopant concentration that creates an electric "drift field" to "aid the movement of carriers." While the purpose is to move carriers towards the active region (the collection well) rather than away from it, the fundamental mechanism is the same as described in several of the '222 patent's claims. Claim 44, which recites a "drift field to aid the movement of carriers," is particularly relevant. The direction of carrier movement is specified in claim 44 as "from the surface layer to an area of the substrate," which is the opposite of the '522 patent's teaching. Therefore, it would not anticipate claim 44, but it could be argued to anticipate the broader claim 39, which only requires aiding carrier movement from the active region to a substrate area without specifying direction relative to the surface.

Summary of Anticipation Analysis

While several cited references disclose the use of graded dopant profiles, their specific implementation and purpose are key to determining anticipation. The Rhodes patents ('366 and '314) appear to be the most relevant prior art, particularly against the claims directed at VLSI and CMOS devices (1, 21, 44), as they teach using graded wells to move unwanted minority carriers away from active surface regions into the substrate. The Currie ('292) and Wieczorek ('856) references also disclose graded dopants in active regions but focus on enhancing transistor channel performance rather than clearing spurious carriers, making them strong anticipatory references for the broader independent claims (39, 41, 42, 43). The Savoye ('522) patent teaches the core concept of a graded drift field but for the opposite purpose of collecting carriers at the surface, which weakens its case for direct anticipation of claims specifying carrier movement away from the surface.

An analysis of US patent 11,121,222 in light of the cited prior art suggests that its claims would have been obvious to a person of ordinary skill in the art (POSA) at the time of the invention, with a priority date of September 3, 2004.

Definition of a Person of Ordinary Skill in the Art (POSA)

A person of ordinary skill in the art (POSA) for this patent would be an individual with a Bachelor's or Master's degree in Electrical Engineering or a related field like Physics. This person would have several years of practical experience in the design and fabrication of semiconductor devices, including knowledge of device physics, ion implantation, epitaxial growth, and the common challenges in VLSI, CMOS, DRAM, and power device technologies circa 2004. A POSA would be familiar with the effects of dopant profiles on carrier transport and device performance.

Obviousness Analysis of Claims

The core inventive concept of the '222 patent is the use of graded dopant concentrations to create a built-in electric drift field. This field is engineered to actively sweep unwanted charge carriers away from sensitive areas (like the device surface, channel regions, or charge storage nodes) and into the substrate, thereby improving device performance. An examination of the prior art reveals that both the problem and the proposed solution were well-established concepts.

Combination 1: Rhodes (US 2003/0042511) and RCA (US 4,481,522)

This combination renders the VLSI-specific claims (e.g., Claims 1, 14, 15, 19, and 21) obvious.

• Rhodes (US 2003/0042511 A1): Published in March 2003, Rhodes teaches a CMOS imager and methods for its formation. Crucially, it addresses the problem of unwanted minority carriers (noise) degrading image quality. Rhodes discloses using a substrate with an epitaxial layer and forming p-wells and n-wells for the CMOS transistors. This reference establishes the foundational VLSI/CMOS structure with active regions and wells, as recited in the '222 patent's claims. Rhodes explicitly discusses the problem of collecting photogenerated carriers efficiently while rejecting unwanted carriers (crosstalk and dark current).

• RCA (US 4,481,522): Issued in 1984, this patent directly teaches the solution to the problem identified in Rhodes and addressed by the '222 patent. The RCA patent describes CCD imagers where a drift field is intentionally created in the substrate. The abstract states, "CCD Imagers with substrates having drift field," and the patent details how this field sweeps signal carriers towards the potential wells for collection while pushing unwanted, thermally generated carriers deep into the substrate where they can recombine. This is precisely the mechanism claimed in the '222 patent: aiding carrier movement from the surface towards an area of the substrate.

• Motivation to Combine: A POSA, when faced with the problem of managing stray minority carriers in a CMOS device as described by Rhodes, would have been motivated to look for solutions in related fields, such as CCD imagers, which faced similar challenges. The RCA patent provides a clear and direct teaching of using a drift field in the substrate for this exact purpose. The POSA would have found it obvious to apply the drift-field concept from RCA to the CMOS structure of Rhodes. Implementing a drift field via a graded dopant profile (as opposed to a uniform one) was a known technique, as the '222 patent itself acknowledges in the context of graded-base bipolar transistors. Therefore, creating graded doping in the wells and/or substrate of the Rhodes CMOS device to generate the carrier-sweeping drift field taught by RCA would have been a predictable and obvious design choice to improve performance by reducing noise and improving charge collection.

Combination 2: Sanken (US 6,737,722) and General Device Knowledge

This combination renders the broader device claims (e.g., Claims 39, 41, 42, 43) obvious.

• Sanken (US 6,737,722 B2): Issued in May 2004, this patent discloses a lateral transistor with a "graded base region." The patent explains that this graded dopant concentration creates an accelerating electric field for minority carriers in the base, which shortens the carrier transit time and improves the high-frequency characteristics of the transistor. This directly teaches the core element of Claim 39: an active region with a graded dopant concentration to aid carrier movement.

• Motivation to Apply: The Sanken patent demonstrates the known benefits of applying a graded dopant profile to an active region of a transistor to improve performance. For a POSA, it would have been an obvious extension to apply this established technique to other semiconductor devices and active regions beyond the specific lateral transistor shown. The principle that a dopant gradient creates a field that aids carrier movement is fundamental device physics. Applying this principle to different device structures to achieve predictable improvements in carrier transport is a standard engineering approach. The dependent claims specifying the dopant type (acceptor for p-type, donor for n-type, or both) simply cover the fundamental and necessary design choices for creating any semiconductor region and do not add a non-obvious element.

Combination 3: Micron (US 6,310,366) and RCA (US 4,481,522)

This combination renders Claim 44, which is specific to a CMOS device with a drift layer and a graded well, obvious.

• Micron (US 6,310,366 B1): Issued in 2001, this patent describes a "Retrograde well structure for a CMOS imager." It directly addresses the problem of dark current and pixel crosstalk by using a non-uniform dopant profile (a retrograde well) to "provide an electric field which directs photogenerated electrons toward the photodiode and away from the channel stop regions." This teaches the use of a specially profiled well in a CMOS device to create a field that directs carriers.

• RCA (US 4,481,522): As described previously, RCA teaches creating a "drift field" in the bulk of the substrate (what Claim 44 calls a "single drift layer") to create a "unidirectional electric drift field" that moves carriers from the surface layer towards the substrate.

• Motivation to Combine: The POSA is presented with two complementary techniques for managing unwanted carriers in CMOS-type imagers. The Micron patent teaches engineering the well region with a non-uniform profile to create a localized field, while the RCA patent teaches engineering the entire substrate to create a global, unidirectional field. A POSA would have found it obvious to combine these two techniques into a single device to achieve superior carrier management. This would involve implementing the substrate-wide drift field from RCA along with the profiled well structure from Micron. The combination directly results in the device of Claim 44: a CMOS device with a drift layer (from RCA) and a graded well region (from Micron), both creating electric fields to aid the movement of carriers away from the surface.

Conclusion

The claims of US patent 11,121,222 appear to be obvious under 35 U.S.C. § 103. The core concept—using a graded dopant profile to create a drift field for sweeping away unwanted minority carriers—was a known principle. Prior art references from the relevant timeframe, such as RCA (US 4,481,522), Sanken (US 6,737,722), Rhodes (US 2003/0042511), and Micron (US 6,310,366), teach the necessary components: the problem of spurious carriers in VLSI devices, the standard CMOS structures, and the use of graded/non-uniform doping in both substrate and well regions to create electric fields for carrier management. A person of ordinary skill in the art would have been motivated to combine these known elements to achieve the predictable performance improvements described in the '222 patent.

Term Details for U.S. Patent No. 11,121,222

Patent Term Adjustments (PTA) / Extensions (PTE):
A detailed review of the prosecution history for U.S. Patent No. 11,121,222 in the USPTO's public records indicates there have been no Patent Term Adjustments (PTA) or Patent Term Extensions (PTE) granted for this patent. The patent's term is therefore the standard 20 years from its earliest effective filing date.

Continuity and Related Applications:
U.S. Patent No. 11,121,222, which issued from application Ser. No. 16/947,294, is a continuation of a long line of preceding applications. This chain of continuation applications establishes a priority date of September 3, 2004.

• Parent Applications: This patent is a continuation of U.S. patent application Ser. No. 16/717,950 (now U.S. Patent No. 10,734,481), which itself is a continuation of several earlier applications stretching back to the original application (Ser. No. 10/934,915) filed on September 3, 2004.

• Child Applications: There is at least one subsequent continuation application that claims priority to this patent family:

  • U.S. patent application Ser. No. 17/371,839 (now U.S. Patent No. 11,316,014).

Patent Family:
This patent is part of a large family of U.S. patents, all titled "Semiconductor devices with graded dopant regions" and naming G.R. Mohan Rao as the inventor. The family shares the same priority date. Other patents in this family include, but are not limited to:

• U.S. Patent No. 8,421,195
• U.S. Patent No. 9,190,502
• U.S. Patent No. 9,647,070
• U.S. Patent No. 10,510,842
• U.S. Patent No. 10,734,481
• U.S. Patent No. 11,316,014

Projected Expiration:
The term of a U.S. patent is typically 20 years from the filing date of the earliest U.S. or international (PCT) application to which priority is claimed. Based on the earliest priority date of September 3, 2004, the projected expiration date for U.S. Patent No. 11,121,222 was September 3, 2024.

However, according to the USPTO's records, the patent's current legal status is "Expired - Fee Related." This indicates that the patent expired prematurely due to a failure to pay the required maintenance fees. The anticipated expiration date based on the priority date has passed.

Defensive Disclosure and Prior Art Derivations for U.S. Patent 11,121,222

Publication Date: May 10, 2026
Subject: Derivative Embodiments of Semiconductor Devices with Graded Dopant Regions
Reference Patent: U.S. Patent 11,121,222 B2 ("the '222 patent")
Core Technology: The use of a non-uniform, or "graded," dopant concentration profile within a semiconductor substrate or well to create a static, built-in electric field. This field is engineered to accelerate the movement of undesirable charge carriers (e.g., minority carriers generated by noise or radiation) away from sensitive active device regions on the surface and toward an inactive region of the substrate, thereby improving device performance, reliability, and noise immunity.

This document discloses a series of derivative works, alternative embodiments, and novel applications of the core technology described in the '222 patent. The purpose of this disclosure is to establish prior art for subsequent inventions that may be considered obvious extensions or variations of the foundational concept.

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Axis 1: Material & Component Substitution

Derivative 1.1: Graded Doping in Wide-Bandgap Compound Semiconductors

• Enabling Description: The principles of the '222 patent are applied to Gallium Nitride (GaN) or Silicon Carbide (SiC) High-Electron-Mobility Transistors (HEMTs). A graded p-type region is formed below the 2D-electron gas (2DEG) channel using selective ion implantation of Magnesium (Mg) in GaN or Aluminum (Al) in SiC. The grading is achieved through a sequence of multi-energy implants followed by a controlled thermal activation anneal. This graded field actively extracts charge carriers trapped in the GaN buffer or SiC substrate, reducing current collapse and improving dynamic on-resistance (Ron), which are critical performance limiters in high-power switching applications. The gradient is established from a low concentration (e.g., 1x1016 cm-3) near the channel to a high concentration (e.g., 5x1017 cm-3) at the substrate interface.

• Mermaid Diagram:

  classDiagram
      direction LR
      class Substrate {
          +Material: SiC or Sapphire
      }
      class BufferLayer {
          +Material: GaN
          +Function: Isolate channel
      }
      class GradedP_Region {
          +Dopant: Magnesium (Mg)
          +Concentration: 1e16 to 5e17 cm^-3
          +Function: Create E-field to extract trapped charge
      }
      class AlGaN_Barrier {
          +Function: Induce 2DEG
      }
      class Channel_2DEG {
          +Location: AlGaN/GaN Interface
          +Function: Primary conduction path
      }
      class Gate {
          +Type: Schottky or MOS
      }
      class Source_Drain {
          +Type: Ohmic contacts
      }
  
      Substrate --|> BufferLayer : Supports
      BufferLayer --|> GradedP_Region : Contains
      GradedP_Region --|> AlGaN_Barrier : Below
      AlGaN_Barrier --|> Channel_2DEG : Creates
      Gate -- Channel_2DEG : Modulates
      Source_Drain -- Channel_2DEG : Accesses
  

Derivative 1.2: Electrically Induced Graded Fields in Ferroelectric Stacks

• Enabling Description: This embodiment replaces the fixed, implanted dopant gradient with a dynamically controllable electric field generated by a ferroelectric layer, such as Hafnium Zirconium Oxide (HZO), integrated below the device's channel region. By applying a bias voltage to a buried control gate, the polarization of the HZO layer can be partially and non-volatilely set, creating a remnant polarization gradient. This gradient induces a corresponding electric field in the underlying silicon substrate, which functions to sweep minority carriers away. The strength and profile of this "clearing field" can be programmed post-fabrication, allowing for performance tuning based on the application's noise environment.

• Mermaid Diagram:

  flowchart TD
      subgraph Device_Stack
          A[Source/Drain Contacts] --> B{Active Channel Region};
          C[Top Gate] --> B;
          B --> D[Silicon Substrate];
          D --> E[Ferroelectric Layer (HZO)];
          E --> F[Buried Control Gate];
      end
  
      subgraph Control
          G(Voltage Control Unit) -- Program/Erase Pulses --> F;
      end
  
      subgraph Physics
          F -- Bias Voltage --> E;
          E -- Creates Polarization Gradient --> D;
          D -- Induces E-Field --> B;
          B -- Sweeps Minority Carriers --> D;
      end
  
      style E fill:#f9f,stroke:#333,stroke-width:2px
  

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Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Graded-Well Structures for Quantum Processors

• Enabling Description: The invention is implemented in control circuitry for silicon-based quantum bits (qubits) operating at milli-Kelvin (mK) temperatures. Spurious charge carriers, generated by environmental radiation or control line noise, can cause qubit decoherence. A graded dopant well is formed around the qubit array using low-energy arsenic and phosphorus implantation. The gradient profile is specifically optimized using cryogenic TCAD simulations to maximize the clearing field strength while minimizing dopant freeze-out effects. The resulting structure creates a potential gradient that directs stray electrons away from the quantum dot locations, increasing qubit coherence times (T2) by an order of magnitude or more compared to uniformly doped wells.

• Mermaid Diagram:

  sequenceDiagram
      participant Env as Environment (Noise/Radiation)
      participant Substrate as Silicon Substrate
      participant GWell as Graded Well
      participant Qubit as Quantum Dot Qubit
  
      Env->>Substrate: Generates spurious e-h pair
      Substrate->>GWell: Electron drifts into well
      GWell->>GWell: E-Field accelerates electron away from surface
      Note right of GWell: Field optimized for T < 1K
      GWell->>Substrate: Electron collected at deep substrate contact
      Qubit->>Qubit: Coherence state (T2) maintained
  

Derivative 2.2: High-Pressure Graded-Channel Piezoresistive Sensors

• Enabling Description: This disclosure describes a MEMS pressure sensor where the sensing element is a silicon nanowire with a graded dopant profile along its length. The device operates at pressures exceeding 1 GPa. The graded doping (e.g., boron, from 1018 cm-3 to 1020 cm-3) serves two purposes. First, it creates a built-in electric field that improves carrier velocity and signal response time. Second, under extreme pressure, the piezoresistive coefficient of silicon becomes highly dependent on carrier concentration. The graded profile linearizes the sensor's response across a wide pressure range, compensating for non-linear stress-mobility effects that would otherwise saturate a uniformly doped device.

• Mermaid Diagram:

  graph LR
      subgraph Sensor
          A[Contact 1] <--> B(Si Nanowire);
          B <--> C[Contact 2];
      end
      subgraph Doping_Profile
          direction BT
          D1(10^18 cm^-3) --> D2(10^19 cm^-3) --> D3(10^20 cm^-3);
      end
      subgraph Physics
          P(High Pressure ~1 GPa) -- Induces Stress --> B;
          B -- Changes Resistivity --> S(Electrical Signal Out);
          G(Graded Doping) -- Linearizes Response --> B;
      end
      B -- Contains --> G;
      style B fill:#bbf,stroke:#333,stroke-width:2px
  

---

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Single Event Upset (SEU) Hardened FPGA

• Enabling Description: The invention is applied to Field-Programmable Gate Arrays (FPGAs) for use in high-radiation environments like space. A deep, retro-graded subterranean well is formed beneath the entire FPGA fabric using a high-energy (MeV) Boron implant. The doping concentration is highest at the bottom of the well and decreases towards the surface. When a high-energy particle strikes the silicon, it generates a dense cloud of electron-hole pairs. The strong vertical electric field within the graded well rapidly separates these pairs, shunting the charge deep into the substrate before it can diffuse laterally into the configuration memory cells (SRAM) or logic blocks, thus preventing a bit-flip (SEU).

• Mermaid Diagram:

  flowchart TD
      A[High-Energy Particle Strike] --> B{Charge Cloud Generation (e-h pairs)};
      subgraph FPGA_Fabric
          C[Configuration SRAM Cell]
          D[Logic Block (LUT)]
      end
      subgraph Substructure
          E[Active Device Layer]
          F[Deep Graded Well]
          G[P+ Substrate Contact]
      end
      B -- Charge Spreads --> F;
      F -- E-Field Shunts Charge Vertically --> G;
      B -.-> |Charge Path Blocked| C;
      B -.-> |Charge Path Blocked| D;
      style F fill:#cde,stroke:#333,stroke-width:4px
  

Derivative 3.2: AgTech - Soil Nutrient Ion-Selective FET (ISFET) Sensor Array

• Enabling Description: A multi-channel sensor for precision agriculture applications. An array of ISFETs is fabricated, where each gate dielectric is functionalized to be sensitive to a specific soil nutrient (e.g., nitrate, potassium, phosphate). The underlying substrate contains a graded well structure as per the '222 patent. In the electrically noisy environment of the soil, stray ionic currents can inject minority carriers into the substrate, causing drift in the ISFET threshold voltage and inaccurate readings. The graded well's built-in field actively clears these injected carriers, stabilizing the sensor baseline and dramatically improving the signal-to-noise ratio, allowing for ppb (parts-per-billion) level detection of nutrients directly in the field.

• Mermaid Diagram:

      graph BT
      subgraph In_Soil
          A(Soil Environment) -- Nutrients & Noise --> B{ISFET Sensor Array};
      end
      subgraph Chip_Cross_Section
          C[Functionalized Gate Dielectric] -- Modulates --> D[ISFET Channel];
          D -- Is Above --> E[Graded Well];
          E -- Sweeps Injected Carriers --> F[Substrate];
      end
      B -- Comprises --> C;
      B -- Comprises --> D;
      B -- Comprises --> E;
      B -- Comprises --> F;
      E -- Stabilizes --> D;
      D -- Produces --> G(Sensor Signal);
  

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Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Optimized Adaptive Clearing Field for Image Sensors

• Enabling Description: A CMOS image sensor incorporates the graded well structure of the '222 patent. The well bias is controlled by an on-chip AI accelerator. An embedded neural network analyzes the image histogram and scene content in real-time. For low-light scenes requiring long exposures, the AI increases the reverse bias on the well, strengthening the clearing field to aggressively sweep away dark current carriers and reduce noise. For bright, fast-moving scenes, the AI reduces the well bias to save power, as dark current is less significant. This creates a closed-loop system that dynamically optimizes the trade-off between image quality and power consumption on a frame-by-frame basis.

• Mermaid Diagram:

  sequenceDiagram
      participant Sensor as Image Sensor
      participant AI as On-Chip NN Accelerator
      participant VCtrl as Voltage Controller
      participant GWell as Graded Well
  
      loop Frame-by-Frame Analysis
          Sensor->>AI: Send image data/histogram
          AI->>AI: Analyze scene (e.g., low-light vs. bright)
          AI->>VCtrl: Calculate optimal bias voltage
          VCtrl->>GWell: Apply new bias
          GWell->>Sensor: Adjust clearing field strength
      end
  

Derivative 4.2: Blockchain-Verified Physically Unclonable Function (PUF)

• Enabling Description: The inherent, uncontrollable process variations in ion implantation mean that the exact dopant profile of a graded region is unique to each individual chip. This uniqueness is harnessed to create a PUF for cryptographic authentication. A challenge-response mechanism is implemented where specific voltages are applied to contacts within the graded region, and the resulting current flow (a complex function of the unique dopant profile) is measured. This response is digitized to form a unique device ID or cryptographic key. During manufacturing, this key is registered on a private blockchain, creating an immutable record that ties the physical device to its digital identity, preventing counterfeiting and ensuring supply chain integrity.

• Mermaid Diagram:

  flowchart LR
      subgraph Device
          A[Challenge Generator] -- Applies Voltages --> B(Graded Dopant Region);
          B -- Produces Unique IV Curve --> C[Response Measurement];
          C -- Digitization --> D{Device-Unique Key};
      end
      subgraph Secure_System
          D -- Stored During Mfg --> E[Blockchain Ledger];
          F[Authenticator] -- Sends Challenge --> A;
          D -- Compared With --> E;
          E -- Verifies --> F;
      end
      style B fill:#ffc,stroke:#333,stroke-width:2px
  

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Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Fail-Safe Mode via Field Reversal in Automotive SoCs

• Enabling Description: A system-on-chip (SoC) for an automotive safety-critical application (e.g., braking control) uses a graded n-well in a p-substrate. Under normal operation, the well is reverse-biased to sweep away minority carriers (electrons). The system includes a charge-pump and monitoring circuit. If an over-voltage event or radiation-induced damage is detected that could compromise the integrity of the clearing field, the monitoring circuit triggers a fail-safe state. In this state, the charge pump is reconfigured to forward-bias the n-well/p-substrate junction. This intentionally floods the active area with carriers, effectively clamping logic levels to a known, safe state (e.g., logic low) and preventing unpredictable behavior, allowing the system to enter a controlled shutdown.

• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Normal_Operation
      Normal_Operation: Well is reverse-biased.
      Normal_Operation: Clearing field is active.
      Normal_Operation --> Fail_Safe : Fault Detected (Overvoltage)
      Fail_Safe: Charge pump reverses bias.
      Fail_Safe: Well is forward-biased.
      Fail_Safe: Active area is flooded with carriers.
      Fail_Safe: Logic state is clamped.
      Fail_Safe --> [*] : System Reset
  

---

Combination Prior Art Scenarios with Open-Source Standards

1. RISC-V Processor Core Hardening: The graded dopant well technology of the '222 patent is integrated into the physical design (GDSII layout) of an open-source RISC-V processor core, such as the "Rocket" or "BOOM" core. The graded well is selectively implemented under critical components identified through fault-injection analysis, including the L1 cache SRAM, the instruction decode pipeline registers, and the floating-point unit. The open-source nature of the core allows for tight co-design, where the well geometry and gradient profile are optimized for the specific layout of these sensitive blocks to maximize protection against soft errors, with the final hardened layout being released under an open-source hardware license like CERN-OHL.

2. CXL I/O Substrate Noise Isolation: In a chiplet-based system using the open-source Compute Express Link (CXL) protocol for high-speed interconnects, the '222 patent's graded drift region is implemented in the I/O chiplet's substrate. The high-speed SerDes transceivers required for CXL are highly sensitive to substrate noise injected by the digital logic in adjacent chiplets. A deep, graded p-well is formed under the CXL PHY, creating a vertical field that collects and removes injected minority carriers before they can interfere with the sensitive analog front-end of the SerDes receivers. This improves the bit-error rate (BER) and allows the CXL interface to run at its maximum data rate, a design publicly disclosed in a whitepaper submitted to the CXL Consortium.

3. USB Power Delivery (USB-PD) Controller Robustness: The graded dopant region is applied to a high-voltage power MOSFET within a USB-PD controller IC that adheres to the open USB-PD 3.1 specification. During high-power (240W) charging operations, significant substrate carrier injection can occur, potentially triggering parasitic bipolar transistor latch-up. A graded n-drift region, as described in FIG. 4 of the '222 patent, is implemented in the DMOS transistor. This design creates a clearing field that enhances the removal of minority carriers (holes), significantly increasing the device's latch-up immunity. The design methodology and TCAD simulation results are published as an application note targeting designers using the open USB-PD standard.