Invalidity dossier
US 10394300
Controlling operating voltage of a processor
Current assignee: Daedalus Prime LLC
Added 9/23/2026, 6:49:18 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 10,394,300 B2
Title: Controlling operating voltage of a processor
Source: https://patents.google.com/patent/US10394300/en (excerpted)
Bibliographic data (as supplied):
- Patent number: US10394300B2
- Application number: US15/966,397; publication US20180314307A1
- Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
- Original assignee: Intel Corp; current assignee listed as Daedalus Prime LLC
- Filing date: 2018-04-30; publication/grant date: 2019-08-27
- Priority date listed: 2013-03-11; anticipated expiration: 2033-03-11
- Status: Active (as listed; the source states legal status is an assumption, not a conclusion)
Purpose: Embodiments relate to power management of a system, and more particularly to operating voltage control in a processor. The stated problem is that voltage increases must precede low-power-state exits for ordering reasons (an extra awake core means higher worst-case current), so a large voltage increase under way can undesirably delay a low-power state exit. "Dynamic loadline handling" is described as optimizing operational voltages by dynamically adjusting an operating voltage based on the worst-case current draw for a particular configuration.
Plain-language scope (from the excerpt): Voltage transitions within a processor may be segmented into two or more segments, with a dispatcher or other control logic controllably causing such multi-phase voltage ramps. A first segment transitions to an interim or "safe" voltage level sufficient to cover all active agents (and at least one additional agent) running at a lower frequency; any additional voltage increase enabling a pending frequency increase is handled in a second segment, which can occur after a low-power state exit of the additional agent. The worst-case voltage ramp before a low-power state exit may thus be a worst-case load line adder (e.g., 50 mV) rather than a full-scale ramp.
What the excerpt does not establish: It provides only figures/definitions and a partial description — not the full claims, detailed description, or cited prior art. It does not establish claim scope, validity, enforceability, litigation outcome, or the accuracy of listed ownership or dates.
Generated 10/1/2026, 9:42:31 PM
Cases on file (3)
Group view →Specific litigation cases in our database that name US patent 10394300. The free-form analysis below may also discuss cases beyond this list.
- Daedalus Prime LLC v. Arrow Electronics, Inc. et al.filed Aug 23, 20221:22-cv-01107U.S. District Court for the District of Delaware (Judge Richard G. Andrews)terminated Mar 1, 2023closed/terminated
Defendants: Arrow Electronics, Inc., Avnet, Inc., Digi-Key Corp., and 6 others
Other patents asserted: 10049080, 8775833, 8898494, 9575895, 10705588
- Daedalus Prime LLC v. Mazda Motor Corp. et al.filed Aug 23, 20221:22-cv-01108U.S. District Court for the District of Delaware (Judge Andrews)closed
Defendants: Mazda Motor Corp., Mazda North American Operations, Mazda Motor of America, Inc., and 6 others
Other patents asserted: 10049080, 8775833, 8898494, 9575895, 10705588
- Daedalus Prime LLC v. Avnet, Inc. et al.filed Aug 23, 2022337-TA-1332U.S. International Trade Commission (Section 337)terminated Feb 27, 2023terminated
Defendants: Avnet, Inc., Digi-Key Electronics, Mercedes-Benz Group AG, and 6 others
Other patents asserted: 10049080, 8775833, 8898494, 9575895, 10705588
Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
Current assignee: Daedalus Prime LLC
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
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This patent in court (3)
3 tracked lawsuits name US 10394300.