US 9147609

I'll search for information on US patent 9147609 across the USPTO database and CAFC dockets.

Let me search more specifically for CAFC docket activity and USPTO records related to this patent.

I found the PTAB IPR. Now let me search specifically for any CAFC (Federal Circuit) appeal docket in 2026, and verify the USPTO status.

US Patent 9147609 (US9147609B2) — Summary

Bibliographic data (high confidence; consistent across Google Patents, PubChem, Justia, and PTAB records)

Abstract (verbatim)

"Various implementations of through silicon vias with pinched off regions are disclosed. A semiconductor substrate includes a plurality of the through silicon vias disposed in the substrate and extending from a top surface of the substrate to a bottom surface of the substrate. A conductive filler is disposed within each of the plurality of through silicon vias, each of the plurality of through silicon vias having a hollow center which reduces thermal stress in the semiconductor substrate. The plurality of through silicon vias also have pinched off regions at the bottom and/or the top portions of the through silicon vias, which prevent contamination during processing of the semiconductor substrate."

Independent claims (18 claims total; claims 1 and 11 are the independent claims) — plain-language overview

Claim 1 (bottom-pinch embodiment): A semiconductor substrate containing multiple devices and multiple through-silicon vias (TSVs) that run from the substrate's top surface to its bottom surface. A conductive filler (e.g., tungsten) lines each via so that each via has a hollow center completely surrounded by the filler — giving the metal room to expand inward rather than outward into the silicon when hot, which reduces thermal stress and cracking. Each via also has a pinched-off region at its bottom — the via tapers closed at the bottom so the hollow center narrows and terminates there, sealing it against contamination during downstream processing (notably backside polishing).

Claim 11 (top-and-bottom pinch embodiment): Same basic substrate/TSV/hollow-center structure as claim 1, but each via has a pinched-off region at its top AND another at its bottom to prevent contamination. The hollow center is again tapered in the bottom pinched-off region. (Per the specification, the top pinch is ensured by a dielectric/oxide layer over the substrate top surface having openings narrower than the via width.)

Dependent claims 2–10 add limitations to claim 1 (e.g., taper-formed bottom pinch; pinch prevents contamination during bottom-surface polishing; metallic filler/tungsten; filler completely filling the bottom to pinch off the hollow center vs. incompletely filling/narrowing it; alternating "width direction"/"length direction" via layout groups; chamfered corners; top pinch). Dependent claims 12–18 add analogous limitations to claim 11 (e.g., dielectric layer with narrower openings over each via; metallic filler/tungsten; orthogonal layout groups; chamfered corners; bottom taper with incomplete fill narrowing the hollow center).

Docket / litigation findings (and uncertainties)

• CAFC 2026 dockets: I found no Federal Circuit appeal specific to patent 9147609 as of the search date. ⚠️ Be careful not to conflate the related appeal I did find: *Appeal No. 26-1886, Harbor Island Dynamic LLC v. [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), which stems from IPR2024-01402 (U.S. Patent 7,745,886)* — a different patent in the same IPR family, not 9147609.
• PTAB (IPR2024-01404): Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc. petitioned for IPR against Harbor Island Dynamic, LLC on Sep. 24, 2024, challenging all 18 claims of the '609 patent. Trial was instituted Apr. 4, 2025. A Final Written Decision (Paper 32, dated Mar. 11, 2026) reportedly found the challenged claims unpatentable, with petitioner prevailing on both the anticipation and obviousness grounds (oral hearing held Jan. 7, 2026). A secondary PTAB-highlights summary dated Apr. 17, 2026 confirms this outcome. I did not confirm whether an appeal of that FWD for the '609 patent has been filed.
• District court: Harbor Island Dynamic, LLC v. Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc., Case No. 2:24-cv-00140-JRG-RSP (E.D. Tex.) is identified as the related litigation.

Sources

• Google Patents: https://patents.google.com/patent/[US9147609](/patent/US9147609)/en
• Justia: https://patents.justia.com/patent/9147609
• PubChem (bibliography/abstract): https://pubchem.ncbi.nlm.nih.gov/patent/US-9147609-B2
• IPR2024-01404 docket (GreyB): https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2024-01404
• PTAB Final Written Decision PDF (Banner Witcoff copy, Mar. 2026): https://bannerwitcoff.com/wp-content/uploads/2026/03/IPR2024-01404.pdf
• CAFC case 26-1886 (ExParte listing — note: from IPR2024-01402, a different patent): https://ai-lab.exparte.com/case/cafc/26-1886/harbor-island-dynamic-llc-v-samsung-electronics-co-ltd

Uncertainty note: I could not pull a live USPTO Patent Center record directly; the bibliographic data above is drawn from the full patent text provided plus the multiple independent sources above, which are mutually consistent. The March 2026 IPR outcome is reported by secondary PTAB-tracking sources; I did not access the USPTO's own FWD page to verify it first-hand. If this patent is central to your analysis, the PTAB unpatentability finding (if it stands or is affirmed on appeal) may affect enforceability — but as of now the patent itself remains granted and in force, subject to the ongoing IPR and E.D. Tex. litigation.

I'll research litigation involving US Patent 9,147,609 across multiple sources.

Let me dig deeper into both the district court case and the PTAB proceeding's current status.

I have the core Samsung case and the IPR. Let me verify whether the NXP case also involves the '609 patent and check the current status of both the district court case and the IPR outcome.

Based on my searches (which I prioritized over any training data), the known litigation involving US Patent 9,147,609 ("Through Silicon Via Structure, Method of Formation, and Integration in Semiconductor Substrate," assigned to Harbor Island Dynamic LLC as of March 2023) is as follows.

1. Harbor Island Dynamic, LLC v. [[Samsung Electronics Co., Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.)

• Plaintiff: Harbor Island Dynamic, LLC (a Quest Patent Research Corp. subsidiary)
• Defendants: Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc.
• Jurisdiction: U.S. District Court for the Eastern District of Texas, Marshall Division
• Case number: 2:24-cv-00140-JRG-RSP (Judge Rodney Gilstrap; Magistrate Judge Roy S. Payne)
• Filing date: February 27, 2024
• Patents-in-suit: 7,745,886; 7,772,673; 9,147,609; and 9,245,826. The '609 patent was asserted against Samsung backside-illuminated image sensors (e.g., S5K2G1XX) and products incorporating them, including the Galaxy S22 Ultra and certain downstream customer products (per RPX/contemporaneous complaint analyses).
• Status: Stayed pending inter partes review — as of the September 25, 2025 related-matters update filed in the PTAB proceedings, the case was stayed with no substantive ruling entered before the stay. Following the PTAB's 2026 final written decisions canceling all claims of the four patents (see below), the case's future is tied to the patent owner's pending Director Review/appeal; I could not confirm from the available sources any final district court disposition (e.g., dismissal or judgment) as of today.

2. Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc. v. Harbor Island Dynamic, LLC — IPR2024-01404 (PTAB)

• Petitioners/Plaintiffs-in-review: Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc. (counsel: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP)
• Patent Owner: Harbor Island Dynamic, LLC (counsel: Fabricant LLP)
• Jurisdiction: U.S. Patent and Trademark Office, Patent Trial and Appeal Board
• Case number: IPR2024-01404 (challenging U.S. Patent 9,147,609; application no. 13/415,744)
• Filing date: Petition filed September 24, 2024
• Status: Trial instituted April 4, 2025; oral argument held February 18, 2026. According to Quest Patent Research Corp.'s SEC filings (Form POS AM covering the year ended December 31, 2025), the PTAB issued final written decisions in February and March 2026 canceling all claims of the four challenged patents (7,745,886; 7,772,673; 9,147,609; and 9,245,826). Harbor Island requested Director Review of the decision regarding U.S. Patent 9,147,609 (and 9,245,826), and appealed the decision regarding the '673 patent. That Director Review was reportedly pending as of the filing.

Related matter checked and excluded

• Harbor Island Dynamic, LLC v. NXP Semiconductors N.V. et al., 2:24-cv-00717-JRG-RSP (E.D. Tex., filed August 30, 2024) — although HID's PTAB mandatory notices list this case as a related district court matter, the PTAB's September 2025 related-matters update ties the NXP case only to IPR2024-01402 and IPR2024-01403 (the '886 and '673 patents), and the NXP amended-complaint analysis identifies only the '886 patent. I found no evidence that the '609 patent is asserted in the NXP case, so I have not counted it as '609 litigation.

Caveats

• I could not verify the exact issuance date of the final written decision in IPR2024-01404 or any post-FWD district court docket entries directly from PACER within this session; the February/March 2026 FWD timeline and the Director Review request come from Quest Patent Research Corp.'s SEC disclosure, which is consistent with the Google Patents litigation flag ("Final Written Decision") for IPR2024-01404.
• The district court case and the IPR are the only matters I identified specifically involving US Patent 9,147,609. If you need docket-level confirmation of the current status of 2:24-cv-00140 (e.g., whether it has been dismissed or judgment entered after the FWD), a PACER or E.D. Tex. docket check would be the authoritative next step.

Proceedings overview

One AIA trial proceeding is on file for US 9,147,609 — IPR2024-01404 (Samsung Electronics v. Harbor Island Dynamic) — and it has run to a Final Written Decision that canceled all 18 claims. Status breakdown: 1 proceeding — claims invalidated (all claims 1–18); 0 active; 0 settled; 0 institution-denied. This is the strongest possible defensive posture: the patent is, on the current record, fully dead — every claim has been found unpatentable, so any demand letter or infringement theory built on US 9,147,609 is unsupportable.

⚠️ Note on the source block: the "PTAB proceedings on file" block states the USPTO ODP API shows no AIA trial proceedings "as of the most recent ingest." That ingest is stale. Web-accessible USPTO-derived records (Google Patents' own PTAB litigation metadata, the PTAB docket aggregators, and the published Final Written Decision itself) confirm IPR2024-01404 was filed 2024-09-24 and reached a Final Written Decision on 2026-03-11. Per the operating rules, I treat the live web evidence as controlling. The proceeding below is real and outcome-determinative.

IPR2024-01404 — Samsung Electronics Co., Ltd. & Samsung Electronics America, Inc. v. Harbor Island Dynamic, LLC

• Type: Inter Partes Review
• Filed: 2024-09-24
• Status: Terminated by Final Written Decision — claims 1–18 canceled (verbatim from the FWD: "claims 1-18 of U.S. Patent No. 9,147,609 B2 have been shown, by a preponderance of the evidence, to be unpatentable")
• Judge panel: APJ Jung (author), joined by APJs Anderson and Peslak — Samsung Elecs. Co. v. Harbor Island Dynamic, LLC, IPR2024-01404, Paper 32 (Mar. 11, 2026)
• Petition grounds (all 18 claims challenged; claims 1 and 11 are the independent claims):
  • Ground 1 — Claims 1–6, 9–14, 17, 18: anticipated under § 102 and/or obvious under § 103 over Cooney (US 2009/0278237 A1). Cooney's "torpedo-shaped" TSV aperture, incompletely filled with a conductive layer (e.g., tungsten), was argued to create an "optional void" corresponding to the claimed hollow center, with constricted/pinched-off top and bottom regions and a tapered bottom.
  • Ground 2 — Claims 7, 15: obvious over Cooney + Dean (US 2011/0057319 A1), for the perpendicular "length direction / width direction" TSV array layout limitation.
  • Ground 3 — Claims 8, 16: obvious over Cooney + Farooq (the FWD lists US 8,327,288 B1, issued 2012-08-07; some docket lists transcribe the number as 8,237,288 — the FWD is authoritative), for the chamfered-corner limitation.
  • Additional instituted ground for claims 8 and 16 over Chen (US 2010/0032843 A1) + Cooney was also decided in the FWD.
• Institution decision: Granted in full — 2025-04-04 (Decision Granting Institution, 35 U.S.C. § 314). A Director Review request was denied on 2025-04-22. Related litigation identified in the proceeding: Harbor Island Dynamic, LLC v. Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc., Case No. 2:24-cv-00140-JRG-RSP (E.D. Tex.).
• Final Written Decision: Paper 32, issued 2026-03-11 (oral hearing held 2026-01-07; transcript entered 2026-02-18). The panel found, at claim-level granularity, that all 18 claims — independent claims 1 and 11 and every dependent claim — are unpatentable. Representative reasoning quoted from the FWD:
  • On the independent-claim core: the Board found Cooney's disclosure of the voided, tapered, pinched-off TSV structure to teach or suggest the claimed hollow-center/conductive-filler/pinched-off-region combination, and rejected Patent Owner's argument that "Cooney does not anticipate or render obvious either Claim 1 or Claim 11 due to its failure to disclose the reduction of thermal stress in the substrate."
  • On claims 7 and 15 (Cooney + Dean): "Weighing the underlying factual determinations, a preponderance of the evidence persuades us that claims 7 and 15 of the '609 patent are unpatentable over Cooney and Dean."
  • On claims 8 and 16 (Cooney + Farooq, and Chen + Cooney): same preponderance finding of unpatentability.
  • Notably, the Board found it unnecessary to resolve a claim-construction dispute over the functional "reduce thermal stress" language because Samsung prevailed on both its anticipation and obviousness theories regardless — a point the PTAB bar has flagged as a "functional language both ways" teachable moment.
  • Disposition: "ORDERED that claims 1-18 of U.S. Patent No. 9,147,609 B2 have been shown, by a preponderance of the evidence, to be unpatentable." (Petitioner's motion to exclude evidence, Paper 26, was dismissed as moot.)
• Settlement / termination: No settlement. The proceeding terminated by FWD, not by agreement.
• Appeal: No Federal Circuit appeal identified in my searches as of 2026-09-02. The 63-day window to appeal under 37 C.F.R. § 90.3 closed ~2026-05-13, so the FWD is now final on its face unless a notice of appeal was filed that has not surfaced in public searches. (If you are in the E.D. Tex. litigation, confirm directly with Samsung's counsel whether Harbor Island filed a CAFC appeal — this is the single most important fact to verify before relying on cancellation.)
• Defensive value: Maximum. All 18 claims have been canceled by a final, un-appealed (on the current record) PTAB decision. A patent owner cannot assert canceled claims, and any infringement theory built on US 9,147,609 is now baseless. The FWD is directly usable in the parallel E.D. Tex. case (2:24-cv-00140-JRG-RSP) and against any other Harbor Island assertion of this patent.

Strategic summary

Claim status — CANCELED vs. SUSTAINED vs. UNTESTED. Every claim of US 9,147,609 is now CANCELED. Claims 1–18 (independent claims 1 and 11; dependents 2–10 and 12–18) were all challenged and all found unpatentable by a preponderance of the evidence in IPR2024-01404, Paper 32 (2026-03-11). Zero claims sustained, zero claims untested. The only caveat is appellate risk: if Harbor Island appeals the FWD to the Federal Circuit, cancellation is stayed pending that appeal; as of this analysis no CAFC docket entry was found.

Estoppel landscape (§ 315(e)(2)). Samsung (and its privies) are estopped from re-litigating in the E.D. Tex. case any ground it raised or reasonably could have raised in the IPR — but that hardly matters now, because the claims are canceled outright and the FWD's findings (Cooney; Cooney + Dean; Cooney + Farooq; Chen + Cooney) are binding between these parties in the co-pending litigation. For a different defendant not in privity with Samsung, § 315(e)(2) estoppel does not attach — but no new IPR is needed: the claims are dead, and a new defendant can simply invoke the FWD. Any defendant facing a fresh Harbor Island letter on this patent should (a) confirm no CAFC appeal is pending, and (b) move to dismiss / for judgment on the pleadings citing the FWD. Even in the (unlikely) event the FWD is vacated on appeal, the Cooney-based art is powerful § 102/§ 103 material that any defendant can still raise in district court or a new IPR.

Pattern signals. This is a single-petitioner, single-proceeding story — not a Unified Patents defensive-aggregator campaign (Unified appears only as the licensee of the PTAB data displayed on Google Patents, not as a petitioner). The real pattern is conventional NPE enforcement: Harbor Island Dynamic LLC (a Texas entity that acquired the patent from Newport Fab LLC d/b/a Tower Semiconductor Newport Beach in 2023) sued Samsung in the Eastern District of Texas (2:24-cv-00140-JRG-RSP, Judge Gilstrap / Magistrate Payne), Samsung answered with IPR and invalidity contentions (served 2024-09-26), the district court denied Samsung's stay motion, and the PTAB then delivered complete cancellation in roughly 17 months from filing. A companion Samsung IPR, IPR2024-01402 (referenced in the same Director-Review request emails as IPR2024-01404), appears to target a sibling Harbor Island patent from the same enforcement campaign — confirm the patent number before relying on it, as it is not a proceeding against the '609 patent itself. The signal for a defendant: this patent has now been through adversarial testing once, and the challenger won everything.

Recommended next steps

1. Treat US 9,147,609 as canceled, but verify finality first. Download the Final Written Decision — Samsung Elecs. Co. v. Harbor Island Dynamic, LLC, IPR2024-01404, Paper 32 (P.T.A.B. Mar. 11, 2026), available at: https://bannerwitcoff.com/wp-content/uploads/2026/03/IPR2024-01404.pdf (case docket index: https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2024-01404). The operative disposition to quote: "claims 1-18 of U.S. Patent No. 9,147,609 B2 have been shown, by a preponderance of the evidence, to be unpatentable."
2. Check the CAFC docket (CourtListener / CAFC PACER) for a notice of appeal filed by Harbor Island before ~2026-05-13. If none exists, the cancellation is final; the patent owner has no enforceable claim to assert. If an appeal does exist, the FWD is stayed and the patent remains presumptively valid pending appeal — but the E.D. Tex. litigation is almost certainly stayed or mooted in the interim.
3. In the E.D. Tex. case (2:24-cv-00140-JRG-RSP): move promptly for judgment based on the FWD. Because Samsung is the IPR petitioner, it gets the full benefit of the cancellation (and, if Harbor Island tries to pursue the same claims on different theories, § 315(e)(2) estoppel as a backstop). If you are a non-Samsung defendant, the FWD is not technically binding on you via estoppel, but the PTAB's unpatentability findings on Cooney et al. give you a ready-made invalidity case.
4. No active PTAB proceeding remains, so there are no upcoming PTAB milestones (institution deadline, oral hearing, or FWD due date) to track for this patent — the statutory one-year trial clock ran out with the 2026-03-11 FWD. The only live milestone is the (unidentified, likely nonexistent) CAFC appeal window, which has already closed.

I'll research the assignment record for US 9147609, starting with the primary sources and cross-references.

The searches surfaced key facts: Harbor Island Dynamic LLC is a QPRC (Quest Patent Research) subsidiary, and the suit against Samsung was filed 2024-02-27. Now I need the recorded assignment details including correspondents. Let me dig into the specific reel/frame records.

Now I have strong RPX/10-K sourcing on QPRC. Let me pull the specific USPTO assignment records and correspondents for each reel/frame, plus inventor background.

I hit the tool-call limit before I could pull the correspondent-of-record data directly from the USPTO Assignment Center, so I'll flag that data gap explicitly rather than guess. The verified chain itself is nonetheless well documented via Google Patents legal events, RPX, and QPRC's SEC filings.

Inventors

Both inventors assigned to the foundry that employed them; this is a routine employee-assignment pattern, not a red flag.

Original assignee

Newport Fab, LLC d/b/a Jazz Semiconductor (later renamed Newport Fab, LLC d/b/a Tower Semiconductor Newport Beach). Google Patents lists "Original Assignee: Newport Fab LLC."

• Line of business: Specialty analog/mixed-signal/RF semiconductor foundry (wafer manufacturing). Jazz Semiconductor, in Newport Beach, CA, was acquired by Tower Semiconductor Ltd. (NASDAQ: TSEM) in 2008; the US entity was renamed "d/b/a Tower Semiconductor Newport Beach" effective 2021-05-12 (recorded 2022-12-08, Reel 062102/0979).
• Products embodying the claims: Plausible — as a foundry, Tower/Jazz offered TSV-enabled wafer processes (e.g., backside-illuminated image-sensor and RF-switch wafers) consistent with the '609 TSV-with-pinched-off-region claims. I cannot verify a specific commercial product mapping from the available sources.
• Current status: Operating. Tower Semiconductor Ltd. remains a going concern. The '609 patent was divested from the Tower/Newport Fab chain in a portfolio sale to Harbor Island Dynamic LLC (executed 2023-02-02, recorded 2023-03-24, Reel 063094/0412), not through bankruptcy.

Assignment timeline

All three recorded links in the chain are visible in the Google Patents legal-event feed for US9147609 (https://patents.google.com/patent/US9147609/en). Correspondent-of-record fields are not reproduced in that feed and the USPTO Assignment Center (https://assignmentcenter.uspto.gov/) was not directly retrievable in this session — correspondents below are marked unverified rather than guessed.

• 2012-03-01 (executed, "effective") / recorded 2012-03-08 — Reel 027832/0171

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Hadi Jebory; David J. Howard
  • Assignee: Newport Fab, LLC d/b/a Jazz Semiconductor
  • Correspondent: Unverified (USPTO Assignment Center not accessible this session)
  • Context: Routine inventors-to-employer assignment recorded on the filing date of the utility application.

• 2021-05-12 (effective) / recorded 2022-12-08 — Reel 062102/0979

  • Conveyance: Change of Name
  • Assignor: Newport Fab, LLC d/b/a Jazz Semiconductor
  • Assignee: Newport Fab, LLC d/b/a Tower Semiconductor Newport Beach
  • Correspondent: Unverified
  • Context: Internal reorg / name change only, reflecting Tower Semiconductor ownership; no change in beneficial ownership.

• 2023-02-02 (effective) / recorded 2023-03-24 — Reel 063094/0412

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Newport Fab, LLC d/b/a Tower Semiconductor Newport Beach, Inc.
  • Assignee: Harbor Island Dynamic LLC (Texas)
  • Correspondent: Unverified
  • Context: Transfer-to-asserter. Portfolio sale (~7–10 patents including '609, '886, '673, '826) from the operating foundry to a QPRC assertion subsidiary, funded by QPRC's litigation-finance facility (QF3). RPX reports the assignment "was recorded with the USPTO on March 24, 2023"; QPRC's SEC filings state the ~$3.3M cash portion of the "HID Portfolio" purchase from Tower Semiconductor was paid March 17, 2023.

No further recorded assignments appear after 2023-03-24; Harbor Island Dynamic LLC is the current record owner.

Timeline diagram

timeline
    title Ownership of US 9147609
    2011 : Provisional application filed
    2012 : Utility filed by Newport Fab Jazz Semi
         : Inventors assign rights to Newport Fab
    2015 : Patent granted
    2022 : Name change to Tower Semi Newport Beach
    2023 : Assigned to Harbor Island Dynamic LLC
    2024 : HID sues Samsung in East Texas
         : Samsung petitions for IPR review
    2025 : IPR instituted by PTAB

NPE / troll-pattern signals

1. Shell-entity transfer — Present. Harbor Island Dynamic LLC is a Texas LLC formed January 2023 (per RPX), weeks before the executed 2023-02-02 assignment (Reel 063094/0412). It has no products and no revenue; its sole function per QPRC's 10-K is holding patents "that [QPRC] intends to monetize" through litigation. HID is a single-purpose, QPRC-controlled assertion vehicle.

2. Known asserter in the chain — Present. HID is a subsidiary of Quest Patent Research Corporation (QPRC), a publicly traded patent-monetization company (OTC) whose revenue is derived exclusively from patent-litigation settlements. QPRC has run parallel assertion campaigns through Multimodal Media LLC, Taasera Licensing LLC, Deepwell IP LLC, Peregrin Licensing LLC, Soundstreak Texas LLC, M-Red Inc., Audio Messaging Inc., LS Cloud Storage Technologies LLC, and Tyche Licensing LLC (RPX/Mondaq, Mar. 3, 2024; QPRC Forms 10-K). RPX tracks HID's campaign at https://litigation.rpxcorp.com/litigation/txedce-[228247](/patent/228247)-harbor-island-dynamic-llc-v-samsung-electronics-co-ltd-et-al.

3. Repeat correspondent across the chain — Unclear. I could not retrieve the correspondent-of-record fields for Reels 027832/0171, 062102/0979, or 063094/0412 from the USPTO Assignment Center in this session, so I will not assert a name. Litigation counsel for HID is Fabricant LLP (per RPX), but litigation counsel is not the same datum as the recording correspondent. This is a data gap, not a negative finding.

4. Cascading transfers — Not present. Only three recorded links over 11 years (inventors→foundry 2012; name change 2021/2022; foundry→HID 2023). This is a single-step divestiture into an assertion vehicle, not a rapid cascade through chained LLCs.

5. Pre-litigation transfer — Not present under the 6-month test (but transfer-to-assert is documented). Assignment executed 2023-02-02 / recorded 2023-03-24 (Reel 063094/0412); first suit, Harbor Island Dynamic LLC v. Samsung Electronics, 2:24-cv-00140-JRG-RSP (E.D. Tex.), was filed 2024-02-27 — roughly 11–12 months later, outside the 6-month window. The monetization purpose is nevertheless express in QPRC's SEC filings and QF3 financing agreements, so the delay reflects litigation-financing logistics rather than an arms-length technology acquisition.

6. Bankruptcy fire-sale — Not present. The assignor (Newport Fab / Tower Semiconductor Newport Beach) is an operating foundry and remains so; the sale was a portfolio divestiture. QPRC itself narrowly avoided bankruptcy via its February 2021 restructuring, but that is the buyer's finances, not a bankruptcy sale of this patent.

7. Privateering — Unclear / not established. No public evidence shows Tower Semiconductor directing HID's suits against Tower's competitors (Samsung, NXP) on Tower's behalf; the available record (QPRC 10-K, RPX) reads as a cash-generating divestiture of non-core fabrication patents to a monetizer that then targeted large semiconductor consumers. I found no SEC or press evidence of a retained interest or direction by Tower.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates at Harbor Island Dynamic LLC (QPRC), an offensive monetizer. No RPX, AST, LOT, Unified Patents, or OIN acquisition is recorded.

Verdict

NPE — high confidence

Two-plus strong signals drive the call: (1) the patent moved from an operating foundry to Harbor Island Dynamic LLC, a single-purpose Texas LLC formed in January 2023 with no products, per Reel 063094/0412 recorded 2023-03-24; and (2) HID is a subsidiary of Quest Patent Research Corp., a publicly traded, litigation-funded patent monetizer whose SEC filings describe the "HID Portfolio" as patents purchased for assertion and whose subsidiary filed Harbor Island Dynamic LLC v. Samsung (2:24-cv-00140, E.D. Tex., filed 2024-02-27) plus a later NXP suit — the classic transfer-to-asserter pattern. Samsung's IPR2024-01404 challenge, instituted in April 2025 per QPRC's 10-K, confirms the patent is in active assertion. The only weak link in the evidentiary chain is the unverified correspondent-of-record data on the three assignment records, which does not change the conclusion.

Verification: USPTO Assignment Center search by patent number 9147609 at https://assignmentcenter.uspto.gov/; legal-event feed at https://patents.google.com/patent/US9147609/en; RPX campaign page at https://litigation.rpxcorp.com/litigation/txedce-228247-harbor-island-dynamic-llc-v-samsung-electronics-co-ltd-et-al; QPRC Form 10-K (filed 2026-03-30, fiscal 2025) via EDGAR/OTC Markets.

I'll research US patent 9147609 and its cited prior art references. Let me start by verifying the patent and its citation list from USPTO sources.

I have strong data on the patent and the first cited reference (Edelstein). Now let me research the remaining four U.S. patent citations and the non-patent citation listed on the face of US9147609.

Now let me research the remaining citations: Dao (US20110237073A1), Beyne/Imec (US20120139127A1), and the non-patent Beyne provisional 61/420,653.

I have reached the limit of my available search steps, so I will now synthesize the analysis from (a) the authoritative full-text record of US 9,147,609 B2 supplied in the conversation, (b) the USPTO/Google Patents/PubChem data retrieved, and (c) the PTAB IPR2024-01404 record excerpts that surfaced during searching.

Prior-Art Analysis of US 9,147,609 B2 ("the '609 Patent")

0. Target patent identification (searched literally as 9147609)

• Patent: US 9,147,609 B2 — "Through Silicon Via Structure, Method of Formation, and Integration in Semiconductor Substrate"
• Inventors: Hadi Jebory; David J. Howard
• Assignee (original): Newport Fab, LLC dba Jazz Semiconductor (now Harbor Island Dynamic LLC)
• Application: US 13/415,744, filed 2012-03-08; Provisional priority: US 61/545,003, filed 2011-10-07 (claimed)
• Granted: 2015-09-29; status Active; adjusted expiration 2032-08-28
• Legal regime: Because the earliest claimed priority date (Oct. 7, 2011) precedes the AIA § 3(n) cutover of Mar. 16, 2013, the claims are examined under pre-AIA 35 U.S.C. § 102 (first-to-invent).
• Verified sources: USPTO PDF (patentimages.storage.googleapis.com/.../US9147609.pdf), PubChem patent summary (US-9147609-B2), Google Patents, and PTAB IPR2024-01404 petition documents.

Claim structure relevant to the § 102 analysis

• Independent claim 1: semiconductor substrate with a plurality of devices; a plurality of through-silicon vias (TSVs) extending top surface → bottom surface; conductive filler in each TSV; each TSV has a hollow center entirely surrounded by the conductive filler to provide space for the filler to expand inward for reducing thermal stress; each TSV has a pinched-off region at a bottom portion to prevent contamination during processing, and the hollow center is tapered in the pinched-off region.
• Independent claim 11: same substrate/TSV/filler/hollow-center limitations, but each TSV has both a pinched-off region at a top portion and another pinched-off region at a bottom portion, the hollow center being tapered in the bottom (another) pinched-off region.
• Dependent claims 2–10 and 12–18 add: tapering of the bottom portion (2), contamination prevention during polishing (3), metallic filler (4, 13), tungsten (5, 14), filler completely filling/pinching off the bottom (6) or incompletely filling/narrowing the hollow center (10, 18), TSV groups laid out in width/length directions (7, 15), chamfered corners (8, 16), a top pinched-off region (9), and a dielectric layer on the top surface with openings narrower than the TSVs (12).

Face-of-the-patent citations (five U.S. patent documents, all marked "* Cited by examiner," plus one non-patent document)

Reference 1 — Edelstein et al. (IBM)

• Full citation: US 2005/0121768 A1, "Silicon Chip Carrier with Conductive Through-Vias and Method for Fabricating Same" — Edelstein, Daniel C.; Tsang, Cornelia K.; Sprogis, Edmund J.; et al., International Business Machines Corporation. Published June 9, 2005 from Appl. No. 10/729,254, filed Dec. 5, 2003; granted as US 7,276,787 B2 (Oct. 2, 2007).
• Prior-art status under pre-AIA § 102: § 102(a), (b), and (e) — filed and published well before Oct. 7, 2011, and more than one year before the '609 filing.
• Brief description: A silicon (or glass/ceramic) chip-carrier substrate with conductive through-vias whose fill is engineered to match the substrate's coefficient of thermal expansion (CTE) and reduce effective modulus/Poisson ratio, thereby lowering thermally induced stress on the substrate. One embodiment (Figs. 2B and 6A–6F) is a conductive via having an inner void (hollow center) at its core, entirely surrounded by conductive metal (e.g., copper), the top and bottom of the via being sealed/capped so the void is enclosed; the void lowers the effective modulus and gives the metal room to expand, reducing stress on the silicon. The '609 prosecution record confirms the Examiner specifically found Edelstein Figs. 2b/6d–f to disclose a "hollow center … entirely surrounded by said conductive filler … to provide space for said conductive filler to expand inward" and that the hollow portion "provides the benefit of reducing thermal stresses on the substrate."
• § 102 / anticipation analysis vs. issued claims:
  • Strongly relevant to: the hollow-center structural and functional limitations of independent claims 1 and 11 (hollow center entirely surrounded by conductive filler; space for inward expansion; reduction of thermal stress), as well as metallic-filler limitations of dependent claims 4, 5, 13, 14 (Cu, W, Ni disclosed).
  • Missing / cannot anticipate as issued: Edelstein's void is a sealed, generally cylindrical core void; the record does not show a pinched-off region at a bottom portion (or top + bottom pinched-off regions) formed by an incompletely filled tapered via bottom, nor a hollow center tapered in the pinched-off region, nor the stated function of preventing contamination during substrate processing/polishing. Those limitations were added to overcome the Examiner's rejection and are the stated reasons for allowance.
  • Bottom line: Edelstein is the closest face-citation for claims 1 and 11 as originally drafted, but it does not fully anticipate any of the allowed claims 1–18 because the pinched-off/tapered-hollow-center limitations are absent.

Reference 2 — Denso Corporation

• Full citation: US 2008/0258307 A1, "Integration Type Semiconductor Device and Method for Manufacturing the Same" — Denso Corporation. Published Oct. 23, 2008; priority to Japanese applications JP 2004-328124 (Nov. 11, 2004) and JP 2005-298076 (Oct. 12, 2005).
• Prior-art status: § 102(a), (b), (e).
• Brief description (with a transparency caveat): The application is in Denso's power-device/integrated-device family and, based on the portions retrieved, concerns a semiconductor device construction (including thick-film/collector electrodes and pad-electrode features with through-hole patterns) and methods aimed at absorbing bonding impact and improving reliability of an integrated power device. I was not able in this session to verify a full-text disclosure of hollow-center, pinched-off through-silicon vias in this document, and nothing retrieved maps onto the '609 independent claims' pinched-off TSV geometry.
• § 102 analysis: On the verified record, Denso '307 appears to be a general/background citation. I did not find disclosure of (i) a plurality of TSVs each having a hollow center entirely surrounded by conductive filler, (ii) bottom (or top-and-bottom) pinched-off regions, or (iii) a tapered hollow center in a pinched-off region. Accordingly, I cannot responsibly assert that it anticipates any of claims 1–18; my confidence in that conclusion is moderate only, because the full text was not independently verified in this search session.

Reference 3 — Sulfridge (Micron Technology)

• Full citation: US 7,795,134 B2, "Conductive Interconnect Structures and Formation Methods Using Supercritical Fluids" — Sulfridge, Marc; Micron Technology, Inc. Application 11/169,838 filed June 28, 2005; published as US 2006/0289968 A1 on Dec. 28, 2006; granted Sept. 14, 2010.
• Prior-art status: § 102(a), (b), (e).
• Brief description: Methods for forming conductive interconnects (e.g., through-wafer interconnects for microelectronic imagers) by forming a via (length ≈100 µm or more) in a substrate and disposing conductive material in the via while the via is exposed to a supercritical fluid (e.g., precipitating copper from a supercritical fluid), producing uniform grain structure and reliable fill of high-aspect-ratio vias. Its focus is complete, void-free fill of vias — the opposite design philosophy of the '609 patent's intentionally hollow, pinched-off TSVs.
• § 102 analysis: No disclosure found of a hollow center entirely surrounded by conductive filler, a pinched-off bottom/top region, or a tapered hollow center. It is relevant background for conductive-fill/deposition limitations (e.g., claims 4–5/13–14 at most, and only generically). It does not anticipate any of claims 1–18 as issued.

Reference 4 — Dao (Thuy B. Dao)

• Full citation: US 2011/0237073 A1, "Method for Forming a Through Silicon Via (TSV)" — Dao, Thuy B. Application filed Mar. 26, 2010; published Sept. 29, 2011.
• Prior-art status: § 102(a), (b), and (e) (published ~1 week before the '609 provisional priority date of Oct. 7, 2011).
• Brief description: A TSV manufacturing method using a Bosch-type etch to form a tapered via opening (top width ≈3.3 µm; bottom width ≈1.3 µm; depth ≈80 µm) through a hard-mask opening that overhangs the via top; multi-step wet-clean/ash/wet-etch sequences to remove etch polymers; then an adhesion layer (Ti/TiN) and conductive fill (tungsten or copper); finally backside substrate removal to expose the tapered via bottom so the TSV extends fully through the substrate. The via is intended to be completely filled and opened at both ends.
• § 102 analysis:
  • Dao discloses certain claim limitations: TSV in a semiconductor substrate with devices, tapered via bottom, conductive (metallic, including W/Cu) fill, and backside thinning/polish to expose the via (relevant to preambles and to dependent claims 2, 4–5, 13–14 in isolation, and to the tapered-bottom concept of claims 6/10/17/18).
  • Missing: any hollow center (Dao teaches void-free fill), a hollow center entirely surrounded by filler, and any pinched-off region (top or bottom) with a tapered hollow center serving to prevent contamination during processing. The '609 prosecution record confirms Dao was used by the Examiner only in combination (with admitted prior art / Beyne / Edelstein), not as a standalone anticipatory reference.
  • Bottom line: Dao does not anticipate any of claims 1–18 as issued; it is a secondary reference relevant to the tapered-TSV and backside-polish context.

Reference 5 — Beyne / IMEC

• Full citation: US 2012/0139127 A1, "Method for Forming Isolation Trenches" — IMEC (Beyne, et al.). Application filed Dec. 7, 2010; published June 7, 2012; claims priority to U.S. Provisional Application No. 61/420,653 (Beyne), filed Dec. 7, 2010 (the separately listed non-patent citation on the face of the '609 patent).
• Prior-art status: Publication date (June 7, 2012) is after the '609 effective filing date (Oct. 7, 2011), so § 102(a)/(b) do not apply by publication date; however, under pre-AIA § 102(e) the reference is prior art as of its U.S. filing date of Dec. 7, 2010 (and the 61/420,653 provisional is independently of record as prior-art evidence dated Dec. 7, 2010).
• Brief description: Although titled "Method for Forming Isolation Trenches," the reference (per the '609 prosecution history, as quoted in the IPR2024-01404 record) discloses through-silicon vias (elements 10b) having a hollow center (element 4) that reduces thermal stress in the semiconductor substrate (see Ex. 1003 pages 176–183, 194: Examiner finding re: Beyne Figs. 10B–H). The hollow center in Beyne was not, however, found to be entirely surrounded by the conductive filler (that limitation was added by amendment after the Beyne-based rejection).
• § 102 analysis:
  • Relevant to: the hollow-center-reduces-thermal-stress concept of claims 1 and 11 (pre-amendment versions).
  • Missing: a hollow center entirely surrounded by conductive filler to provide space to expand inward; pinched-off regions at the bottom (claim 1) or top and bottom (claim 11); and a hollow center tapered in the pinched-off region. These are precisely the limitations added during prosecution to distinguish Beyne, and they form the Examiner's stated reason for allowance.
  • Bottom line: Beyne does not anticipate claims 1–18 as issued. It is the most pertinent face-citation for the "hollow center for thermal stress" limitation, alongside Edelstein.

Synthesis: "Most relevant prior art" ranking (face citations only)

1. Edelstein (US 2005/0121768 A1) — strongest for the hollow-center/entirely-surrounded-by-filler/inward-expansion/reduced-thermal-stress limitations of claims 1 and 11; missing the pinched-off + tapered-hollow-center limitations that define the allowed claims.
2. Beyne/IMEC (US 2012/0139127 A1 + provisional 61/420,653) — strongest for hollow-center-reduces-thermal-stress, available only under § 102(e); missing the "entirely surrounded" and pinched-off/tapered limitations.
3. Dao (US 2011/0237073 A1) — tapered TSV bottom, W/Cu fill, backside exposure; no hollow center or pinched-off region; combination reference only.
4. Micron/Sulfridge (US 7,795,134 B2) — void-free supercritical-fluid via fill; background for fill methods; no meaningful anticipation case.
5. Denso (US 2008/0258307 A1) — general background in the power-device/integrated-device field; no verified disclosure matching the claimed TSV geometry (moderate confidence due to incomplete full-text verification this session).

Important limitation to the § 102 analysis: All five patent citations were considered by the Examiner during prosecution, and the claims were allowed over this exact set of references, with the Examiner expressly finding that the prior art failed to disclose (i) "a pinched off region at a bottom portion to prevent contamination during processing … and wherein said hollow center is tapered in said pinched off region" (claim 1) and (ii) the corresponding top-and-bottom pinched-off/tapered-hollow-center combination (claim 11). A § 102 anticipation case against the issued claims 1–18 based solely on these face citations is therefore weak. Notably, the IPR2024-01404 petition (filed by Samsung, PTAB case number IPR2024-01404) does not rely on these face citations; it challenges claims 1–18 using different references not cited on the '609 face — Cooney (US 2009/0278237 A1), Dean (US 2011/0057319 A1), Chen (US 2010/0032843 A1), and Farooq (US 8,237,288 B2) — which the petition asserts were never before the Examiner. Those references fall outside the scope of your request (the face citations), but they are the most relevant new prior art in the active litigation posture of this patent.

Key sources: USPTO patent PDF (US9147609.pdf); Google Patents US9147609B2; PubChem patent summary US-9147609-B2; PTAB IPR2024-01404 petition documents (ptacts.uspto.gov); Google Patents pages for US20050121768A1, US20080258307A1, US7795134B2, US20110237073A1, US20120139127A1.

Caveat on confidence: I verified the full bibliographic data for every citation and the substantive content for references 1, 3, 4, and 5 from primary records. For the Denso reference (2), I could not retrieve the complete specification within my search-step limit; its characterization rests on partial text and family metadata, and its § 102 assessment should be treated as provisional until the full text is checked.

I'll research the cited prior art references and analyze obviousness combinations against US 9,147,609. Let me start by gathering information on each cited reference and the IPR history.

Let me research the remaining cited references and the IPR proceedings.

I have gathered sufficient detail on the patent and the cited references to provide the § 103 obviousness analysis. Note at the outset: I was unable to retrieve the outcome of IPR2024-01404 (the PTAB proceeding identified on the patent's Google Patents page) within the search step limit, and I could not retrieve the full text of Denso's US20080258307A1. My analysis below is based on the five prior-art references listed in the patent's "Citations (5)" section plus the Beyne provisional (U.S. Appl. No. 61/420,653), which is the non-patent citation. Where I lack high-confidence detail, I say so.

§ 103 Obviousness Analysis — U.S. Patent 9,147,609 B2

I. The patent in suit and the relevant claims

US 9,147,609 ("Through silicon via structure, method of formation, and integration in semiconductor substrate"; Jebory & Howard; filed Mar. 8, 2012; priority Oct. 7, 2011) is directed to narrow through-silicon vias ("TSVs") having a hollow center surrounded by conductive filler and a pinched-off region at the bottom (and, in claim 11, at the top) that prevents contamination during backside processing (e.g., polishing) of the substrate.

Independent claim 1 requires, in substance:

1. A semiconductor substrate having a plurality of devices;
2. a plurality of TSVs extending from the top surface to the bottom surface of the substrate;
3. a conductive filler within each TSV;
4. a hollow center entirely surrounded by the conductive filler to provide space for the filler to expand inward, reducing thermal stress; and
5. a pinched-off region at a bottom portion preventing contamination during processing, the hollow center being tapered in the pinched-off region.

Independent claim 11 adds a pinched-off region at the top portion in addition to the bottom pinched-off region. Key dependent claims: metallic filler/tungsten (claims 4-5, 13-14); bottom taper pinching off the hollow center (claims 6, 17); orthogonal layout groups (claims 7, 15); chamfered corners (claims 8, 16); top pinch-off (claim 9); incomplete bottom fill narrowing the hollow center (claims 10, 18); and a top dielectric layer with openings narrower than the TSV (claim 12).

II. The cited prior art (from the patent's "Citations (5)" and the non-patent citation)

III. Level of ordinary skill and the governing framework

Under Graham v. John Deere, obviousness is judged from the standpoint of a person of ordinary skill in the art (PHOSITA) — here, roughly a process integration engineer or TSV/3D-interconnect engineer with several years of experience in deep-silicon etching (Bosch DRIE), conformal CVD/ALD metal deposition (especially tungsten), CMP/backside grinding, and knowledge of CTE-mismatch stress in silicon, as of the October 7, 2011 priority date. Under KSR Int'l Co. v. Teleflex, the analysis is flexible: predictable solutions to known problems in a field of evident improvement, and the combination of familiar elements according to known methods, are readily obvious.

IV. Obviousness of independent claim 1 — primary combination: Dao (US20110237073A1) in view of IBM (US20050121768A1), optionally further in view of IMEC (US20120139127A1) and/or Micron (US7795134B2)

A. Element-by-element mapping

• Substrate with devices + plurality of TSVs extending top-to-bottom. Dao expressly forms a transistor over the substrate (its flow block 51) adjacent to the via region and removes backside substrate material to expose the via bottom, thereby forming a TSV extending through the substrate. Beyne likewise describes a silicon wafer with FEOL active devices and TSVs opened by backside thinning. The "plurality" limitation is inherent in both (Dao's figures show arrays; Beyne's substrate is described with plural TSV structures).

• Conductive filler in each TSV. Dao fills the tapered via with tungsten (or Cu) over a Ti/TiN adhesive layer; Beyne lists W and Cu; Micron teaches conductive fill of through-wafer vias.

• Hollow center entirely surrounded by conductive filler, to reduce thermal stress by permitting inward expansion. This is the principal structural difference from Dao standing alone, which fills the via completely. But IBM US20050121768A1 discloses, as one of its enumerated stress-management embodiments, "a conductive via having an inner void with low CTE," and its background explains the exact problem the '609 patent addresses: CTE mismatch between the metal fill and silicon builds stress that leads to plastic deformation of metal and/or cracking of the carrier. IBM thus supplies both the structure (a via conductor with an internal void) and the reason to leave the via center unfilled (reduced thermal-mechanical stress). The "entirely surrounded ... expand inward" language tracks IBM's teaching that the void provides compliant space.

• Bottom pinched-off region, with the hollow center tapered in it. Dao's blind via is deliberately tapered — wider at the top (~3.3 µm) and narrower at the bottom (~1.3 µm) — precisely so that deep-via fill can be completed reliably. A PHOSITA practicing Dao's flow but applying IBM's hollow-core teaching would deposit a conformal tungsten film (CVD, as the '609 itself uses) into Dao's tapered blind via without completely filling the upper bore. Because the via narrows toward its bottom, the conformal film closes/seals at the narrow bottom taper first, forming a self-terminating bottom closure ("pinched-off region") while leaving the hollow center above it — the hollow center necessarily "tapered in the pinched-off region" because it is defined by the tapered sidewalls. The '609 specification confirms this is exactly the mechanism it relies on: the taper permits the filler to fill/pinch off the bottom (claims 2 and 6) and to seal the via against contamination before backside polishing.

B. Motivation to combine and reasonable expectation of success

1. Same field and overlapping problem. Dao (TSV fabrication in device substrates), IBM (through-via stress management in silicon carriers), Beyne (TSV stress reduction in 3D integration), and Micron (high-aspect via filling) all operate in the same art of forming conductive vias through silicon, and all are responsive to the two problems the '609 claims solve: reliable filling of deep narrow vias, and CTE-mismatch stress in silicon around metal-filled vias. IBM's background and Beyne's background each explicitly identify thermally induced mechanical stress, mobility degradation of neighboring devices, and cracking as known deficiencies of large metal-filled TSVs — the same deficiencies recited in the '609 Background.

2. Express invitation to combine in IBM. IBM's abstract lists multiple interchangeable embodiments for stress relief (annular fill regions, core-of-substrate-material, CTE-matched core, inner void, composite paste). Selecting the "inner void" embodiment and implementing it in Dao's tapered-via process is textbook obvious design choice — not inventive selection among unpredictable alternatives.

3. Known deposition physics supplies the pinch-off. The '609 specification itself concedes that a "natural loading effect exists when depositing fillers, which causes an increased deposition at the top of vias," and that conformal CVD/ALD of a metal such as tungsten onto sidewalls of a blind, bottom-tapered via will bridge and close at the narrow bottom. This is ordinary knowledge of a PHOSITA in 2011. Beyne independently demonstrates the accepted technique of deliberately "pinch[ing]-off" an opening by depositing a layer (there, a dielectric liner closing a narrow trench to trap an airgap for stress relief). A PHOSITA would therefore have a reasonable expectation that depositing W into Dao's tapered blind via would seal the bottom taper (pinch-off) while leaving a stress-relieving hollow center per IBM.

4. Contamination prevention during polishing is a recognized, predictable benefit. The '609's stated function of the bottom pinch-off — preventing slurry/debris contamination when the backside is ground to expose the filler (claim 3) — is an inherent and foreseeable property of a metal-sealed via bottom in Dao's own backside-thinning step (Dao block 70 removes substrate to expose the fill). Dao's entire disclosure is about preventing contamination of a TSV (there, polymer residue) to achieve a reliable via; extending that contamination-avoidance rationale to sealing the via bottom during backside grinding is an obvious application of the same goal. Beyne likewise discloses mechanical backside thinning to open TSVs, and IBM warns of contamination risks in open vias.

Conclusion as to claim 1: Dao '073 + IBM '768 (with Beyne '127 and/or Micron '134 as corroborating references) renders claim 1 obvious. The combination uses Dao's tapered, blind, W-filled TSV flow; IBM's express hollow-core stress-relief teaching supplies the motivation not to fill the center; the geometry and conformal-deposition physics supply the bottom pinch-off and tapered hollow center; and both Dao and Beyne supply the backside-thinning context in which the seal prevents contamination.

V. Obviousness of dependent claims

• Claims 2, 6, 17 (bottom taper forming/sealing the pinch-off; W fill): Dao's tapered blind via (3.3 µm → 1.3 µm) and tungsten fill are directly disclosed; the pinch-off at the taper is the predictable result discussed above. Claims 4, 5, 13, 14 (metallic filler, tungsten) read on Dao's W fill and Beyne's W disclosure.
• Claims 3 and 10/18 (preventing contamination during polishing; incomplete bottom fill narrowing the hollow center): inherent consequences of the Dao + IBM combination and of Dao's backside-removal step.
• Claim 12 (top dielectric layer with opening smaller than the TSV width): Dao's structure is nearly a literal anticipation of this feature — its hard-mask opening (~2.5 µm) is expressly described as "hav[ing] a smaller diameter than a top of [the] tapered via opening and thus overhang[ing]" the via. Applying that same mask geometry to generate a top pinch-off (claim 9) during a top-closing deposition is obvious.
• Claim 11 (top and bottom pinch-off regions): Dao supplies both geometric features needed — the overhanging narrow top opening and the tapered bottom — and the loading effect (acknowledged in the '609 itself) supplies the top closure. IBM supplies the hollow-center rationale. Obvious.

VI. Claims less likely to fall on this record

• Claims 7/15 (first group laid out in a width direction, second group in a length direction, i.e., orthogonal orientation) and claims 8/16 (chamfered corners): these array-layout and corner-shape limitations (aimed at interrupting cleavage planes and completing the deep etch) are not disclosed in any of the five cited references or the Beyne provisional as retrieved. A challenger would need additional prior art (e.g., layout-design or etch-mask references) to reach these claims. They are the most likely survivor claims on the cited record.
• I likewise have no basis to opine on Denso US20080258307A1's contribution because I could not retrieve its full text; based on its title it appears directed to pad/electrode structures in an integrated device, which the examiner may have cited for the general proposition of integration-type device structures rather than for the TSV hollow-center/pinch-off features.

VII. Secondary considerations and caveats

• No objective indicia of non-obviousness (long-felt need solved, industry praise, copying, unexpected results) are apparent on this record. To the contrary, the '609's own description of the "loading effect" and conventional CVD/ALD deposition tends to confirm that the fabrication is routine.
• The asserted claims recite structural results (hollow center, pinch-off, taper) that are inherent in the standard practice of conformally depositing W into a tapered blind via and backside-grinding — a strong signal of obviousness under the inherency and "obvious to try" doctrines.
• Caveat: The patent page identifies IPR2024-01404 (petitioner identified in the legal-events record as [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) and Samsung Electronics America, Inc.; the Unified Patents metadata describes a final written decision). Because I could not retrieve the PTAB's decision, this analysis should be treated as an independent merits assessment, not a prediction of that proceeding's outcome. If the PTAB issued a Final Written Decision, its claim constructions and findings would supersede portions of this analysis.

VIII. Bottom line

The strongest § 103 case on the cited record is Dao (US20110237073A1) as the primary reference, combined with IBM (US20050121768A1) — with IMEC/Beyne (US20120139127A1 and provisional 61/420,653) and Micron (US7795134B2) as supporting references — rendering claims 1-6, 9-14, 17, and 18 obvious. Claim 12 is particularly vulnerable given Dao's overhanging hard mask. Claims 7, 8, 15, and 16 (orthogonal layout groups and chamfered corners) are not addressed by the cited references and would require additional prior art to be shown obvious.