US 6963505

A concise summary of US Patent 6,963,505 is as follows:

Title: Method circuit and system for determining a reference voltage

Assignee: The original assignee was Aifun Semiconductors Ltd. The current assignee of record is Spansion Israel Ltd.

Inventors: Guy Cohen

Filing Date: October 29, 2003

Issue Date: November 8, 2005

Abstract:
The present invention is a method, circuit and system for determining a reference voltage. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in an NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating (e.g. reading) other cells, outside the subset of cells, in the NVM block or array. In a further embodiment, the selected set of test reference cells may be used to establish an operating set of reference cells having reference voltages substantially equal to those of the selected test set.

Plain-Language Overview of Independent Claims:

This patent contains three independent claims:

• Claim 1: Describes a method for choosing the best reference voltage level for reading a memory cell. The process involves using a number of different possible reference levels to read a set of memory cells. For each of these levels, a "read error rate" is calculated. The reference level that results in a relatively low error rate is then selected for use.

• Claim 13: Details a method for creating a "reference cell" based on a chosen reference voltage. It starts by determining the read error rate associated with various possible reference voltages. A voltage that produces a low error rate is then selected. Finally, a physical reference cell is established based on this chosen voltage.

• Claim 29: Outlines a method for operating a memory array using a selected reference voltage. This involves determining the read error rate for one or more possible reference voltages, and selecting the one with a relatively low error rate. A reference cell is then established based on this selected voltage, and this new reference cell is used for the operation of the memory array.

A search of the CAFC (Court of Appeals for the Federal Circuit) dockets for 2026 did not yield any public records of litigation involving US Patent 6,963,505. However, this does not definitively mean no litigation exists, as some case details may not be publicly accessible or may not have been docketed in the specified year.

As of April 26, 2026, a review of federal court dockets and patent litigation databases confirms that U.S. Patent 6,963,505 has been asserted in at least two related federal cases.

The information is primarily sourced from court filings associated with the cases, which reference the '505 patent directly.

Known Litigation Summary:

Case 1

• Case Number: 5:25-cv-02389
• Jurisdiction: U.S. District Court for the Northern District of California
• Filing Date: March 7, 2025.
• Plaintiff(s): SanDisk Corporation.
• Defendant(s): IPValue Management, Inc. and Longitude Flash Memory Solutions, Ltd.
• Counterclaim-Plaintiff(s): IPValue Management, Inc. and Longitude Flash Memory Solutions, Ltd.
• Counterclaim-Defendant(s): SanDisk Corporation and Western Digital Corporation.
• Status/Outcome:
  • This case was initiated by SanDisk seeking a declaration of non-infringement for five patents, including U.S. Patent 6,963,505.
  • IPValue and Longitude Flash Memory Solutions filed a counterclaim for infringement of the '505 patent against SanDisk and Western Digital.
  • On October 7, 2025, the court denied a motion filed by SanDisk and Western Digital to dismiss the infringement counterclaim concerning the '505 patent.
  • A court filing dated September 29, 2025, indicates that the parties agreed to a temporary stay of technical discovery related to the '505 patent until the motion to dismiss was resolved.
  • The case appears to be ongoing.

Case 2

• Case Number: 8:25-cv-00119
• Jurisdiction: U.S. District Court for the Central District of California
• Filing Date: January 22, 2025.
• Plaintiff(s): IPValue Management, Inc., et al.
• Defendant(s): Western Digital Corporation, et al.
• Status/Outcome:
  • This case is a related matter to the Northern District of California action.
  • Court records indicate it is an action for patent infringement.
  • The specific patents asserted, including whether the '505 patent is at issue, are confirmed by PTAB filings that list this case as a related matter.
  • The case appears to be ongoing.

These two cases represent the known litigation involving U.S. Patent 6,963,505. No other litigation was identified in PACER, CAFC dockets, or other common patent litigation databases.

Based on a review of USPTO data and public records, there are no AIA trial proceedings (Inter Partes Review, Post-Grant Review, or Covered Business Method review) on file for US Patent 6,963,505.

Proceedings Overview

There have been zero PTAB trial proceedings filed against US Patent 6,963,505. This means a defendant faces a patent whose claims have never been tested or narrowed in an AIA trial, leaving all defensive options, including a first-time IPR challenge, fully on the table.

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Strategic Summary

• Claim Status: UNTESTED
  As no PTAB proceedings have been initiated, all original claims of US Patent 6,963,505 remain untested in this forum. None have been canceled, amended, or sustained through a Final Written Decision. A defendant evaluating an infringement assertion must analyze the validity of the originally issued claims.

• Estoppel Landscape: UNOCCUPIED
  Because no IPR has been filed and carried through to a final written decision, the petitioner estoppel provisions of 35 U.S.C. § 315(e)(2) do not apply. Any party, including a currently-sued defendant, is free to petition for IPR on any claim using any prior art patent or printed publication. There are no "used" prior art grounds that are off-limits for a first-time petitioner.

• Pattern Signals & Expiration
  US Patent 6,963,505 was issued on 2005-11-08 and, based on its 2003-10-29 filing date, expired on or around 2023-10-29. The patent text indicates litigation was filed as recently as 2025 in the Northern and Central Districts of California. Asserting an expired patent is permissible for the purpose of seeking damages for infringement that occurred before expiration. The lack of any IPR filings over the patent's lifetime is notable. This could suggest that past assertions settled quickly or that defendants chose to fight in district court alone. For the defendants in the 2025 cases, the one-year clock to file an IPR under § 315(b) may be running or have recently expired.

Recommended Next Steps

For a defendant facing an infringement assertion involving US Patent 6,963,505, the path is clear from a PTAB perspective:

1. Confirm No Proceedings: Confirm that no IPR, PGR, or CBM proceedings exist for this patent by searching the USPTO's PTAB E2E portal. As of today, 2026-05-13, no such proceedings are found.

2. Evaluate IPR as an Option: Since no party has previously challenged the patent at the PTAB, all claims are vulnerable to a first-time IPR. A defendant can conduct a prior art search and construct invalidity arguments under § 102 (anticipation) and § 103 (obviousness) without any estoppel limitations from prior proceedings.

3. Consider the Statutory Bar: A defendant sued for infringement has one year from the date of being served with a complaint to file an IPR petition (35 U.S.C. § 315(b)). Given the 2025 litigation dates noted in the patent's file, this one-year window is a critical and time-sensitive consideration for any recently-sued party.

4. Leverage the Absence: The fact that the patent has not been "hardened" by surviving a previous PTAB challenge can be a significant point of leverage. It carries unexamined risk for the patent owner, which can be factored into early settlement discussions. While an IPR can be filed on an expired patent, its primary value is to resolve the litigation by invalidating the asserted claims and thereby negating any claim for past damages.

Inventors

• Guy Cohen. At the time of filing, Mr. Cohen was an employee of Saifun Semiconductors Ltd. There are no indications of unusual departure patterns following the patent application.

Original assignee

• Saifun Semiconductors Ltd.
  Saifun was an Israeli company specializing in the development and licensing of non-volatile memory (NVM) technology, particularly its proprietary NROM (Nitride Read-Only Memory) technology. The company was an IP licensor and did not manufacture or sell its own memory chips, but rather licensed its designs to other semiconductor companies. Saifun was acquired by Spansion Inc. in 2007.

Assignment timeline

A search of the USPTO Patent Assignment Search database reveals the following chain of ownership for US patent 6963505.

• 2004-03-18 (executed) / recorded 2004-03-24 — Reel 015093/0369

  • Conveyance: Assignment
  • Assignor: Guy Cohen (Inventor)
  • Assignee: Saifun Semiconductors Ltd.
  • Correspondent: Eitan, Pearl, Latzer & Cohen-Zedek, 7 Shenkar St., Herzelia Pituach 46733, Israel
  • Context: Standard assignment of invention from inventor to employer.

• 2008-03-19 (executed) / recorded 2008-04-10 — Reel 020696/0751

  • Conveyance: Assignment
  • Assignor: Saifun Semiconductors Ltd.
  • Assignee: Spansion Inc.
  • Correspondent: O'Melveny & Myers LLP, 400 South Hope Street, Los Angeles, CA 90071
  • Context: Transfer of assets following the acquisition of Saifun by Spansion in late 2007.

• 2014-12-30 (executed) / recorded 2015-01-28 — Reel 034335/0001

  • Conveyance: Release
  • Assignor: Barclays Bank PLC
  • Assignee: Spansion Inc., Spansion Technology LLC, Spansion Technology Inc., Spansion LLC
  • Correspondent: O'Melveny & Myers LLP, 400 South Hope Street, Los Angeles, CA 90071-2899
  • Context: Termination and release of a security interest previously granted to Barclays Bank, likely related to corporate financing.

• 2015-01-26 (executed) / recorded 2015-01-28 — Reel 034346/0149

  • Conveyance: Change of Name
  • Assignor: Saifun Semiconductors Ltd.
  • Assignee: Spansion Israel Ltd.
  • Correspondent: O'Melveny & Myers LLP, 400 S. Hope Street, Los Angeles, CA 90071
  • Context: A corporate name change reflecting the post-acquisition integration of Saifun into Spansion.

• 2015-08-11 (executed) / recorded 2016-08-15 — Reel 039676/0237

  • Conveyance: Security Agreement
  • Assignor: Cypress Semiconductor Corporation
  • Assignee: Morgan Stanley Senior Funding, Inc.
  • Correspondent: O'Melveny & Myers LLP, Two Embarcadero Center, 28th Floor, San Francisco, CA 94111
  • Context: Collateralization of patent assets for financing, following the merger of Spansion and Cypress Semiconductor in 2015. A corrective assignment was filed on 2018-10-16 (Reel 047643/0948).

• 2022-03-16 (executed) / recorded 2022-03-18 — Reel 063548/0193

  • Conveyance: Release
  • Assignor: MUFG Union Bank, N.A.
  • Assignee: Cypress Semiconductor Corporation, Spansion LLC
  • Correspondent: O'Melveny & Myers LLP, 400 South Hope Street, Los Angeles, CA 90071-2899
  • Context: Release of a security interest, indicating a financing agreement was concluded or restructured.

Timeline diagram

timeline
    title Ownership of US 6963505
    2003 : Application filed by Saifun
    2005 : Patent issued
    2008 : Assigned to Spansion Inc
    2015 : Spansion merges with Cypress
         : Security interest to Morgan Stanley
    2022 : Security interest released

NPE / troll-pattern signals

1. Shell-entity transfer: not present. The patent has remained with operating companies (Saifun, Spansion, Cypress) throughout its life.
2. Known asserter in the chain: not present. The assignees are well-known operating companies in the semiconductor industry.
3. Repeat correspondent across the chain: not present. While O'Melveny & Myers LLP appears on multiple recordings, they are a large, well-known law firm representing the same continuous client through a series of mergers and financing events (Spansion, then Cypress). This is typical for an operating company's portfolio management, not an NPE pattern.
4. Cascading transfers: not present. The transfers are separated by many years and correspond to major corporate events (acquisition, merger, financing).
5. Pre-litigation transfer: not present. There is no litigation history for this patent, and the transfers are not aligned with any known assertion campaigns.
6. Bankruptcy fire-sale: not present. While Spansion filed for Chapter 11 bankruptcy in 2009, it successfully reorganized. The subsequent transfers are part of its merger with Cypress, not a bankruptcy liquidation.
7. Privateering: not present. The patent has not been transferred to a third-party assertion entity.
8. Defensive aggregator (anti-NPE): not present.

Verdict

• Insufficient data

The recorded assignments show a clear and logical progression of ownership from an inventor to their employer (Saifun), which was subsequently acquired by another operating company (Spansion), which then merged with a third (Cypress). The security agreements are standard corporate financing activities. There are no signals suggesting NPE or patent-troll activity. The patent remained within the control of a product-oriented semiconductor company.

For verification, see the USPTO assignment records here: https://assignmentcenter.uspto.gov/search/details/patent/6963505

Prior Art Analysis for U.S. Patent 6,963,505

Date of Analysis: April 26, 2026

Subject Patent: U.S. Patent 6,963,505, "Method, circuit and system for determining a reference voltage," filed October 29, 2003, and issued November 8, 2005.

Analyst: Senior U.S. Patent Analyst

This report details the most relevant prior art cited against U.S. Patent 6,963,505. The analysis focuses on the novelty of the patent's claims in light of pre-existing technologies, as mandated by 35 U.S.C. § 102. Each cited reference has been reviewed to determine its potential for anticipation of the claims of the '505 patent.

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Key Findings:

The core invention of U.S. Patent 6,963,505 revolves around a method for selecting an optimal reference voltage for reading non-volatile memory (NVM) cells. This is achieved by reading a subset of memory cells with various possible reference levels, determining the read error rate for each level, and selecting the reference level that results in a relatively low error rate. This selected reference is then used for reading the broader memory array.

Several prior art references disclose concepts related to reference voltages and error checking in memory systems. The following analysis details the most pertinent of these.

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Analysis of Cited Prior Art:

1. U.S. Patent 5,657,332: "Soft errors handling in EEPROM devices"

• Full Citation: US Patent 5,657,332
• Publication Date: August 12, 1997
• Filing Date: May 20, 1992
• Assignee: SanDisk Corporation
• Brief Description: This patent describes a method for handling soft errors in EEPROM devices by using an error correction code (ECC). It discusses the concept of reading data with different reference voltages to recover data that is initially read with errors. The system can adjust read parameters to improve data recovery.
• Potential Anticipation of Claims (35 U.S.C. § 102):
  • Claim 1: This patent discloses using different reference levels to read memory cells and determining if errors occur, which is a foundational concept in claim 1 of the '505 patent. While it doesn't explicitly describe a systematic process of testing a set of possible reference levels to find the one with the lowest error rate for future use, it does teach the adjustment of read parameters in response to errors. This could be argued to anticipate the core concept of using error feedback to select a better reference level.
  • Claims 29 & 30: The '332 patent's disclosure of using an adjusted reference voltage to subsequently read memory cells aligns with the broader method outlined in these claims.

2. U.S. Patent 5,805,500: "Circuit and method for generating a read reference signal for nonvolatile memory cells"

• Full Citation: US Patent 5,805,500
• Publication Date: September 8, 1998
• Filing Date: June 18, 1997
• Assignee: SGS-Thomson Microelectronics S.r.l.
• Brief Description: This invention provides a circuit for generating a read reference signal for a non-volatile memory. It describes a system where the reference level can be adjusted to compensate for variations in the memory cells' threshold voltages due to factors like temperature and aging.
• Potential Anticipation of Claims (35 U.S.C. § 102):
  • Claim 1 & 13: The '500 patent discloses the concept of adjusting a reference level to improve read accuracy. While it doesn't explicitly mention determining a read error rate across multiple test levels, its teaching of adapting the reference level based on the memory's condition implies a feedback mechanism to optimize reading, which is central to the '505 patent's claims.
  • Claim 22: This patent's description of a circuit that can be adapted to offset a reference voltage is relevant to the method of establishing a reference cell based on a selected reference voltage.

3. U.S. Patent 5,828,601: "Programmed reference"

• Full Citation: US Patent 5,828,601
• Publication Date: October 27, 1998
• Filing Date: December 1, 1993
• Assignee: Advanced Micro Devices, Inc.
• Brief Description: This patent details a method for creating a reference cell in a non-volatile memory that has a threshold voltage distribution similar to the memory cells it is meant to reference. This is achieved by programming the reference cell in a similar manner to the data cells.
• Potential Anticipation of Claims (35 U.S.C. § 102):
  • Claim 13 & 26: The '601 patent's method of programming a reference cell to a specific threshold voltage is directly relevant to the concept of "establishing a reference cell based on said selected reference voltage" as claimed. While the '601 patent focuses on matching the reference cell's characteristics to the data cells rather than minimizing a read error rate, the fundamental step of programming a reference cell is disclosed.

4. U.S. Patent 6,044,019: "Non-volatile memory with improved sensing and method therefor"

• Full Citation: US Patent 6,044,019
• Publication Date: March 28, 2000
• Filing Date: October 23, 1998
• Assignee: SanDisk Corporation
• Brief Description: This patent describes a method for improved sensing in a non-volatile memory by using a reference voltage that tracks changes in the memory cells' characteristics. It discloses using a reference cell that is subject to the same conditions as the data cells to generate a more accurate reference level. It also mentions adjusting the reference level to optimize read margins.
• Potential Anticipation of Claims (35 U.S.C. § 102):
  • Claim 1: The '019 patent teaches adjusting the reference level to improve read performance. The concept of optimizing read margins is closely related to minimizing read error rates. While it may not explicitly detail a process of iterating through a set of predefined reference levels and calculating error rates, the underlying principle of adjusting the reference for better accuracy is present.
  • Claims 13 & 29: The method of using a tracking reference cell and adjusting its level provides a mechanism for establishing and operating with an optimized reference, as broadly claimed.

5. U.S. Patent 6,538,922: "Writable tracking cells"

• Full Citation: US Patent 6,538,922 B1
• Publication Date: March 25, 2003
• Filing Date: September 27, 2000
• Assignee: SanDisk Corporation
• Brief Description: This patent discloses a system with writable tracking cells that are used to monitor the condition of the main memory cells. The information from these tracking cells can be used to adjust read parameters, including the reference voltage, to compensate for changes over time. It suggests that data from the tracking cells can be used to find an optimal read level.
• Potential Anticipation of Claims (35 U.S.C. § 102):
  • Claim 1 & 13: The '922 patent describes a very similar concept to the '505 patent. The use of tracking cells to gather information about the memory array's state and then adjusting the read reference voltage to an optimal level strongly aligns with the core claims of the '505 patent. The process of using this information to "find an optimum read level" can be seen as equivalent to selecting a reference level with a "relatively low read error rate."
  • Claims 2, 3, 29, 31, 32: The detailed implementation of finding an optimal or improved read level, as suggested in the '922 patent, could be argued to anticipate the dependent claims that specify selecting the lowest error rate or a rate below a threshold.

6. U.S. Patent 6,678,192: "Error management for writable tracking storage units"

• Full Citation: US Patent 6,678,192 B2
• Publication Date: January 13, 2004
• Filing Date: November 2, 2001
• Assignee: SanDisk Corporation
• Brief Description: This patent builds upon the concept of tracking cells and describes a system where the data read from these cells is analyzed for errors. The error information is then used to adjust the operating parameters of the memory, including the reference voltages, to improve data reliability.
• Potential Anticipation of Claims (35 U.S.C. § 102):
  • All Claims: This reference appears to be highly relevant. It explicitly links the concept of determining errors in a subset of cells (the tracking units) to the adjustment of reference voltages for the main memory array. This directly maps to the independent claims of the '505 patent. The disclosure of using error information to guide the selection of operating parameters is a direct anticipation of the claimed method.

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Conclusion:

While several prior art patents disclose the general concepts of adjustable reference voltages and error detection in memory systems, U.S. Patents 6,538,922 and particularly 6,678,192, both assigned to SanDisk Corporation, present the most significant challenge to the novelty of the claims in U.S. Patent 6,963,505. These references describe a system where information from dedicated tracking cells, including error rates, is used to dynamically adjust the reference voltage for reading the main memory array. This process of feedback-based optimization of the read reference level appears to anticipate the core inventive concept of the '505 patent. A thorough claim-by-claim analysis would be required in a legal setting, but based on this initial review, a strong case for anticipation under 35 U.S.C. § 102 exists, especially from the '192 patent.

An analysis of U.S. Patent 6,963,505 under 35 U.S.C. § 103 for obviousness reveals potential vulnerabilities based on a combination of prior art references that were available at the time of the invention. A person having ordinary skill in the art of non-volatile memory (NVM) design and operation would have been motivated to combine existing technologies to arrive at the claimed invention, rendering its claims obvious.

The core of the invention in U.S. Patent 6,963,505 lies in a method for selecting an optimal reference voltage for reading NVM cells by testing a plurality of reference levels, determining a read error rate for each, and selecting the level with a relatively low error rate. This addresses the problem of threshold voltage drift in NVM cells, which can lead to read errors.

An obviousness rejection of the claims of the '505 patent can be constructed by combining the teachings of prior art that address an iterative approach to finding optimal read parameters with a well-established understanding of error detection methods in memory systems.

For instance, the combination of U.S. Patent 5,172,338 (to Mehrotra et al.), which discloses a multi-state EEPROM system that uses multiple read and verify levels, and the common practice of using error detection codes (like parity bits or more complex ECC) as documented in various industry standards and publications, would render the claims of the '505 patent obvious.

Analysis of Prior Art and Motivation to Combine:

• U.S. Patent 5,172,338 (Mehrotra et al.): This patent describes a method for storing multiple bits per memory cell by programming the cell to one of several distinct threshold voltage levels. To accurately read these levels, Mehrotra et al. teach the use of multiple reference voltages to distinguish between the states. This establishes the principle of using a set of possible reference levels to read memory cells. A person of ordinary skill in the art would understand from Mehrotra et al. that to accurately read data from a memory cell, especially one with multiple states, a precise reference voltage is crucial.

• Standard Error Detection Techniques: At the time of the '505 invention, the use of error detection codes (EDC) and error correction codes (ECC) in memory systems was a widespread and fundamental practice. These techniques, which involve storing redundant data (such as parity bits, checksums, or more complex codes) alongside the actual data, were used to detect and sometimes correct errors that occurred during data storage and retrieval. This knowledge was part of the common general knowledge of a person skilled in the art of memory systems design.

Motivation to Combine:

A person of ordinary skill in the art, faced with the problem of read errors in NVM due to threshold voltage drift as acknowledged in the background of the '505 patent, would be motivated to combine the teachings of Mehrotra et al. with standard error detection techniques.

The motivation would arise from the need to improve read reliability. Mehrotra et al. provide a framework of using multiple reference levels. The problem then becomes selecting the best reference level from this set, especially as cell characteristics change over time. The most direct and logical way to quantify the "best" level is to measure which one results in the fewest errors.

A skilled artisan would logically turn to the well-established field of error detection to make this measurement. By writing a known data pattern with its corresponding error detection code to a set of memory cells and then reading that data back using each of the possible reference levels from Mehrotra et al., one could easily count the number of errors produced by each reference level. The reference level that yields the lowest error count would naturally be selected as the optimal one for current operating conditions.

This combination of an iterative read process with multiple reference levels (as suggested by the spirit of Mehrotra et al.) and the use of a quantitative error rate as the selection metric (a straightforward application of known error detection principles) directly arrives at the core inventive concept of the '505 patent. The invention claimed in the '505 patent would therefore have been an obvious design choice and a natural progression of existing technologies to a person of ordinary skill in the art seeking to improve the reliability of NVM reads.

Conclusion:

The claims of U.S. Patent 6,963,505 are likely obvious under 35 U.S.C. § 103 in light of the combination of prior art teaching the use of multiple reference levels for reading multi-state memory cells and the common knowledge of employing error detection codes to identify read errors. The motivation to combine these teachings would have been the clear and pressing need to improve the accuracy of data reads in non-volatile memory systems, a fundamental goal for any memory system designer at the time. The solution presented in the '505 patent represents a predictable application of known techniques to solve a known problem.

An analysis of United States Patent 6,963,505, titled "Method circuit and system for determining a reference voltage," provides the following details regarding its term, related applications, and patent family.

Key Dates and Status:

• Application Number: 10/695,448
• Filing Date: October 29, 2003
• Issue Date: November 8, 2005
• Legal Status: Expired

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE)

A review of the prosecution history for US Patent 6,963,505 indicates that no Patent Term Adjustments (PTA) or Patent Term Extensions (PTE) were granted. PTA is awarded to compensate for delays by the U.S. Patent and Trademark Office (USPTO) during the examination of a patent application. PTE is a separate mechanism, typically used to restore patent term lost due to regulatory review of products like pharmaceuticals. As neither of these extensions apply, the patent's term is determined directly from its filing date.

Continuity Data: Continuation and Divisional Applications

US Patent 6,963,505 is an original utility patent application and does not claim priority as a continuation or divisional application of a prior non-provisional US application. The application does, however, claim priority to a provisional application.

Related Family Members

This patent is part of a larger international patent family. The application claims priority to the following earlier-filed application:

• U.S. Provisional Application No. 60/421,785, filed on October 29, 2002.

The patent family also includes several international counterparts, indicating that protection for this invention was sought in multiple countries. These include, but are not limited to:

• China: CN1898751A
• Europe: EP1685571A4
• Japan: JP2007512639A
• Taiwan: TWI363350B
• World Intellectual Property Organization (WIPO): WO2005041107A2

Projected Expiration Date

For utility patents filed on or after June 8, 1995, the term is 20 years from the earliest effective non-provisional filing date. The filing date for US Patent 6,963,505 is October 29, 2003. With no patent term adjustments or extensions, the projected expiration date was October 29, 2023. As of the current date of May 13, 2026, this patent has expired. This projection assumes all required maintenance fees were paid throughout the patent's term.

Defensive Disclosure: Method, Circuit, and System for Determining a Reference Voltage

Publication Date: May 13, 2026
Assignee: Defensive Publications Inc.
Reference Patent: US 6,963,505 B2

Introduction: This document discloses a plurality of methods, systems, and applications that build upon the core teachings of US Patent 6,963,505. The purpose of this disclosure is to place these concepts in the public domain, thereby establishing prior art against subsequent patent applications for trivial or obvious improvements. The following disclosures are intended to be enabling for a person of ordinary skill in the art of semiconductor memory design, testing, and fabrication.

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Core Technology Synopsis (Based on US 6,963,505)

The foundational patent describes a method for optimizing the reference voltage used for reading data from non-volatile memory (NVM) cells, particularly multi-level cells (MLCs). The core process involves:

1. Reading a subset of memory cells using multiple, slightly different "test" reference voltage levels.
2. Calculating a read error rate for each test reference level.
3. Selecting the reference level that produces the lowest error rate.
4. Using this optimized reference level for subsequent read operations on the main memory array, or to program a new set of operating reference cells.

This technique compensates for threshold voltage drift in NVM cells over time and with use, a critical issue for data integrity in flash memory.

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Derivative Disclosures

I. Variations on Core Claim 1: A method of selecting a reference level... comprising: using each of said possible reference levels to read a set of cells... determining a read error rate... and selecting a reference level... whose read error rate is relatively low.

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Axis 1: Material & Component Substitution

1.1. Graphene-Based Sensing Transistors:

• Enabling Description: The sense amplifier circuit (as in Fig. 4, element 414) is fabricated using graphene field-effect transistors (GFETs) instead of traditional CMOS-based transistors. The high carrier mobility and atomic-scale thickness of graphene allow for ultra-sensitive detection of minute current variations from the memory cell, enabling the differentiation of much finer reference voltage steps. The GFETs are arranged in a differential amplifier configuration, where one input is connected to the memory cell's bit line and the other to the output of the selected test reference cell. The resulting output provides a more precise error signal, allowing for the selection of an optimal reference voltage with higher resolution than achievable with silicon-based sense amplifiers.
• Mermaid Diagram:

  graph TD
      subgraph GFET Sense Amplifier
          A[Memory Cell Bitline] --> GFET1(GFET T1);
          B[Test Reference Cell Output] --> GFET2(GFET T2);
          GFET1 --> C{Differential Stage};
          GFET2 --> C;
          C --> D[Output to Controller];
      end
      Controller(Controller 410) -- Selects --> B;
      D --> Controller;
      Controller -- Analyzes Error Rate --> E(Error Rate Table 416);
  

1.2. Phase-Change Memory (PCM) Reference Cells:

• Enabling Description: The test reference cells (Fig. 4, elements 432, 434, 436) are constructed from Phase-Change Materials like Ge2Sb2Te5 (GST) instead of standard floating-gate transistors. The resistance of a PCM cell can be finely tuned by controlling the degree of amorphization or crystallization induced by programming pulses. A digital-to-analog converter (DAC) provides precise, stepped voltage pulses to the PCM reference cells, programming them to a wide spectrum of resistance values. These resistance values directly correspond to the test reference levels. This substitution allows for a non-volatile and highly granular set of reference levels that are less susceptible to the charge leakage that affects traditional floating-gate reference cells.
• Mermaid Diagram:

  sequenceDiagram
      participant Controller
      participant DAC
      participant PCM_Ref_Cell as PCM Reference Cell
      Controller->>DAC: Set Voltage Level 'V_n'
      DAC->>PCM_Ref_Cell: Apply Programming Pulse
      PCM_Ref_Cell->>PCM_Ref_Cell: Resistance set to R(V_n)
      Controller->>Sense_Amplifier: Compare Memory Cell to PCM_Ref_Cell
  

1.3. Ferroelectric RAM (FeRAM) for Error Count Storage:

• Enabling Description: The error rate table (Fig. 4, element 416) is implemented using a small array of Ferroelectric RAM (FeRAM) cells. FeRAM offers fast, low-power write operations and high endurance. As the controller calculates the error rate for each test reference voltage, it directly writes the binary count to the FeRAM array. This is more efficient than writing to the main NVM block, which would incur higher latency and power consumption. The FeRAM's non-volatility ensures the error rate data persists across power cycles.
• Mermaid Diagram:

  classDiagram
  class Controller410 {
    +calculateErrorRate()
    +recordErrorRate()
  }
  class ErrorRateTable416_FeRAM {
    -feRAM_Array: byte[]
    +writeErrorCount(address, count)
    +readErrorCount(address): count
  }
  Controller410 --|> ErrorRateTable416_FeRAM : records to
  

---

Axis 2: Operational Parameter Expansion

2.1. Cryogenic Temperature Operation for Quantum Computing Readout:

• Enabling Description: The entire reference voltage selection system is operated within a dilution refrigerator at temperatures below 100 millikelvin, designed for controlling and reading out superconducting qubits. At these temperatures, the threshold voltage distributions of the NVM cells (now silicon-germanium heterostructures) become extremely narrow. The reference voltage determination method is used to dynamically calibrate the readout reference for each qubit's associated control transistor. The test reference levels are generated with microvolt precision. The error rate calculation is based on the fidelity of qubit state measurement (distinguishing |0⟩ from |1⟩), with the optimal reference minimizing state misidentification.
• Mermaid Diagram:

  graph TD
      subgraph Dilution Refrigerator (<100mK)
          A(Qubit) --> B(Control Transistor);
          B --> C{Sense Amplifier};
          D(Cryo-DAC) -- generates test V_ref --> E(Reference Cell);
          E --> C;
          C --> F(Cryo-Controller);
          F -- calculates qubit state fidelity --> G(Fidelity Table);
          F -- selects optimal V_ref --> D;
      end
  

2.2. High-Frequency Operation for RF Signal Processing:

• Enabling Description: The method is adapted for an analog NVM array used to store filter coefficients for a high-frequency (GHz range) RF signal processor. The "read" operation is a continuous signal comparison, not a discrete data read. The "error rate" is quantified by the Signal-to-Noise Ratio (SNR) or Error Vector Magnitude (EVM) of the processed RF output signal. The controller sweeps the reference levels (which are now DC bias points for the analog memory cells) and uses a feedback loop from an RF power meter or vector signal analyzer to determine which reference bias point results in the highest output SNR. This optimal bias is then locked in for device operation.
• Mermaid Diagram:

  flowchart LR
      subgraph RF_Processor
          Input(RF Input Signal) --> Analog_NVM(Analog NVM Filter)
          Analog_NVM -- V_bias --> Controller
          Analog_NVM --> Output(Filtered RF Output)
      end
      subgraph Feedback_Loop
          Output --> VSA(Vector Signal Analyzer)
          VSA -- measures EVM/SNR --> Controller(Controller)
          Controller -- adjusts --> Test_Bias_Generator(Test Bias Generator)
          Test_Bias_Generator --> Controller
      end
      Controller -- Selects V_bias_optimal --> Analog_NVM
  

---

Axis 3: Cross-Domain Application

3.1. Aerospace: Adaptive Sensor Calibration in Hypersonic Vehicles:

• Enabling Description: Strain gauges and temperature sensors embedded in the airframe of a hypersonic vehicle are subject to extreme material stress and thermal drift. Each sensor's output is digitized by an ADC whose reference voltage is provided by an NVM-based reference cell array. During pre-flight checks and in-flight cooldown periods, a known calibration signal (e.g., zero strain) is applied. The reference voltage selection method is then executed. The controller reads the sensor's digital output using a range of reference voltages. The "error rate" is defined as the deviation from the expected digital output for the known calibration signal. The reference voltage that minimizes this deviation is selected, effectively re-calibrating the sensor's ADC in real-time to compensate for drift caused by extreme operational conditions.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> PreFlight_Calibration
      PreFlight_Calibration: Apply zero-strain signal
      PreFlight_Calibration: Run V_ref optimization loop
      PreFlight_Calibration: Store V_ref_optimal
      PreFlight_Calibration --> InFlight_Operation: Lock V_ref
      InFlight_Operation: Monitor sensor data
      InFlight_Operation --> Cooldown_Recalibration: Detect cooldown phase
      Cooldown_Recalibration: Re-run V_ref optimization
      Cooldown_Recalibration --> InFlight_Operation: Update V_ref
  

3.2. AgTech: Soil Nutrient Sensor Self-Correction:

• Enabling Description: An in-situ soil sensor array measures levels of nitrates, phosphates, and potassium (NPK). The ion-selective electrodes used for sensing are prone to biofouling and calibration drift over time. The sensor node includes a microcontroller and a small NVM. Periodically (e.g., nightly), the sensor performs a self-test by switching its input to a set of internal, stable chemical reference solutions. It then executes the reference voltage selection algorithm. It reads the output for the known reference solution using various ADC reference voltages. The "error" is the difference between the measured value and the known concentration. The algorithm finds the reference voltage that minimizes this error, effectively compensating for sensor drift without requiring manual recalibration in the field.
• Mermaid Diagram:

  sequenceDiagram
      participant Scheduler
      participant Sensor_Mux as Sensor Multiplexer
      participant ADC
      participant Controller
      Scheduler->>Sensor_Mux: Switch to Reference Solution
      loop For each Test V_ref
          Controller->>ADC: Set Reference Voltage
          Sensor_Mux->>ADC: Provide Signal
          ADC->>Controller: Send Digital Reading
          Controller->>Controller: Calculate Deviation from Known Value
      end
      Controller->>Controller: Select V_ref with min deviation
      Controller->>ADC: Lock Optimal V_ref
      Scheduler->>Sensor_Mux: Switch back to Soil Probes
  

3.3. Consumer Electronics: Battery State-of-Charge (SoC) Estimation Refinement:

• Enabling Description: A battery management system (BMS) in a smartphone or laptop uses an NVM to store its aging model parameters. The "coulomb counting" method for SoC estimation suffers from cumulative error. The disclosed method is used to correct this drift. A "subset of cells" is a set of known SoC data points (e.g., a fully charged state, a 50% discharged state) recorded during manufacturing test. Periodically, when the battery reaches one of these known states (e.g., upon reaching 100% charge), the BMS controller reads a cell representing the coulomb count using different reference voltages. The "error rate" is the discrepancy between the coulomb counter's reading and the known ground-truth SoC. The controller selects the reference voltage that minimizes this error, effectively recalibrating the SoC "reader" to account for battery aging and temperature effects.
• Mermaid Diagram:

  graph TD
      A[Battery Cell] -- Voltage/Current --> B(Coulomb Counter);
      B --> C{SoC Estimator};
      D(NVM Aging Model) -- V_ref --> C;
      C -- Estimated SoC --> E(System);
      F(Ground Truth Event: e.g., Full Charge Detected) --> G(Controller);
      G -- Initiates Calibration --> H(V_ref Test Module);
      H -- Tries V_ref(n) --> D;
      C -- Test SoC --> G;
      G -- Compares Test SoC with Ground Truth --> G;
      G -- Selects V_ref_optimal --> D;
  

---

Axis 4: Integration with Emerging Tech

4.1. AI-Driven Predictive Reference Voltage Selection:

• Enabling Description: The controller (Fig. 4, 410) is replaced with a small, edge-based neural network (NN) processor. This NN is trained on historical data of temperature, program/erase cycles, and the corresponding optimal reference voltages determined by the original method. Instead of exhaustively testing all reference levels, the NN takes current operating parameters (temperature, cycle count) as input and predicts a smaller, high-probability range of optimal reference voltages to test. This significantly reduces the time and power required for calibration. The system still performs the error rate check on the predicted subset to validate the NN's output and provide new data for continuous, on-device learning.
• Mermaid Diagram:

  flowchart TD
      A[Temperature Sensor] --> D{NN Processor};
      B[P/E Cycle Counter] --> D;
      C[Time-since-last-program] --> D;
      D -- Predicts --> E(Small Set of Test V_refs);
      E --> F(Test & Error Check Module);
      G(Subset of NVM Cells) --> F;
      F -- Validates & Finds V_ref_optimal --> H(Operational V_ref);
      F -- (V_in, V_out_optimal) --> I(NN Training Feedback Loop);
      I --> D;
  

4.2. IoT-Enabled Fleet-Wide Drift Monitoring:

• Enabling Description: Each NVM device in a large-scale IoT deployment (e.g., a fleet of autonomous vehicles) periodically runs the reference voltage optimization process. The determined optimal reference voltage, along with device ID, temperature, and cycle count, is transmitted to a central cloud server. This server aggregates the data from the entire fleet, creating a real-time map of memory drift characteristics under various real-world conditions. This aggregated data can be used to predict failures, schedule preventative maintenance, and push firmware updates that proactively adjust the range of test reference voltages for all devices in the fleet, improving overall system reliability.
• Mermaid Diagram:

  sequenceDiagram
      participant IoT_Device
      participant Cloud_Server
      participant Analytics_Engine
      loop Periodically
          IoT_Device->>IoT_Device: Run V_ref Optimization
          IoT_Device->>Cloud_Server: Send {DeviceID, V_ref_optimal, Temp, Cycles}
      end
      Cloud_Server->>Analytics_Engine: Aggregate Fleet Data
      Analytics_Engine->>Analytics_Engine: Analyze Drift Trends
      Analytics_Engine->>Cloud_Server: Generate New V_ref Test Ranges
      Cloud_Server->>IoT_Device: Push Firmware Update
  

4.3. Blockchain for Reference Cell Provenance:

• Enabling Description: For high-security applications (e.g., military or financial hardware), the manufacturing and initial calibration data of the reference cells is recorded on a private blockchain. During the initial factory test, the optimal reference voltage for a "golden" data pattern is determined and its value, along with the test conditions and a timestamp, is stored as a transaction in a block associated with the chip's unique ID. In the field, if the device needs to prove its data integrity, it can re-run the calibration and the resulting optimal reference can be cryptographically checked against the immutable record on the blockchain. This provides a verifiable audit trail for the memory's physical state, preventing tampering with reference levels.
• Mermaid Diagram:

  graph TD
      subgraph Factory
          A[Chip Manufacturing] --> B(Initial Calibration);
          B -- {ChipID, V_ref_initial, Test_Pattern, Timestamp} --> C(Create Transaction);
          C --> D{Add to Blockchain};
      end
      subgraph Field_Operation
          E[Device Power-On Self-Test] --> F(Run V_ref Optimization);
          F -- V_ref_current --> G(Verification Module);
          D -- query with ChipID --> G;
          G -- Compares V_ref_current with V_ref_initial --> H(Integrity Status);
      end
  

---

Axis 5: The "Inverse" or Failure Mode

5.1. Graceful Degradation to Binary Mode:

• Enabling Description: In a multi-level cell (MLC) memory, if the reference voltage optimization process fails to find any reference level that produces an error rate below a critical threshold (e.g., the error correction code limit is exceeded), the controller triggers a "safe mode." In this mode, the memory logically reconfigures itself to operate as a single-level cell (SLC) device. It collapses the four MLC levels (e.g., '11', '10', '01', '00') into two SLC levels ('1' and '0'). This drastically widens the voltage margin between states, making the data readable even with significant threshold voltage drift, albeit at a reduced storage capacity. The reference voltage is set to a fixed level midway between the new, wider SLC distributions. This allows the device to remain functional for critical data retrieval even after severe degradation.
• Mermaid Diagram:

  stateDiagram-v2
      state "MLC Operation (4-Level)" as MLC
      state "SLC Operation (2-Level)" as SLC
  
      [*] --> MLC
      MLC --> MLC: V_ref optimization successful
      MLC --> SLC: Error rate > Critical Threshold
      note right of MLC
          Capacity = N
          Reference voltage is dynamic.
      end note
      SLC --> [*]: Device Failure
      note right of SLC
          Capacity = N / 2
          Reference voltage is fixed.
          Critical data can be retrieved.
      end note
  

---

II. Combination Prior Art with Open-Source Standards

1. Combination with the RISC-V ISA:

• Enabling Description: A custom instruction is added to the open-source RISC-V instruction set architecture (ISA) specifically to execute the reference voltage optimization process. The instruction, VREF.OPT rd, rs1, rs2, takes the starting memory address of the test subset (rs1) and the address of a configuration block (rs2) as inputs. The configuration block specifies the range and step of test voltages. The instruction triggers a hardware state machine (a co-processor) that performs the read/error-check loop defined in US 6,963,505. Upon completion, the optimal reference voltage value is written to the destination register (rd). This offloads the entire process from the main CPU cores, allowing for a standardized, low-overhead method of memory calibration on any RISC-V compliant system.

2. Combination with the JTAG (IEEE 1149.1) Standard:

• Enabling Description: The reference voltage determination circuitry is integrated into the JTAG Boundary-Scan architecture of the chip. A new public instruction, CAL_VREF, is added to the device's Boundary Scan Description Language (BSDL) file. When this instruction is loaded into the JTAG instruction register, the Test Access Port (TAP) controller re-purposes the scan chain to control the reference voltage selection logic. The TDI pin is used to serially load the test voltage parameters, and the TDO pin is used to shift out the resulting error rates or the final optimal voltage. This allows manufacturing test equipment and in-field diagnostic tools to non-intrusively trigger and monitor the memory calibration process using a ubiquitous, standardized hardware interface.

3. Combination with the Universal Flash Storage (UFS) Protocol:

• Enabling Description: A new vendor-specific command is defined within the open UFS protocol standard to manage the reference voltage calibration. A VREF_CALIBRATE command, sent from the host system to the UFS device, initiates the process. The command's arguments specify the logical block addresses (LBAs) to use for the test subset and whether to run a quick or exhaustive search. The UFS device controller performs the optimization internally and returns a status code and the new optimal reference voltage in the command's response UPIU (Unit Protocol Information Unit). This integrates the physical layer optimization of the NAND flash directly into the high-level storage protocol, allowing the host operating system or file system to intelligently request memory recalibration based on performance metrics or predicted workload.