US 5828601

I'll search for this patent's litigation and docket status, then summarize.

Let me check for any specific litigation or CAFC docket activity tied to this patent number.

US 5,828,601 — "Programmed Reference"

Bibliographic data (from the patent record)

Assignment chain of record: Advanced Micro Devices (1993-12-01) → Spansion Inc. (2007-03-19) → Spansion LLC (2007-03-26) → Cypress Semiconductor Corporation (2015-06-26). Security interests recorded to Barclays Bank PLC and Morgan Stanley Senior Funding, Inc. along the way.

Abstract

"A programmable reference used to identify a state of an array cell in a multi-density or low voltage supply flash EEPROM memory array. The programmable reference includes one or more reference cells, each reference cell having a floating gate which is programmed to control its threshold value. The array cells are read by applying an identical voltage to the gate of the array cell and the reference cell and comparing outputs to determine the array cell state. During read of an array cell, the programmable reference cell is biased the same as the array cell, so that the difference in threshold values between reference cells and array cells remain constant with a change in VCC. Circuitry is included for programming the reference cells utilizing a simple resistor ratio. Programming is performed at test time, preferably by the manufacturer, to assure VCC remains within strict tolerances. The array cells are programmed and read without resistor biasing and under looser tolerances using the reference cells at a later time."

The technical problem and the invention's move

The patent's background frames two prior art reference schemes — the sense ratio method (FIG. 1; differing resistor ratios on the drains, so the output varies with resistor process/temperature and VCC) and the bias gate method (FIG. 3; resistor ratio on the reference gate to shift VGS, which is more accurate but still drifts with VCC, temperature, and process). The margin problem is quantified: single density gives a 1.10 V margin (4.00 V − 2.90 V), 3/2 density 0.55 V (4.00 V − 3.45 V), and double density 0.33 V.

The invention's central trick: program the reference cell's floating gate itself so the threshold difference is baked into the cell, then during read apply the identical gate voltage to array cell and reference cell with identical bias conditions — no sense ratio, no gate resistor. The scheme is therefore "lopsided" by design: the bias-gate/resistor-ratio method is used only at manufacture/test time to set the reference thresholds (under tight VCC and temperature control), while normal array program and read happens later under loose tolerances.

Plain-language overview of each independent claim

Claim 1 — the basic read architecture.
A memory with (i) an array cell holding one of n threshold values, (ii) a reference cell whose floating gate is programmed to a reference threshold deliberately placed between two successive array threshold values, (iii) a comparison circuit wired to both cell outputs, and (iv) a single power supply that feeds the same supply voltage to both gates. The last element is the point of novelty: identical gate drive means the cell and reference see the same operating point, so their threshold difference — the thing the comparison actually resolves — survives supply variation.

Claim 4 — the full program/verify system.
Adds the complete ecosystem: n program reference cells (used to program array cells), n−1 read reference cells (each programmed between two successive program-reference thresholds), a reference program-verify means, an array program-verify means that keeps programming the array cell until it matches a chosen program reference cell, a power supply for the read voltage to both array and read-reference gates, and a comparison circuit reporting which program reference cell's threshold the array was set to. Note the asymmetry in the claim language: the reference verify voltage varies "significantly less" than the array verify voltage (claim 5) — i.e., references are set precisely at test, arrays are set loosely later.

Claim 10 — the reference-programming apparatus.
A machine for burning in the reference cells one at a time, comprising:

• a reference count circuit that walks through cells sequentially, announcing the target via a COL signal and a ROW signal, and advancing only when an updated RDSO signal says the current cell passed;
• a program-verify signal circuit supplying the program/verify gate voltage (VPX), the drain program voltage (VPROG), and the VERIFY strobe;
• a sense bias circuit routing the verify voltage to the selected cell's gate per ROW;
• a data buffer reference circuit routing the program voltage to the selected cell's drain per COL;
• a golden bit cell (unprogrammed, UV-erased);
• a reference bias circuit with multiple resistor ratios selectively coupled between the read voltage and the golden bit's gate per COL; and
• a comparison circuit that, during VERIFY, compares golden-bit drain vs. selected-reference drain and emits RDSO when they are substantially equal.

The resistor ratio is chosen so that throttling the golden cell's gate by a fixed amount reproduces the drain current of a cell programmed to the desired threshold — a one-time, test-time application of the bias-gate method.

Claim 13 — the programming method (6 steps).
(a) select the first reference cell and the first resistor ratio; (b) couple that ratio to the golden bit's gate; (c) apply program voltage to charge the selected cell's floating gate; (d) apply the reference verify voltage to the selected cell's gate and through the selected resistor ratio to the golden bit's gate, generating both outputs; (e) compare them, and loop back to (c) if not substantially equal; (f) advance to the next reference cell and next resistor ratio, repeating (b)–(e) until all n are done. Claim 12 (dependent) recites the comparison circuit for claim 10 as reference sense circuit → first preamplifier (selected cell) → second preamplifier (golden bit) → sense amplifier producing RDSO.

Claim 14 — the word-line-level architecture.
A first word line and a second word line both driven by one power supply at a substantially identical supply voltage; the array cell's gate on the first word line; n−1 read reference cells' gates on the second word line, each floating gate programmed between two different successive array threshold values; and read sense amplifiers each comparing the array cell's source-drain path against a respective reference cell's source-drain path. Claim 15 adds n verify reference cells on that same second word line, each programmed to a different one of the n array thresholds, with their own verify sense amplifiers; claim 16 states n > 2.

What I could and could not confirm

Verified from the patent record itself: all bibliographic data above, the abstract, the five independent claims (1, 4, 10, 13, 14), and the dependent-claim structure (claims 2, 3, 5–9, 11, 12, 15, 16 are dependent). Note the literal wording defects in the patent as printed — claim 12 recites "a first sense amplifier voltage voltage" and "second sense amplifier voltage voltage"; I have preserved those literally rather than correcting them.

Litigation / docket — no authoritative finding, and I want to flag this clearly:

• The Google Patents page carries a "Family has litigation" marker linking to a Darts-IP family record (family ID 22577486). I could not retrieve the underlying case, court, parties, or outcome from that pointer, and I am not asserting that any particular suit exists.
• My searches surfaced numerous Spansion/Cypress lawsuits (Macronix v. Spansion ITC 337-TA-922 and the parallel N.D. Cal. action; Fast Memory v. Spansion in N.D. Tex.; Samsung/Spansion matters; In re Cypress Semiconductor, CAFC 09-M898), but those are tied to other patents — e.g., the '608, '959, '360, '557, '630 patents — and I found no document naming US 5,828,601 as an asserted patent.
• I found no CAFC 2026 docket activity involving 5,828,601. Independent of that null result, the practical ceiling is that the patent expired 2015-10-27, so it cannot be asserted for post-expiration infringement, and no 2026 appellate activity would be expected from a live case on the patent itself.
• Treat the absence of findings as "not found," not as "confirmed never litigated." A definitive answer would require running the Darts-IP family 22577486 record directly, or searching PACER/RPX for the patent number across district courts and the ITC.

Distinguishing numbers (to avoid cross-contamination): unrelated hits for the string "5828601" appeared for Brazilian and Lithuanian corporate registry entries, an FCC document ID, an Australian application number AU 5828601, and chromatographic retention data. None of these refer to US Patent 5,828,601 and should not be conflated with it.

I'll search for litigation involving US patent 5828601.

Let me search more specific litigation databases.

Let me dig deeper into the Darts-IP litigation signal and district court records.

Litigation Search: U.S. Patent No. 5,828,601 ("Programmed Reference")

Bottom line: I found no district-court patent infringement litigation (or ITC §337 action) in which U.S. Patent No. 5,828,601 was asserted as a patent-in-suit. What I did find is a related administrative priority contest (a USPTO interference) involving the '601 patent, plus a flag on the Google Patents family record indicating litigation exists somewhere in the family. Details and caveats below.

1. What was found: USPTO Interference No. 105,606 (not district-court litigation)

This is the only proceeding I could confirm that directly involves the '601 patent. It is a patent interference before the Board of Patent Appeals and Interferences (BPAI), i.e., an administrative priority contest, not infringement litigation:

Related Federal Circuit appeals (both involving the '601 inventors/patent):

Per the Federal Circuit's own summary (via JD Supra's analysis of Hollmer v. Harari): "The case before the Federal Circuit stemmed from an interference proceeding (Interference No. 105,606) between Harari and Mehrotra ... and Hollmer and Cleveland (the inventors of U.S. Patent 5,828,601)."

• https://www.courtlistener.com/opinion/[801817](/patent/801817)/hollmer-v-harari/
• http://g.casetext.com/case/harari-v-hollmer
• https://www.jdsupra.com/post/contentViewerEmbed.aspx?fid=7294901a-d1be-40a0-8de6-a952f8de0532

Note: These were NOT infringement suits. The plaintiff/defendant framing requested does not cleanly apply — the "parties" were adverse inventors contesting priority of invention.

2. Unverified litigation signal: Darts-IP family flag

The Google Patents record for US5828601A carries a banner: "Family has litigation — First worldwide family litigation filed" pointing to a Darts-IP database entry (family ID 22577486):

• https://patents.darts-ip.com/?family=22577486

I could not retrieve the underlying Darts-IP litigation record (the database is a paywalled/licensed product — "Global patent litigation dataset by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License"). Therefore I cannot confirm the plaintiff, defendant, jurisdiction, case number, filing date, or status from that source. This flag is a lead, not a verified case. It may also reflect litigation on a family member (e.g., the EP, JP, KR, or TW counterparts) rather than the U.S. '601 patent itself.

Family members (for context, per Google Patents):

• US 5,828,601 (the patent at issue)
• EP 0656628 B1
• JP 3813640 B2 (and JP 2006196184 A)
• KR 100357444 B1
• TW 302479 B
• DE 69432452 T2

3. Ownership / assignment history (relevant to any litigation stance)

Assignment records in the Google Patents record show the patent changed hands, which matters for identifying a potential plaintiff:

• 1993-12-01 – Assigned to Advanced Micro Devices, Inc. (original assignee)
• 2007-03-19 – Assigned to Spansion Inc.
• 2007-03-26 – Assigned to Spansion LLC
• 2015-06-26 – Assigned to Cypress Semiconductor Corporation (from Spansion LLC)
• Current assignees: Cypress Semiconductor Corp; Spansion Inc.
• Legal status: Expired – Lifetime (anticipated expiration flagged 2015-10-27)

4. What I did NOT find (and explicit caveats)

• No district-court infringement case (D. Del., E.D. Tex., N.D. Cal., D. Minn., etc.) naming US 5,828,601 as a patent-in-suit appeared in searches of public litigation databases, CourtListener, PACER-related materials, or press releases.
• No ITC Section 337 investigation naming the '601 patent.
• No PTAB proceeding (IPR/PGR) on the '601 patent surfaced.
• No CAFC appeal of an infringement judgment on the '601 patent found — the two CAFC cases above are interference appeals, not infringement appeals.
• Multiple searches returned irrelevant hits where "5828601" matched unrelated numbers (e.g., an AU patent document number, Brazilian/Lithuanian registry entries, a Univ. of Connecticut case, an EPO document). I excluded those.

The searches I ran were not exhaustive, and this response is limited to what surfaced. Authoritative confirmation would require querying Darts-IP (family 22577486), Lex Machina, Unified Patents' litigation portal, or PACER/RECAP directly — sources I could not fully retrieve here. If the Darts-IP flag corresponds to real litigation, I could not verify whether it targets the U.S. '601 patent or a foreign family member, nor identify the parties.

Summary Table

If you require a definitive "yes/no" on infringement litigation, I do not have high confidence either way — the Darts-IP family flag suggests something exists, but I could not retrieve it, and I found no affirmative district-court record. I would recommend pulling the Darts-IP family 22577486 record directly to resolve this.

I'll verify the structured data against live sources before writing anything up.

Let me run a few more targeted checks for any AIA trial or appellate activity tied specifically to this patent's number.

Proceedings overview

Zero AIA trial proceedings on file. The USPTO Open Data Portal structured block returns no IPR, PGR, or CBM involving US 5,828,601, and my independent searches of PTAB dockets and public petition/final-written-decision literature surfaced no petition, institution decision, FWD, or appeal tied to this patent number — so the count is 0 total (0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denied). The bottom-line defensive posture is unusual and, frankly, dispositive: this patent expired on 2015-10-27 (anticipated expiration per Google Patents' legal-status data) and carries a status of "Expired - Lifetime," so no PTAB activity was ever needed to neutralize it. There is no "hardened by surviving two IPRs" story here — the patent simply ran out its term untouched, and all 16 claims are UNTESTED at the Board.

No proceedings to enumerate

There is no {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry to write, because no AIA trial number exists. Rather than manufacture one, here is what I verified and what I ruled out:

• ODP/PTAB structured data: canonical list is empty — "no AIA trial proceedings for this patent as of the most recent ingest."
• Web search for US5828601 / 5,828,601 + IPR/PGR/CBM: returned only unrelated patents sharing the "582" digits. Specifically, searches surfaced (a) a different '582 patent claiming an LC resonant circuit, subject to Realtek's opposition in an ITC-adjacent IPR (see the PTAB petition excerpt at ptacts.uspto.gov), and (b) a different '582 patent covering online advertising, asserted in district court. Neither is US 5,828,601. Do not conflate these numbers — this is exactly the kind of digit-collision that produces a fabricated "IPR history."
• Litigation flag: the Google Patents record for US5828601 carries a "Family has litigation" badge pointing to a Darts-IP family entry (family ID 22577486). The page itself does not name a district court case, and I could not confirm any case asserting this patent. Treat the litigation flag as unverified for the '601 specifically. The AMD flash-memory enforcement activity I did find — e.g., AMD v. Alliance Semiconductor (settled 2000, U.S. Pat. Nos. 5,007,691 and 5,126,808, per Semiconductor Digest) and Advanced Micro Devices, Inc. v. [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.) (N.D. Cal. 3:08-cv-00986, asserting the '592, '830, '893, '990 and other AMD patents) — involves different patents, not the '601.
• Federal Circuit: no appeal docketed from any PTAB proceeding, because there was no PTAB proceeding. No CAFC opinion construing or invalidating the '601 claims was found.

Caveat on confidence: I am reporting "no PTAB activity found," not a metaphysical guarantee. Pre-AIA ex parte reexamination is not an AIA trial and would not appear in the ODP AIA-trial feed; I did not confirm one way or the other whether a reexam request was ever filed against the '601. If you need that confirmed, pull the file wrapper at USPTO Patent Center for Application No. 08/160,582.

Strategic summary

Claim status — all untested, and moot. Claims 1–16 (independent claims 1, 4, 10, 13, and 14, with 2, 3, 5–9, 11, 12, 15, 16 depending therefrom) were never adjudicated by the PTAB. That is not the "narrowed but hardened" posture a defendant usually confronts; it is the posture of a patent that was never worth challenging because its economic life ended first. US5828601 issued 1998-10-27 and expired 2015-10-27. For anyone receiving an assertion letter today, the controlling fact is § 286's six-year damages lookback (recovery reaches back only to roughly 2020) combined with the absence of injunctive exposure on an expired right. Any demand premised on ongoing infringement of the '601 is legally defective on its face — the patent cannot be infringed after expiration.

Estoppel landscape — § 315(e)(2) is inapplicable. Because no IPR was ever instituted, there is no estoppel against anyone, and there is no petitioner/privy to trace. There is likewise no § 325(d) record built up from a prior Board challenge. If — counterfactually — someone attempted a late IPR, the art the examiner already considered would be the natural starting point: U.S. Pat. No. 4,449,203 (Motorola, "Memory with reference voltage generator"), U.S. Pat. No. 4,495,602 (Mostek, "Multi-bit read only memory circuit"), U.S. Pat. No. 5,386,388 (Intel, "Single cell reference scheme for flash memory sensing and program state verification"), WO 90/12400 (Sundisk, "Multi-state EEPROM read and write circuits"), U.S. Pat. No. 5,218,569 (Banks), and U.S. Pat. No. 5,258,958 (Toshiba), among the 11 references of record and the 71 citing documents. Any such challenge would face § 325(d) and a patent whose claims are in any event expired. Note the inventors themselves incorporated the Banks '569 and Sheppard '602 patents for the comparison and program-verify circuitry.

Pattern signals — none present. No petitioner filed multiple IPRs on this patent (there is no petitioner at all). The patent owner never had occasion to defend at the Board, so there is no history of aggressive PTAB appeals. There is no defensive aggregator in the chain — no Unified Patents, RPX, or similar entity filing here; the only defensive-patent-community practitioner in the ownership history is the security-interest and assignment chain (AMD → Spansion Inc. (2007-03-19) → Spansion LLC (2007-03-26) → Cypress Semiconductor (2015-06-26)), reflecting the AMD/Spansion flash-memory divestiture and the subsequent Cypress–Spansion merger.

Recommended next steps

1. If you are a defendant and a demand letter cites US 5,828,601: the answer is expiration, not IPR. The patent expired 2015-10-27 and its status is "Expired - Lifetime." There is no live claim to invalidate and no ongoing infringement to enjoin. Quote the anticipated-expiration date from the Google Patents record and pair it with the § 286 six-year damages cap. This is a document-and-close scenario, not a validity fight.
2. Do not build a defense narrative around PTAB history that does not exist. Because there is no FWD, there are no canceled claims to quote, no institution decision to distinguish, and no Board claim construction to leverage or avoid. Any brief that characterizes the '601 as "having survived IPR" or "having been invalidated in IPR" is fabricated and citable as such.
3. For the record, verify the reexam question directly. The ODP AIA-trial feed does not capture pre-AIA ex parte reexamination. Pull the full file wrapper at USPTO Patent Center for application 08/160,582 to confirm whether any reexamination request (control number in the 90/xxx,xxx series) was ever filed. Until you do, state the absence of PTAB activity as verified and the absence of reexam history as unverified.
4. Ignore the "Family has litigation" badge unless you can source it. The Darts-IP link (family 22577486) on the Google Patents page does not identify a case, and my searches tied AMD's flash enforcement to other patents (5,007,691; 5,126,808; 5,545,592; 5,559,990). If the family litigation matters to your diligence, resolve it through Darts-IP, Lex Machina, or CourtListener directly rather than inferring from the badge.

Where to pull the primary sources referenced above: PTAB decisions and petitions — USPTO PTAB E2E / PTAB Decisions and the public ptacts.uspto.gov petition repository; district court records — CourtListener (e.g., AMD v. Samsung, N.D. Cal. 3:08-cv-00986, D.I. 143 at courtlistener.com/docket/4171947).

I'll pull what I can from the supplied record first, then probe for the assignment metadata the Google Patents mirror doesn't carry.

Ownership Reconstruction — US 5,828,601 "Programmed reference"

Patent data: App. No. 08/160,582 · filed 1993‑12‑01 · issued 1998‑10‑27 · 16 claims · inventors Hollmer & Cleveland · original assignee Advanced Micro Devices, Inc.

Source note (important): The authoritative copy of this patent supplied to me (Google Patents US5828601A, https://patents.google.com/patent/[US5828601A](/patent/US5828601A)/en) reproduces the USPTO assignment events in its Legal Events panel, but that mirror does not export reel/frame numbers or correspondent-of-record fields. I attempted live retrieval of the assignment-center records and could not recover reel/frame or correspondent data for this patent within the search budget. Where I do not have a reel/frame I say so rather than invent one. One reel/frame is recoverable — see the 2020‑11‑03 entry below. Verify all of this directly at https://assignmentcenter.uspto.gov/ (search "5828601") or https://assignment.uspto.gov/patent/index.html.

Inventors

Unusual patterns: none observed. Both inventors are on the record as assigning to the original corporate employer on the filing date itself (1993‑12‑01), which is the normal employee-invention posture for an operating semiconductor company. There is no recorded inventor-side assignment, no inventor-change filing, and no evidence in the record of inventors departing the original assignee within 12 months of filing. No portfolio fire-sale precursor signal here.

Original assignee

Advanced Micro Devices, Inc. (AMD) — named on the face of the patent.

• Line of business: AMD was, at filing and issuance, an operating merchant semiconductor manufacturer; its flash EEPROM business (the group from which the inventors came) was a significant NOR-flash supplier in the 1990s. The specification is squarely addressed to AMD's commercial problem — reference tracking for low-voltage-supply and multi-density (multi-level) flash EEPROM arrays (see the Background, discussing the shrinking working margin at 3/2 and double density).
• Product embodying the claims: The claimed subject matter is a reference scheme (programmed floating-gate reference cells + comparison circuit + shared supply voltage to array and reference gates — claim 1) rather than a standalone part. AMD did ship NOR-flash products in this era using floating-gate reference sensing, and the patent family was carried forward inside the AMD flash business. A specific part-number-to-claim mapping is not established by the assignment record; I flag that as unverified rather than assert it.
• Current status: AMD is operating (fabless; still headquartered in Santa Clara/Sunnyvale, CA). It no longer owns this patent. AMD's flash business was contributed to the AMD‑Fujitsu joint venture FASL LLC (formed April 2003), renamed Spansion LLC on 2004‑06‑28, taken public as Spansion Inc. on 2005‑12‑21, and the patent was recorded out of AMD in March 2007 (see timeline).

Assignment timeline

All entries below are the recorded events as surfaced on Google Patents' Legal Events panel for US5828601A (which is populated from USPTO assignment data). Reel/frame is not exposed for entries 1–8 in the source I hold except where noted in entry 9. Correspondent-of-record is likewise not exposed in that source.

1. 1993‑12‑01 (executed) / recorded 1993‑12‑01 — Reel not available in source

   • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST — SEE DOCUMENT FOR DETAILS)
   • Assignor: Cleveland, Lee E. and Hollmer, Shane C.
   • Assignee: Advanced Micro Devices, Inc.
   • Correspondent: not exposed in the source I hold — cannot assess recurrence.
   • Context: Initial employee-invention assignment, executed on the filing date.

2. Recorded 2007‑03‑19 (execution date not exposed) — Reel not available in source

   • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
   • Assignor: Advanced Micro Devices, Inc.
   • Assignee: Spansion Inc.
   • Correspondent: not exposed.
   • Context: Internal corporate reorganization / spinoff conveyance — transfer of AMD flash-memory IP into the Spansion entity that had been IPO'd in Dec 2005 under the Dec 2005 Contribution Agreement among AMD, AMD Investments, Fujitsu, FMH and Spansion.

3. Recorded 2007‑03‑26 (execution date not exposed) — Reel not available in source

   • Conveyance: Assignment
   • Assignor: Spansion Inc.
   • Assignee: Spansion LLC
   • Correspondent: not exposed.
   • Context: Same-day internal reorganization — pushing the record title from the public holding company down to the wholly-owned operating subsidiary, seven days after entry 2.

4. Recorded 2010‑06‑04 — Reel not available in source

   • Conveyance: Security Agreement (NOT a transfer of title)
   • Assignor: Spansion Inc., Spansion LLC, Spansion Technology Inc., Spansion Technology LLC
   • Assignee: Barclays Bank PLC
   • Correspondent: not exposed.
   • Context: Securitization / secured-lender collateral filing — this sits immediately after Spansion's Chapter 11 (filed 2009, emerged May 2010) and is consistent with exit-financing collateral.

5. Recorded 2015‑03‑13 — Reel not available in source

   • Conveyance: Release of Security Interest
   • Assignor: Barclays Bank PLC
   • Assignee: Spansion LLC, Spansion Technology LLC, Spansion Inc. (the grantors)
   • Correspondent: not exposed.
   • Context: Securitization unwind — Barclays releases its lien, clearing title ahead of the Cypress acquisition.

6. Recorded 2015‑03‑21 — Reel not available in source (see entry 9)

   • Conveyance: Security Interest (NOT a transfer of title)
   • Assignor: Cypress Semiconductor Corporation, Spansion LLC
   • Assignee: Morgan Stanley Senior Funding, Inc.
   • Correspondent: not exposed.
   • Context: Securitization — post-merger credit-facility lien granted by the combined Cypress/Spansion obligor group (Cypress's acquisition of Spansion closed 2015‑03‑12).

7. Recorded 2015‑06‑26 — Reel not available in source

   • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
   • Assignor: Spansion, LLC
   • Assignee: Cypress Semiconductor Corporation
   • Correspondent: not exposed.
   • Context: Merger / acquisition — Cypress Semiconductor's acquisition of Spansion, recorded as a title transfer a few months after the deal closed.

8. 2015‑10‑27 — anticipated expiration (not an assignment). This is consistent with the pre‑URAA 17‑years‑from‑issue term: 1998‑10‑27 + 17 years = 2015‑10‑27. The patent is expired. All later recordings are filings against an expired patent.

9. Recorded 2020‑11‑03 — Reel 035240 / Frame 0429 (this reel/frame is the previously recorded reel/frame referenced by the corrective document; it appears in the assignment text attached to this patent's record)

   • Conveyance: Corrective Assignment — "CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST."
   • Assignor: Cypress Semiconductor Corporation and Spansion LLC
   • Assignee: Morgan Stanley Senior Funding, Inc.
   • Correspondent: not exposed. ⚠️ Note the correction text expressly references US 8,647,899, not the '601 patent, so reel 035240/0429 is a portfolio-level lien covering multiple patents — treat that reel/frame as belonging to the Morgan Stanley security-interest family rather than as the '601-specific title transfer.
   • Context: Correction of a security-interest record — housekeeping, not a change in ownership.

Net ownership chain of record: Advanced Micro Devices, Inc. → Spansion Inc. → Spansion LLC → Cypress Semiconductor Corporation. Two liens (Barclays 2010, Morgan Stanley 2015) encumbered the chain, one of which was released in 2015.

Timeline diagram

timeline
    title Ownership of US 5828601
    1993 : Inventors assign to AMD
         : Application filed
    1998 : Patent issued to AMD
    2007 : AMD transfers to Spansion Inc
         : Spansion Inc to Spansion LLC
    2010 : Barclays security agreement
    2015 : Barclays releases security
         : Morgan Stanley security interest
         : Spansion LLC to Cypress
         : Patent term expires
    2020 : Morgan Stanley corrective filing

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. No link in the chain has a "IP / Patents / Licensing / Holdings / Ventures" suffix, and no single-purpose LLC appears. Every assignee is a named operating semiconductor company with a public footprint: AMD, Spansion Inc. (NYSE-listed holdco), Spansion LLC (operator of the Austin, TX wafer fab), Barclays Bank PLC (lender), Morgan Stanley Senior Funding (lender), Cypress Semiconductor. The Delaware-entity point is true of Spansion Inc. and Spansion LLC, but both are paired with real fabs, real headcount and real product revenue — not the registered-agent-only pattern.

2. Known asserter in the chain — NOT PRESENT. None of Acacia, Marathon, Intellectual Ventures, IPNav, Wi‑LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, or any Spangenberg vehicle appears anywhere in the recorded chain — including the security-interest holders.

3. Repeat correspondent across the chain — UNCLEAR / NOT ASSESSABLE. The correspondent-of-record field is not exposed in the assignment data I can retrieve for this patent, so I cannot test for a recurring recording attorney. I decline to infer one. This is a data gap, not a clean negative — if you can run the Assignment Center query directly, the correspondents on the 2007 AMD→Spansion pair and the 2015 Cypress pair are the fields worth capturing, since mixed operating-company/NPE shops (e.g. the Westerman, Hattori, Daniels & Adrian correspondent visible on adjacent AMD/Spansion assignment records for app. 11/066,567) are exactly the firms that appear on both sides of the line.

4. Cascading transfers — PRESENT AS A PATTERN, BUT EXPLAINED. Entries 2 and 3 are two consecutive assignments seven days apart (recorded 2007‑03‑19 and 2007‑03‑26), well inside the <24-month threshold. However, no shell indicia accompany them: same corporate family, no change in beneficial control, and the transfer is downstream of the publicly documented December 2005 AMD/Fujitsu Contribution Agreement and Spansion Inc. IPO. Classify as internal reorganization, not a shell cascade.

5. Pre-litigation transfer — UNCLEAR. Google Patents flags this family as having litigation ("First worldwide family litigation filed", family ID 22577486, https://patents.darts-ip.com/?family=22577486). I could not identify the specific case or patent-in-suit. The one date that would fit a pre-litigation pattern — the 2015‑06‑26 Spansion LLC → Cypress transfer — follows, rather than precedes, the Spansion litigation era (Spansion v. Samsung, ITC Inv. No. 337‑TA‑664, filed Nov 2008; Macronix/Spansion disputes 2014–2015), and the patent expired 2015‑10‑27, four months after that transfer. No 6‑month pre-suit transfer is evidenced.

6. Bankruptcy fire-sale — PARTIAL. Spansion, Inc. did file Chapter 11 (2009) and emerged May 2010 — a genuine bankruptcy event at the assignee level. But no sale of this patent in the proceedings is recorded. The only related filings are the Barclays security agreement (2010‑06‑04, entry 4) and the Barclays release (2015‑03‑13, entry 5), i.e. collateral, not asset disposition. The patent stayed in the Spansion entity and was later rolled into Cypress. So: bankruptcy at the entity, no fire-sale of this asset.

7. Privateering — NOT PRESENT. No operating-company-to-NPE transfer exists in the record. The 2015 transaction moved the patent from one operating semiconductor maker (Spansion LLC) to another (Cypress), both of which make products reading on the claims.

8. Defensive aggregator — NOT PRESENT. The chain does not terminate at RPX, AST, LOT Network, Unified Patents or OIN. It terminates at Cypress Semiconductor Corporation (now itself owned by Infineon Technologies following the April 2020 Cypress acquisition; note the change of control is not reflected as a '601-specific assignment in this record, and the patent had already expired by then).

Verdict

Operating-company assertion.

The entire recorded chain consists of operating semiconductor manufacturers: inventors Cleveland and Hollmer assigned to Advanced Micro Devices, Inc. on the filing date 1993‑12‑01; AMD recorded the patent out to Spansion Inc. (2007‑03‑19) and then to Spansion LLC (2007‑03‑26) as part of the documented AMD/Fujitsu flash spin-off; and Spansion LLC assigned to Cypress Semiconductor Corporation (recorded 2015‑06‑26) following the March 2015 merger. The only other recorded instruments are security agreements, not title transfers — Barclays Bank PLC (recorded 2010‑06‑04) and Morgan Stanley Senior Funding, Inc. (recorded 2015‑03‑21, corrected 2020‑11‑03 at reel 035240/0429), the former released on 2015‑03‑13. There is no NPE, no shell LLC, no licensing-only vehicle, and no defensive aggregator anywhere in the chain; the Google Patents family-level litigation flag is consistent with Spansion's own aggressive enforcement posture as an operating company, though I could not tie the '601 patent itself to a named suit. Note for completeness that the patent expired 2015‑10‑27 (17 years from issue), so it is unassertable today regardless of ownership.

Verify at: https://assignmentcenter.uspto.gov/ (query "5828601") and https://assignment.uspto.gov/patent/index.html — these will supply the reel/frame and correspondent fields that this analysis flags as missing.

I'll verify the patent against the USPTO record and examine each cited reference. Let me run targeted searches.

Let me pull details on the remaining cited references.

Prior-Art Analysis — US 5,828,601 ("Programmed Reference")

1. Patent identification (literal)

The number 5828601 resolves to:

I searched only for the literal string 5828601. No similar-numbered document (e.g., the AU application number AU 5828601, or the unrelated "5828601" corporate/FCC hits flagged in the earlier section) is treated here as this patent. The record above is confirmed as US 5,828,601.

2. Scope and method — read this before the analysis

The prior art below is the examiner-cited reference list printed on the face of the patent ("Patent Citations (11)"). That face list is the authoritative set of what the examiner considered. I retrieved the full text of the key references (US 5,386,388; US 5,218,569; US 4,449,203; US 4,495,602; WO 90/12400 bibliographic) and only bibliographic/title-level data for several others. Where I could not retrieve a reference's full disclosure, I say so explicitly and do not assert what it contains. A §102 mapping is only meaningful against the disclosure actually reached.

Also note two references expressly incorporated by reference into the '601 specification itself (US 5,218,569 / Banks, and US 4,495,602 / Sheppard, Mostek) — these are prior art by the applicant's own admission, independent of examiner citation.

3. The eleven cited references

(1) US 4,449,203 — Motorola, Inc. — "Memory with reference voltage generator"

• Filed 1981-02-25 · Issued 1984-05-15 · §102(b) (issued > 1 yr before the 1993-12-01 filing)
• Disclosure (retrieved): Four-state ROM. Reference column lines 16/17/18 are driven by reference transistors of different threshold voltages whose gates are tied to the same row-select lines as the storage transistors; three comparators compare the selected bit line against the three reference voltages and a translator outputs two bits. Array and reference transistors are the same physical size, with matched parasitic capacitance.
• Claim relevance: This is the closest cited art on claim 1/14's "same supply voltage to the gate of the array cell and the reference cell" element, because array and reference share one row-select drive. But the references carry fabricated (implanted/differing) thresholds, not floating gates storing a programmed charge, so the "floating gate which stores an electrical charge to allow a reference threshold value to be programmed" limitation of claims 1/14 is not met. → potential §102 read on claims 1, 14 and dependents 2, 3, 8, 9, 16 is arguable but incomplete; realistically a §103 reference.

(2) US 4,495,602 — Mostek Corporation (inv. Douglas P. Sheppard) — "Multi-bit read only memory circuit"

• Filed 1981-12-28 · Issued 1985-01-22 · §102(b) · also incorporated by reference in the '601 spec
• Disclosure (retrieved): ROM with per-column sets of reference transistors having different predetermined threshold voltages; a single word-line drive is applied concurrently to the selected storage transistor and the reference transistors; comparators/latches decode relative turn-on times into multi-bit data.
• Claim relevance: Same profile as ref. (1) — strong teaching of shared gate drive + comparator (claims 1, 14), but references are mask/fabricated-threshold devices, not programmed floating-gate references. Likely §103, not clean §102.

(3) US 4,811,291 — Thomson Composants Militaires et Spatiaux — "Safety device for electrically programmable read-only memory"

• Filed 1986-05-23 · Issued 1989-03-07 · §102(b)
• Disclosure not retrieved. Title/assignee indicate an EPROM programming-safety/redundancy device, not a reference-scheme teaching.
• Claim relevance: Appears unlikely to anticipate any claim; at most tangential background. I flag this as not verified, not as exonerated.

(4) WO 90/12400 — Sundisk Corporation (Mehrotra & Harari) — "Multi-state EEPROM read and write circuits and techniques"

• Priority 1989-04-13 · Published 1990-10-18 · §102(b) printed publication
• Disclosure: Read/write circuits and reference-cell techniques for multi-bit-per-cell EEPROM — i.e., plural reference levels to resolve multiple states of an EEPROM cell.
• Claim relevance (high): Directly relevant to claims 1, 4, 14 and dependents 6, 8, 9, 15, 16 (multi-state EEPROM cell read against multiple references). Cross-reference to the earlier section: this WO publication is the published counterpart of the *Harari/Mehrotra "Multi-State EEPROM Read and Write Circuits and Techniques" application — the opposing application in Interference No. 105,606 and the two Federal Circuit appeals (Harari v. Hollmer, 602 F.3d 1348; Hollmer v. Harari, 681 F.3d 1351). In other words, the examiner cited the later adverse party's own publication against the '601. The open anticipation question is whether it teaches reference cells as programmed floating gates biased at the same gate voltage as the array cell, or merely reference levels/currents.

(5) EP 0 409 697 A1 — Gemplus Card International — "MOS integrated circuit with adjustable threshold voltage"

• Priority 1989-07-20 · Published 1991-01-23 · §102(b)
• Disclosure not retrieved. Title indicates an adjustable-threshold MOS device (security/smart-card context).
• Claim relevance: Potentially relevant only to the generic "program/adjust a threshold" idea; not a reference-cell read-scheme disclosure as far as I can verify. No confident §102 mapping — flag as unverified.

(6) US 5,091,888 — Fujitsu Limited — "Semiconductor memory device"

• Filed 1989-07-13 · Issued 1992-02-25 · §102(b)
• Disclosure not retrieved. Generic title; likely background sense/reference circuitry.
• Claim relevance: Low-to-moderate; no asserted mapping absent the disclosure.

(7) US 5,119,330 — Oki Electric Industry Co., Ltd. — "Nonvolatile memory system for multiple value storing"

• Filed 1989-03-31 · Issued 1992-06-02 · §102(b)
• Disclosure: Multi-value nonvolatile memory system (multiple reference levels for multi-level sensing).
• Claim relevance: Relevant to the plural-reference-for-multi-level concept → potential §102 read on claims 1, 3, 4, 9, 14, 16; disclosure not fully retrieved, so this is a lead, not a conclusion.

(8) US 5,157,626 — NEC Corporation — "Semiconductor memory"

• Filed 1989-11-21 · Issued 1992-10-20 · §102(b)
• Disclosure not retrieved. Generic.
• Claim relevance: Low; no asserted mapping.

(9) US 5,218,569 — Gerald J. Banks — "Electrically alterable non-volatile memory with n-bits per memory cell"

• Filed 1991-02-08 · Issued 1993-06-08 · §102(a)/(e) and incorporated by reference in the '601 spec
• Disclosure (retrieved): EANVM storing Kⁿ states; Kⁿ−1 unique reference levels; comparator means per level; reference voltages generated by cells made during the same/similar process steps as the memory device; programming means + comparator means for program-verify.
• Claim relevance (high): The "n−1 references for n states" architecture maps directly onto claims 1, 4, 14 and dependents 3, 9, 16, and "references made by the same process" maps onto claim 7 (same-IC thermal tracking). Open question for anticipation: whether Banks recites the reference cells as charge-programmed floating-gate cells that are then driven by the same gate supply as the array cell. → potential §102(a)/(e) on claims 1, 3, 4, 7, 9, 14, 16, but likely stronger as §103 for the read-biasing feature.

(10) US 5,258,958 — Kabushiki Kaisha Toshiba — "Semiconductor memory device"

• Filed 1989-06-12 · Issued 1993-11-02 · §102(a)/(e) (issued ~1 month before the '601 filing)
• Disclosure not retrieved. Toshiba multi-level memory sensing family.
• Claim relevance: Potential bearing on claim 1/14 read-comparison architecture; no asserted mapping without the disclosure.

(11) US 5,386,388 — Intel Corporation — "Single cell reference scheme for flash memory sensing and program state verification"

• Filed 1990-11-30 · Issued 1995-01-31 · §102(e) (U.S. patent granted on an application filed before the '601 filing/invention)
• Disclosure (retrieved): Trimmable single-cell reference devices matched to the array memory cell; the same word-line gate potential turns on both the memory cell and the trimmable reference; currents compared through matched 1:1 resistive loads (SAR = 1), making the scheme insensitive to control-gate voltage and to temperature/process, with a third reference added for read. Explicitly framed as an improvement over non-1:1 sense-ratio referencing.
• Claim relevance (highest in the set): This reference reaches the '601's central moves — (a) identical gate voltage applied to array cell and reference cell, and (b) a threshold-set reference cell compared against the array cell — and is also close to claim 4's program-verify ecosystem and claim 14's shared-word-line architecture. Potential §102(e) mapping: claims 1, 4, 14, 15 and dependents 2, 5, 6, 8, 9, 12, 16. Caveat: Intel trims the reference threshold (device modification) rather than programming a charge-storing floating gate, and its focus is binary program/erase verification rather than n−1 read references placed between successive multi-level states. So a clean §102 anticipation is arguable; §103 is the more realistic attack.

4. Also cited/relied on in the specification

5. Ranking and the bottom line on §102

Most relevant prior art, in order:

1. US 5,386,388 (Intel) — closest to the "same supply voltage to both gates + trimmed reference + matched loads" combination (claims 1, 4, 14, 15).
2. US 5,218,569 (Banks) — closest to "n−1 references for n states" and same-process references (claims 1, 4, 7, 14).
3. WO 90/12400 (Sundisk / Mehrotra & Harari) — multi-state EEPROM read/reference circuits; the interference-linked reference (claims 1, 4, 14).
4. US 4,449,203 (Motorola) and US 4,495,602 (Mostek) — closest on shared word-line gate drive, but fabricated-threshold (non-floating-gate) references.

Honest assessment: None of the eleven cited references, on the disclosure I was able to review, appears to be a complete §102 anticipation of independent claim 1, 4, or 14, because the '601's pointed limitation is the combination of (i) a floating-gate reference cell whose threshold is programmed, (ii) placed between two successive array threshold values, and (iii) read with the identical supply voltage on both gates while both devices are identically biased. References (1), (2), and (11) teach the identical-gate-drive element but not the programmed-floating-gate reference; reference (9) and (4) teach the multi-level reference architecture but the read-biasing is not the claimed identical-drive scheme. The strongest §102 candidate is US 5,386,388 under §102(e); the strongest §103 candidates are US 5,386,388 combined with US 5,218,569 and/or WO 90/12400.

Claims 10–13 (the reference-programming apparatus and method — reference count circuit, golden bit, selectable resistor ratios, cascode preamps, sense amps) appear least anticipated by the cited set: no cited reference discloses the golden-bit-plus-resistor-ratio verify loop. The nearest are US 5,386,388 (trimming) and EP 0 409 697 (adjustable threshold), neither of which reaches that apparatus.

Explicit limitations of this analysis:

• Full disclosure text was retrieved for items 1, 2, 9, 11 (and WO 90/12400 bibliographically); items 3, 5, 6, 7, 8, 10 were assessed on the face-of-patent citation data only, and I have not asserted substantive content for them. If you need a definitive §102 statement for those, their full texts must be pulled.
• I did not retrieve independent third-party prior art (non-cited); this analysis is confined to the patent's own cited references, plus the two admissions-by-incorporation.
• Treat every "potential §102" above as a mapping to be tested, not a legal conclusion of invalidity.

I'll ground the analysis in the prior art references listed on the patent page. Let me verify the content of the key references in parallel.

Obviousness Analysis — U.S. 5,828,601 ("Programmed Reference")

Scope note. This builds on the previously generated bibliographic and litigation sections without repeating them. Because the filing date is 1993-12-01, the pre-AIA version of 35 U.S.C. § 103 governs (the AIA first-inventor-to-file provisions apply only to applications filed on or after 2013-03-16). This matters for putting the references into the right statutory pigeonholes.

A. Legal framework applied

B. Prior-art status of each reference listed on the patent page

Two references the '601 specification itself incorporates by reference are also fair game as applicant admissions about the state of the art: US 5,218,569 (Banks) and US 4,495,602 (Sheppard) — the latter listed on the front page as US4495602A (the same document; the number and the listing are consistent, not a discrepancy). The specification cites both as "typical" circuitry for the comparison and program-verify functions (col. describing FIGS. 4A and 6).

Timing flag: US5386388 is the most structurally on-point reference, but it is §102(e) art, not §102(a)/(b) art. If a court or the Office were to apply a pre-AIA §102(e)-to-§103 analysis, the reference remains combinable — this is the routine treatment in this art — but it should be identified as §102(e) rather than as a printed publication.

C. Level of ordinary skill (PHOSITA)

A person with a B.S. in electrical engineering or solid-state physics and roughly 3–5 years of experience designing non-volatile memory sense/program circuits (or equivalent). This is consistent with qualification statements used in contemporaneous flash-memory IPR petitions (e.g., the expert declaration filed in IPR2016-00320 concerning U.S. 6,169,503, which describes a comparable "bachelor's degree in electrical engineering and several years of flash memory circuit design" baseline). Someone at this level in 1993 had available the full multi-state EEPROM literature — Sundisk, Intel, Toshiba, Oki, NEC, Motorola and Banks were all publishing in the same space at the same time.

D. What the cited art actually teaches

Group 1 — Multi-state cells read against reference devices driven by the same word line

• Sheppard / US4495602 (Mostek, §102(b)): a memory transistor "fabricated to have one of a plurality of threshold voltages with each threshold voltage corresponding to a data state," plus "a plurality of reference transistors with each reference transistor having a separate threshold voltage." Critically, the abstract states: "The drive signals are applied through the word lines concurrently to the selected memory transistor and corresponding reference transistors to cause the transistors to transition from a first state to a second state," and decoding determines the data state from the transition order. This is, element-for-element, claim 1's "power supply supplying the supply voltage to the gate of the array cell … and … to the gate of the programmable reference cell."
• US4449203 (Motorola) and US5119330 (Oki): multi-level ROM/EEPROM sensing with reference-level generation.

Group 2 — Programmable reference cells that track the array cell (the core idea of the '601)

• Sundisk / WO1990012400 (§102(b)) — the strongest reference. Its stated objects include "memory read and program techniques that automatically compensate for effects of temperature, voltage and process variations." It teaches "master reference cells" that are "independently and externally programmable, either by the memory manufacturer or the user," set to "breakpoint thresholds … within the threshold window," and—expressly—that "by virtue of being an identical device as that of the memory cells, the reference cells closely track the same variations due to manufacturing processes, operating conditions and device aging." The EP family member (EP0539358A1) claim 20 recites master reference cells, means for programming group reference cells to the levels of the master reference cells, and reading by comparison with the group reference cells. That is the '601's "program reference cells set the read reference cells, which then read the array."
• US5386388 (Intel) — reference cells with preset threshold potentials coupled to the same word line as the memory cell, generating a read reference current and separate verify reference currents, plus "switching means" to couple the read reference during reading and the verify reference during program verification. Claim 1 of '388 recites: "first circuit means … coupled to said word line of said one memory cell and having a first threshold potential … such that a first gate potential applied to said word line causes said first circuit means to generate said first reference current and causes said one memory cell to generate a memory cell current." This is claim 14 of the '601 almost verbatim, plus claim 15's separate verify references.
• US5218569 (Banks) — floating-gate cells electrically programmed to Kⁿ thresholds; "Kn-1 unique reference levels and comparator means which comprise Kn-1 comparators"; and a program/verify loop in which "the input data is used to select one of the three reference levels. A series of program/verify cycles are executed until the cell being programmed has been verified against the selected verify reference voltage."

Group 3 — Program-verify and bias-gate techniques admitted as known by the '601 itself

• The '601 background describes the bias-gate method (FIG. 3; resistor divider 302/304 on the reference gate) as "another traditional referencing scheme." The reference bias circuit 610 of the '601 is simply that admitted technique applied to a "golden bit."
• The '601 specification states outright that "typical circuitry for an array cell program-verify circuit 504 … is shown and described in U.S. Pat. No. 5,218,569 by Banks," and that "traditional circuitry for programming a single floating gate memory cell can be utilized to provide the program-verify signal circuitry 602."

E. Independent claims

Claim 1 — basic read architecture

Primary combination: Sundisk WO'400 + Intel US5386388 + Sheppard US4495602.

Motivation. All three are in the same field and address the same problem the '601 recites — reference drift with Vcc, temperature and process in a shrinking read margin. Sundisk supplies the express motivation ("automatically compensate for effects of temperature, voltage and process variations"; "improved read circuits … simpler, easier to manufacture and have improved accuracy"). Sheppard and Intel supply the mechanism: drive array cell and reference from the same word line so the gate-bias term cancels in the comparison. A PHOSITA reading the '601's own background (which complains that sense-ratio and bias-gate schemes drift because of resistor and Vcc variation) would have immediately recognized that removing the resistor divider from the read path — i.e., biasing both gates identically, as Intel and Sheppard already did — eliminates exactly the error source identified. Under KSR, "if a technique has been used to improve one device, and a person of ordinary skill would recognize that it would improve similar devices in the same way, using the technique is obvious."

Note on breadth: claim 1 does not require n > 2 (that is dependent claim 3), so with n = 2 it reads on the ordinary single-midpoint-reference flash cell — the precise scheme of Intel '388. Claim 1 is thus the most exposed claim in the patent.

Claim 4 — full program/verify ecosystem

Motivation. Sundisk explicitly teaches the two-tier reference architecture (master references that are set once, local references programmed from them) for the stated purpose of tracking cell aging and process variation. Intel '388 teaches splitting the reference set into a read reference and a program-verify reference, selected by a switch. Banks '569 teaches the incremental program/verify loop against a selected reference level. Combining these yields claim 4's architecture with the predictable benefit each reference already provides. The '601 specification's own admissions make this combination essentially a recitation of the art it builds on.

Claim 10 — reference-programming apparatus

The claim is a collection of standard blocks: a reference count circuit (COL/ROW sequencing), a program-verify signal circuit (VPROG/VPX/VERIFY), a sense bias circuit, a data buffer reference circuit, a golden bit cell, a reference bias circuit with plural resistor ratios, and a comparator.

• Sequential selection by row/column decode is the ordinary addressing machinery of every EPROM/ROM of the era — Sheppard '602 shows exactly this with column-decode signals CD1–CD4 and word line 30.
• The "golden bit + resistor ratios on its gate" is the admitted bias-gate method (the '601 background's FIG. 3), merely relocated from the read path to a one-time test-time programming path. The '601's own FIG. 12 description confirms this is a resistor divider (resistors 1221–1225) switched by the column signal.
• Program/verify signal generation and sequencing is Banks '569's program/verify timing circuit, which the '601 admits is "traditional."

Motivation / KSR. "[A] combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results." Each block here performs precisely its known function: the counter counts, the decoder decodes, the buffer drives the bit line, the comparator compares. The only asserted benefit (setting references precisely at test time under tight tolerances) is achieved by using the admitted bias-gate technique for its known purpose. Claim 10 is a strong candidate for §103 rejection over Intel '388 + Banks '569 + Sheppard '602 + applicant-admitted bias-gate art, particularly because claim 10's own recitation of the golden bit and resistor ratios tracks the '601's admission of prior art.

Claim 13 — six-step programming method

Steps (a)–(f) are: select cell/ratio; couple ratio to golden gate; program; verify against golden bit through the ratio; loop; advance.

• Programming reference cells one at a time with a program/verify loop is Banks '569 and Intel '388.
• Applying a fixed gate-voltage offset via a resistor ratio to reproduce a target threshold current is the bias-gate method, described in the '601 background as "another traditional referencing scheme."
• Sequentially marching through multiple references, each with its own ratio, is conventional test-time trimming.

Motivation. The specification itself states the rationale: "This method utilizes the fact that the golden bit will be saturated according to … I_D = K(V_GS − V_t)², so that reducing the gate voltage V_GS by a fixed amount using a resister ratio will provide the same current as a reference cell that has been programmed to a desired threshold value." That is an express design rationale that a PHOSITA could have derived from the known bias-gate technique; it is a predictable, mechanical application of the known method to a new number of reference levels. (Note also the minor literal defects in the printed claims elsewhere: claim 12 recites "a first sense amplifier voltage voltage" and "second sense amplifier voltage voltage," preserved as printed.)

Claims 14 and 15 — word-line architecture

• Claim 14 requires a first word line, a second word line, one power supply giving a "substantially identical supply voltage" to both, the array cell's gate on the first, n−1 reference cells' gates on the second (each programmed between two different successive array thresholds), and read sense amplifiers comparing source-drain paths. Intel '388 discloses reference cells coupled to the same word line as the memory cell, and Sheppard '602 discloses concurrent identical word-line drive to memory and reference transistors. Either alone or in combination reads on this claim.
• Claim 15 adds n verify reference cells on the same second word line, one per array threshold, plus verify sense amplifiers. Intel '388 discloses precisely this read/verify split with switching means, and Banks '569 discloses verify reference levels selected according to the data to be programmed.

Motivation. Avoiding the sense-ratio/bias-gate read error is the stated goal of both Sundisk and the '601; identical word-line drive is the mechanism both Intel and Sheppard already use. The combination is a substitution of one known reference-biasing technique for another, with a predictable improvement in margin stability.

F. Consolidated motivations to combine (answer to the §103 "why")

1. Same field, same problem, same solution space. Every reference is a multi-state/flash EEPROM or multi-bit ROM sense or program circuit. The problem (shrinking read margin with density and Vcc) is expressly identified in Sundisk and in the '601's own background.
2. Express statement of purpose in the prior art. Sundisk's objects — "automatically compensate for effects of temperature, voltage and process variations" and "improved read circuits which are simpler, easier to manufacture and have improved accuracy" — supply the motivation directly for removing resistor ratios from the read path and biasing reference and array cells identically.
3. Matched devices are the recognized way to cancel process/temperature. Sundisk ("identical device as that of the memory cells, the reference cells closely track the same variations"), Banks ("stable reference voltages are generated by way of cells made during the same (or similar) process steps as the memory device"), and Intel ("incorporated on said substrate") all teach it — supporting dependent claim 7 as well.
4. The remaining piece is admitted prior art. The bias-gate programming technique and the program-verify loop the '601 relies on are described in the '601 itself as "traditional" and are attributed to Banks.
5. Predictable results / no unexpected mechanism. The '601 claims no surprising behavior; its asserted benefit (a working margin that stays constant as Vcc varies) is the arithmetic consequence of driving two matched floating-gate devices from the same supply and comparing their drain currents.

Corroboration that "matched reference cell" was a standard technique: the '601's own forward-citation list is full of later patents framed around this exact concept — e.g., Saifun's "Reading array cell with matched reference cell" (US 2005/0057953 A1) and "Operating array cells with matched reference cells" (US 7,457,183 B2), and SanDisk's "Writable tracking cells" (US 6,538,922 B1) and "Error management for writable tracking storage units" (US 6,678,192 B2). The fact that the industry subsequently treated "matched"/"tracking" reference cells as an off-the-shelf design choice is KSR-style evidence that the '601's core move was within ordinary skill.

G. Dependent claims

H. The applicant's best counter-arguments, and why they are likely to fail

Under the KSR "predictable results" rubric, the strongest non-obviousness story the '601 could tell is that no single reference discloses the complete combination — a programmable floating-gate reference (not an implant-programmed ROM reference as in Sheppard), deliberately placed between data states, plus identical gate drive, plus the golden-bit verification architecture. That is a genuine "no single reference" argument, but it is a §103 argument that in this case the art defeats:

• Sundisk supplies the programmable, between-states reference cell and the tracking rationale — it is not an implant-programmed ROM reference.
• Intel '388 supplies the identical-word-line reference architecture and the read/verify reference split on the same device.
• Banks supplies the program/verify-against-a-selected-reference loop, which the '601 admits is conventional.
• The bias-gate/"golden bit" scheme is admitted prior art in the '601's own background; the specification's own reasoning for why it works (the square-law saturation relation) is arithmetic any PHOSITA could apply.

Any argument that the combination is "too many references" is weakened by the fact that all four are in the same art, address the identical problem, and are cited on the '601's own face or admitted in its specification.

I. Secondary considerations

• No unexpected results. The claimed advantages (constant margin; tracking process/temperature) are the expected consequence of matched devices and identical bias — the opposite of a "results unexpected in view of the prior art" showing.
• No nexus. Multi-state flash was an industry-wide commercial trend in the early 1990s (Sundisk, Intel, Toshiba, Oki, NEC, AMD). Any commercial success of AMD/Spansion multi-density parts is attributable to market demand for higher density, not to the specific claim elements; absent proof tying success to the claimed combination, no nexus exists.
• No evidence in the record of licensing-based or industry-praise secondary indicia.
• Simultaneous independent solutions (Sundisk 1990; Intel 1992; the '601 filed 1993) cut against non-obviousness by showing the problem was recognized and being solved by ordinary skill at the time.

J. Confidence and caveats

• High confidence: the content of WO1990012400/Sundisk, US5386388/Intel, US5218569/Banks and US4495602/Sheppard, all of which I verified against available full text (URLs below). The claim-element mapping in §§E–G follows the printed claim language of the '601.
• Moderate confidence: the precise content of the more peripheral citations (US4449203, US4811291, EP0409697, US5091888, US5119330, US5157626, US5258958). These corroborate the state of the art (multi-level reference sensing, reference-voltage generation) but I did not pull each full text; they are supporting references rather than the hinges of the combinations.
• Timing nuance: US5386388 is §102(e)(2) art (U.S. application filed 1992-12-30, issued 1995-01-31), not a §102(b) printed publication. This does not remove it from a §103 combination but should be characterized correctly.
• Interference context (not repeated here): the previously generated litigation section identified BPAI Interference No. 105,606 between Harari/Mehrotra and Hollmer/Cleveland and the related Federal Circuit appeals. Two of the most damaging references here — WO1990012400 and US5218569 — belong to that same Sundisk/Harari line of work and to Banks, respectively. I note the overlap as an observation about the art, not as a legal conclusion about the interference.
• I am not asserting a validity or invalidity holding. This is a prior-art-based obviousness analysis using the references the patent page itself lists, per the task instruction. A definitive determination would require full claim construction, the complete texts of every reference, and any prosecution-history estoppel.

Sources relied on:

• https://patents.google.com/patent/[US5828601](/patent/US5828601)/en (the patent)
• https://patents.google.com/patent/WO1990012400A1/en and https://patentimages.storage.googleapis.com/9a/26/87/fdcc5f5d2d72eb/WO1990012400A1.pdf (Sundisk)
• https://www.freepatentsonline.com/[5386388](/patent/5386388).html (Intel)
• https://patents.google.com/patent/US5218569 and https://uspto.report/patent/grant/5218569 (Banks)
• https://patents.google.com/patent/US4495602 and https://patentimages.storage.googleapis.com/2f/68/8c/22f704c31594ee/US4495602.pdf (Sheppard)
• https://www.usitc.gov/intellectual_property/documents/pub3046.pdf (Sundisk multi-state reference-cell context, discussed in a different patent's investigation)
• https://cmosedu.com/jbaker/expert_witness/2015/IPR2016_00320.pdf (contemporaneous PHOSITA qualification statement in a flash-memory IPR)