Invalidity dossier
US 6044019
Non-volatile memory with improved sensing and method therefor
Current assignee: SanDisk Technologies LLC
Added 9/23/2026, 8:02:44 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 6,044,019 A
Title: Non-volatile memory with improved sensing and method therefor
Source: https://patents.google.com/patent/US6044019/en
Bibliographic facts from the supplied record: Application US09/177,809; filed 1998-10-23; priority date 1998-10-23; granted/publication date 2000-03-28; legal status listed as "Expired – Lifetime" with anticipated expiration 2018-10-23. Original assignee SanDisk Corp; current assignee listed as SanDisk Technologies LLC. Named inventors: Raul-Adrian Cernea, Rushyah Tang, Douglas Lee, Chi-Ming Wang, Daniel Guterman.
Purpose: The invention "relates generally to floating gate semiconductor memories such as electrically erasable programmable read-only memories (EEPROM) and flash EEPROM, and specifically to circuits and techniques for reading or sensing their memory states."
Plain-language scope (per the excerpt): The patent addresses reading non-volatile memory cells by sensing conduction current. Cells are programmed by successive voltage pulses that add incremental charge to the floating gate; between pulses the cell is read back ("verified") to compare its source-drain current against a breakpoint level, and programming stops once the cell is verified in the desired region of the partitioned conduction window. A reference current source, which "may be externally programmable," provides that breakpoint current I_ref. Memory states may be two-state (one bit per cell) or partitioned into more than two regions for multi-state/multi-level storage, increasing the information an array can store—such multi-state EEPROM/flash EEPROM being described in U.S. Pat. No. 5,172,338. The excerpt summarizes general array structure (FIG. 1 bit lines, word lines, source/drain/control/floating gates), addressing via row and column decoders, and a read circuit (FIG. 2). Classifications include G11C16/28 (differential sensing/reference cells) and G11C11/5642 (sensing or reading circuits for multi-state floating-gate storage).
What the excerpt does not establish: It is explicitly an excerpt; the detailed "improved sensing" circuit specifics and all claim language are not included, so the claimed scope cannot be stated. The excerpt also does not establish the full specification, figure contents, or the nature of the "improvement" over prior-art sensing.
I have not researched litigation, ownership history, validity, or prior art, per your instructions.
Generated 10/1/2026, 9:41:39 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
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