US 6786575

US Patent 6,786,575 (US6786575B2) — Summary

Verified bibliographic data (confirmed by the Google Patents record provided, plus USPTO-format front-page data from the Indiana University/USPTO OG archive, FreePatentsOnline, and PubChem):

Abstract (verbatim):

An ink jet heater chip having improved thermal. The chip includes a semiconductor substrate, a first metal resistive, a second metal conductive layer on a first portion of the resistive layer and on a second portion of the resistive layer defining a heater resistor element. A passivation layer having a thickness defined by a deposition process is deposited on the second metal conductive layer and heater resistor element. A cavitation layer is deposited on the passivation layer and etched. A dielectric layer is deposited and etched to provide a dielectric layer overlying the first portion of the resistive layer. An electrical conduit via is etched in the dielectric layer. A third metal conductive layer is deposited in the via for electrical contact with the second metal conductive layer. Separately deposited dielectric and passivation layers enable independent control of the thickness of the dielectric and passivation layers.

Note: The published abstract as printed begins "having improved thermal." (incomplete sentence — a known typographical error in the record). I have reproduced it literally rather than "correcting" it.

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Plain-language overview of the claims

There are 6 claims; only claim 1 is independent. Claims 2–6 depend from claim 1. (I have preserved the claim text literally, including the apparent typographical errors in the issued record, e.g., "poriton," "matal," "renging," "deposited and etch.")

Claim 1 (independent — the chip itself): A thermal ink-jet heater chip with improved thermal efficiency, built up as a layered stack on a semiconductor substrate:

• a first metal resistive layer on the substrate;
• a second metal conductive layer patterned onto two spaced-apart portions of the resistive layer (a "first portion" and a "second portion"), so the exposed resistive material between them forms the heater resistor element;
• a passivation layer over the conductive metal and the heater resistor element whose thickness is set by deposition alone (no thickness-reducing etch over the resistor) — and the passivation layer is removed/absent from the second metal conductor that sits over the first portion of the resistive layer;
• a cavitation layer (etch-patterned) over the passivation layer above the heater resistor element — likewise absent over the first-portion conductor;
• a dielectric layer (separately deposited and etched) of a second, independently controlled thickness over the first portion of the resistive layer;
• an electrical via etched through that dielectric layer; and
• a third metal conductive layer deposited on the dielectric layer and into the via to make electrical contact down to the second metal conductive layer.

In plain terms: by splitting the former single thick passivation/inter-metal-dielectric stack into (i) a thin, deposition-only passivation layer over the heater (less thermal barrier → ~20% lower heater energy) and (ii) a separate thick dielectric layer located only where inter-conductor insulation is needed (away from the resistor), the chip gets good insulation between metal layers without sacrificing thermal efficiency of the resistor.

Claim 2: The passivation layer is a silicon carbide (SiC) + silicon nitride (Si₃N₄) combination, total thickness about 3,100–4,500 Å.

Claim 3: The cavitation layer is tantalum, about 4,000–6,000 Å thick.

Claim 4: The semiconductor substrate additionally contains NMOS or CMOS transistors (drive circuitry integrated on-chip).

Claim 5: The inter-metal dielectric layer is a stack of silicon oxide / phosphorus-doped spin-on-glass (PSOG) / silicon oxide with a combined thickness of about 7,900–11,700 Å.

Claim 6: An ink-jet printhead that incorporates the heater chip of claim 1.

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CAFC 2026 docket search — results and uncertainty

I searched for CAFC 2026 docket activity tied specifically to 6786575. I could not confirm any specific Federal Circuit appeal for this exact patent number.

What the searches did surface (as of the search date) is closely related but not number-specific:

• Law360 (Jul. 16, 2026): "The Federal Circuit on Thursday upheld the PTAB's decisions to invalidate all claims Canon had challenged in three Slingshot Printing patents covering chips and temperature sensors in inkjet printers."
• IPWatchdog (2026): "CAFC Affirms Two PTAB Obviousness Rulings in Canon Printhead Patent Disputes" — final written decisions finding claims of three patents owned by Slingshot Printing LLC unpatentable as obvious, following Canon IPRs.
• Law360 (Jul. 21, 2026): The Federal Circuit "declined to reboot claims in a Slingshot Printing patent covering a printhead for an inkjet printer challenged by Canon," less than a week after the three-patent affirmance.

Caveat: None of these summaries identified the challenged patent numbers. Given that 6786575 is Slingshot-owned, expired (2022), and in the thermal-inkjet-printhead space, it may be among the patents at issue in these Canon IPR/CAFC matters — but I have no authoritative confirmation that 6786575 specifically is in any 2026 CAFC docket. I could not retrieve the underlying CAFC docket numbers (e.g., appeal Nos. 2025-xxxx) in the searches performed.

Other litigation note (from the Google Patents record itself): the patent's family page flags a district-court case, Texas Western District Court, 6:19-cv-00549 (Slingshot Printing litigation), with the litigation date marked "Critical." That is a district-court case, not a CAFC 2026 docket.

Bottom line: If you need a definitive CAFC 2026 docket tie to 6786575, the available search results do not support one with certainty — I would recommend a direct check of the CAFC docket database (PACER/CM/ECF) or the PTAB's IPR trial listings to map the specific patent numbers in Slingshot Printing LLC v. Canon before relying on any connection.

Known Litigation Involving U.S. Patent No. 6,786,575 (US6786575B2)

Based on the searches, there is one identified U.S. district court case in which US 6,786,575 was asserted, plus related PTAB (IPR) activity that ended in settlement. I could not verify any other district-court case naming this specific patent (e.g., the Slingshot v. Canon cases in E.D.N.Y. and the 2026 CAFC appeals involved other Slingshot portfolio patents such as 7,195,341, 7,290,864, 7,484,823, and 7,594,708 — not 6,786,575).

District Court Case

Slingshot Printing LLC v. HP Inc.

• Plaintiff: Slingshot Printing LLC (Delaware LLC, Silver Spring, MD)
• Defendant: HP Inc.
• Jurisdiction: [U.S. District Court for the Western District of Texas, Waco Division](/courts/western-district-of-texas-waco) (Judge Alan D. Albright), later transferred/reassigned to the Austin Division
• Case No.: 6:19-cv-00549-ADA (W.D. Tex.); subsequent Austin Division docket references identify the transferred case as 1:20-cv-00187-ADA (W.D. Tex.)
• Filing date: September 20, 2019
• Patents asserted: The complaint asserted ten patents, including 6,786,575 (along with 6,213,587; 6,575,563; 6,676,246; 7,018,012; 7,195,341; 7,290,864; 7,410,246; 7,484,823; and 7,559,629)
• Status / Outcome: The case was transferred from Waco to Austin (a docket entry states "Case transferred to Austin. No further filings allowed in Waco case"). HP petitioned for inter partes review of several Slingshot patents. In March 2021, HP and Slingshot filed joint motions to terminate the related IPRs (e.g., IPR2020-01084, IPR2020-01086, IPR2020-01659) stating that "the parties have settled their dispute and executed a settlement agreement" (IPR terminations entered around March 29, 2021, with a refund notice in May 2021). The district court litigation was therefore resolved by settlement (~March–April 2021). I could not retrieve the final dismissal order from the docket in my searches, so I cannot confirm the precise dismissal language or date with certainty.

Related PTAB Proceedings (context)

• HP Inc. filed IPRs against Slingshot Printing LLC (e.g., IPR2020-01084, -01085, -01086, -01090; IPR2020-01659) covering Slingshot's inkjet-printhead patent portfolio. These were terminated after the parties' settlement. Note: the specific IPRs I was able to inspect identified other patents (e.g., 6,394,593 in IPR2020-01084); I did not confirm an IPR petition specifically challenging 6,786,575.

Caveats / Confidence

• The primary source identifying this litigation is the Google Patents "litigation" flag for US6786575, which points to W.D. Tex. case 6:19-cv-00549, consistent with the complaint I located (DocketAlarm / RPX / UniCourt / Justia).
• The exact relationship between docket numbers 6:19-cv-00549, 1:20-cv-00184, and 1:20-cv-00187 is not fully clear from my search results; 1:20-cv-00187-ADA appears to be the Austin Division renumbering of the transferred Waco case, while 1:20-cv-00184 is a separate W.D. Tex. Slingshot v. HP docket that I could not confirm asserted 6,786,575.
• I was unable to complete a PACER/CAFC/Unified Patents portal check of every docket entry within the tool-call limit, so there may be additional filings (e.g., later dismissals, appeals) not captured here. No CAFC appeal specifically involving 6,786,575 surfaced in my searches.

If you need the exact final judgment/termination order in 6:19-cv-00549 / 1:20-cv-00187, PACER (W.D. Tex.) or the Unified Patents litigation portal would be the next step.

Proceedings overview

Zero AIA trial proceedings exist on US 6786575. The USPTO Open Data Portal returns no IPR/PGR/CBM proceedings for this patent as of the most recent ingest, and web searching surfaced no PTAB petition (instituted or denied), no Final Written Decision, and no settlement targeting U.S. Patent No. 6,786,575 specifically. The defensive posture is therefore simple but decisive for a different reason: this patent expired on 2022-12-17 (20 years from its 2002-12-17 filing, per the "Expired – Lifetime" status on the USPTO/Google Patents record). No PTAB proceeding was ever needed or brought, and no claim of this patent has ever been canceled, sustained, or tested in an AIA trial.

The closest PTAB activity sits in the same Slingshot/Lexmark/Funai printhead family — but on different patents — and must not be confused with a challenge to 6,786,575:

• Canon U.S.A., Inc. / Canon Inc. v. Slingshot Printing LLC — IPRs on sibling heater-chip patents 7,290,864 (e.g., IPR2023-00309), 7,484,823, and 7,594,708, with PTAB obviousness FWDs affirmed by the Federal Circuit on 2026-07-16 (Slingshot Printing LLC v. Canon U.S.A., Inc., Nos. 2025-1032 et seq.; Chen, Hughes, Cunningham). Another related Canon-v.-Slingshot appeal was decided around 2026-07-21.
• HP Inc. v. Slingshot Printing LLC — a batch of 2020 IPRs (e.g., IPR2020-01085 against 6,243,115; IPR2020-01086 against 7,014,299; IPR2020-01090 against 7,244,015; IPR2020-01659 against 7,410,246) that were terminated-settled on 2021-03-29, following settlement of Slingshot v. HP Inc., No. 6:19-cv-00549 (W.D. Tex.), the very case in which 6,786,575 was one of ten patents-in-suit.
• 6,786,575 was asserted in that W.D. Tex. litigation (and is flagged in the Google Patents litigation metadata for 6:19-cv-00549), but no IPR petition against 6,786,575 has been located in ODP or web sources.

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PTAB activity on US 6,786,575 — none on file

No proceedings to report

• Type: n/a (no Inter Partes Review, Post-Grant Review, or Covered Business Method review filed)
• Filed: n/a
• Status: No PTAB proceeding of any kind — no institution decisions, no Final Written Decisions, no settlements, no appeals — exists for this patent number.
• Judge panel: n/a
• Petition grounds: n/a
• Institution decision: n/a
• Final Written Decision: n/a
• Settlement / termination: n/a
• Appeal: n/a
• Defensive value: The absence of PTAB challenges is not the operative defense. The operative fact is that the patent is expired (anticipated expiration 2022-12-17; last maintenance fee paid 2016-02-24, 12th year). If you are being accused today, the accuser can seek damages only for infringing acts before 2022-12-17 (and, under 35 U.S.C. § 286, only for acts within six years before the complaint), and cannot seek any prospective or injunctive relief. Any demand letter implying ongoing liability post-expiry is overreaching.

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Strategic summary

Claims status. All six claims of US 6,786,575 (claims 1–6: claim 1 independent, claims 2–6 dependent, claim 6 an ink-jet printhead claim) remain exactly as granted — none CANCELED, none SUSTAINED by a PTAB merits decision, none UNTESTED in the sense that matters. The claims were never run through an AIA trial because no petition was ever filed. Note that the claim set is largely directed to a passivation-layer/dielectric-layer heater-stack architecture (separately deposited passivation and inter-metal dielectric, cavitation layer, via, third metal conductor), which is a different technical target than the bondpad-array and thermal-sensor claims of the sibling patents that Canon did successfully attack. Do not assume the Canon wins on 7,290,864 / 7,484,823 / 7,594,708 transfer to this patent — they are different claims and different prior-art records.

Estoppel landscape. § 315(e)(2) estoppel is a non-issue here because there is no IPR by any petitioner against this patent. Critically, the Canon IPRs and HP IPRs were brought against different patents, so Canon and HP are not estopped as to this patent's claims. However, the practical point is that 6,786,575 expired before any new IPR petition could realistically be filed (petitions against expired patents generally require the petitioner to have been sued or to otherwise have standing, and here any damages exposure ended 2022-12-17). If you are a defendant and want a validity lever, § 282(b) invalidity defenses in district court — using the same Canon/HP art families (e.g., Benjamin, Giere, Parish, Uenishi, Hayasaki references, among others) — remain fully available; there is no IPR estoppel bar because no IPR was brought on this patent.

Pattern signals. The portfolio-level pattern is unmistakable: Slingshot (formerly Lexmark/Funai printhead IP) asserted a ten-patent basket against HP in W.D. Tex. (6:19-cv-00549) and separately sued Canon in E.D.N.Y. HP's response was a wave of 2020 IPRs that settled in March 2021 (joint termination, settlement treated as business confidential). Canon's response was a wave of IPRs that went the distance and won, with Federal Circuit affirmance in July 2026. This patent — despite being asserted against HP — was evidently not among the patents HP chose to petition, and Canon never targeted it either. That is a meaningful signal: after years of aggressive family-wide assertion and multiple IPR waves against sibling patents, no petitioner saw 6,786,575 as worth the fight — consistent with its narrow heater-stack claim scope and its early (2022) expiry.

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Recommended next steps

1. Lead with expiry, not PTAB history. There is no FWD to link because none exists. Instead, cite the USPTO assignment/status record showing "Expired – Lifetime" with anticipated expiration 2022-12-17 (https://patents.google.com/patent/US6786575/en). In any negotiation or motion, demand that the accuser identify pre-2022-12-17 infringing acts within the § 286 six-year window — anything else is not actionable.
2. Do not let the accuser trade on the Canon wins. The 2026-07-16 Federal Circuit affirmance in Slingshot v. Canon (Nos. 2025-1032 et seq.; opinions at the Federal Circuit / CourtListener) invalidated claims of 7,290,864, 7,484,823, and 7,594,708 — not 6,786,575. If a demand letter cites this patent alongside those, the invalidation of the siblings actually weakens the portfolio narrative, but you must still address this patent's claims on their own merits.
3. If validity becomes necessary, the art is already assembled. Because no IPR was filed on this patent, there is no estoppel and you may use any § 102/§ 103 grounds in district court. The public Canon IPR records (IPR2023-00309 and related, via PTAB E2E / PTACTS) and HP's 2020 IPR exhibits identify the heater-chip prior art (Benjamin, Giere, Parish, Uenishi, Hayasaki families, plus the 14 references cited during original prosecution, e.g., US 6,331,049 "Printhead having varied thickness passivation layer," US 5,844,586, US 6,120,135). A § 101/§ 112 or § 103 defense can be built from those references without any PTAB filing.
4. Confirm the record yourself before relying on it. The ODP canonical data shows zero proceedings, and I found no web evidence of a petition against this patent — but if you are in active litigation, run a PTAB E2E and USPTO Patent Center check under the patent number to confirm no petition was filed under a continuation/child number (the family includes continuation US 6,951,384, which is also expired). If anything new has been docketed after the most recent ODP ingest, it would not appear in the canonical block above.

Bottom line: There are no PTAB proceedings on US 6,786,575 — not because the claims were validated, but because no one ever bothered to challenge a patent that expired on 2022-12-17. The practical defense is expiry plus the § 286 damages bar, with a clean slate for district-court invalidity arguments if the accuser tries to reach back before expiration.

I'll research the ownership chain for US 6786575, cross-referencing the recorded assignments with litigation and asserter data.

I have the litigation picture. Now let me pull the USPTO assignment records with correspondent details and research Slingshot's asserter profile.

The litigation and RPX/Unified classification data are coming together. Now let me try to pull correspondent details from the specific USPTO reel/frame records.

I've reached my search limit, but I have sufficient verified data from the Google Patents legal-event feed (which mirrors USPTO assignment records), the complaint docket, and RPX/Unified Patents classifications to complete the analysis. One important data limitation up front: correspondent-of-record names are not exposed in the Google Patents assignment mirror, and my session's searches could not reach the USPTO Assignment Center's interactive records, so the correspondent field below is marked not-retrievable rather than guessed.

Inventors

• Frank Edward Anderson — employer at filing: Lexmark International, Inc. (he assigned his rights to Lexmark on the original assignment, reel 013597/0494, executed 2002-12-16).
• George Keith Parish — employer at filing: Lexmark International, Inc. (same original assignment, reel 013597/0494). Note: the USPTO record misspells his middle name "GEROGE" in the assignor block.

No evidence of any unusual post-filing inventor exodus; both appear to be Lexmark Lexington-area inkjet engineers, and the patent remained with Lexmark for a decade before the portfolio sale. (Departure patterns are not determinable from the assignment records alone.)

Original assignee

Lexmark International, Inc. — named assignee on the issued patent and the original employer-assignee. Primary business: printers (inkjet and laser) and consumables. Lexmark shipped products embodying the claims — thermal inkjet printheads, heater chips, and cartridges were core Lexmark inkjet products. Current status: Lexmark sold its entire inkjet technology/patent portfolio (1,500+ US and foreign assets) to Funai Electric Co., Ltd. in 2013 for roughly $100M (RPX Patent Watch, June 12, 2019); the remainder of Lexmark was later acquired by Apex Technology/PAG (Ninestar group) in 2016 and taken private. Lexmark therefore no longer owns this patent.

Assignment timeline

Three recorded assignments appear in the USPTO-derived legal-event feed (Google Patents). Correspondent data was not retrievable from available sources; each entry notes that limitation.

• 2002-12-16 (executed) / recorded 2002-12-17 — Reel 013597/0494

  • Conveyance: Assignment (of inventors' interest)
  • Assignor: Frank Edward Anderson; George Keith Parish
  • Assignee: Lexmark International, Inc.
  • Correspondent: not retrievable in this session (USPTO Assignment Center records not accessible; do not fabricate)
  • Context: Original employer-assignment from the two inventors to Lexmark at filing.

• 2013-04-01 (effective) / recorded 2013-05-14 — Reel 030416/0001

  • Conveyance: Assignment
  • Assignor: Lexmark International, Inc.; Lexmark International Technology, S.A.
  • Assignee: Funai Electric Co., Ltd.
  • Correspondent: not retrievable in this session
  • Context: The ~$100M, portfolio-wide sale of Lexmark's inkjet technology and patents (including this one) to Funai — Lexmark's strategic exit from the inkjet business, not a liquidation.

• 2019-03-29 (effective) / recorded 2019-03-29 — Reel 048745/0551

  • Conveyance: Assignment
  • Assignor: Funai Electric Co., Ltd.
  • Assignee: Slingshot Printing LLC
  • Correspondent: not retrievable in this session — this is the one recording where a repeat-correspondent check would matter most; per RPX, the assignment records suggest Funai retained an economic interest in Slingshot's later litigation.
  • Context: Transfer of 100+ US inkjet patents from operating company Funai to a newly formed Delaware LLC (Slingshot) that does not practice the claims; per RPX (June 12, 2019): "New NPE Begins Litigating Former Lexmark Patents Among More Than 100 Received from Funai."

Current assignee of record: Slingshot Printing LLC (Delaware LLC, 8455 Colesville Road, Suite 830, Silver Spring, MD 20910 — the address stated in its complaint). The patent reached its 20-year term and is now expired (anticipated expiration 2022-12-17; status "Expired - Lifetime").

Timeline diagram

timeline
    title Ownership of US 6786575
    2002 : Filed by Lexmark
    2004 : Patent issued
    2013 : Sold to Funai Electric
    2019 : Transferred to Slingshot LLC
         : Slingshot sues HP in W D Tex
    2022 : Patent expired

NPE / troll-pattern signals

1. Shell-entity transfer — present. Slingshot Printing LLC is a Delaware LLC formed to hold patents, ships no products, and is headquartered at a Silver Spring, MD office address used as its principal place of business in litigation (Complaint, Slingshot Printing LLC v. HP Inc., No. 6:19-cv-00549, W.D. Tex.). RPX's Patent Market/Patent Watch (June 12, 2019) explicitly described Slingshot as a "recently formed NPE" that received the assets from Funai (reel 048745/0551).

2. Known asserter in the chain — present. Unified Patents' litigation database classifies Slingshot Printing LLC as "NPE (Patent Assertion Entity)" and tracks it as a high-frequency plaintiff in W.D. Tex. (cases 6:19-cv-00362, 1:20-cv-00184, 6:19-cv-00549, and others against HP); RPX independently flags Slingshot as an NPE litigating former Lexmark patents.

3. Repeat correspondent across the chain — unclear / not assessable. Correspondent-of-record names were not retrievable from the sources available this session. Only three assignments exist across 17 years, so there is no accessible data showing a single repeat attorney running the chain. This signal must be marked not determinable, not inferred.

4. Cascading transfers — not present. The chain is a clean three-hop path — inventors → Lexmark (2002), Lexmark → Funai (2013), Funai → Slingshot (2019) — with multi-year gaps, not chained LLC transfers inside 24 months.

5. Pre-litigation transfer — present. The Funai → Slingshot assignment (reel 048745/0551) was recorded 2019-03-29; the first infringement complaint naming US 6786575 — Slingshot v. HP, No. 6:19-cv-00549, W.D. Tex. (Judge Albright) — was filed 2019-09-20, inside the 6-month window. Slingshot had already sued HP in June 2019 (e.g., 6:19-cv-00362) on sibling Lexmark/Funai patents, confirming the transfer was arranged to enable assertion.

6. Bankruptcy fire-sale — not present. Lexmark's divestiture was a negotiated ~$100M asset sale to Funai (2013), and Funai's 2019 transfer to Slingshot was not tied to any bankruptcy proceeding in the available record.

7. Privateering — present. Funai — an operating OEM/consumer-electronics company that manufactured inkjet hardware for Lexmark and produced KODAK-brand printers — transferred 100+ patents to NPE Slingshot, which immediately sued printer-market competitor HP. RPX reported the assignment records "suggesting that Funai might hold an economic interest in Slingshot's litigation," and HP's defense team moved to draw Funai into the dispute (per Action Intelligence coverage). This is the classic operating-company-to-NPE privateering structure.

8. Defensive aggregator (anti-NPE) — not present. The chain terminates at Slingshot Printing LLC, an asserting NPE; no RPX, AST, LOT, Unified, or OIN endpoint appears.

Verdict

NPE — high confidence

The chain ends at Slingshot Printing LLC, a productless Delaware LLC that RPX and Unified Patents both classify as an NPE/patent-assertion entity, which received 100+ assets from operating company Funai (reel 048745/0551, recorded 2019-03-29) and filed suit naming US 6786575 within six months (Slingshot v. HP, 6:19-cv-00549, filed 2019-09-20). Multiple strong signals converge: a shell-entity transfer from an operating assignee, a known asserter at the end of the chain, pre-litigation transfer timing, and privateering indicators (RPX-reported Funai economic interest; HP's attempt to join Funai). The case settled in 2021 (dismissals and terminated IPRs), and the patent has since expired, but the ownership record unambiguously shows an assertion-driven NPE chain rather than operating-company enforcement.

Verify at the USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search patent number 6786575; reels 013597/0494, 030416/0001, 048745/0551) — correspondent names for each recording should be pulled there for any follow-up work.

I'll ground this against live sources before analyzing. Let me pull the record for 6786575 and the key cited references.

Prior‑Art Analysis — U.S. Patent No. 6,786,575 B2

Target verified. US 6,786,575 B2, "Ink jet heater chip and method therefor," Application No. 10/321,946, filing/priority date Dec. 17, 2002, granted Sep. 7, 2004; inventors Frank Edward Anderson and George Keith Parish; assignee of record at issue Lexmark International, Inc. (later Funai → Slingshot); attorney/agent of record per the USPTO front page: Goldberg Segalla LLP. I have checked this against the USPTO‑format front‑page data as reproduced by FreePatentsOnline (https://www.freepatentsonline.com/6786575.html) and the Google Patents record. I did not return results for any other patent number; every reference below is one that appears on the face of 6,786,575.

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1. The exact citation list in 6,786,575 (do not substitute)

The front page of 6,786,575 lists 15 references: 14 U.S. patents and 1 foreign (EP) document. The "U.S. Patent References" block on the USPTO front page, in the order printed, is:

Foreign reference: EP 0 572 032 B1,"Ink jet recording method," 1996‑09‑18 (Canon Kabushiki Kaisha). Note that the Google Patents "Patent Citations (15)" table also lists US 6,252,617 B1 ("Ink jet recording method," Hasegawa et al., Canon) — this is the U.S. member of the same Canon family as EP 0 572 032 B1, so the disclosure is counted once but printed in both forms. I have kept both as printed rather than collapsing them.

Two "family" citations (marked "Family Cites Families" on Google Patents — i.e., cited in the child/parent case US 6,951,384 rather than on the face of 6,786,575), included for completeness because they are the substantive thin‑film‑printhead references in the family:

• US 4,862,197 A (Stoffel; Hewlett‑Packard; filed 1986‑08‑28; issued 1989‑08‑29) — "Process for manufacturing thermal ink jet printhead and integrated circuit (IC) structures produced thereby."
• US 5,883,650 A (Hewlett‑Packard; filed 1995‑12‑06; issued 1999‑03‑16) — "Thin‑film printhead device for an ink‑jet printer."

Important scope note (please don't let this slide): US 4,862,197 and US 5,883,650 appear in the family citation list, not in 6,786,575's own "Patent Citations" list. The earlier Obviousness section of this analysis referred to "US 5,883,650A (HP; 1999)" among "references in the patent's own cited‑art list." That is a slight mischaracterization — 5,883,650 is a family‑level citation. It does not change the §103 conclusion (see §4 below), but for a claim chart I'd cite it as family‑cited, not front‑page‑cited.

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2. The § 102 legal frame (pre‑AIA, because the application was filed Dec. 17, 2002)

Pre‑AIA 35 U.S.C. § 102 governs. The two operative categories here:

• § 102(b) — the reference was patented or described in a printed publication more than one year before the Dec. 17, 2002 filing date, i.e., on or before Dec. 17, 2001. All but one of the cited references fall here.
• § 102(e) — a U.S. patent granted on an application filed before the applicant's invention date (in practice, before the Dec. 17, 2002 filing date). One cited reference falls here.
• § 102(a)/(g) — the reference was known/used/published before the invention date. Several of the 1985–1992 references could also be characterized this way, but § 102(b) is the cleanest and strongest footing for all of them.

⚠️ Contradiction to flag with the earlier Obviousness section

The previously generated Obviousness section states that US 6,331,049 B1 "issued Dec. 18, 2001 … so it is § 102(b) art." That is incorrect. Dec. 18, 2001 is one day after the one‑year critical date (Dec. 17, 2001), so US 6,331,049 B1 is not § 102(b) art. It is available only as § 102(e) art, by virtue of its Mar. 12, 1999 filing date. The disclosure is still fully available — and under § 102(b) via its EP family member EP 1 034 932 A2, published Sep. 13, 2000, which comfortably predates the critical date — but the statutory basis is different. Anyone building a claim chart should cite the EP 1 034 932 A2 publication (2000‑09‑13) under § 102(b) and/or US 6,331,049 under § 102(e), not "US 6,331,049 under § 102(b)."

All other front‑page references issued on or before Nov. 13, 2001 (the latest of the remainder is US 6,315,398 B1) and are squarely § 102(b) art.

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3. The critical § 102 finding: no single cited reference anticipates any claim

Anticipation under § 102 requires that one single reference disclose every element and limitation of the claim, arranged as in the claim (Net MoneyIN v. VeriSign; Schering Corp. v. Geneva Pharms.). Because claim 1 is the only independent claim and claims 2–6 all depend from and incorporate claim 1, no dependent claim can be anticipated by a reference that does not itself disclose all of claim 1.

Measured against claim 1's full element set — (a) semiconductor substrate; (b) first metal resistive layer; (c) second metal conductive layer on first and second portions of the resistive layer defining a heater resistor element; (d) passivation layer deposited and etched, over the conductor and resistor, whose "first thickness [is] defined by a deposition process alone," with the conductor overlying the first portion of the resistive layer substantially devoid of the passivation layer; (e) cavitation layer over the heater resistor (also absent over the first‑portion conductor); (f) a separately deposited and etched dielectric layer overlying the first portion of the resistive layer, of a second thickness; (g) a via etched in that dielectric layer; and (h) a third metal conductive layer deposited on the dielectric layer and in the via for electrical contact with the second metal conductor —

the honest answer is: none of the 17 references below anticipates any of claims 1–6. Every one of them is missing at least element (d)'s two‑part limitation (passivation thickness set by deposition alone, plus the lead region substantially devoid of passivation) and/or element (f) (a separate dielectric layer deposited over the first‑portion conductor, distinct from the passivation). That is precisely the "split the stack" feature that 6,786,575 claims as its point of novelty, and it is why the examiner allowed the case over this art.

I lay out below, reference by reference, what each reference does show and which claim it comes closest to — with an explicit statement that closeness is not § 102 anticipation.

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4. Reference‑by‑reference analysis

4.1 US 6,331,049 B1 — Leban; Hewlett‑Packard Company

• Full citation: US 6,331,049 B1, "Printhead having varied thickness passivation layer and method of making same," Marzio Leban, filed Mar. 12, 1999, issued Dec. 18, 2001.
• Family: EP 1 034 932 A2, published Sep. 13, 2000 (B1 granted later); EP app. 00301608.6, filed Feb. 29, 2000, priority US 267,216 (Mar. 12, 1999).
• § 102 status: § 102(e) (US patent, Mar. 12, 1999 filing) — not § 102(b) (see §2 flag). The EP 1 034 932 A2 publication (Sep. 13, 2000) is § 102(b) art and carries the same disclosure.
• Brief description (verified against the patent PDF and EPO publication): Discloses a thermal ink‑jet printhead whose passivation layer (120/220) is of varied thickness — relatively thin (121/221) over the ink‑expulsion (resistive) element to reduce turn‑on energy (TOE), and relatively thick (122/222) over the circuitry/lead regions to protect against capacitive coupling. The specification expressly ties passivation thickness to TOE and reports that thinning passivation from 0.75 µm to 0.38 µm yields a ≈22 % TOE reduction. A tantalum protection/cavitation layer (124) and surface conductor (126)/contact pad (128) contacted through a via (25) are also shown, as are beveled conductor edges (13, 15) at the resistor. FIG. 3 performs a complete etch of passivation over the resistor region followed by re‑deposition of thin Si₃N₄/SiC.
• Closest claim(s): Claim 1 (closest single reference overall — discloses the substrate, resistive/conductive/resistor‑defining structure, thin‑over‑resistor/thick‑over‑circuitry passivation, Ta protection layer, and via‑to‑conductor). Also element‑level relevance to claim 2 (Si₃N₄/SiC bilayer; 0.38 µm = 3,800 Å thin region falls inside the claimed 3,100–4,500 Å) and claim 3 (Ta at ≈0.6 µm = 6,000 Å, the top of the claimed 4,000–6,000 Å).
• What it does NOT disclose (why it is not § 102 art against claim 1): It does not disclose the conductor over the first portion of the resistive layer as "substantially devoid of the passivation layer," with a separate, independently deposited dielectric layer substituted over that first portion. In 6,331,049 the same passivation is simply left thicker over the circuitry; the thick/thin regions are one and the same layer. It also does not disclose the "deposition process alone" characterization in the claim‑1 sense — its FIG. 3 thinned region is produced by etching then re‑depositing, and the thin/thick variation is a patterning of one passivation.
• Verdict: No § 102 anticipation of any claim. It is the strongest § 103 primary reference (see the Obviousness section).

4.2 US 5,844,586 A — Berry et al.; Standard Microsystems Corporation

• Full citation: US 5,844,586 A, "Process for making ink jet heater chips," filed Apr. 8, 1996, issued Dec. 1, 1998.
• § 102 status: § 102(b).
• Brief description (verified from the patent PDF): Monolithic heater‑chip process flow. An MOS driver transistor (10) is formed in the substrate (18); a stacked metallurgy of a TaAl resistive layer (28, ≈1000 Å, Ta:Al 40–60/60–40 at.%) and an Al‑Cu (or Al‑Cu‑Si) conductive layer (30, ≈5200 Å) is sputter‑deposited and patterned so the resistive layer forms the heating element. A passivation layer (Si₃N₄/SiC) is deposited, and — the reference's stated advance — a conductive protective (cavitation) layer is deposited and patterned over the passivation before any photolithographic or etching step on the passivation layer, forming a cavitation layer at each heater region; the passivation is thereafter patterned and etched to open vias; a second conductive layer is then deposited, patterned and etched to define bond pads and interconnect. Completed with a thick film and nozzle plate defining ink reservoirs.
• Closest claim(s): Claim 1 (substrate; TaAl resistive layer; Al conductor defining the resistor; Si₃N₄/SiC passivation; Ta cavitation layer; via through passivation to underlying conductor; top‑level metal contacting through the via) and claim 4 (NMOS/CMOS drive transistors integrated in the substrate — expressly disclosed). Strong element‑level support for claims 2 and 3.
• What it does NOT disclose (why it is not § 102 art against claim 1): It keeps the passivation over the lead/conductor regions where the top metal runs (passivation is opened only at vias, not cleared from the whole first‑portion lead), and it does not teach a separate inter‑metal dielectric layer deposited over the first‑portion conductor. There is no "thickness defined by a deposition process alone" limitation and no "substantially devoid of passivation" over the first‑portion conductor.
• Verdict: No § 102 anticipation of any claim. Supply‑side support for the § 103 combination with 6,331,049.

4.3 US 5,980,025 A — Burke et al.; Xerox Corporation

• Full citation: US 5,980,025 A, "Thermal inkjet printhead with increased resistance control and method for making the printhead," Cathie J. Burke and Alan D. Raisanen, filed Nov. 21, 1997, issued Nov. 9, 1999.
• § 102 status: § 102(b).
• Brief description (verified via Espacenet bibliographic record and Google Patents): Improves resistance control in a polysilicon‑resistor thermal printhead by growing a thin buffer oxide layer on the resistor surface so the resistor is mechanically isolated from the overlying nitride and tantalum layers; the buffer oxide permits a thinner nitride layer, reducing stress‑induced resistance changes. Per the analysis in the earlier Obviousness section, its thick PSG/thermal‑oxide dielectric is masked and etched so it is removed from the central bubble‑generating region of the heater, after which the thinner‑than‑normal nitride is deposited directly over the heaters followed by the tantalum layer.
• Closest claim(s): Claim 1 at the element level — separately managing a thick dielectric (kept off the heater region) and a thin, deposition‑controlled nitride passivation over the resistor, plus a Ta layer over the nitride. Element‑level relevance to claim 3 (Ta cavitation).
• What it does NOT disclose: The reference is directed to resistance control / stress isolation, not to the claim‑1 architecture. It does not disclose a second metal conductive layer on two portions of a resistive layer defining a heater resistor element with a third metal layer contacting the second through a via in a separate dielectric in the claimed arrangement, and it does not disclose the "substantially devoid of passivation over the first portion" limitation. Its resistor is polysilicon, not a first metal resistive layer in the claimed TaAl‑type stack.
• Verdict: No § 102 anticipation of any claim. Useful § 103 gap‑filler on the "dielectric off the heater" and "thin deposition‑controlled passivation over the resistor" ideas.

4.4 US 6,120,135 A — Murthy et al.; Lexmark International, Inc.

• Full citation: US 6,120,135 A, "Printhead having heating element conductors arranged in spaced apart planes and including heating elements having a substantially constant cross‑sectional area in the direction of current flow," Ashok Murthy and Steven Robert Komplin, filed July 3, 1997, issued Sep. 19, 2000. (Priority: US 887,583, Jul. 3, 1997; EP counterpart EP 0 890 438 A2, published Jan. 13, 1999; related EP 0 899 108 A2 to Komplin et al.)
• § 102 status: § 102(b) (issued Sep. 19, 2000; and the EP counterpart published Jan. 13, 1999). Same assignee as 6,786,575 (Lexmark) — but because it issued more than one year before the Dec. 17, 2002 filing, it is § 102(b) art and cannot be disqualified under pre‑AIA § 103(c), which reaches only art qualifying solely under § 102(e)/(f)/(g). This is worth stating explicitly in any chart, because a challenger will be asked about common ownership.
• Brief description (verified from the patent text and claims): A heater chip in which first conductors and second conductors are in vertically spaced‑apart planes, with a heating element positioned between them. A dielectric layer (interposed between the first conductor and a current transfer layer) has openings positioned in‑line with the heating elements so current can flow between the first and second conductors through the heating elements; the heating element has a substantially constant cross‑sectional area along the current‑flow axis. Claim 1 recites the dielectric interposed between first conductors and the current transfer layer with openings for transferring current.
• Closest claim(s): Claim 1 at the element level — a dedicated dielectric layer between stacked conductor planes, patterned with an opening/via for current transfer — which is the functional role of 6,786,575's dielectric spacer (58/66) over the first‑portion conductor beneath the third metal.
• What it does NOT disclose: The claimed stack is different (vertical current flow between spaced planes, constant cross‑section resistor, current‑transfer layer of low thermal conductivity). It does not disclose a thin deposition‑only passivation over the heater resistor with the lead region substantially devoid of passivation and a separate dielectric substituted there. Its "dielectric" is an inter‑plane insulator, not a substitute for passivation over a first‑portion lead.
• Verdict: No § 102 anticipation of any claim. Best § 103 support for the "separate dielectric with via" element.

4.5 US 6,013,160 A — Raisanen et al.; Xerox Corporation

• Full citation: US 6,013,160 A, "Method of making a printhead having reduced surface roughness," Alan D. Raisanen et al., filed Nov. 21, 1997, issued Jan. 11, 2000.
• § 102 status: § 102(b).
• Brief description: A process for making a thermal ink‑jet printhead (same filing date and Xerox family as US 5,980,025) directed to reducing surface roughness of the printhead structure during fabrication — passivation/planarization techniques to smooth the topology (e.g., over the resistor and leads) prior to nozzle‑plate attachment.
• Closest claim(s): Claim 1 only at the level of general passivation‑layer processing of a thermal ink‑jet heater stack.
• What it does NOT disclose: It is a process/planarization reference. It does not disclose the structural claim‑1 architecture — the separately deposited dielectric over the first‑portion conductor, the deposition‑only passivation thickness, or the "substantially devoid" limitation.
• Verdict: No § 102 anticipation of any claim. Background/§ 103 art at most. (I did not retrieve the full text of this reference within the session; the characterization above is limited to what its title and family position support, and I flag that limitation rather than guess at specifics.)

4.6 US 6,252,617 B1 — Hasegawa et al.; Canon Kabushiki Kaisha (≡ EP 0 572 032 B1)

• Full citation: US 6,252,617 B1, "Ink jet recording method," Hasegawa et al., priority May 29, 1992, issued June 26, 2001; and EP 0 572 032 B1, "Ink jet recording method," Canon, published (B1) Sep. 18, 1996 (priority 1992‑05‑29).
• § 102 status: § 102(b) (both the US patent, issued June 26, 2001, and the EP B1, published Sep. 18, 1996).
• Brief description: A Canon ink‑jet recording method — i.e., directed to the method of driving/ejecting in a thermal (bubble‑jet) recording apparatus, not to heater‑chip layer architecture. It appears in this record as a method reference, not a stack reference.
• Closest claim(s): None of claims 1–6 in structural terms; at most claim 6 for the generic "ink jet printhead" environment.
• What it does NOT disclose: No substrate/first‑resistive‑layer/second‑conductor‑layer/passivation/dielectric/via/third‑metal stack, and nothing about passivation thickness defined by deposition alone or a lead region devoid of passivation.
• Verdict: No § 102 anticipation of any claim. Environment‑only art. (Characterization limited to the title/bibliographic record; I did not pull the full text within the session — flagged rather than guessed.)

4.7 US 6,315,398 B1 — Burke et al.; Xerox Corporation

• Full citation: US 6,315,398 B1, "Thermal ink jet heater design," Burke et al., priority Oct. 21, 1992, issued Nov. 13, 2001.
• § 102 status: § 102(b) (issued Nov. 13, 2001 — more than one year before the Dec. 17, 2002 filing).
• Brief description: Directed to thermal ink‑jet heater design — the geometry/materials of the resistive heater element and its surrounding layers in a thermal printhead (heater‑resistor design and its protective layers).
• Closest claim(s): Claim 1 at the element level (a thermal heater element in a layered thin‑film stack); generic support for claims 2/3 if it discloses Si₃N₄/SiC and Ta layers.
• What it does NOT disclose: Nothing in the record before me suggests it discloses the three‑metal, dual‑layer‑passivation‑plus‑separate‑dielectric architecture of claim 1 or the "thick dielectric over the first‑portion conductor / thin deposition‑only passivation over the resistor" split. Its subject matter is heater design, not inter‑metal dielectric substitution.
• Verdict: No § 102 anticipation of any claim. § 103 background. (Full text not retrieved; characterization limited to title/subject matter — flagged.)

4.8 US 6,310,639 B1 — Kawamura et al.; Hewlett‑Packard Company

• Full citation: US 6,310,639 B1, "Printer printhead," Kawamura et al., priority Feb. 7, 1996, issued Oct. 30, 2001.
• § 102 status: § 102(b).
• Brief description: An HP printer printhead reference (the 1996 "Printer printhead" family, co‑pending with the 6,331,049 Leban line and the 6,139,131 Prasad line). Directed to printhead structure including the thin‑film heater stack and its passivation/protection layers.
• Closest claim(s): Claim 1 at the element level (thin‑film printhead substrate with resistive heater and passivation); claim 6 (printhead incorporating a heater chip).
• What it does NOT disclose: On the record available, it does not disclose the claim‑1 architecture — the separate dielectric layer over the first‑portion conductor, or passivation cleared from that conductor so it is "substantially devoid" of passivation and cavitation.
• Verdict: No § 102 anticipation of any claim. § 103 background. (Full text not retrieved; characterization limited — flagged.)

4.9 US 6,139,131 A — Prasad et al.; Hewlett‑Packard Company

• Full citation: US 6,139,131 A, "High drop generator density printhead," Prasad et al., filed Aug. 30, 1999, issued Oct. 31, 2000.
• § 102 status: § 102(b).
• Brief description: A printhead (and printhead substrate) design aimed at high drop‑generator density — layout/interconnect architecture that fits many heater resistors and their conductors on a die, typically by moving interconnect to additional metal levels and reducing the front‑edge lead width.
• Closest claim(s): Claim 1 at the element level (multi‑level conductor routing over a heater substrate with dielectric between levels); claim 6 (printhead).
• What it does NOT disclose: Density/layout art. It does not disclose the claimed thin deposition‑only passivation over the resistor with the first‑portion conductor substantially devoid of passivation and cavitation, replaced by a separately deposited dielectric of independently controlled thickness.
• Verdict: No § 102 anticipation of any claim. § 103 background. (Full text not retrieved; characterization limited to title/subject matter — flagged.)

4.10 US 5,157,418 A — Tamura; Canon Kabushiki Kaisha

• Full citation: US 5,157,418 A, "Ink jet recording head with through‑hole wiring connector," Tamura, priority June 3, 1988, issued Oct. 20, 1992. (Current U.S. Class 347/58 on the 6,786,575 front page.)
• § 102 status: § 102(b).
• Brief description: An ink‑jet recording head using a through‑hole wiring connector to route electrical connections through/around the head structure (a wiring/interconnect architecture reference, not a passivation‑stack reference).
• Closest claim(s): Claim 1 only at the level of general wiring/interconnect to an ink‑jet head.
• What it does NOT disclose: Nothing about the heater‑stack passivation/dielectric split, deposition‑only passivation thickness, or a third metal contacting a second metal through a via in a separate dielectric over a resistive layer.
• Verdict: No § 102 anticipation of any claim. (Full text not retrieved; characterization limited — flagged.)

4.11 US 5,081,473 A — Hawkins et al.; Xerox Corporation

• Full citation: US 5,081,473 A, "Temperature control transducer and MOS driver for thermal ink jet printing chips," Hawkins et al., filed July 26, 1990, issued Jan. 14, 1992.
• § 102 status: § 102(b).
• Brief description: Integrates a temperature‑control transducer with an MOS driver on a thermal ink‑jet printing chip — i.e., on‑chip drive electronics and thermal sensing in the thin‑film structure.
• Closest claim(s): Claim 4 at the element level only (MOS transistors/drive circuitry integrated on the heater‑chip substrate) — but note claim 4 depends from claim 1 and cannot be anticipated absent all of claim 1.
• What it does NOT disclose: No claim‑1 passivation/dielectric architecture, no three‑metal stack with the claimed via/dielectric‑over‑first‑portion arrangement.
• Verdict: No § 102 anticipation of any claim. Element‑level § 103 support for claim 4. (Full text not retrieved; characterization limited — flagged.)

4.12 US 4,951,063 A — Hawkins et al.; Xerox Corporation

• Full citation: US 4,951,063 A, "Heating elements for thermal ink jet devices," Hawkins et al., filed May 22, 1989, issued Aug. 21, 1990.
• § 102 status: § 102(b).
• Brief description: Directed to the heating elements (resistors) of thermal ink‑jet devices — resistor material/geometry and the protective layers immediately over the resistor.
• Closest claim(s): Claim 1 at the element level (resistive heater element with overlying protection); possible element‑level relevance to claims 2/3 if it discloses Si₃N₄/SiC and Ta overlayers.
• What it does NOT disclose: The dual‑deposition architecture — a passivation whose thickness is set by deposition alone over the resistor, the first‑portion conductor substantially devoid of passivation/cavitation, and a separate dielectric with a via beneath a third metal layer.
• Verdict: No § 102 anticipation of any claim. § 103 background. (Full text not retrieved; characterization limited — flagged.)

4.13 US 4,947,192 A — Hawkins et al.; Xerox Corporation

• Full citation: US 4,947,192 A, "Monolithic silicon integrated circuit chip for a thermal ink jet printer," Hawkins et al., filed Mar. 7, 1988, issued Aug. 7, 1990. (Current U.S. Class 347/59 on the 6,786,575 front page.)
• § 102 status: § 102(b).
• Brief description: A monolithic silicon IC chip for a thermal ink‑jet printer — integration of heater resistors and their drive circuitry (and interconnect) in a single silicon chip. This is the archetypal "driver transistors on the heater chip substrate" reference.
• Closest claim(s): Claim 4 at the element level (NMOS/CMOS transistors on the heater‑chip substrate). Because claim 4 depends from claim 1, this cannot be § 102 anticipation of claim 4.
• What it does NOT disclose: The claim‑1 stack, the deposition‑only passivation thickness, the "substantially devoid" lead region, or the separate dielectric‑with‑via over the first portion.
• Verdict: No § 102 anticipation of any claim. Strong element‑level § 103 support for the claim‑4 transistor integration. (Full text not retrieved; characterization limited — flagged.)

4.14 US 4,532,530 A — Hawkins; Xerox Corporation

• Full citation: US 4,532,530 A, "Bubble jet printing device," Hawkins, filed Mar. 9, 1984, issued July 30, 1985.
• § 102 status: § 102(b).
• Brief description: The foundational bubble‑jet (thermal ink‑jet) printing device reference — the basic drop‑on‑demand thermal ejection architecture (resistive heater in an ink channel adjacent a nozzle, addressed by current pulses to nucleate a vapor bubble). It is the earliest general environment reference in the list.
• Closest claim(s): Claim 6 (an ink‑jet printhead) at the broadest environment level, and claim 1 only for the generic "heater resistor element in a thermal printhead."
• What it does NOT disclose: Not a thin‑film layer‑stack reference in the 6,786,575 sense; nothing about passivation/dielectric thickness control, deposition‑only passivation, or a separate inter‑metal dielectric with a via.
• Verdict: No § 102 anticipation of any claim. Foundational background/§ 103 art. (Full text not retrieved; characterization limited to title/subject matter — flagged.)

4.15 EP 0 572 032 B1 — Canon Kabushiki Kaisha

• Covered jointly with US 6,252,617 B1 at §4.6 above (same Canon "Ink jet recording method" family; published 1996‑09‑18; § 102(b)). Method‑of‑recording art; no § 102 anticipation of any claim.

4.16 (Family‑cited) US 4,862,197 A — Stoffel; Hewlett‑Packard

• Full citation: US 4,862,197 A, "Process for manufacturing thermal ink jet printhead and integrated circuit (IC) structures produced thereby," Stoffel, filed Aug. 28, 1986, issued Aug. 29, 1989.
• § 102 status: § 102(b). (Also cited in the child 6,951,384, and is within the same Lexmark family background.)
• Brief description: A process for manufacturing a thermal ink‑jet printhead and the resulting IC structures — the classic HP process‑flow reference for building the heater substrate (resistor/conductors/passivation/protective layers) with drive circuitry.
• Closest claim(s): Claim 1 at the element level (process‑built thin‑film heater structure); claim 4 element level (IC/driver integration).
• What it does NOT disclose: The claim‑1 three‑metal/dual‑layer architecture with a separately deposited dielectric over the first‑portion conductor and a deposition‑only passivation thickness over the resistor.
• Verdict: No § 102 anticipation of any claim. § 103 background. (Family‑cited, and full text not retrieved — flagged.)

4.17 (Family‑cited) US 5,883,650 A — Hewlett‑Packard

• Full citation: US 5,883,650 A, "Thin‑film printhead device for an ink‑jet printer," filed Dec. 6, 1995, issued Mar. 16, 1999.
• § 102 status: § 102(b).
• Brief description: A thin‑film printhead device — a thin‑film heater stack (substrate, resistive layer, conductors, passivation, protective/cavitation layer) for an ink‑jet printer. This is one of the most frequently cited "conventional thin‑film heater stack" references in the printhead art.
• Closest claim(s): Claim 1 at the element level (conventional thin‑film heater stack); claims 2/3 element level (passivation and cavitation materials/thicknesses).
• What it does NOT disclose: The claimed split — thin, deposition‑only passivation over the resistor plus a separate dielectric over the first‑portion conductor — and the "substantially devoid" limitation.
• Verdict: No § 102 anticipation of any claim. § 103 background. (Family‑cited, and full text not retrieved — flagged.)

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5. Summary table — claim 1 element coverage (element‑level relevance, NOT anticipation)

No column is a full row of ✔ → no single‑reference anticipation of claim 1, and therefore none of dependent claims 2–6 either.

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6. Bottom line

1. Target confirmed: US 6,786,575 B2 (App. 10/321,946; filed/priority Dec. 17, 2002; granted Sep. 7, 2004; Lexmark; Anderson & Parish; Goldberg Segalla LLP). Front page carries 14 U.S. patents + EP 0 572 032 B1, plus 2 family‑level U.S. references (4,862,197 and 5,883,650) that are not on 6,786,575's own face.

2. § 102 result: no anticipation. Not one of the 17 references anticipates any of claims 1–6, individually. Every reference is missing at least the two‑part claim‑1 feature that the examiner allowed over: (i) a passivation layer over the resistor whose thickness is "defined by a deposition process alone," and (ii) the second metal conductor over the first portion of the resistive layer being "substantially devoid" of passivation and cavitation, with a separate deposited/etched dielectric layer substituted there, through which a via is etched to a third metal layer.

3. Closest references (all § 103, not § 102): US 6,331,049 B1 (Leban/HP) is the closest single reference — it publishes the same thin‑over‑heater/thick‑over‑circuitry design rule and the same ≈20–22 % TOE‑reduction rationale, and its FIG. 3 even performs an etch‑and‑re‑deposit of a thin passivation region. US 5,844,586 A (Berry/Standard Microsystems) supplies the full TaAl/Al‑stack, deposit‑cavitation‑before‑etching‑passivation, via‑to‑conductor, top‑metal process flow plus the on‑substrate MOS driver of claim 4. US 6,120,135 A (Murthy/Lexmark) supplies a dedicated dielectric between stacked conductors with in‑line openings/vias, and US 5,980,025 A (Burke/Xerox) supplies dielectric removed from the heater region + a thin, deposition‑controlled nitride over the resistor.

4. Flagged contradiction with the earlier Obviousness section: 6,331,049 B1 (issued Dec. 18, 2001) is not § 102(b) art — it is one day past the one‑year critical date (Dec. 17, 2001). It is § 102(e) art (filed Mar. 12, 1999), and its disclosure is § 102(b) via EP 1 034 932 A2 (Sep. 13, 2000). Cite the EP publication, or the US patent under § 102(e), accordingly.

5. Verification status / limitations. Full‑text verification was performed this session for US 6,331,049 B1 (+ its EP 1 034 932 A2), US 5,844,586 A, US 5,980,025 A, and US 6,120,135 A (+ EP 0 890 438 A2 / EP 0 899 108 A2). Characterizations of US 6,013,160 A, US 6,315,398 B1, US 6,310,639 B1, US 6,139,131 A, US 6,252,617 B1, EP 0 572 032 B1, US 5,157,418 A, US 5,081,473 A, US 4,951,063 A, US 4,947,192 A, US 4,532,530 A, US 4,862,197 A, and US 5,883,650 A are limited to their titles, bibliographic data, and family/classification positions as they appear in the 6,786,575 record and search results; I did not retrieve their full texts within the search budget, so those entries are deliberately hedged rather than asserted in detail. If any of those older references is to carry weight in a claim chart, pull the full texts from patentimages/Google Patents and re‑verify before relying on it.

Obviousness Analysis — U.S. Patent 6,786,575 B2 ("Ink jet heater chip and method therefor") under 35 U.S.C. § 103 (pre-AIA)

1. Scope, legal framework, and references considered

The '575 patent issued September 7, 2004, from an application filed December 17, 2002 (no earlier priority claim). Pre-AIA §§ 102/103 therefore govern. All prior art used here must have been available before the filing date; every reference in the patent's own cited-art list qualifies (patented/published between 1985 and December 18, 2001). I treat the patent's cited-art list as the primary universe, per the instructions, and I verified the content of the most important references against live records (Google Patents, FreePatentsOnline, EPO) rather than relying on recollection.

The dispositive inquiry under Graham v. John Deere, 383 U.S. 1 (1966), and KSR Int'l Co. v. Teleflex, 550 U.S. 398 (2007), is whether the claimed subject matter as a whole would have been obvious to a person of ordinary skill in the art (POSITA) at the time of invention, considering: (1) the scope and content of the prior art; (2) differences between the prior art and the claims; (3) the level of ordinary skill; and (4) objective indicia of non-obviousness. Under KSR, a court must also consider whether there was a "reason, suggestion, or motivation" in the known problem itself, and combinations of known elements yielding predictable results are generally obvious.

Key references (all cited on the face of '575):

• US6331049B1 (Leban; Hewlett-Packard; filed Mar. 12, 1999; issued Dec. 18, 2001; EP family member EP1034932A2 published Sep. 13, 2000) — "Printhead having varied thickness passivation layer and method of making same." Verified disclosure: passivation layer relatively thin over the ink-expulsion element to reduce turn-on energy (TOE) and relatively thick over regions containing circuitry, to protect against capacitive coupling; explicitly states "thinning the passivation layer from 0.75 microns to 0.38 microns achieves a TOE reduction of approximately 22%"; FIG. 3 embodiment performs a complete etch of passivation over the resistor and re-deposits a thin Si₃N₄/SiC layer so the thin-layer thickness is set by deposition ("permits more accurate control of the thickness of region 221"); tantalum cavitation layer (~0.6 µm); via 125 through the passivation to the underlying conductor; gold contact pads and surface conductor. Source: https://patents.google.com/patent/[US6331049](/patent/US6331049) (and PDF: https://patentimages.storage.googleapis.com/e9/b0/c4/7ca65e71a4689b/US6331049.pdf; EP biblio: http://data.epo.org/pise-server/rest/collections/lgpi/EP1034932B1.pdf).
• US5844586A (Berry & Maniaci; Standard Microsystems; filed Apr. 8, 1996; issued Dec. 1, 1998) — "Process for making ink jet heater chips." Verified disclosure: monolithic heater chip with MOS drive transistors on the substrate; stacked metal film of TaAl resistive heater material + overlying thicker aluminum conductor, patterned to define a resistor at the heater region; blanket Si₃N₄ + SiC passivation; a tantalum cavitation/protective layer deposited and patterned over the heater region before any passivation etch; passivation later patterned/etched to form vias to the underlying Al conductor; Ta/Au deposited through the via to form the top-level contact. Source: https://patents.google.com/patent/[US5844586](/patent/US5844586).
• US6120135A (Murthy et al.; Lexmark; filed Jul. 3, 1997; issued Sep. 19, 2000) — "Printhead having heating element conductors arranged in spaced apart planes…". Verified disclosure: vertically spaced first and second conductor planes with a dedicated inter-metal dielectric layer interposed, the dielectric having openings positioned in-line with the heating elements to transfer current between conductor levels. Source: https://patents.google.com/patent/US6120135A/en.
• US5980025A (Xerox; filed Nov. 21, 1997; issued Nov. 9, 1999) — Verified disclosure: a thick PSG/thermal-oxide dielectric layer (13) is "masked and etched to produce vias … and concurrently removed from the central bubble generating region of the heater element," after which a thinner-than-normal silicon nitride layer (≈500–2,500 Å) is deposited directly over the heaters, followed by a tantalum layer, so the passivation over the resistor is deposition-controlled and thin while dielectric remains where needed. Source: https://patents.google.com/patent/[US5980025](/patent/US5980025) (and PDF: https://patentimages.storage.googleapis.com/67/66/9c/5a89071b59dfb8/US5980025.pdf).
• US6315398B1 (Xerox; 2001), US6310639B1 (HP; 2001), US6139131A (HP; 2000), US5883650A (HP; 1999), US6013160A (Xerox; 2000), US4947192A / US4951063A / US5081473A / US4532530A (Xerox/Canon), US4862197A (HP; 1989) — background art in the same field corroborating the conventional thin-film heater stack (resistive layer, Al conductor leads, Si₃N₄/SiC passivation, Ta cavitation layer, via, top metal). I verified full text only for US6315398B1 and US5980025A among these; characterizations of the others below are limited to what the titles/abstracts on the record support, and I flag that limitation.

POSITA: A person with a B.S./equivalent in electrical engineering, materials science, or chemical engineering and roughly 2–5 years of experience in semiconductor thin-film processing or thermal inkjet printhead/MEMS fabrication, conversant with PECVD/sputter deposition of Si₃N₄, SiC, TaAl and Ta; photolithography; wet/dry etching; and the TOE/cavitation-reliability trade-offs of thermal inkjet heater stacks. The '575 specification itself is written at this level and cites the above references as background.

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2. Claim 1 element map against the prior art

Claim 1 requires (paraphrasing literal text, including the issued-record typos): a substrate; a first metal resistive layer; a second metal conductive layer on first and second portions of the resistive layer defining a heater resistor element between them; a passivation layer deposited and etched over the conductor and resistor whose thickness is "defined by a deposition process alone," with the conductor over the first portion substantially devoid of the passivation layer; a cavitation layer over the heater resistor (also absent over the first-portion conductor); a separately deposited and etched dielectric layer overlying the first portion (a second thickness); a via in that dielectric; and a third metal conductive layer on the dielectric and in the via, contacting the second metal conductor.

No single reference shows every claim 1 feature in the precise physical layout of FIG. 11 of '575 (thin deposition-only passivation + cavitation over the resistor and second-portion lead, with a separately deposited thick dielectric substituted for passivation over the first-portion lead only). The obviousness case therefore rests on combining references, discussed next.

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3. Proposed combinations and why they are obvious

3.1 Primary combination: US6331049B1 + US5844586A (optionally + US6120135A or US5980025A)

Rationale. US6331049B1 is the closest single reference. It identifies the exact problem addressed by '575 — passivation thickness over the resistor drives TOE — and teaches the exact design rule '575 exploits: thin passivation over the heater (≈22% TOE reduction; 0.38 µm, i.e., 3,800 Å, disclosed) and thick dielectric over conductor/circuitry regions for inter-level isolation and capacitive-coupling protection. Its FIG. 3 embodiment already performs a complete removal of the passivation over the resistor followed by a fresh thin deposition, i.e., precisely the "thickness defined by a deposition process alone" concept that '575 touts as its improvement (see '575, col. describing FIGS. 7–11, passivation layer 52 at 3,100–4,500 Å vs. 6331049's 3,800 Å thinned region and re-deposited thin region 221). '575's own specification admits the conventional route it improves upon — blanket thick passivation (6,600–7,400 Å) etched down over the resistor — and '575's "advance" is the routine converse: deposit the passivation at the desired thin thickness from the outset, and place thick dielectric only where inter-metal insulation is needed.

Where 5844586A fills the process gaps. US5844586A supplies the full thermal-inkjet process flow that '575 claims to improve: (i) MOS transistors on the substrate (claim 4); (ii) the TaAl resistive + Al conductor stacked film patterned into a heater resistor between conductor leads; (iii) a Si₃N₄/SiC passivation blanket; (iv) a tantalum cavitation layer deposited and patterned over the heater region and removed elsewhere before the passivation is etched; and (v) vias etched through the remaining passivation to the underlying Al conductor, followed by top-level metal (Ta/Au) contacting the conductor through the via. This is, element-for-element, the sequence of '575 FIGS. 1–9 except for the substitution of a separately deposited inter-metal dielectric over the first-portion lead.

Where US6120135A and US5980025A fill the structural gaps.

• US6120135A (owned by the same assignee as '575, but issued Sep. 19, 2000, more than one year before the Dec. 17, 2002 filing, so it is § 102(b) art and not excludable under pre-AIA § 103(c) — which only disqualifies art qualifying only under § 102(e)/(f)/(g)) teaches the use of a dedicated inter-metal dielectric layer between vertically spaced conductor planes, patterned with openings/vias for current transfer — the functional role of '575's dielectric layer 58/66 over the first-portion lead beneath the third metal.
• US5980025A teaches removing a thick dielectric from over the heater's bubble-generation region and separately depositing a thinner, deposition-controlled nitride passivation directly over the resistor, followed by Ta — corroborating both the "dielectric kept off the heater" idea and the "thin passivation by deposition over the resistor" idea that '575 claims as novel.

The only real gap between the combination and claim 1 is that 6331049/5844586 keep the original passivation (thick in 6331049) over the lead region where the top metal runs, whereas claim 1 requires that lead region to be "substantially devoid of the passivation layer," with a separately deposited dielectric substituted. A POSITA would find this an obvious, even trivial, rearrangement:

1. 6331049 already teaches the function — thick dielectric over the lead/circuitry region for isolation; the material and the layer identity are not claimed to be critical ('575 itself concedes passivation and dielectric "may be provided by the same materials and serve similar purposes").
2. 6331049 FIG. 3 demonstrates the technique of completely stripping passivation from a selected region using its own mask and re-depositing a fresh layer of controlled thickness. Applying that identical, taught technique to the lead region (strip, then deposit the thick dielectric where the third metal will route) rather than to the heater region yields claim 1's structure directly.
3. The '575 process (FIGS. 7–11) uses the same photolithographic mask that defines the cavitation layer to strip the passivation from the first-portion lead, and 5844586 teaches that same ordering principle (pattern the cavitation layer before etching the passivation). Reusing a mask to clear the passivation under the later dielectric is a standard process-efficiency step.

Motivation (KSR). The known problem was high heater TOE/energy at high firing frequencies, with passivation thickness as the dominant thermal barrier — a problem both 6331049 and '575 quantify identically (~20–22% energy reduction by thinning the passivation over the resistor). The field had a finite set of known solutions: thin the passivation over the resistor (6331049), move thick dielectric off the heater (5980025), and use dedicated inter-metal dielectric layers with vias between stacked conductors (6120135). Combining them is the use of known techniques to solve the known problem with a predictable result — '575's own stated ~20% improvement is essentially the number 6331049 already published (22%). There is no teaching away: nothing in 6331049, 5844586, 5980025, or 6120135 discourages clearing passivation from a lead region that will be covered by a separately deposited IMD.

3.2 Alternative primary: US5980025A + US6331049B1 (or + US5844586A)

If a challenger wants a primary reference that already separates the "dielectric removed from the heater region" from the "thin passivation deposited over the heater," US5980025A is attractive: its thick PSG/oxide layer 13 is etched away from the central bubble-generation region, a thin (~1,500 Å) pyrolytic nitride is then deposited directly over the heaters, and Ta is deposited over that. Adding 6331049's express teaching that thick dielectric must be retained over circuitry/leads for isolation and its via/top-metal structure yields a chip in which thin deposition-controlled passivation sits over the resistor while thick dielectric remains only over the lead/conductor regions — again claim 1's architecture. 5844586 supplies the TaAl/Al resistor-with-leads geometry and the Ta cavitation/via/top-metal process.

3.3 How the combination reads on the two "distinguishing" limitations

• "First thickness defined by a deposition process alone." 6331049 FIG. 3 (etch-and-refill of thin Si₃N₄/SiC region 221) and 5980025 (thin nitride 17 deposited after the overlying dielectric is removed from the heater) both produce a passivation thickness over the resistor that is set by the deposition step, with no thinning etch of the final layer. A POSITA seeking process control would prefer depositing the thin final layer directly (as 6331049 notes, the refill approach "permits more accurate control of the thickness"), making the claimed limitation an obvious choice among disclosed alternatives.
• Lead region "substantially devoid" of passivation and cavitation. 5844586 inherently removes the cavitation layer everywhere except the heater region and opens the passivation down to the underlying Al conductor at contact points; 6331049 removes passivation down to the conductor at via 125. Extending that clearance from a point contact to the whole lead region that will be buried under a dedicated IMD (as in 6120135's stacked-conductor dielectric) is an obvious layout/process choice — the lead region performs no ink-protection function, so retaining passivation there has no purpose once a separate IMD is deposited.

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4. Dependent claims

• Claim 2 (SiC + Si₃N₄ passivation, ~3,100–4,500 Å): US6331049B1 expressly uses Si₃N₄ and/or SiC and discloses a thinned region of 0.38 µm = 3,800 Å, inside the claimed range; 5844586 discloses the Si₃N₄/SiC bilayer. Selecting thickness within a disclosed range for a known purpose (TOE reduction) is a routine optimization. Obvious.
• Claim 3 (Ta cavitation layer, ~4,000–6,000 Å): 6331049 discloses tantalum at ~0.6 µm = 6,000 Å (top of the claimed range); 5844586 and 5980025 disclose Ta cavitation layers. Obvious.
• Claim 4 (NMOS/CMOS transistors in the substrate): 5844586 discloses MOS drive transistors integrated on the heater substrate; 6331049 shows control logic in the substrate; the '575 spec itself treats transistor integration as conventional. Obvious.
• Claim 5 (IMD = silicon oxide / phosphorus-doped spin-on-glass / silicon oxide, ~7,900–11,700 Å combined): This is the weakest link for a challenger on this record. The cited references I verified disclose PSG/oxide dielectric composites (5980025; US6315398B1's PSG step region) and dielectric interposed between conductor planes (6120135), and PSOG/oxide sandwich IMDs were conventional in multilevel-metal semiconductor processing generally. But I did not verify that any single cited reference discloses the exact three-layer oxide/PSOG/oxide stack at the claimed cumulative thickness. A challenger would need to rely on a combination plus general knowledge, and the patent owner's best defense is that the specific tri-layer PSOG stack (and its thickness window) is not shown in the cited printhead art. Obviousness is plausible but weaker than for claims 1–4 and 6.
• Claim 6 (printhead containing the claim 1 chip): every printhead reference in the art (6331049 with its inkwell/orifice-plate structure; '575's own FIG. 6 conventional assembly) teaches combining the heater chip with ink chambers, nozzles, and an orifice plate. Obvious if claim 1 falls.

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5. Objective indicia and counterarguments

Secondary considerations. Nothing in the record before me shows long-felt need, industry praise, licensing, or commercial success tied to the claimed structure. Critically, the claimed benefit (~20% heater-energy reduction) is not unexpected — US6331049B1 published the same order of improvement (22%) from thinning passivation over the resistor years earlier, and '575's specification acknowledges the passivation-thickness/thermal-efficiency trade-off as known. Under KSR, that cuts against non-obviousness.

Where the patent owner has the strongest arguments:

1. The examiner considered all of the above references (they appear in the "Citations"/"Patent Citations" sections of the '575 record) and still allowed the claims. That is not a legal bar to an invalidity finding — in district court there is no presumption that considered art was overcome, and in IPR the Board is not bound by prosecution — but a petitioner relying solely on the same art already of record must present a developed rationale, not just a new argument.
2. The specific division of labor — a thin, deposition-only passivation retained over the resistor and second-portion lead while a separately deposited thick IMD is placed only over the first-portion lead — is not a single-reference teaching. The patent owner will argue that 6331049 teaches away from stripping passivation over the lead (it deliberately keeps thick passivation over circuitry) and that the claimed arrangement is a new stack architecture, not an obvious rearrangement.
3. Claim 5's specific tri-layer IMD stack and thickness range may lack a direct prior-art anchor.

Counter to those arguments. The claimed arrangement is, at bottom, the same functional solution 6331049 published (thin over the heater, thick where conductors/circuitry need isolation), implemented with process steps that were all individually known (5844586's cavitation-first/etch-via process; 6120135's dedicated IMD-with-vias between stacked conductors; 5980025's removal of dielectric from the heater region and re-deposition of thin passivation). Whether one leaves the thick dielectric in place (6331049) or strips and re-deposits it only over the lead (claim 1) is a choice between known, equivalent means to serve the same function, producing a predictable result — the paradigm KSR obviousness case. A reasonably strong § 103 case exists against claims 1–4 and 6 (primary combination 6331049 + 5844586, optionally + 6120135 and/or 5980025), with claim 5 the most defensible claim in the patent.

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6. Bottom line

• Claim 1 — strong case of obviousness over US6331049B1 in view of US5844586A, further supported by US6120135A (dedicated IMD with vias between stacked conductors) and US5980025A (dielectric removed from the heater region; thin deposition-controlled passivation over the resistor). The claimed thin/deposition-only passivation over the heater and the separately deposited dielectric over the lead are predictable implementations of teachings already in 6331049 (FIG. 3 etch-and-refill; thick-over-lead isolation) and 5844586 (cavitation-first, via-to-conductor, top-metal process).
• Claims 2, 3, 4, and 6 — obvious for the reasons above (ranges and materials expressly disclosed in 6331049/5844586; transistor integration disclosed in 5844586; printhead assembly conventional).
• Claim 5 — weakest challenger position on the cited art; the exact oxide/PSOG/oxide stack and thickness range are not verified as disclosed in any single reference.
• Overall: a § 103 challenge would most plausibly succeed against claims 1–4 and 6, with claim 5 as the most likely survivor; success would require the fact-finder to accept that the "separate layer" rearrangement over the lead region is an obvious design choice rather than a new architecture.

Grounding caveat: detailed full-text verification was performed for US6331049B1, US5844586A, US6120135A, US5980025A, and US6315398B1. Characterizations of US6013160A, US5883650A, US6310639B1, US6139131A, and the pre-1995 Xerox/Canon/HP references are limited to their titles/abstracts as listed in the patent record; if a claim-by-claim invalidity position is to be built on those, their full texts should be retrieved and checked.