US 7195341

I'll verify the current record for US 7,195,341 against live sources before summarizing.

US Patent 7,195,341 — Concise Record Summary

Verification note on identifiers: Searches for the literal string "7195341" return several unrelated items I am excluding — JP 7195341 B2 (a Japanese patent for a wavelength-dispersive X-ray spectrometer, issued 2022-12-23) and U.S. Trademark Registration No. 7195341 (MAYXLMEI, jewelry). Neither is the patent at issue. The reference below is the US utility patent only.

Date caveat: You state the current date is April 26, 2026. Several sources I located are dated after that (Law360 July 21, 2026; IPWatchdog July 16, 2026) and the system date provided to me is 2026-09-24. Per your instruction to treat live search results as ground truth, I report those items with their stated dates rather than discarding them.

Bibliographic data

Abstract (as issued)

"A semiconductor substrate for a micro-fluid ejection device. The substrate includes plurality of micro-fluid ejection actuators disposed adjacent a fluid supply slot in the semiconductor substrate. A plurality of power transistors, occupying a power transistor active area of the substrate, are disposed adjacent the ejection actuators and are connected through a first metal conductor layer to the ejection actuators. An array of logic circuits, occupying a logic circuit area of the substrate, is disposed adjacent the plurality of power transistors and is connected through a polysilicon conductor layer to the power transistors. A power conductor and a ground conductor for the ejection actuators is routed in a second metal conductor layer. The power conductor overlaps at least a portion of the power transistor active area of the substrate and the ground conductor overlaps at least a portion of the logic circuit area of the substrate."

Independent claims — plain language

The patent has 8 claims. Two are independent in form: claim 1 (the substrate) and claim 8 (an ejection head incorporating that substrate). Claims 2–7 depend from claim 1.

Claim 1 — the semiconductor substrate. A chip for an inkjet-style micro-fluid ejection device that stacks three wiring levels in a particular way to save die area:

1. Heater/actuator column — a column of ejection actuators (heater resistors) sitting next to an ink supply slot through the substrate.
2. Power transistor column — a column of driver transistors next to the actuators, wired to them in the first metal layer. This transistor column defines a "power transistor active area."
3. Logic column — a column of control logic next to the transistors, wired to them through a polysilicon layer (not metal). This is the key trick: it frees up metal routing space above the logic, because the logic-to-transistor control signals are carried in polysilicon instead of a third metal layer.
4. Power bus — routed in the second metal layer, positioned so it overlaps at least part of the power transistor active area.
5. Ground bus — also in the second metal layer, positioned so it overlaps at least part of the logic circuit area.

Stated commercial purpose: keep the buses wide (low resistance, more energy to the heaters) without widening the die, using only two metal layers plus polysilicon rather than three metal layers.

Claim 8 — the ejection head. A micro-fluid ejection head (i.e., a complete printhead assembly) that comprises the substrate of claim 1. It adds no new structural limitations of its own; its scope rises or falls with claim 1.

Dependent claims 2–7 (for completeness): heater resistors (2); at least three fluid supply slots with associated arrays and conductors (3); FETs as the power transistors (4); the logic circuits being chosen from primitive address logic, predrive circuits, data registers, or combinations (5); a columnar array of temperature sense resistors (TSRs) between the power transistors and the actuators (6); and non-metal TSR material (7).

2026 CAFC docket check — this patent

Slingshot Printing LLC v. Canon U.S.A., Inc., No. 24-1956 (Fed. Cir.) — the only 2026 Federal Circuit matter involving 7,195,341 that my searches surfaced.

• Opinion issued April 23, 2026, nonprecedential ("NOTE: This disposition is nonprecedential").
• Panel: Circuit Judges Prost, Clevinger, and Stark.
• Holding: Affirmed the PTAB's final written decision in IPR2022-01414 that claims 1–5 and 8 of the '341 patent are unpatentable as obvious over U.S. Patent No. 6,412,917 (Torgerson) and U.S. Patent No. 7,240,997 (Bruce). Slingshot's three arguments (Torgerson's polysilicon logic-to-transistor connection; motivation to combine; APA sufficiency) all rejected on substantial-evidence grounds.
• Primary source: https://www.cafc.uscourts.gov/opinions-orders/24-1956.OPINION.4-23-2026_2681303.pdf
• Docket entry: CourtListener lists an "Opinion" (Doc. 48) and "Judgment" (Doc. 49) dated Apr 23, 2026 — https://www.courtlistener.com/docket/73188636/slingshot-printing-llc-v-canon-usa-inc/

PTAB record: IPR2022-01414, Canon U.S.A., Inc. et al. v. Slingshot Printing LLC — filed 2022-08-23; institution 2023-04-13; termination (FWD) 2024-04-09 (per ipverse.greyb.com case record, which lists Respondent Patent Number 7195341 and Application 10956939).

Do not confuse with other 2026 Slingshot/Canon appeals on different patents: 24-2127 (U.S. 7,152,951, Law360 July 21, 2026) and the July 16, 2026 rulings on U.S. 7,290,864 and U.S. 7,484,823/7,594,708 (IPWatchdog). Those do not involve 7,195,341.

Uncertainty / items I could not authoritatively confirm

1. Certificate of cancellation under 35 U.S.C. § 318(b). I could not confirm from an authoritative USPTO source whether the certificate canceling claims 1–5 and 8 has posted. A search of the USPTO databases was not conclusive; this should be checked directly at https://ptab.uspto.gov (PTAB E2E) or PatentCenter for 7,195,341. My searches did not return a source confirming the certificate.
2. Exact three-judge PTAB panel on the FWD and whether Ground 2 (Furukawa + Torgerson) was reached after Ground 1 — the CAFC opinion affirms on Ground 1 (Torgerson + Bruce) and does not indicate reliance on Ground 2. Confirm from the FWD signature block in PTAB E2E.
3. Claims 6 and 7 were never separately challenged and carry no independent validity — they depend from canceled claim 1 — but no tribunal has ruled on them directly.
4. Current assignee string. Google Patents lists Slingshot Printing LLC, consistent with the recorded 2019-03-29 assignment (reel 048745/0551). I did not independently re-pull the USPTO Assignment Center record for this run; the reel/frame numbers in the earlier sections of this analysis should be verified at https://assignmentcenter.uspto.gov/ if a formal chain of title is needed.
5. The patent is expired (2025-06-18) regardless of the validity outcome, which caps any damages theory at pre-expiration conduct.

Bottom line: US 7,195,341 is a Lexmark-origin inkjet printhead layout patent (King & Rowe), filed and issued 2004/2007, now owned by Slingshot Printing LLC and expired. Its sole substantive independent claim (claim 1) covers routing a second-metal power bus over the power-transistor active area and a second-metal ground bus over the logic area, enabled by running logic-to-transistor control signals in polysilicon; claim 8 claims a printhead containing that substrate. Claims 1–5 and 8 were held unpatentable as obvious by the PTAB and that holding was affirmed by the Federal Circuit on April 23, 2026.

I'll search for litigation involving US Patent 7,195,341 across the relevant dockets.

I have good data on the IPR and CAFC appeal. Now let me search the specific district court dockets listed for this patent.

I have identified the key dockets. Let me now verify the final dispositions of the district court cases and check for any other litigations involving this patent.

Based on my searches, here is the litigation picture for US Patent 7,195,341 B2 ("Power and ground buss layout for reduced substrate size"). Note: the task states a current date of April 26, 2026, but some fetched results are dated later (July 2026); where that occurs I flag it. All patent numbers below are interpreted literally as given.

Litigation involving US Patent 7,195,341

1. Slingshot Printing LLC v. HP Inc. — No. 6:19-cv-00549 (W.D. Tex.)

• Plaintiff: Slingshot Printing LLC
• Defendant: HP Inc.
• Jurisdiction / court: [U.S. District Court for the Western District of Texas, Waco Division](/courts/western-district-of-texas-waco) (later transferred to Austin); Judge Alan D. Albright
• Case number: 6:19-cv-00549
• Filing date: September 20, 2019
• Patents asserted: The '341 patent was one of ten asserted (also 6,213,587; 6,575,563; 6,676,246; 6,786,575; 7,018,012; 7,290,864; 7,410,246; 7,484,823; and 7,559,629), per the complaint (Docket No. 1).
• Status/outcome: Case was transferred from the Waco docket to Austin ("Case transferred to Austin. No further filings allowed in Waco case"). HP filed related IPR petitions (e.g., IPR2020-01659, which terminated March 2021 after a joint motion following settlement). The final disposition of the district case was not confirmed in my search results; UniCourt listed it as "Pending" as of late 2019, and I could not verify the terminal order. Outcome: not fully confirmed — likely resolved by settlement/transfer-related disposition, but I could not verify a final judgment.

2. Slingshot Printing LLC v. Canon U.S.A., Inc., Canon Solutions America, Inc., et al. — No. 2:22-cv-00123 (E.D.N.Y.) ("Slingshot I")

• Plaintiff: Slingshot Printing LLC
• Defendants: Canon U.S.A., Inc.; Canon Solutions America, Inc. (and related Canon entities, with Canon Inc. identified as corporate parent)
• Jurisdiction / court: U.S. District Court for the Eastern District of New York (Central Islip); judges assigned over time included Joan M. Azrack, then Hector Gonzalez, then Nusrat J. Choudhury, with Magistrate Judge Lee G. Dunst (PacerMonitor current listing: Judge Choudhury / Magistrate Dunst)
• Case number: 2:22-cv-00123
• Filing date: January 7, 2022
• Patents asserted: 7,152,951; 7,195,341; 7,559,629; and 7,938,523 (per Canon's Answer, which admits the '341 patent is among the "Patents in Suit")
• Status/outcome: Stayed December 1, 2022, pending resolution of IPR2022-01414 (and related IPRs) covering all asserted claims. PacerMonitor lists the case as terminated in 2024 (termination date displayed as "?? 31, 2024" — month masked in the retrieved record, consistent with entry of final disposition after the PTAB's April 9, 2024 Final Written Decision). The precise termination order (dismissal with/without prejudice or settlement) was not confirmed in my searches. Outcome: terminated 2024; specific final order not independently verified.

3. Canon U.S.A., Inc. and Canon Inc. v. Slingshot Printing LLC — IPR2022-01414 (PTAB)

• Petitioner: Canon U.S.A., Inc. and Canon Inc.
• Patent owner / respondent: Slingshot Printing LLC
• Tribunal: Patent Trial and Appeal Board (application no. 10/956,939; patent 7,195,341)
• Proceeding number: IPR2022-01414
• Filing date: August 23, 2022
• Claims challenged: 1–5 and 8
• Status/outcome: Institution granted April 13, 2023. Final Written Decision (April 9, 2024): claims 1–5 and 8 held unpatentable as obvious over U.S. Patent No. 6,412,917 (Torgerson) and U.S. Patent No. 7,240,997 (Bruce). Patent owner (Slingshot) appealed to the Federal Circuit.

4. Slingshot Printing LLC v. Canon U.S.A., Inc. (and Canon Inc.) — No. 24-1956 (Fed. Cir.)

• Appellant: Slingshot Printing LLC
• Appellees: Canon U.S.A., Inc. (and Canon Inc.)
• Court: U.S. Court of Appeals for the Federal Circuit
• Case number: 24-1956
• Filed: June 11, 2024 (Notice of Appeal from IPR2022-01414)
• Status/outcome: Affirmed April 23, 2026 (nonprecedential per Justia's opinion dated 04/23/2026). The Federal Circuit rejected Slingshot's three arguments (Torgerson's disclosure of the polysilicon conductor-layer connection, motivation to combine Torgerson and Bruce, and alleged APA insufficiency of the Board's analysis) and affirmed the PTAB's obviousness ruling. Net effect: claims 1–5 and 8 of the '341 patent stand invalid as obvious. (The Recycler independently confirms the CAFC affirmed the invalidation.) Note: a later IPWatchdog article dated July 16, 2026 — after the stated current date — describes a separate CAFC affirmance involving other Slingshot patents (7,290,864; 7,484,823; 7,594,708) in appeals 25-1032/25-1033; those do not involve the '341 patent and are listed only to avoid confusion.

Summary table

Caveats

• I could not pull live PACER dockets directly; district-court termination orders for 6:19-cv-00549 and 2:22-cv-00123 were not confirmed in detail (PacerMonitor's termination date for the E.D.N.Y. case was partially masked in the retrieved snippet). If you need the precise final orders (e.g., dismissal with prejudice vs. settlement), they should be pulled from PACER.
• The IPR and CAFC outcomes are well documented and corroborated by PTAB records (ipverse.greyb.com), the Justia CAFC opinion for 24-1956, and press coverage.
• My searches did not surface any other district-court litigations naming the '341 patent beyond the HP and Canon matters above (e.g., no separate suits against Brother, Epson, etc. appeared), and Google Patents' litigation index for this patent lists the same four matters (W.D. Tex. 6:19-cv-00549; E.D.N.Y. 2:22-cv-00123; IPR2022-01414; Fed. Cir. 24-1956).

Proceedings overview

There is one AIA trial proceeding on US 7,195,341: IPR2022-01414 (Canon U.S.A., Inc. & Canon Inc. v. Slingshot Printing LLC). It is not settled and not denied — it was instituted on all challenged claims, resolved in a Final Written Decision holding claims 1–5 and 8 unpatentable, and that decision was affirmed by the Federal Circuit on 2026-04-23. The bottom line for a defendant: every claim of the patent that was tested is dead — and because the only untested claims (6–7) depend from canceled claim 1, the patent has no surviving enforceable claim of any practical value.

Flag on the structured "PTAB proceedings on file" block: The USPTO ODP-derived block states "no AIA trial proceedings … as of the most recent ingest." That is an ingest lag, not reality. Multiple independent public sources (USPTO PTACTS docket documents, the PTAB docket aggregators, the CAFC opinion, and the Federal Circuit's own opinion list) unambiguously confirm IPR2022-01414, filed 2022-08-23. Treat the structured block as stale.

IPR2022-01414 — Canon U.S.A., Inc. & Canon Inc. v. Slingshot Printing LLC

• Type: Inter Partes Review (pre-AIA § 103)
• Filed: 2022-08-23
• Status: "Final Written Decision – Appealed" (docket aggregator status) — i.e., trial phase terminated by FWD on 2024-04-09; patent owner appealed; CAFC affirmed 2026-04-23. No settlement occurred.
• Judge panel: The Final Written Decision was authored by APJ Mitchell G. Weatherly (per Patexia's docket summary). Aggregator listings also associate APJs Jo-Anne M. Kokoski, Josiah C. Cocks, Frances L. Ippolito, Christopher L. Ogden, and John D. Hamann with the docket — some of those judges sat on the parallel Canon IPRs against other Slingshot patents, so the exact three-judge panel for this FWD should be confirmed from the FWD signature block in PTAB E2E. (I could not verify the signature page directly.)
• Petition grounds (claims 1–5 and 8):
  • Ground 1: Obvious under 35 U.S.C. § 103 over Torgerson (US 6,412,917, "Energy Balanced Printhead Design") + Bruce (US 7,240,997).
  • Ground 2: Obvious under 35 U.S.C. § 103 over Furukawa (JP 1996-108536 A) + Torgerson.
  • Supporting evidence included the Declaration of Stephen F. Pond, Ph.D. (Ex. 1007); patent owner responded with Steven J. Dietl as its expert (Ex. 2003).
• Institution decision: Granted 2023-04-13 — the Board instituted review of all challenged claims (the CAFC expressly notes "[t]he Board instituted review of all of the challenged claims"). The Board rejected in the institution decision patent owner's early arguments that Torgerson lacks a polysilicon connection between logic circuits and power transistors.
• Final Written Decision (2024-04-09): Claims 1, 2, 3, 4, 5, and 8 — all challenged claims — held unpatentable as obvious over Torgerson + Bruce (Ground 1). The Board found Torgerson teaches logic circuits connected to power transistors through a polysilicon layer (crediting Canon's expert that "as a practical matter … it's necessary that Torgerson's polysilicon gate fingers … extend to its logic circuits"). On the ground-conductor limitation, the Board agreed Torgerson alone does not teach "placing a ground conductor in the second metal layer in [an] overlapping relationship with at least a portion of the logic circuit area," but found a skilled artisan would have been motivated to implement Bruce's second-metal-layer ground bus in Torgerson — both references being "from the same field of endeavor as the '341 patent," with Bruce's approach "one of a finite number of known, predictable solutions" driven by design need/market pressure to reduce substrate size. The Board then reviewed Canon's arguments and evidence on the remaining limitations of claim 1 and dependent claims 2–5 and 8 and found obviousness shown by a preponderance. (Whether the FWD separately reached Ground 2 — Furukawa + Torgerson — after deciding Ground 1 is not confirmed from the sources I could access; the Ground 2 combination was fully briefed and argued at the 2024-01 hearing, but the CAFC's affirmance rests on Ground 1 only.)
• Settlement / termination: No settlement. The trial phase terminated with the FWD on 2024-04-09. Patent owner did not concede; it appealed.
• Appeal: Yes — Slingshot Printing LLC v. Canon U.S.A., Inc., No. 24-1956 (Fed. Cir.), Patent Owner's Notice of Appeal filed 2024-06-11. Slingshot raised three issues: (1) Torgerson does not disclose logic circuits connected to power transistors through a polysilicon conductor layer; (2) the Board erred on motivation to combine Torgerson + Bruce; and (3) the Board's analysis of remaining limitations was insufficient under the APA. In a nonprecedential opinion dated 2026-04-23, the Federal Circuit affirmed, holding the Board's polysilicon finding supported by substantial evidence (rejecting Slingshot's "inherency not pleaded" and "rewriting the FWD" arguments), the motivation-to-combine finding supported by substantial evidence (Torgerson and Bruce are same-field references, and Bruce's second-metal ground bus was one of a finite number of predictable solutions), and the Board's remaining-limitations analysis adequate under the APA.
• Defensive value: Claims 1–5 and 8 are unpatentable — finally and on appeal. Under 35 U.S.C. § 318(b), the Director is required to cancel those claims once the appeal is exhausted (I could not independently verify that the certificate of cancellation has already posted, but the CAFC mandate should have issued well before 2026-09-03). Dependent claims 6–7 were never individually challenged, but both depend from claim 1 and cannot survive its cancellation. Any infringement theory built on claim 1 — or on claims 2–8 that incorporate it — is now essentially sanction-bait, and the patent expired 2025-06-18 in any event, capping any conceivable damages at pre-expiration conduct.

Strategic summary

Canceled vs. sustained vs. untested — the effective map of 7,195,341. The IPR petition challenged claims 1–5 and 8 (the entire claim chain that matters: claim 1 is the sole independent substrate claim; claims 2–7 depend from it; claim 8 is the printhead claim incorporating claim 1's substrate). The PTAB held all challenged claims (1–5, 8) unpatentable as obvious over Torgerson + Bruce, and the CAFC affirmed on 2026-04-23. Claims 6–7 (temperature-sense-resistor features) were not separately litigated, but because they depend from claim 1, they have no independent validity once claim 1 is canceled. So there is no claim of the '341 patent that a plaintiff can assert with a straight face today: claims 1–5 and 8 are invalidated on the merits, claims 6–7 fall with claim 1, and the patent is expired (2025-06-18 adjusted expiration), so no injunction and only time-barred pre-expiration damages could ever be at issue.

Estoppel landscape. Section 315(e)(2) estoppel binds Canon U.S.A., Canon Inc., and their privies in the parallel E.D.N.Y. litigation (Slingshot Printing LLC v. Canon U.S.A., Inc., No. 2:22-cv-00123) and any other forum: Canon cannot re-raise in district court any ground it raised or reasonably could have raised in IPR2022-01414 — that covers the Torgerson, Bruce, and Furukawa art and all obvious combinations among them. For a new defendant who is not Canon's privy, no estoppel attaches from this IPR, but the practical reality is that the art that killed the patent is now public record: the strongest § 102/§ 103 case (Torgerson + Bruce, and the alternative Furukawa + Torgerson path) is fully developed, with expert declarations and a CAFC affirmance to cite. A non-party defendant can also simply move to dismiss or for judgment on the pleadings citing the FWD and the affirmed cancellation obligation.

Pattern signals. The Canon IPRs were not an isolated strike: Canon ran a coordinated multi-patent IPR campaign against Slingshot's printhead portfolio (the same week's CAFC output included affirmance of PTAB obviousness findings on Slingshot's 7,290,864 and 7,484,823/7,594,708 patents). Slingshot (the Lexmark → Funai → Slingshot chain) has defended aggressively but unsuccessfully — it opposed institution, fought through a full trial with expert testimony, and appealed the FWD to the CAFC, losing at every stage on this patent. The earlier HP assertion (6:19-cv-00549, W.D. Tex., reassigned 2:20-00187) ended in a stipulated dismissal with prejudice in 2021 — consistent with a monetization campaign that is now largely defanged by IPR. Unified Patents appears only as a litigation-data aggregator in the record, not as a petitioner here.

Recommended next steps

• If you are Canon (or a privy): You are estopped from re-litigating the IPR grounds in the E.D.N.Y. case, but you don't need to — cite the FWD (IPR2022-01414, Paper, 2024-04-09) and the CAFC affirmance. Slingshot Printing LLC v. Canon U.S.A., Inc., No. 24-1956, slip op. (Fed. Cir. Apr. 23, 2026): "we affirm the Board's determination that claims 1–5 and 8 of the '341 patent are unpatentable." Opinion PDF: https://www.cafc.uscourts.gov/opinions-orders/24-1956.OPINION.4-23-2026_2681303.pdf (Justia mirror: https://law.justia.com/cases/federal/appellate-courts/cafc/24-1956/24-1956-2026-04-23.html). Ask the district court to enter judgment / dismiss with prejudice now that the FWD is final.
• If you are any other defendant receiving a demand letter citing 7,195,341: The patent expired 2025-06-18, and claims 1–5 and 8 have been held unpatentable in a final, CAFC-affirmed FWD. Confirm in PTAB E2E (https://ptab.uspto.gov) that the certificate of cancellation under 35 U.S.C. § 318(b) has issued; if it has, the patent's claims no longer exist and the demand is moot. If a certificate has not yet posted, the FWD + affirmance still foreclose any viable theory on claims 1–5 and 8, and claims 6–7 (dependent on claim 1) cannot stand.
• If you are evaluating a new IPR (non-Canon defendant, patent already expired, and pre-2025 damages threatened): the estoppel-free ground is strong but the window is effectively closed by the prior FWD — a petitioner can rely on the same Torgerson/Bruce combination, and the PTAB's prior unpatentability findings plus the CAFC affirmance make a second petition nearly costless to win, though § 315(e)(2) does not bar you since you weren't a party.
• Verify before filing: (1) the exact three-judge panel and the Ground 2 (Furukawa) disposition, if any, from the FWD itself in PTAB E2E; and (2) the posting date of the certificate of cancellation. Neither was independently confirmable from the sources available to me, but neither affects the bottom line — the patent's enforceable claim set is gone.

Inventors

• David G. King — Engineer at Lexmark International, Inc. (Lexington, KY) at the time of filing; named assignor to Lexmark on reel 015869/0340. Lexmark's inkjet printhead development group.
• Kristi M. Rowe — Engineer at Lexmark International, Inc. at the time of filing; named assignor on the same reel.

Both inventors assigned their rights to Lexmark on the filing date itself (2004-09-30), consistent with normal employed-inventor practice. I have no data indicating either inventor departed Lexmark within 12 months of filing, so I will not infer a departure pattern.

Original assignee

Lexmark International, Inc. (Lexington, KY) is the entity named on the issued patent. Lexmark was a major inkjet-printer OEM and did ship products embodying the claims — the '341 patent covers the driver/logic chip layout inside Lexmark's thermal inkjet printhead cartridges, and Lexmark manufactured those cartridges through 2012–2013. Current status: still operating as a private imaging company; taken private in 2016 by a consortium (Apex Technology/PAG), now under Ninestar-group ownership. Critically, Lexmark exited the inkjet business in 2012–2013 and sold its inkjet technology and patent portfolio (~1,500+ US/foreign assets, ~$100M) to Funai Electric Co., Ltd.

Assignment timeline

Verification caveat: I could not pull the USPTO Assignment Center records directly in this environment, so the reel/frame numbers below come from the USPTO-echoed legal-event log on Google Patents (reels 015869/0340, 030416/0001, 048745/0551). Those three events are corroborated by RPX/Unified Patents and press coverage of the Lexmark→Funai→Slingshot chain. Correspondent-of-record names are not shown on the Google Patents legal-event log and could not be retrieved here — verify each entry at https://assignmentcenter.uspto.gov/ by patent number 7195341 before relying on correspondent analysis.

• 2004-09-30 (executed) / recorded 2004-09-30 — Reel 015869/0340

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: David G. King; Kristi M. Rowe
  • Assignee: Lexmark International, Inc.
  • Correspondent: not retrievable in this environment
  • Context: Standard employed-inventor assignment at filing; conveys the application (then 10/956,939) to Lexmark.

• 2013-04-01 (effective) / recorded 2013-05-14 — Reel 030416/0001

  • Conveyance: Assignment
  • Assignor: Lexmark International, Inc.; Lexmark International Technology, S.A.
  • Assignee: Funai Electric Co., Ltd.
  • Correspondent: not retrievable in this environment
  • Context: Portfolio sale accompanying Lexmark's exit from inkjet — Funai paid ~$100M for Lexmark's inkjet-related technology and more than 1,500 US/foreign patent assets; this is the single largest ownership event in the chain.

• 2019-03-29 (effective) / recorded 2019-03-29 — Reel 048745/0551

  • Conveyance: Assignment
  • Assignor: Funai Electric Co., Ltd.
  • Assignee: Slingshot Printing LLC (Maryland LLC)
  • Correspondent: not retrievable in this environment
  • Context: Transfer-to-asserter — Funai conveyed more than 100 US inkjet assets to newly formed Slingshot Printing LLC, which began suing HP ~10 weeks later (see NPE signals below).

No other assignments, security agreements, mergers, or name changes are recorded on the Google Patents legal-event log for this patent.

Timeline diagram

timeline
    title Ownership of US 7195341
    2004 : Filed by Lexmark inventors
    2007 : Patent issued to Lexmark
    2013 : Lexmark sells portfolio to Funai
    2019 : Funai assigns to Slingshot LLC
         : Slingshot sues HP in Texas
    2024 : PTAB finds claims unpatentable
    2026 : CAFC affirms PTAB decision

NPE / troll-pattern signals

1. Shell-entity transfer — present. Reel 048745/0551 (recorded 2019-03-29) moved the patent from Funai Electric, an operating consumer-electronics/OEM manufacturer, to Slingshot Printing LLC, a Maryland LLC with no inkjet products in commerce. RPX's Patent Market/Patent Watch (June 12, 2019) describes Slingshot as a "recently formed NPE" that received "more than 100 US assets from Funai" that year.

2. Known asserter in the chain — present. RPX expressly labels Slingshot Printing LLC an NPE asserting former Lexmark patents; Unified Patents' litigation database logs Slingshot as plaintiff in W.D. Texas case 6:19-cv-00549 (this patent) and later Eastern District New York and CAFC matters. Slingshot does not sell products; its sole business is asserting the acquired Funai/Lexmark inkjet portfolio.

3. Repeat correspondent across the chain — unclear. The correspondent-of-record names on reels 015869/0340, 030416/0001, and 048745/0551 could not be retrieved in this environment. No recurrence finding can be made without pulling the Assignment Center records; this is the one signal to verify manually at assignmentcenter.uspto.gov.

4. Cascading transfers — not present. The chain has only two post-issuance links (2013 and 2019), spaced ~6 years apart — not the <24-month churn of chained LLCs typical of cascading transfers. The Lexmark→Funai→Slingshot sequence is a portfolio sale plus a single downstream carve-out, not a shell ladder.

5. Pre-litigation transfer — present. The Slingshot assignment was recorded 2019-03-29; Slingshot filed its first HP infringement suit naming former Lexmark patents on 2019-06-11 (W.D. Tex. 6:19-cv-00549, which the Unified Patents log links to this patent). That is roughly 10 weeks — well inside the 6-month window — and the assignment gave Slingshot clean standing to sue.

6. Bankruptcy fire-sale — not present. Lexmark's 2013 transfer was a negotiated portfolio divestiture following its strategic exit from the inkjet business, not a Chapter 7/11 asset sale. (Funai's own later financial difficulties post-date its 2019 transfer of this patent out of the chain and are irrelevant to this patent's record.)

7. Privateering — present. RPX reported that "assignment records suggest that Funai might hold an economic interest in Slingshot's litigation," i.e., the operating company (Funai) transferred the patents to an NPE that asserts against competitors (HP) while Funai retains a financial stake. The June 2019 HP suits targeted HP inkjet cartridges and printers that competed with the Lexmark-derived inkjet technology Funai had licensed and then monetized.

8. Defensive aggregator (anti-NPE) — not present. The chain terminates at Slingshot Printing LLC, an assertive NPE, not at RPX, AST, LOT Network, Unified Patents, or OIN. Inverse of a defensive-aggregation outcome.

Verdict

NPE — high confidence.

The patent moved from an operating company (Funai) to a productless Maryland LLC (Slingshot Printing LLC) on reel 048745/0551, recorded 2019-03-29; RPX and Unified Patents both identify Slingshot as an NPE; and Slingshot filed its first infringement suit naming this patent family within ~10 weeks of the transfer (W.D. Tex. 6:19-cv-00549, filed 2019-06-11), with RPX reporting indicia that Funai retained an economic interest — a privateering structure. That is four corroborating signals (shell-entity transfer, known asserter, pre-litigation transfer, privateering), all anchored to specific reel/frame and litigation records rather than naming alone. The one unverified element is correspondent recurrence, which requires a manual lookup at the USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search patent number 7195341; confirm reel/frame 015869/0340, 030416/0001, and 048745/0551).

I've reached the search-step limit, so I'll now compile the prior-art analysis from the authoritative patent record (the face-of-patent citation list embedded in the full text you provided) plus the live-search verifications I completed on the closest references (US6309053B1, US6422676B1, US6554404B2, US6575562B1, US20030011658A1/US6616268B2, US4887098A, US5144341A). References I could not open in full are flagged as "title/record-level only."

Prior-Art Analysis — US 7,195,341 B2 (7195341)

A. Legal frame and scope

• Applicable statute: The application was filed September 30, 2004, well before the AIA's March 16, 2013 effective date. Anticipation is therefore assessed under pre-AIA 35 U.S.C. § 102(a)/(b)/(e).
• Critical date for § 102(b): September 30, 2003 (one year before filing). Every face-of-patent citation published before that date is at least § 102(b) art; later-published U.S. patents/applications (e.g., US6726311B2, published 2004-04-27) are still § 102(a)/(e) art because their effective filing dates precede 2004-09-30.
• Claims at issue: Claim 1 (sole independent claim) requires, in combination: (a) a columnar array of ejection actuators adjacent a fluid-supply slot; (b) a columnar array of power transistors adjacent the actuators, connected to them through a first metal conductor layer, occupying a "power transistor active area"; (c) a columnar array of logic circuits adjacent the power transistors, connected to them through a polysilicon conductor layer, occupying a "logic circuit area"; (d) a power conductor in a second metal conductor layer overlapping the power transistor active area; and (e) a ground conductor in the second metal conductor layer overlapping the logic circuit area. Claims 2–7 are dependent; claim 8 is a micro-fluid ejection head incorporating the claim-1 substrate.
• Anticipation standard: One reference, alone, must disclose every limitation, expressly or inherently. For the reasons below, no single face-of-patent citation is a clean § 102 anticipation of claim 1 as I read them; the closest references each miss at least one of the distinguishing features (the polysilicon logic-to-FET interconnect and/or the second-metal ground bus over the logic area, rather than over the FET active area). Several references are credible § 102 candidates against specific dependent claims.

B. Closest references (highest relevance to claim 1 and its dependent claims)

1. US6309053B1 — Hewlett-Packard Co. (Torgerson, Joseph M.; Hurst, David M.)

• "Ink jet printhead having a ground bus that overlaps transistor active regions"
• Filed 2000-07-24 (US09/621,922); published 2001-10-30 → § 102(b)/(e) art. (Verified via EP1303412A1 family record and Justia.)
• Description: A slot-fed thermal inkjet printhead with columnar arrays of ink drop generators, columnar arrays of FET drive circuits, and a ground bus that partially overlies the FET active regions (drains/sources/gates) to shrink die width. Ground bus width varies along the column to equalize parasitic resistance; drain/source electrodes can share the ground-bus metallization layer.
• Claim mapping: Directly reads on claim 1 limitations (a), (b) (columnar FET array adjacent generators), and conceptually on the "bus overlapping an active area" idea of (d). However, the overlap taught is a ground bus over transistor active regions — the opposite of claim 1's split (power bus over the power-transistor area and ground bus over the logic area) — and it does not teach a polysilicon layer interconnecting logic circuits to the FETs. It is therefore not a complete anticipation of claim 1 on my reading. It is the strongest face-citation for claim 4 (FETs) and, with a heater-resistor embodiment, claim 2; it also supports claim 8 if combined with a nozzle plate (but § 103, not § 102). Note that this patent shares an inventor family with the art later used in IPR2022-01414.

2. US6422676B1 — Hewlett-Packard Co.

• "Compact ink jet printhead"
• Filed 2001-06-19 (US09/883,398); published 2002-07-23 → § 102(b)/(e) art. (Verified via Google Patents family record and WO2002102597A3.)
• Description: Continuation-lineage companion to US6309053B1; discloses a compact slot-fed printhead layout of ink drop generators and ground busses with FET drive circuit arrays, with the ground bus arranged to overlie the FET drive circuit region to conserve substrate area.
• Claim mapping: Same analysis as US6309053B1 — strong for claims 2, 4, 8 aspects; does not disclose the polysilicon logic-to-FET interconnect or ground-over-logic placement of claim 1.

3. US20030011658A1 → issued as US6616268B2 — Lexmark International, Inc. (Parish, George Keith)

• "Power distribution architecture for inkjet heater chip"
• Filed 2001-04-12; published 2003-01-16; issued 2003-09-09 → § 102(b)/(e) art. (Verified via Justia and FreePatentsOnline.)
• Description: A Lexmark heater chip in which a polysilicon layer is selectively masked/etched to form at least one input for each driving transistor and plural polysilicon electrical connections, with a single metallization providing the power and ground distribution; power and ground sides of the chip are in opposing relation with transistors between them. The stated goal is eliminating the second/third metal layer.
• Claim mapping: This is the face-citation closest to claim 1 limitation (c) — polysilicon-layer interconnection to the gates/inputs of the power transistors — and to claim 4 (transistors) and claim 5-type logic (address lines to gates). It also bears on claims 2 and 8. Missing for § 102 anticipation of claim 1: it affirmatively teaches away from a second metal power/ground layer (single-metal architecture), so it does not disclose second-metal power and ground conductors over the transistor and logic areas, respectively.

4. US20030210301A1 — Xerox Corp.

• "Polysilicon feed-through fluid drop ejector"
• Filed 2002-05-08; published 2003-11-13 → § 102(a)/(e) art (within one year of filing, so § 102(b) may not apply; § 102(a)/(e) does).
• Description (title/record level): Uses polysilicon as a feed-through conductor in a drop ejector — relevant to the patent's general proposition that polysilicon interconnects can be tolerated where timing is not critical.
• Claim mapping: Potentially relevant to the polysilicon-conductor concept in claim 1 limitation (c), but directed to a different function (feed-through of drive signals, not logic-to-FET interconnection in a two-metal bus-over-circuit layout). Not a § 102 anticipation of claim 1 on the record.

5. US5144341A — Xerox Corp.

• "Thermal ink jet drivers device design/layout"
• Filed 1991-04-26; published 1992-09-01 → § 102(b) art. (Verified via Google Patents citation record.)
• Description: Driver device design/layout for thermal inkjet heads — arranging drive transistors relative to heaters for density/space efficiency.
• Claim mapping: General background for claim 1 limitations (a)–(b); no showing of the polysilicon logic interconnect or the specific two-metal bus-over-circuit split. Not an anticipation of claim 1; weak-to-moderate for claims 2 and 4.

6. US4887098A — Xerox Corp.

• "Thermal ink jet printer having printhead transducers with multilevel interconnections"
• Filed 1988-11-25; published 1989-12-12 → § 102(b) art. (Verified via Google Patents citation record.)
• Description: Early disclosure of multilevel interconnections to printhead transducers.
• Claim mapping: Bears generally on the multi-level conductor stack concept (first metal / second metal / polysilicon) in claim 1, but does not disclose the claimed placement of power and ground busses over the transistor and logic areas. Not an anticipation.

C. Complete face-of-patent citation table (all 33 listed references)

Dates below are the priority (filing) and publication dates shown in the authoritative Google Patents record for 7195341. "§ 102 potential" is stated conservatively; a full anticipation finding would require element-by-element proof from the reference text, which for most of these I have not opened in full.

Note on two extra entries that appear in the "Patent Citations (36)" sub-list: US5030971B1 is the 2000 reexamination certificate of #6, and US6153114A is a member of the #15 (US5883650/US6239820) family — not independent art.

D. Bottom line

1. No single face-of-patent citation is a clean § 102 anticipation of claim 1 based on what the records disclose. The claim's combination — first-metal actuator-to-transistor interconnect + polysilicon logic-to-transistor interconnect + second-metal power bus over the power-transistor active area + second-metal ground bus over the logic area — is not shown in any one cited document.
2. The two most dangerous single references are:
   • US6309053B1 / US6422676B1 (HP): disclose a bus overlapping the FET active area — the direct conceptual ancestor of the invention (the patent's own Fig. 7 "prior art" description), but with the ground bus over the transistor area, not the logic area, and with no polysilicon logic interconnect.
   • US20030011658A1 / US6616268B2 (Lexmark/Parish): discloses the polysilicon gate-input interconnection concept closest to limitation (c), but in a single-metal architecture.
3. Dependent-claim § 102 candidates: Claim 2 (heater resistors) — US6309053, US6422676, US6616268; Claim 3 (≥3 slots) — US5469199 (widest multi-slot architecture); Claim 4 (FETs) — US6309053, US6422676, US5144341; Claim 5 (primitive address logic/predrive/data registers) — US5644342, US6575562, US6616268; Claims 6–7 (TSR column; non-metal TSR) — no face citation appears to disclose a TSR column between the power transistors and actuators in the claimed arrangement; Claim 8 — same as claim 1 (no single-reference anticipation).
4. Litigation context flag (from earlier sections): In IPR2022-01414 the PTAB and Federal Circuit (aff'd Apr. 23, 2026) found claims 1–5 and 8 obvious (§ 103) over Torgerson US 6,412,917 and Bruce US 7,240,997 — references that are not among the 7195341 face-of-patent citations. That outcome underscores that the killing combination required two references (obviousness), consistent with my conclusion that no single face citation anticipates claim 1.

Confidence caveats: Full-text verification was possible only for the handful of references listed in Section B and item D(2) above. Descriptions of the remaining references rest on their titles, dates, and assignees as printed in the 7195341 record plus domain knowledge, and an element-by-element anticipation showing would require reading each reference in full.

Obviousness Analysis — US 7,195,341 B2 ("Power and ground buss layout for reduced substrate size")

1. Legal frame and the person of ordinary skill

Statute. The application was filed September 30, 2004, so the analysis is under pre-AIA 35 U.S.C. § 103. A claim is unpatentable if the differences between the claimed subject matter and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art ("PHOSITA"). Under Graham v. John Deere and KSR Int'l Co. v. Teleflex, the inquiry is: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; and (4) secondary considerations. KSR also directs that obviousness can be shown by "a design need or other market pressure to solve a problem and there are a finite number of identified, predictable solutions," and warns against rigid application of a teaching-suggestion-motivation test.

PHOSITA. A designer of thermal inkjet (micro-fluid ejection) printhead chips circa 2003–2004: a few years of experience in thin-film semiconductor device layout for thermal inkjet printheads, familiar with slot-fed die architecture (heater resistor arrays, FET drive arrays, decoder/predrive logic, polysilicon gate fabrication, two-metal-layer conductor stacks, ground/power bus routing, and temperature-sense-resistor structures), and aware of the persistent cost-driven pressure to shrink die width without increasing bus resistance.

Claims to evaluate. Claim 1 is the sole independent claim. For § 103 purposes its five structural limitations are, in shorthand:

• [A] columnar array of ejection actuators adjacent a fluid supply slot;
• [B] columnar array of power transistors adjacent the actuators, connected to them through a first metal conductor layer, occupying a "power transistor active area";
• [C] columnar array of logic circuits adjacent the power transistors, connected to them through a polysilicon conductor layer, occupying a "logic circuit area";
• [D] a power conductor in a second metal conductor layer overlapping at least a portion of the power transistor active area; and
• [E] a ground conductor in the second metal conductor layer overlapping at least a portion of the logic circuit area.

Dependent claims 2–7 add heater resistors (2), ≥3 fluid supply slots (3), FETs (4), logic-circuit types (5), a TSR column between power transistors and actuators (6), and non-metal TSR material (7). Claim 8 is a micro-fluid ejection head incorporating the claim-1 substrate.

Key insight from the § 102 prior-art section (incorporated by reference, not repeated here): no single face-of-patent citation cleanly anticipates claim 1. The claim's combination — first-metal actuator-to-transistor interconnect, polysilicon logic-to-transistor interconnect, second-metal power bus over the transistor area, and second-metal ground bus over the logic area — is a combination of features that were individually old and distributed across the prior art. That structure makes § 103 the natural and, as the litigation record confirms, the successful avenue of attack.

2. The strongest combination: Torgerson (US 6,412,917 family) + Bruce (US 7,240,997)

This is the combination adopted by the PTAB in IPR2022-01414 (Final Written Decision, April 9, 2024) and affirmed by the Federal Circuit on April 23, 2026 (Slingshot Printing LLC v. Canon U.S.A., Inc., No. 24-1956). I have verified the bibliographic details live: US 6,412,917 B1 (Torgerson et al., Hewlett-Packard, "Energy Balanced Printhead Design," filed 2001-01-30, issued 2002-07-02) and US 7,240,997 B2 (Bruce, Hewlett-Packard, "Fluid ejection device metal layer layouts," filed 2004-02-25, issued 2007-07-10). Two points deserve precision because the identifier strings matter:

• US 6,412,917 is a member of the same Hewlett-Packard Torgerson family whose later continuation US 6,726,311 B2 appears on the face of the '341 patent (prior-art table entry #32, "Energy balanced printhead design," priority 2001-01-30, published 2004-04-27). The family also includes the face-cited US 6,309,053 B1 (Torgerson/Hurst, "Ink jet printhead having a ground bus that overlaps transistor active regions," entry #20) and US 6,422,676 B1 (entry #24). These are cumulative disclosures from one design line and can be used interchangeably or in parallel.
• US 7,240,997 (Bruce) is not a face citation of the '341 patent, but it is § 102(e) prior art: its effective filing date (2004-02-25) precedes the '341's filing date (2004-09-30), even though it issued later (2007-07-10).

What Torgerson alone supplies (limitations [A]–[D] and much of [C])

Torgerson's slot-fed thermal inkjet printhead discloses essentially the entire physical topology of claim 1 except the precise placement of the ground conductor:

• [A]: a thin-film substructure ("die 11") with ink feed slots (a three-slot embodiment has slots 71) and columnar arrays of ink drop generators/heater resistors 56 adjacent each slot.
• [B]: columnar FET drive circuit arrays 81 adjacent the drop-generator arrays, with drain electrodes connected to the heater resistors 56 by heater-resistor leads — i.e., the transistor-to-actuator connection in the lower conductor level (the first metal conductor layer). The FET drive circuits occupy the "power transistor active area" of the die.
• [C]: columnar arrays of decoder logic circuits 35 (associated with address buses 33 and primitive-select traces 86a–86d) that control the gates of the FET drive circuits — the claimed "logic circuits." Critically for the claim's distinguishing feature, the FET drive circuits' gate structures include polysilicon fingers, and the Board credited the evidence that "as a practical matter… it's necessary that Torgerson's polysilicon gate fingers… extend to its logic circuits" — i.e., the logic-to-transistor interconnection runs through the polysilicon conductor layer. (This finding was upheld as supported by substantial evidence on appeal.)
• [D]: power conductors (primitive-select/power traces 86a–86d, routed in the upper conductor level) that overlap the FET active areas — the reference's whole point is that running a bus over the transistor active regions shrinks the die.

What Torgerson does not clearly teach is limitation [E] in its claimed form: a ground conductor in the second metal layer that overlaps the logic circuit area rather than the transistor active area.

What Bruce supplies (limitation [E])

Bruce discloses metal-layer layouts for a fluid ejection device in which a ground portion (8) is placed in the second metal layer (11) of the printhead substrate, overlying circuit/logic regions, connected by vias to first-metal ground portions. Bruce states the advantages of exactly the design choice claim 1 [E] requires:

1. "reduced energy variation due to decreased ground resistance resulting from the greater ground area";
2. it "avoids costs associated with increased die sizes which result where ground resistance is decreased by widening ground paths in the first metal layer, with corresponding increases in the die size"; and
3. it enables additional energy-variation improvement by increasing the second-metal-layer thickness.

So the only real difference between the combination and claim 1 is the destination of the ground bus: Torgerson's ground bus 181 is associated with the FET array, while claim 1 puts the second-metal ground bus over the logic area. That is precisely the modification Bruce teaches as beneficial.

Why a PHOSITA would combine them

• Same field, same problem. Both Torgerson and Bruce are thermal inkjet printhead die references from Hewlett-Packard addressing the identical engineering tension that the '341 patent's own Background describes: shrinking substrate width while keeping bus resistance (and thus energy delivered to the heater resistors) acceptable. Torgerson expressly identifies the need for a "compact" printhead with many drop generators; Bruce expressly ties second-metal ground routing to avoiding die-size increases. Where two references "from the same field of endeavor" address an "overlapping problem — reducing the substrate size," a motivation to combine is not merely colorable; it is the kind of routine design optimization KSR treats as obvious.
• Finite, predictable solutions. The design choice at issue — where to route the second-metal ground bus so it does not consume additional die width — is a layout-selection problem with a small set of known answers: over the FET active area (Torgerson's answer), over the logic area (Bruce's answer), or on a dedicated strip (the admitted prior-art Fig. 7 of the '341 patent). Picking among "a finite number of identified, predictable solutions" driven by "design need [and] market pressure" is the KSR paradigm of obviousness.
• No incompatibility. Bruce's second-metal ground bus does not require abandoning anything in Torgerson. It is a routine modification of the ground plane level in a stack that Torgerson already builds with an upper conductor level over the transistor areas. The claimed "only two metal conductor layers + polysilicon" architecture is preserved: Torgerson already uses polysilicon for the logic-to-FET path, freeing the upper metal above the logic circuits for Bruce's ground bus. The two disclosures fit together without re-engineering.
• Reasonable expectation of success. Both references describe functioning, product-grade HP printhead architectures. Combining a ground-bus-routing teaching from one HP printhead patent into another HP printhead patent of the same era would be expected to succeed; nothing in either reference suggests the modification is difficult or unpredictable.
• The '341 patent's own characterization confirms the incremental nature. The patent concedes (Fig. 7 discussion) that the prior art already routed power and ground busses in the second metal layer over the transistor active area. The claimed advance is relocating the ground bus over the logic area by exploiting the prior polysilicon logic-to-FET routing. That is a positional optimization of known conductors over known circuits — the type of change that, without unexpected results, does not clear the § 103 bar.

The counterargument and why it fails

The strongest non-obviousness argument is that Torgerson's ground bus 181 is routed in the lower metal layer (with the source terminals strapped to it), so the PHOSITA would not necessarily have moved it to the second metal layer; and that the logic circuits in Torgerson sit under first-metal power/ground interconnections that would have to be cleared before a second-metal ground bus could overlie them. The Board's answer, affirmed on appeal, is that this ignores Bruce's express teaching why a second-metal ground bus is desirable (lower resistance, no die-size penalty) and the routine nature of the relocation; the "clearing" concern is exactly what Torgerson's own polysilicon logic-to-FET routing already accommodates. Substantial evidence supported the Board on both points, and the CAFC rejected Slingshot's inherency and APA arguments.

3. Alternative combinations from the face-of-patent record

Independent of the IPR combination, the § 102 prior-art section's closest references combine naturally under § 103. Three pairings are worth articulating.

Combination 1: HP "bus-over-transistor" line (US 6,309,053 B1 and/or US 6,422,676 B1) + Lexmark/Parish polysilicon interconnect (US 2003/0011658 A1 → US 6,616,268 B2)

• US 6,309,053 / US 6,422,676 supply limitations [A], [B], [D] (columnar heater/FET arrays around feed slots; bus metallization deliberately overlapping FET active areas to shrink die width) and claim 4 (FETs), claim 2 (heater resistors).
• US 6,616,268 / US 2003/0011658 (Parish, Lexmark — the '341 patent's own assignee's earlier work) supplies limitation [C]: it teaches forming polysilicon electrical connections/inputs to each driving transistor — i.e., routing the gate-control (logic-to-power-transistor) interconnection in polysilicon rather than in a dedicated metal level.
• Why combine: the PHOSITA reads the HP references and sees that the only thing preventing the ground bus from sweeping across the logic area (not just the FET area) is that the logic-to-FET wiring occupies conductor real estate over the logic. Parish teaches the solution to exactly that congestion problem — push the control interconnection down into polysilicon. Once the polysilicon layer carries the logic-to-transistor signals (Parish), the second metal layer above the logic is freed, and the HP design philosophy (overlap the busses on circuits to save width) leads directly to placing the ground bus over the logic area: limitation [E]. The result is the claimed two-metal-plus-polysilicon stack.
• The obviousness "hook" is stronger than it first appears because Parish is a Lexmark patent on the same heater-chip architecture the '341 patent improves; the '341 inventors are presumed to have known their own company's prior chip. A § 103 case would not need to prove that Parish alone suggests the final layout — only that the PHOSITA, motivated by the shared size-reduction goal, would combine Parish's polysilicon teaching with HP's overlapping-bus teaching.
• Obstacle to address: Parish affirmatively teaches away from a second metal layer — its object is a single-metal power/ground distribution. A challenger must explain why that does not defeat the combination: Parish's teaching-away is directed at eliminating an entire metal level for cost reasons, whereas the '341 architecture keeps two metals but changes where the second-metal bus lies. The HP references independently establish that a second metal layer was routine and desirable in competing designs. On balance this combination is viable but weaker than the Torgerson + Bruce combination because of the teaching-away wrinkle; the Torgerson/Bruce pairing has no such wrinkle.

Combination 2: HP ground-bus line (US 6,309,053 / US 6,422,676) + multi-slot wide-array reference (US 5,469,199) for claim 3

Claims 3 (≥3 slots) adds nothing beyond what the HP references already show — US 6,309,053 discloses three ink feed slots 71/72/73 each feeding its own columnar arrays of drop generators, FET arrays, and ground buses — and US 5,469,199 ("Wide inkjet printhead," HP, 1995) independently shows wide multi-slot architecture. Combination is trivial for a PHOSITA scaling a proven single-slot column to three slots, as every multi-color thermal printhead manufacturer did. This is combination-of-known-elements-with-predictable-result territory.

Combination 3: Furukawa (JP 1996-108536 A) + Torgerson — the IPR's alternative ground

The IPR petition's Ground 2 paired Furukawa, a Japanese inkjet recording-head reference disclosing a drive-circuit board with columnar arrays of heaters 101 and multilayer aluminum wiring, with Torgerson supplying the fluid-supply-slot and columnar-FET/logic features Furukawa lacks. Because Torgerson already carries nearly the entire claim, Furukawa adds essentially nothing that Torgerson does not supply; this ground is a belt-and-suspenders fallback and needs no separate motivation analysis beyond the same field-of-art and size-reduction rationale. (Whether the FWD reached Ground 2 after deciding Ground 1 was not confirmable from my sources; the CAFC affirmance rests on Ground 1 alone, so the practical importance of Ground 2 is low.)

4. Dependent claims and claim 8

• Claim 2 (heater resistors): Torgerson uses heater resistors 56; so do the HP references, Parish, and essentially the entire thermal-inkjet art. Obvious as a matter of course.
• Claim 3 (≥3 slots): Torgerson's three-slot embodiment reads directly; US 5,469,199 provides independent support. Straightforward.
• Claim 4 (FETs): Torgerson's "FET drive circuits 85" is explicit. No separate inventive weight.
• Claim 5 (primitive address logic / predrive / data registers): Torgerson's decoder logic circuits 35 decode address information on address bus 33 to "turn on the FET drive circuit of an addressed or selected ink drop generator," which the Board found necessarily entails primitive address logic and predrive circuits. Face-cited US 5,644,342 (HP, "Addressing system for an integrated printhead") and US 6,575,562 (Lexmark, "Performance inkjet printhead chip layouts") independently teach on-die primitive/address decode logic. Obvious.
• Claim 8 (ejection head): once the claim-1 substrate is obvious, adding the barrier/nozzle superstructure (present in Torgerson's printhead 100A itself, and in every cited printhead reference) is the routine completion of a printhead. Obvious.

Claims 6–7 (TSR column; non-metal TSR material). These were not challenged in IPR2022-01414, so there is no agency finding on them. On the present record, the face citations do not clearly disclose a columnar TSR array interposed between the power transistors and the actuators (flagged in the prior-art section). A § 103 case on claims 6–7 would need a TSR reference (temperature-sense resistors were standard on thermal printheads of the era — e.g., for the ink-temperature sensing the '341 itself describes as known in the class B41J2/04563 art) plus a showing that using the same non-metal resistive film (TaAl or similar) for the TSR as for the heater resistors, thereby allowing an overlying second-metal power bus, was a predictable materials choice. That case is buildable but was never built, and it is now academic: claims 6–7 depend from claim 1, and claim 1 is invalidated. Under the doctrine of dependent claims, they cannot stand independently.

5. Secondary considerations (Graham factor four)

On the record available: no evidence of long-felt need, unexpected results, industry skepticism, or licensing indicating non-obviousness was credited anywhere in the IPR or on appeal. The claimed layout's own benefits (bus resistance preserved while die width shrinks) are precisely the benefits the prior art (Torgerson, Bruce) already promised from overlapping-bus layouts. Commercial success, if argued, would be contaminated by the fact that the layout appears in the patentee's own inkjet cartridges sold while Lexmark was a market participant — and the CAFC's affirmance confirms no secondary consideration overcame the prima facie case.

6. Bottom line

1. The decisive combination is Torgerson (US 6,412,917 family — equivalently the face-cited US 6,309,053 / US 6,422,676 / US 6,726,311 line) + Bruce (US 7,240,997). Torgerson supplies everything except the second-metal ground bus over the logic area; Bruce supplies that exact teaching and its rationale. Both address the same problem (substrate-size reduction without resistance penalty); the modification is a finite, predictable layout choice with a reasonable expectation of success; there is no teaching away. The PTAB so held (claims 1–5 and 8 unpatentable, April 9, 2024) and the Federal Circuit affirmed (April 23, 2026). The face-of-patent record independently corroborates that result.
2. A viable alternative without Bruce is HP's bus-over-FET layout (US 6,309,053 / US 6,422,676) combined with Lexmark/Parish's polysilicon logic-to-transistor routing (US 6,616,268 / US 2003/0011658 A1); it is slightly weaker because Parish teaches away from a second metal layer, but the HP references cure that by showing the second metal level was standard.
3. Dependent claims 2–5 and claim 8 fall with claim 1 on the same combinations; claims 6–7, though never separately tried, are dependent on the invalidated claim 1 and have no independent viability.
4. Net assessment: on any of the principal combinations, claim 1 would have been obvious to the PHOSITA defined above; the Torgerson + Bruce combination is the cleanest and is now judicially confirmed.

Confidence caveats: My live verification covered the bibliographic identities of US 6,412,917, US 7,240,997, and the US 6,309,053 family, and the PTAB FWD's own motivation analysis as excerpted in public records. The detailed claim-by-claim mapping for the FWD is drawn from those excerpts and the earlier litigation summary; I did not pull the full FWD or the CAFC slip opinion directly. Element-level citation to column/line numbers should be confirmed against Ex. 1004 (Torgerson), Ex. 1005 (Bruce), and the FWD in PTAB E2E before the combination is used in any filing.