US 7018012

I'll search for information on this specific patent number, including USPTO records and any CAFC 2026 docket activity.

Let me run additional targeted searches for CAFC activity and USPTO records.

Summary — U.S. Patent No. 7,018,012 (US7018012B2)

I verified the number against USPTO-derived records (Google Patents / Justia) and the W.D. Tex. complaint docket. US 7,018,012 B2 is the correct patent for the title below (not to be confused with similarly numbered patents such as 7,014,299 or 7,018,012-related family members).

Bibliographic data

• Title: Microfluid ejection device having efficient logic and driver circuitry
• Patent / Application: US 7,018,012 B2 (application no. 10/713,483; also published as US20050104928A1)
• Inventors: J. Glenn Edelen, George K. Parish, Kristi M. Rowe
• Original assignee: Lexmark International, Inc. (Lexington, KY) — per assignment recorded 2003-11-14
• Later assignments: Lexmark → Funai Electric Co., Ltd. (recorded 2013-05-14); Funai → Slingshot Printing LLC (recorded 2019-03-29). Google Patents currently lists Slingshot Printing LLC as assignee, with its standard caveat that the listing may be inaccurate; the USPTO assignment record chain above is the better source.
• Filing date: November 14, 2003 (also the priority date)
• Issue date: March 28, 2006
• Status: Expired – Lifetime (adjusted expiration noted as 2024-10-13; 12th-year maintenance fee paid in 2017)

Abstract (verbatim)

"A semiconductor substrate for a microfluid ejection head. The substrate includes a plurality of fluid ejection actuators disposed on the substrate. A plurality of driver transistors are disposed on the substrate for driving the plurality of fluid ejection actuators. Each of the driver transistors have an active area ranging from about 1000 to less than about 15,000 μm². A plurality of logic circuits including at least one logic transistor are coupled to the driver transistors. The driver and logic transistors are provided by a high density array of MOS transistors wherein at least the logic transistors have a gate length of from about 0.1 to less than about 3 microns."

Plain-language overview of independent claims

The patent has three independent claims (1, 13, and 22), plus dependent claims. They describe shrinking the on-chip drive/logic circuitry of microfluid (e.g., inkjet) printheads to save substrate area:

• Claim 1 — Semiconductor substrate for a microfluid ejection head: A substrate carrying (a) fluid ejection actuators, (b) driver transistors for those actuators, each driver transistor having a small active area of about 1,000 to under 15,000 μm², and (c) logic circuits (at least one logic transistor each) coupled to the driver transistors. Both the driver and logic transistors form a high-density array of MOS transistors, with at least the logic transistors having a gate length of about 0.1 to under 3 microns. In plain terms: a printhead chip whose power transistors are individually compact and whose control transistors use small (sub-3-micron) geometry to pack more function into less silicon area.

• Claim 13 — Microfluid ejection cartridge: Adds the cartridge context: a cartridge body with a fluid supply and an ejection head in fluid communication with it. The head has a semiconductor substrate with fluid ejection actuators, driver transistors each having an active-area width of about 100 to under 400 microns, and logic circuits (at least one logic transistor) operatively coupled to the drivers. Again, all driver and logic transistors form a high-density MOS array with at least the logic transistor at 0.1 to under 3 microns gate length. A nozzle plate is attached to the substrate to eject fluid when the actuators fire. Plainly: a replaceable ink/fluid cartridge whose printhead chip uses compact, fine-geometry transistors to save area.

• Claim 22 — Semiconductor substrate for an inkjet printhead (DLC variant): A substrate with heater resistors that carry a protective diamond-like carbon (DLC) layer about 1,000–3,000 Angstroms thick, driver transistors for the actuators, and logic circuits (at least one logic transistor) coupled to the drivers. Driver and logic transistors again form a high-density MOS array with at least the logic transistors at 0.1 to under 3 microns gate length. Plainly: the same high-density/small-geometry transistor scheme combined with DLC-protected heater resistors for the inkjet thermal firing elements.

(Claim 11 — "A printhead for an ink jet printer containing the semiconductor substrate of claim 1" — is formally a dependent/incorporating claim rather than a fourth independent claim.)

Litigation / CAFC status

• District court: US 7,018,012 was asserted by Slingshot Printing LLC v. HP Inc., No. 6:19-cv-00549 (W.D. Tex., Waco Division, filed 2019-09-20, Judge Alan D. Albright), where 7,018,012 is expressly listed among the patents-in-suit in the complaint. Public reporting indicates the Slingshot–HP disputes were settled and Slingshot moved to dismiss the HP lawsuits.
• PTAB: HP filed related inter partes review petitions (e.g., IPR2020-01084/-01085/-01086/-01090) referencing these Slingshot complaints; those proceedings pertained to other Slingshot patents, and I did not find a specific IPR directed to 7,018,012 in these searches.
• CAFC 2026: I searched for CAFC 2026 docket activity for "7018012" and found no CAFC appeal entries. I have no authoritative evidence of any pending 2026 Federal Circuit case involving this patent.

Uncertainty notes

• I did not access the USPTO Patent Center or Public PAIR directly in these searches; bibliographic data is corroborated by Google Patents/Justia USPTO-derived records and court filings.
• The "current assignee" (Slingshot Printing LLC) is from assignment records; the patent is expired, and Google's legal-status fields carry disclaimers.
• No CAFC 2026 docket results were located; absence of results is not definitive proof that none exists, but I found no public record of one.

I'll search for litigation involving US Patent 7018012.

The initial searches returned no results. Let me try broader queries.

The search results confirm Slingshot Printing LLC (assignee of the '012 patent) has been active in litigation. Let me search for the specific case number referenced on the patent record and related filings.

Litigation Involving U.S. Patent No. 7,018,012 (US7018012B2, "Microfluid ejection device having efficient logic and driver circuitry")

Based on my searches, yes, known litigation exists. The patent (interpreted literally as US 7,018,012 B2, per the Google Patents record you provided) has been asserted by Slingshot Printing LLC, the current assignee (via Funai Electric Co., Ltd., which acquired it from Lexmark International, Inc.).

Confirmed case: Slingshot Printing LLC v. HP Inc.

• Plaintiff: Slingshot Printing LLC (Delaware LLC, Silver Spring, MD)
• Defendant: HP Inc.
• Jurisdiction: U.S. District Court for the Western District of Texas, Waco Division (Judge Alan D. Albright presiding)
• Case number: 6:19-cv-00549
• Filing date: September 20, 2019 (the complaint bears docket header "Case 6:19-cv-00549 Document 1 Filed 09/20/19")
• Patents asserted: US 7,018,012 was one of ten patents-in-suit in that complaint, listed together with 6,213,587; 6,575,563; 6,676,246; 6,786,575; 7,195,341; 7,290,864; 7,410,246; 7,484,823; and 7,559,629 (confirmed from the complaint, filed as an exhibit in IPR2020-01086).
• Outcome/current status: Settled and dismissed. HP's securities filings disclose that on January 31, 2021, HP and Slingshot entered into an agreement to resolve all litigation, after which the lawsuits (including this one) were dismissed. Industry reporting (Actionable Intelligence / The Recycler) confirms Slingshot moved to dismiss its suits against HP following the settlement.

Context you should know (broader Slingshot v. HP campaign)

The '012 patent was part of a larger, multi-complaint patent campaign by Slingshot against HP in the W.D. Tex.:

• June 11, 2019: Slingshot filed three initial complaints (e.g., 6:19-cv-00362) asserting sixteen patents.
• September 20, 2019: Slingshot filed a fourth complaint (6:19-cv-00549, the case identified above, which included the '012 patent) and amended the three earlier complaints — collectively asserting thirty-two patents.
• January 23, 2020: A fifth complaint was filed after one patent was dropped and re-asserted.
• Per HP's disclosures, the five co-pending litigations collectively asserted 31 patents against HP's inkjet printers, cartridges, and printheads, and were all resolved by the January 31, 2021 settlement agreement.

Other possible proceedings — with a caution

• The Google Patents record for US7018012 itself flags a Texas Western District Court matter at 6:19-cv-00549, which is consistent with the case above.
• I also found inter partes review and Federal Circuit activity involving Slingshot Printing LLC and Canon U.S.A., Inc./Canon Inc. (e.g., IPR2023-00312/-00313, Federal Circuit appeals) and Slingshot v. Canon district-court litigation, plus related PTAB challenges by HP. However, I could not confirm from the search results available that US 7,018,012 specifically was asserted in the Canon cases — the Canon disputes I confirmed involved other Slingshot/Lexmark patents (e.g., 7,484,823; 7,594,708; and temperature-sensor/chip patents). I do not have high-confidence evidence tying the '012 patent to the Canon litigation, so I am flagging it as unverified rather than asserting it.

Bottom line

The one litigation I can confirm with reasonable specificity involving US 7,018,012 is Slingshot Printing LLC v. HP Inc., No. 6:19-cv-00549 (W.D. Tex., filed Sept. 20, 2019), which was resolved by settlement and dismissal effective around January 31, 2021. If you need docket-level confirmation of the dismissal order or the exact list of claims asserted, PACER (W.D. Tex.) or the Unified Patents litigation portal would be the authoritative sources to check next.

I'll verify whether any PTAB proceedings exist for this patent, starting with the USPTO ODP data and then web searches for anything not yet indexed.

Initial searches show no IPR activity. Let me check more specifically, including the known litigation (Texas Western District Court case 6:19-cv-00549) and the Unified Patents/Slingshot chain.

I'm finding useful litigation context. Now let me specifically hunt for IPR proceedings against this exact patent — HP and Canon both litigated against Slingshot, and HP filed IPRs on several Slingshot patents. I need to confirm whether any petition named US 7,018,012.

Proceedings overview

Total AIA trial proceedings on US 7,018,012: 0 (0 active · 0 with claims invalidated · 0 with claims sustained · 0 settled · 0 institution-denied).

The USPTO Open Data Portal (ODP) block supplied in this prompt reports no AIA trial proceedings (IPR/PGR/CBM) for US 7,018,012, and my web searches did not surface any petition, institution decision, or Final Written Decision naming this patent. There is therefore no PTAB-created estoppel, no canceled claim, and no Board validity finding of any kind on this patent. For a defendant, that cuts both ways: all 30 claims remain exactly as issued and are entirely UNTESTED at the PTAB, but the patent expired by adjusted term on 2024-10-13 (status "Expired – Lifetime"), so any exposure is limited to pre-expiration damages and cannot be defeated by pointing to a prior IPR win.

Because there are no proceedings, there are no per-proceeding sections to populate. What follows is the verification trail, the adjacent-proceeding context you should know about (so you don't confuse it with this patent), and the strategic read.

Adjacent activity — NOT on US 7,018,012 (do not conflate)

The patent's Google Patents file shows heavy district-court assertion by Slingshot Printing LLC (the current assignee, which took the Lexmark/ Funai inkjet portfolio in 2019):

• Slingshot Printing LLC v. HP Inc., 6:19-cv-00549 (W.D. Tex., Waco, Judge Albright, filed 2019-09-20) — asserted 10 patents including US 7,018,012 (along with 6,213,587; 6,575,563; 6,676,246; 6,786,575; 7,195,341; 7,290,864; 7,410,246; 7,484,823; 7,559,629). A follow-on Austin action (1:20-cv-00187) and a settlement with HP (joint dismissal, ~2021) followed.
• HP responded with IPRs on other patents in the same Slingshot portfolio — e.g., IPR2020-01084/-01085/-01086/-01090 (IPR2020-01086 is captioned as a review of US 7,014,299, not 7,018,012) and IPR2020-01659, which was terminated on 2021-03-29 after the parties settled (settlement agreement treated as business confidential). None of these petitions, so far as the record shows, challenged US 7,018,012.
• A 2026-07-16 Law360 headline reports the Federal Circuit affirmed PTAB decisions invalidating all challenged claims in three Slingshot patents (chips/temperature sensors in inkjet printers) in Canon-related proceedings. I could not confirm — and therefore do not assert — that US 7,018,012 is among those three patents. This is the single most important item to verify before advising a client, because if 7,018,012 were among them it would change this analysis completely; nothing in the search results places it there.

Strategic summary

Claim status. All 30 claims of US 7,018,012 (independent claims 1, 13, 22 and their dependents) are SUSTAINED by default — i.e., UNTESTED — before the PTAB. No claim has been canceled, no claim has been amended in an IPR, and no Board panel has ever construed a term of this patent. The only "narrowing" event in the file is the ordinary expiration of the term (adjusted expiration 2024-10-13; maintenance fees paid through the 12th year, large entity).

Estoppel landscape (§ 315(e)(2)). There is no petitioner and no estoppel running against anyone from an IPR on this patent. For a defendant facing assertion today, all prior-art grounds remain fully available — § 102, § 103, and § 112 challenges can be raised fresh in district court or in a new petition (subject to the § 315(b) one-year bar measured from service of this complaint, which will usually have run by now given the 2019–2020 suits). Because the patent is expired, the practical battleground is damages for pre-2024-10-13 conduct only, plus the ordinary clear-and-convincing validity defense in court.

Pattern signals. (1) No repeat-petitioner pattern exists on this patent — the serial IPR activity by HP targeted sibling portfolio patents, and those that reached termination did so by settlement, which leaves no estoppel and no precedential validity findings against the portfolio. (2) Slingshot's ownership chain (Lexmark → Funai Electric (2013) → Slingshot Printing LLC (2019)) is a monetization/NPE posture, and the patent has been asserted in at least the W.D. Tex. actions; the "Unified Patents" references on the Google Patents page are litigation-data-source attributions, not evidence Unified Patents is a party. (3) The absence of any IPR on 7,018,012 despite years of high-stakes litigation is itself a signal: challengers either valued the other portfolio patents more highly, viewed this patent as a weak damages driver, or the early settlement mooted the need. Do not read the absence as "the patent is strong."

Recommended next steps

1. Confirm the Canon/CAFC item before anything else. Pull the 2026-07-16 Federal Circuit affirmance identified by Law360 and confirm the three Slingshot patent numbers. If US 7,018,012 is not among them (the available evidence suggests the challenged patents were different chip/temperature-sensor patents), this report's "no PTAB activity" conclusion stands.
2. Verify directly against USPTO PTAB E2E / ODP. Run a patent-number search for 7,018,012 in the PTAB Trial Search (uspto.gov/PTAB) and the ODP API to confirm no petition has been filed that post-dates the most recent ingest in the structured block. Given the 2026 Canon-related activity in the portfolio, re-check monthly.
3. If you are a defendant being newly served: there are no FWDs to cite and no IPR-based leverage to invoke. Your play is (a) the expired-patent limitation — damages only for acts before 2024-10-13 and no injunction; (b) full merits invalidity in court with no § 315(e)(2) estoppel constraints; and (c) if you are within one year of service, consider whether a fresh IPR is worth the cost on a patent whose remaining value is capped at pre-expiration damages.
4. If you are evaluating the portfolio-wide threat: the HP IPRs (IPR2020-01084/-01085/-01086/-01090, IPR2020-01659) and the Canon IPRs show the PTAB is receptive to challenges on neighboring Slingshot/Lexmark inkjet patents — useful precedent and expert-witness material for any new petition, even though none of it is binding on this patent.

Bottom line, stated plainly: No IPR, PGR, or CBM has ever been filed on US 7,018,012, so no claim is dead and no claim is PTAB-hardened — the patent is simply expired and PTAB-untested. Any advice implying "the troll has no case because claims were canceled" would be wrong on this record; the accurate defensive headline is "expired patent, untested claims, no estoppel, full invalidity defense available."

Inventors

• J. Glenn Edelen — employer at filing: Lexmark International, Inc. (Lexington, KY), per the original assignment of inventors' interest.
• George K. Parish — employer at filing: Lexmark International, Inc. (Lexington, KY).
• Kristi M. Rowe — employer at filing: Lexmark International, Inc. (Lexington, KY).

All three executed an assignment to Lexmark on the filing date (2003-11-14), reel 014708/0465. No unusual post-filing departure pattern was found in the records retrieved; the file history and litigation record do not show inventor movement relevant to the later transfers (the 2013 and 2019 transfers were corporate portfolio transactions, not inventor-driven).

Original assignee

Lexmark International, Inc. (Lexington, Kentucky) is the entity on the issued patent and the original assignee.

• Product embodiment: Yes. Lexmark was a major operating ink-jet printer / printhead manufacturer and shipped thermal inkjet printheads of the type claimed (driver + logic MOS transistors co-located with heater resistors on a semiconductor substrate).
• Line of business: Imaging — printers, printheads, and supplies (ink/toner), plus software/services in later years.
• Current status: Still operating, but restructured: taken private in 2016 by Apex/PAG consortium (delisted from NYSE), and — critically — Lexmark exited the consumer inkjet business around 2012–2013 and sold its inkjet technology and patent portfolio to Funai Electric Co., Ltd. in that process (reel 030416/0001). Lexmark therefore no longer owns this patent and no longer sells the consumer inkjet products that would embody it.

Assignment timeline

Recorded assignments for US 7,018,012 (source: Google Patents legal-events feed, which mirrors the USPTO assignment database; reel/frame numbers as recorded):

• 2003-11-14 (executed) / recorded 2003-11-14 — Reel 014708/0465

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: J. Glenn Edelen, George K. Parish, Kristi M. Rowe (inventors)
  • Assignee: Lexmark International, Inc.
  • Correspondent: not retrievable in this session (USPTO Assignment Center record was not pulled; Google Patents does not display the correspondent). No recurrence flag possible on this link without reel-level correspondent data.
  • Context: Original employer assignment from inventors to Lexmark on the filing date — standard, non-event.

• 2013-04-01 (effective date) / recorded 2013-05-14 — Reel 030416/0001

  • Conveyance: Assignment
  • Assignor: Lexmark International, Inc.; Lexmark International Technology, S.A.
  • Assignee: Funai Electric Co., Ltd. (Japan)
  • Correspondent: not retrievable in this session (see caveat above).
  • Context: Portfolio sale — Lexmark transferred its inkjet patent assets (this patent included) to Funai as part of Lexmark's exit from the consumer inkjet business; a strategic divestiture, not a bankruptcy sale.

• 2019-03-29 (executed and recorded) — Reel 048745/0551

  • Conveyance: Assignment
  • Assignor: Funai Electric Co., Ltd.
  • Assignee: Slingshot Printing LLC (Delaware LLC; address per complaint: 8455 Colesville Road, Suite 830, Silver Spring, MD 20910)
  • Correspondent: not retrievable in this session (see caveat above).
  • Context: Transfer of the Funai/Lexmark inkjet portfolio into a licensing/assertion LLC — the step that immediately preceded Slingshot's first infringement campaign against HP (suit filed 2019-09-20, W.D. Tex. 6:19-cv-00549, naming US 7,018,012 among ten patents).

Caveat on correspondents: The correspondent-of-record field is visible only in the USPTO Assignment Center reel images, which I could not retrieve in this session. All three reel/frame numbers above are confirmed from the Google Patents legal-events record; the correspondent names should be verified by pulling each reel at https://assignmentcenter.uspto.gov/ before relying on the "repeat correspondent" analysis. I have not fabricated any correspondent.

Timeline diagram

timeline
    title Ownership of US 7018012
    2003 : Filed by Lexmark inventors
         : Assigned to Lexmark International
    2006 : Patent granted
    2013 : Sold to Funai Electric
    2019 : Assigned to Slingshot Printing LLC
         : Slingshot sues HP in Texas

NPE / troll-pattern signals

1. Shell-entity transfer — present. Reel 048745/0551 (recorded 2019-03-29) moved the patent from Funai (an operating electronics company) to Slingshot Printing LLC, a Delaware LLC whose only stated place of business is a single suite (8455 Colesville Road, Suite 830, Silver Spring, MD 20910, per the HP complaint). Slingshot sells no products; trade press (Actionable Intelligence) describes it as "a non-practicing entity that has the rights to a slew of inkjet printing patents that formerly belonged to [Funai/Lexmark]."

2. Known asserter in the chain — present. Slingshot Printing LLC is a high-frequency patent plaintiff: it sued HP Inc. in W.D. Tex. (6:19-cv-00549, filed 2019-09-20, asserting US 7,018,012 among ten patents; refiled/reassigned as 1:20-cv-00187/6:20-cv-00048) and Canon in E.D.N.Y. (2:22-cv-00123 and 2:22-cv-01852, 2022). Unified Patents classifies Slingshot as "NPE (Patent Assertion Entity)" in the related IPR proceedings (e.g., IPR2022-01416). It is not on the classic Acacia/Marathon/IPNav list, but it is a confirmed, litigating NPE per Unified Patents and RPX-tracked dockets.

3. Repeat correspondent across the chain — unclear (insufficient data). Correspondent names on reels 014708/0465, 030416/0001, and 048745/0551 could not be retrieved in this session. Note: the litigation counsel for Slingshot (Raymond W. Mort III, Ronald M. Daignault, Chandran B. Iyer, et al. on 6:19-cv-00549) is a distinct data point from the assignment correspondent, and no assignment-correspondent recurrence can be verified here. Pull the three reels at assignmentcenter.uspto.gov to complete this check.

4. Cascading transfers — not present. Only two post-original transfers exist (Lexmark→Funai in 2013; Funai→Slingshot in 2019), separated by ~6 years. This is not a rapid chained-LLC cascade.

5. Pre-litigation transfer — present. The Funai→Slingshot assignment was recorded 2019-03-29 (reel 048745/0551) and Slingshot's first infringement suit naming this patent — Slingshot v. HP, 6:19-cv-00549 — was filed 2019-09-20, i.e., within six months. The transfer to the asserting LLC immediately before suit is the classic standing/venue-enabling arrangement.

6. Bankruptcy fire-sale — not present. Lexmark did not enter bankruptcy; the 2013 Funai transfer (reel 030416/0001) was a negotiated divestiture on Lexmark's exit from inkjet. (Funai's own later financial distress occurred after the 2019 Slingshot transfer and was not the cause of it; I could not independently verify Funai's later bankruptcy filings in this session.)

7. Privateering — present (circumstantial). Funai — the operating company that owned the former-Lexmark inkjet portfolio — transferred it to Slingshot, which then asserted against operating printer competitors HP and Canon. The W.D. Tex. court ordered production of "any agreements between Slingshot Printing LLC (and any affiliates) and Funai Electric Co., Ltd. (and any affiliates)" (docket text, 1:20-cv-00184), confirming the Funai–Slingshot relationship was central and non-arm's-length in character, though the revenue-share terms themselves are not public. This is the classic privateer shape, but I cannot cite a public agreement, so weight it accordingly.

8. Defensive aggregator (anti-NPE) — not present. The chain terminates at Slingshot, an asserting NPE; no RPX/AST/LOT/Unified/OIN involvement. (Inverse signal: patents in this portfolio have been heavily IPR-challenged — Canon IPRs such as IPR2022-01415/01416 and IPR2023-00312 — and several claims were invalidated on appeal, so the portfolio has been substantially weakened rather than "neutralized" by a defensive buyer.)

Verdict

NPE — high confidence.

Three strong, independently verifiable signals drive this: (1) the shell-entity transfer of the patent from an operating company (Funai) to a product-less Delaware LLC — Slingshot Printing LLC — at reel 048745/0551 (recorded 2019-03-29); (2) Slingshot's confirmed status as a litigating NPE, per Unified Patents' own NPE classification and its infringement suits against HP (6:19-cv-00549, naming US 7,018,012) and Canon; and (3) the pre-litigation timing — assignment recorded 2019-03-29, first suit filed 2019-09-20, within six months. The only unverified element is correspondent recurrence (signal 3), which requires pulling the reel images at the Assignment Center.

Verification links:

• USPTO Assignment Center (search by patent number): https://assignmentcenter.uspto.gov/
• Google Patents legal events for US 7,018,012: https://patents.google.com/patent/US7018012/en
• First asserted in Slingshot v. HP (W.D. Tex. 6:19-cv-00549): https://portal.unifiedpatents.com/litigation/Texas%20Western%20District%20Court/case/6%3A19-cv-00549

I'll research this systematically. First, let me verify the patent and its citation list against USPTO records, then examine each cited reference for § 102 anticipation analysis.

Let me search for the key Xerox and HP references cited against the '012 patent.

Now let me examine the remaining cited references — Canon, ITRI, Silverbrook, and the HP family.

I have gathered sufficient verified data on the patent, its claims, and the cited art. The tool-use limit has been reached, so I will now complete the analysis from the verified records already retrieved. I'll be explicit about which limitations I could verify from full text versus which I could not, and I will not fabricate content for references whose full text I could not retrieve.

Prior-Art Analysis — US 7,018,012 B2

Governing legal framework (important — pre-AIA statute)

US 7,018,012 was filed November 14, 2003, so pre-AIA 35 U.S.C. § 102 governs. Practical cutoffs for the cited art:

• § 102(b): Patented or described in a printed publication more than one year before 2003-11-14 → public before 2002-11-14.
• § 102(a): Known/used/patented/described by others before the applicant's invention date → published between 2002-11-15 and 2003-11-13 (or earlier, if the applicant's invention date is later than the reference date).
• § 102(e): A U.S. patent whose application was filed by another before 2003-11-14, even if it issued after the '012 filing date (relevant for US 6,666,545, granted 2003-12-23).

The claims to test

• Claim 1 (semiconductor substrate for a microfluid ejection head): fluid ejection actuators + driver transistors each having an active area of ~1,000 to <15,000 μm² + logic circuits (≥1 logic transistor) coupled to the drivers, all as a high-density MOS array with at least the logic transistors at 0.1 to <3 μm gate length.
• Claim 13 (ejection cartridge): adds cartridge body/fluid supply, nozzle plate, and requires driver transistors of active-area width ~100 to <400 μm and logic-transistor gate length 0.1–<3 μm.
• Claim 22 (inkjet printhead substrate): same MOS array/logic geometry combined with heater resistors having a diamond-like-carbon (DLC) protective layer 1,000–3,000 Å thick.
• Notable dependent claims: heater resistance 70–150 Ω (3, 14, 23); LDD drain (4, 16, 24); driver active-area width 100–400 μm (5, 25); gate-selection logic (6, 17, 26); driver on-resistance <20 Ω (7, 18, 27); LDD source and drain (8, 19, 28); driver gate length 0.1–<3 μm (9, 21, 29); driver channel length 0.1–<3 μm (10, 30); DLC layer (12, 20); printhead (11).

Key analytical caveat: The claims issued over this art, meaning the examiner did not find any single reference to disclose all limitations. The three limitations that recur as the gating gaps in nearly every reference are the numeric ranges — driver active area (1), driver active-area width (13), logic gate length 0.1–<3 μm (all three independents), and the DLC protective layer (22, 12, 20). A § 102 anticipation requires every element in a single reference, arranged as claimed; a reference that misses one numeric limitation cannot anticipate as a matter of law (only obviousness combinations under § 103 could reach the claim).

Tier 1 — Closest art: Xerox monolithic thermal-inkjet chips (driver + logic + resistors on one substrate)

1. US 4,947,192 — "Monolithic silicon integrated circuit chip for a thermal ink jet printer"

• Inventors/Assignee: Hawkins et al.; Xerox Corporation
• Filed: March 7, 1988 | Granted: August 7, 1990 (verified from Google Patents and the EP 0494076 file wrapper, which describes it as the foundational "eleven mask" NMOS chip)
• Description: The foundational Xerox chip: MOS transistor switches (78, 80, 82) monolithically integrated on the same silicon substrate as polysilicon bubble-generating heater resistors, with on-chip addressing circuitry — verified from the abstract ("monolithic integration of MOS transistor switches … onto the same silicon substrate containing the resistive elements," single polysilicon layer, resistor on 1–4 μm field oxide). IEEE/Hawkins profile confirms the device family integrated 5-V addressing logic, 13-V predriver circuitry, and 40-V MOSFETs with the heaters.
• § 102 mapping: Discloses claim 1[A]–[D] and 22's structural core: substrate + heater resistors + on-substrate driver MOS transistors + on-substrate logic circuits. Missing for § 102: the driver active-area range of 1,000–<15,000 μm² (claim 1[C]) and the logic gate length of 0.1–<3 μm (1[E]) — the process era used ~5 μm gates (EP 0494076 states phosphorus lateral diffusion "under the 5 micron (μm) gates" was a concern in the '192 process). No DLC (22).
• Verdict: Cannot anticipate any independent claim standing alone (numeric limits absent); strongest § 103 primary reference for claims 1 and 13's structural elements. Does not anticipate.

2. US 5,010,355 — "Ink jet printhead having ionic passivation of electrical circuitry"

• Inventors/Assignee: Hawkins et al.; Xerox
• Filed: December 26, 1989 | Granted: April 23, 1991
• Description: Companion to '192; adds ionic (mobile-ion) passivation protection for the monolithically integrated MOS drive/address circuitry against conductive inks. Verified as incorporated-by-reference base art in US 6,102,528.
• § 102 mapping: Same structural coverage as '192 (actuators/drivers/logic on one substrate). Passivation is a dielectric/ionic barrier, not a DLC layer — so dependent claims 12/20 and independent claim 22's DLC limitation are not met.
• Verdict: No single-reference anticipation of 1/13/22; numeric driver/logic geometry limitations and DLC absent.

3. US 5,075,250 — "Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead"

• Inventors/Assignee: Hawkins et al.; Xerox
• Filed: January 2, 1991 | Granted: December 24, 1991
• Description: Process companion to '192 — verified full-text excerpts show the reduced-mask phosphorous implant process producing logic enhancement/depletion devices, drivers, and transducers on one chip, with lightly doped source/drain regions (relevant to dependent claims 4, 8, 16, 19, 24, 28 requiring LDD).
• § 102 mapping: A method claim for making the chip; as apparatus art it shows the same architecture as '192. Missing: numeric active-area and sub-3 μm logic-gate limits; no DLC.
• Verdict: No anticipation; supports LDD dependent claims only in combination.

4. US 5,081,473 — "Temperature control transducer and MOS driver for thermal ink jet printing chips"

• Inventors/Assignee: Hawkins et al.; Xerox
• Filed: July 26, 1990 | Granted: January 14, 1992
• Description: Verified from the full text: a MOS driver element with an n⁻ drift layer and field plate lies on the same silicon chip as the resistive transducer; temperature-control transducer; ~35–40 V common bus. Demonstrates co-integration of a high-voltage MOS driver with heater resistors and control on one die.
• § 102 mapping: Covers claim 1[B]–[D] structurally. Missing: active-area range, logic gate length range, and (for 13) the cartridge context and (for 22) DLC.
• Verdict: No anticipation of the independents due to missing numeric limitations.

5. US 6,102,528 — "Drive transistor for an ink jet printhead"

• Inventors/Assignee: Burke et al.; Xerox (confirmed from patent full text)
• Filed: October 17, 1997 | Granted: August 15, 2000
• Description: Verified in detail: a drive transistor for heating elements of a high-resolution thermal inkjet printhead integrally formed on p-type silicon within a printhead containing both the heating elements and printhead addressing circuitry; LDD n⁻ drift region + n⁺ drain contact + p-type pocket implant; reduced source-drain spacing to support resolutions to 1200 spi "without increasing the required substrate area." One embodiment (claim 9) specifies a gate length of 3 μm, drift length 3 μm, breakdown >65 V.
• § 102 mapping: This is the closest single reference to claim 1's architecture: substrate + heaters + driver transistor + addressing circuitry co-integrated; LDD drain (dep. claims 4/16/24); compact transistor spacing for reduced area (the concept behind 1[C]). Critical gaps: (i) its compact-geometry teaching is aimed at the driver (gate length 3 μm — at or above the claimed logic ceiling of "<3 μm"), while claim 1/13/22 require the logic transistors to be 0.1–<3 μm; (ii) no express disclosure of driver active area of 1,000–<15,000 μm² or width of 100–<400 μm; (iii) no DLC; (iv) no cartridge claim.
• Verdict: Does not anticipate claim 1 (or 13/22). The pocket-implant/LDD driver structure and the reduced-area objective make it the strongest § 103 primary reference against claims 1, 9/10/21/29/30 and the LDD dependents.

Tier 2 — Closest art: Hewlett-Packard compact-printhead FET family (2001–2003)

6. US 6,422,676 B1 — "Compact ink jet printhead"

• Inventors/Assignee: Torgerson et al.; Hewlett-Packard Company
• Filed: June 19, 2001 | Granted: July 23, 2002
• Description: Verified from the full text: inkjet printhead with a silicon thin-film substructure (die) in which active devices including FET drive circuits are formed in the top of the silicon substrate (gate-oxide/polysilicon-gate layer), alongside patterned thin-film heater resistors, passivation layers, barrier layer, and orifice plate; FET drive circuit array and ground bus layouts disclosed. A compact-layout printhead die.
• § 102 mapping: Covers claim 1[A]/[B]/[C-structure]/[D] and, combined with the barrier/orifice-plate disclosure, the cartridge/printhead context of claim 13 (substrate + drivers + logic + nozzle plate) and dependent claim 11. I could not verify from retrieved text any express disclosure of the claimed driver active area 1,000–<15,000 μm² (claim 1), driver width 100–<400 μm (claim 13), logic gate length 0.1–<3 μm, or DLC.
• Verdict: No anticipation of any independent claim on the verified record; excellent § 103 secondary reference.

7. US 6,478,404 B2 — "Ink jet printhead"

• Inventors/Assignee: Torgerson, Browning, MacKenzie, Miller, Bakkom; Hewlett-Packard (verified from the patent PDF and the IPR2020-01086 exhibit copy)
• Filed: January 30, 2001 | Granted: November 12, 2002 (one day inside the § 102(b) one-year bar)
• Description: Verified: an inkjet printhead having three columnar arrays of drop generators (heater resistors) producing small drop volumes for multipass printing at resolution ≥1/(2P), and three columnar arrays of FET drive circuits respectively adjacent the columnar arrays of drop generators — a narrow, densely packed die layout.
• § 102 mapping: Discloses substrate + plural heater-resistor actuators + plural FET driver circuits + (implied) drive/select logic, arranged in dense columnar arrays adjacent one another — the same "high-density array" concept as claim 1. Missing (verified): none of the retrieved text quantifies driver active area (1[C]), driver width (13), or sets logic gate length at 0.1–<3 μm (1[E]); no DLC (22).
• Verdict: No anticipation of the independents on the verified record; strong § 103 combination reference (and was in fact used by HP as prior art in the Slingshot portfolio IPRs).

8. US 6,488,363 B2 — "Energy balanced printhead design"

• Inventors/Assignee: Torgerson; Hewlett-Packard
• Filed: January 30, 2001 | Granted: December 3, 2002
• Description: Energy-balancing design across drop generators (resistor/power-balance circuitry). Related continuation 6,726,311 (verified) claims columnar FET arrays with gate-oxide thickness ≤800 Å and ≥100 Ω resistors — the same design family.
• § 102 mapping: Same substrate/FET/heater architecture as the HP family; adds power/energy-balance context. Missing the same numeric limitations (active area, <3 μm logic gate length, DLC).
• Verdict: No anticipation of independents; relevant to dependent claims 3/14/23 (heater resistance ≥100 Ω appears in the family).

9. US 6,523,935 B2 — "Narrow ink jet printhead"

• Inventors/Assignee: Torgerson et al.; Hewlett-Packard
• Filed: January 30, 2001 | Granted: February 25, 2003
• Description: Narrow printhead die — compact layout of drop generators and FET drive circuits to minimize die width. The W.D. Tex./WO-family record shows the '012 family's own WO application cites it, so it was in the examiner's art stack.
• § 102 mapping: Narrowing die width is the same design motivation as '012's active-area reduction, but the retrieved record does not show the specific 1,000–<15,000 μm² driver-active-area or 100–<400 μm width numbers, nor the logic gate-length range, nor DLC.
• Verdict: No anticipation; § 103 secondary reference.

Tier 3 — Canon recording-head art (heater + power MOSFET + logic on one substrate)

10. US 6,302,504 B1 — "Recording head and recording apparatus using the same"

• Inventors/Assignee: Imanaka, Mochizuki, Kasamoto, Furukawa, Mori, Watanabe, Ozaki; Canon (verified via Espacenet/Justia)
• Filed: June 26, 1996 | Granted: October 16, 2001
• Description: Verified in detail: a recording-head substrate with electrothermal transducers (heaters), MOS power transistors (nMOSFETs) connected in series with each heater, and MOS logic circuits (shift register, latch, AND gates, voltage converter/level shifter boosting gate drive) all on a single substrate. Claim 32 expressly discusses gate-length variation of the MOS power transistor in manufacturing — showing small-geometry MOS fabrication awareness.
• § 102 mapping: The most complete structural match to claim 1[D]/[E]-concept (logic circuits driving MOS power transistors) and claim 13's cartridge context (claims 25–26 add carriage/power supply — a printer cartridge environment). Missing: no verified disclosure of the 1,000–<15,000 μm² driver active area or 100–<400 μm width; no express logic-gate-length range of 0.1–<3 μm (it discusses gate-length variation correction, not a sub-3 μm logic geometry); no DLC (22); not a "microfluid ejection cartridge" per se as claimed in 13.
• Verdict: No anticipation on the verified record; among the strongest § 103 references for claims 1 and 13.

11. US 2002/0125511 A1 — "Semiconductor device, method of manufacturing the same and liquid jet apparatus"

• Inventor/Assignee: Mineo Shimotsusa; Canon
• Filed: February 16, 2001 | Published: September 12, 2002
• Description: Canon liquid-jet (inkjet) head substrate with electrothermal conversion elements and switching insulated-gate transistors (per the family record; Canon's later EP/US relatives describe heater-driving NMOS with logic on one substrate). Not retrieved in full text.
• § 102 mapping: Likely covers the substrate + heater + switching-transistor + logic architecture of claims 1/13. Cannot verify any numeric limitation from retrieved text; flag as requiring full-text check before reliance.
• Verdict: No anticipation demonstrable on this record.

12. US 5,911,111 — "Method of manufacturing an insulated gate transistor"

• Inventors/Assignee: Kataoka et al.; Canon
• Filed: January 18, 1995 | Granted: June 15, 1999
• Description: A manufacturing method for an insulated-gate transistor (MOSFET). Canon recording-head process technology; not itself a printhead apparatus disclosure.
• § 102 mapping: As a method it cannot anticipate the apparatus claims 1/13/22. Potentially relevant only to process limitations (none present in the claims).
• Verdict: No anticipation.

Tier 4 — Remaining U.S. and foreign citations

13. US 6,592,207 B1 — "Power distribution arrangement for an inkjet printhead"

• Inventor/Assignee: Kia Silverbrook; Silverbrook Research Pty Ltd
• Filed: October 16, 1998 | Granted: July 15, 2003
• Description: Power/ground distribution architecture for large inkjet nozzle arrays with drive transistors and CMOS control logic. Not retrieved in full text.
• § 102 mapping: Discloses a large integrated printhead with drivers + logic but is directed to power distribution (bus layout), not transistor active-area minimization or sub-3 μm logic geometry. Missing numeric limits; no DLC.
• Verdict: No anticipation; § 103 secondary art.

14. US 6,666,545 B2 — "Driver transistor structure of inkjet print head chip and the method for making the same"

• Inventors/Assignee: Liu et al.; Industrial Technology Research Institute (ITRI)
• Filed: October 26, 2001 | Granted: December 23, 2003 — after the '012 filing date (2003-11-14)
• Description: Driver-transistor structure (LDD-type source/drain engineering, refractory plugs to prevent spiking, per the family CN1206104C and related US 6,841,830 record) for inkjet printhead chips.
• § 102 timing caveat: Granted/published after the '012 filing date, so it is not § 102(a)/(b) prior art. Because it was filed (2001-10-26) by a different inventive entity before the '012 filing, it is potentially § 102(e) prior art if the earlier-filed application supports the disclosure. This is the one citation whose timing, not just content, must be vetted before any § 102 reliance.
• § 102 mapping: Driver-transistor structure art for an inkjet chip. Retrieved text does not show the '012 numeric driver-area or logic-gate-length limits or DLC.
• Verdict: No anticipation shown; possible § 102(e) art for obviousness only.

15. WO 2000/061372 A1 — "Drive circuit for a thermal ink jet printhead"

• Applicant: Olivetti Lexikon S.p.A.
• Filed: April 12, 1999 | Published: October 19, 2000
• Description: Drive circuit for a thermal inkjet printhead. Not retrieved in full text; per title it is circuit-level (drive/select) art rather than a substrate-layout disclosure.
• § 102 mapping: Cannot be mapped to the numeric transistor-geometry limitations without full text; title-level disclosure does not reach claims 1/13/22.
• Verdict: No anticipation demonstrable on this record.

16. US 6,365,917 B1 — "Semiconductor device"

• Inventor/Assignee: Yamazaki; Semiconductor Energy Laboratory Co., Ltd.
• Filed: November 25, 1998 | Granted: April 2, 2002
• Description: General semiconductor device (TFT/display-oriented SEL work). Not an inkjet/microfluid ejection head disclosure on its face.
• § 102 mapping: Lacks the fluid ejection actuators and printhead context entirely. No anticipation.

17. US 2001/0035863 A1 — "Electronic device and driving method thereof"

• Inventor/Assignee: Hajime Kimura; Semiconductor Energy Laboratory Co., Ltd.
• Filed: April 26, 2000 | Published: November 1, 2001
• Description: Electronic device driving method (SEL TFT art). No fluid-ejection actuator context on its face.
• § 102 mapping: No anticipation of the printhead claims.

18. US 5,055,859 — "Integrated thermal printhead and driving circuit"

• Inventors/Assignee: Wakabayashi et al.; Casio Computer Co., Ltd.
• Filed: November 16, 1988 | Granted: October 8, 1991
• Description: Integrated thermal (contact) printhead with driving circuit — thermal-transfer printing, not inkjet/microfluid ejection. Shares the "heating element + drive transistor + logic integrated" motif but in a non-fluid context.
• § 102 mapping: Lacks fluid ejection actuators/chambers/nozzle plate. No anticipation of 1/13/22 (actuator limitation fails).

19. JP H02-134256 A — "Thermal head and its manufacturing method" (JP 2-134256)

• Applicant: Casio Computer Co., Ltd.
• Filed: November 16, 1988 | Published: May 23, 1990
• Description: Thermal head (contact printing) and manufacture; Japanese-language counterpart of the Casio thermal-head driver art.
• § 102 mapping: Same non-fluid limitation as US 5,055,859. No anticipation.

20. JP H03-205833 A — "Manufacture of semiconductor device" (JP 3-205833)

• Applicant: Murata Mfg. Co., Ltd.
• Filed: January 5, 1990 | Published: September 9, 1991
• Description: Generic semiconductor manufacturing method (per the title); no printhead context retrievable.
• § 102 mapping: No disclosure of a microfluid ejection head. No anticipation.

21. US 4,308,549 — "High voltage field effect transistor"

• Inventor/Assignee: Yeh; Xerox Corporation
• Filed: December 18, 1978 | Granted: December 29, 1981
• Description: High-voltage FET device structure (Xerox early work). Not printhead-specific.
• § 102 mapping: No actuators/logic array. Background MOS art only. No anticipation.

22. US 4,472,875 — "Method for manufacturing an integrated circuit device"

• Inventors/Assignee: Christian et al.; Teletype Corporation
• Filed: June 27, 1983 | Granted: September 25, 1984
• Description: IC manufacturing method. Generic process art; no printhead context.
• § 102 mapping: No anticipation.

23. US 4,567,353 — "High-accuracy temperature control"

• Inventor/Assignee: Aiba; Sharp Kabushiki Kaisha
• Filed: April 7, 1977 | Granted: January 28, 1986
• Description: Temperature-control circuitry for a thermal (contact) printhead — background temperature-sensing art.
• § 102 mapping: No fluid-ejection actuator/array. No anticipation.

Supplemental note — "Family Cites" references (on the WO/EP family records, not the US face)

The Google Patents family file additionally lists five references that appear on the PCT/EP search reports rather than on the US patent's face: US 6,398,347 B1 ("Energy balanced ink jet printhead," HP, filed 2000-07-24 — HP FET-driver design family, same analysis as Tier 2); CN 2,457,829 Y (printer heating drive circuit); JP 2002-370363 A and JP 2002-370348 A (Canon, June 15, 2001 — inkjet head substrates with heaters and drive elements, structurally similar to US 6,302,504); and CN 1,206,104 C (ITRI — Chinese family member of US 6,666,545). None was verified to disclose the '012 numeric geometry or DLC limitations; treat them as § 103 combination art only.

Bottom line

No cited reference anticipates any independent claim (1, 13, or 22) under § 102 on the record I could verify. The recurring reasons are the same three gating limitations, none of which I found expressly disclosed in any single reference:

1. Driver-transistor active area of 1,000–<15,000 μm² (claim 1) / active-area width 100–<400 μm (claim 13) — the closest art (Xerox US 6,102,528; HP US 6,422,676/6,478,404/6,488,363/6,523,935; Canon US 6,302,504) pursues reduced area as a goal without the claimed ranges.
2. Logic-transistor gate length of 0.1–<3 μm — the cited logic/driver art predates or does not state sub-3 μm logic geometry (the era art referenced ~3–5 μm gates).
3. DLC protective layer of 1,000–3,000 Å (claim 22; deps. 12, 20) — no cited reference discloses DLC heater passivation (the art uses SiN/SiC/Ta).

Closest single references for § 103 (not § 102) combinations: US 6,102,528 (driver geometry + LDD + addressing on-chip) or US 6,422,676/6,478,404 (HP die layout with FET drive arrays) combined with US 6,302,504 (Canon logic-on-substrate) and a DLC-passivation reference (none present in the citation list — meaning claim 22's DLC limitation is the least likely to be met by this art set). Watch-item: US 6,666,545 issued after the '012 filing date and is usable only under § 102(e), if at all.

Full-text verification still needed for: US 6,422,676, US 6,488,363, US 6,523,935, US 6,592,207, US 6,666,545, US 2002/0125511, WO 2000/061372, US 6,365,917, US 2001/0035863, and the JP documents — where numeric-limitation disclosure could not be confirmed or excluded from the text I retrieved. My anticipation conclusions for those references are therefore stated conservatively and should be confirmed against the complete documents before any invalidity position is finalized.

Obviousness Analysis of US 7,018,012 B2 Under 35 U.S.C. § 103

Scope and approach

This analysis uses the 23 prior-art references listed in the "Citations" section of the Google Patents record for US 7,018,012 B2, plus the five "Family Cites" entries, which represent the art the examiner (and third parties) considered during prosecution. I supplemented the record with the full text/abstracts of the most load-bearing references (Xerox US 6,102,528; Xerox US 4,947,192; Xerox US 5,075,250; HP US 6,422,676 and US 6,478,404; ITRI US 6,666,545). For references where I could not retrieve full text (e.g., WO 00/61372, US 6,523,935, US 6,302,504, US 2002/0125511, US 6,592,207, US 6,365,917), my characterizations are based on titles, bibliographic data, and well-established state of the art, and are flagged accordingly.

The patent is expired (adjusted expiration 2024-10-13), was asserted in Slingshot Printing LLC v. HP Inc., 6:19-cv-00549 (W.D. Tex.), and was settled/dismissed (~Jan. 2021) with no IPR, no claim construction, and no final validity determination on any of its 30 claims. Accordingly, this is an untested § 103 case, and the ranges below are assessed at their ordinary meaning.

1. The claimed invention in functional terms

Dependent claims add routine refinements: heater resistance 70–150 Ω (3, 14, 23); driver LDD drain (4, 16, 24); driver active-area width 100–400 μm (5, 25); logic "selects a gate" of the drivers (6, 17, 26); driver on-resistance <20 Ω (7, 18, 27); LDD source and drain (8, 19, 28); driver gate length 0.1 to <3 μm (9, 21, 29); driver channel length 0.1 to <3 μm (10, 30); DLC layer (12, 20).

What the invention actually is (and what a § 103 challenger should emphasize): not a new circuit function, not a new material, and not a new architecture — it is a dimensional/geometry optimization of an old, well-documented structure (monolithic thermal-inkjet chip with on-chip logic + MOS power drivers + heater resistors), asserting compact transistor footprints (small active area, sub-3-micron logic gates) to shrink silicon area and cost.

2. Person of ordinary skill in the art (POSITA)

A POSITA as of November 2003 would be a B.S./M.S. electrical engineer or materials scientist with ~3–5 years in (i) MOS/VLSI device design and semiconductor processing, and (ii) thermal-inkjet printhead integration (thin-film resistors, power FET drivers, on-chip addressing logic). She would be fluent in MOS scaling rules, breakdown/punch-through trade-offs for high-voltage drivers, and the economics of die-per-wafer cost. All references below are in her core literature.

3. The cited art is a ready-made obviousness record

The cited references are not disparate — they form a single, self-referencing line of development in monolithic thermal-inkjet chips, with express cross-citations and a shared problem statement:

• US 6,102,528 (Xerox, "Drive transistor for an ink jet printhead," filed 1997, issued 2000) — the single closest reference. Its background states the problem the '012 patent claims to solve: as resolution rises above 300 spi it became "difficult, if not impractical, to layout compact MOSFET drive transistor switches that fit into the space available behind each heating element without increasing the size of the silicon substrate required," and "when the silicon area required for each printhead increases, the number of printheads which can be made from each silicon wafer decreases, thus driving up the manufacturing cost." '528 discloses a drive transistor integrally formed on p-type silicon within a printhead containing both the heating elements and printhead addressing circuitry means (i.e., logic + drivers + heaters on one chip), solves the punch-through/breakdown barrier with a pocket implant and graded drift region, "enabl[ing] production of printheads with resolutions up to 1200 spi," and gives a working example with 3 μm gate length and >65 V breakdown. At 1200 spi the nozzle pitch is ~21 μm, and at 600 spi ~42 μm — the per-driver active areas the '012 patent claims (1,000 to <15,000 μm², widths 100 to <400 μm) are precisely the sizes the geometry forces once a '528-style compact driver is placed behind each heater.
• US 4,947,192 (Xerox, "Monolithic silicon integrated circuit chip for a thermal ink jet printer," 1990) — foundational disclosure of "a monolithic silicon semiconductor integrated chip incorporating both MOS transistor drivers and resistive heater elements" on one substrate, described in the chip as containing "active driver, logic and resistive heater elements," using polysilicon-gated MOS switches and polysilicon resistors on field oxide. Discloses all structural elements of claim 1 except the numbers.
• US 5,075,250 (Xerox, "Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead," 1991) — the companion process for producing "logic, driver and transducer elements on the surface of a common silicon substrate," including n− drift-layer implants for the logic and driver sections — i.e., the LDD-type structures of dependent claims 4/8/16/19/24/28.
• US 6,666,545 (ITRI, "Driver transistor structure of inkjet print head chip," filed 2002, published 2003) — § 102(e) prior art (filed 2002-01-08, before the '012 priority date of 2003-11-14). Discloses the integrated-driver-head (IDH) chip, a large-area MOSFET made of parallel comb-gate elements behind each heater, and body contacts embedded in the source so that "the area occupied by the driver transistor can be largely saved, which is good for minimizing the inkjet print head chip and reducing manufacturing costs" — an express motivation to shrink the driver footprint. Its "active region width ... over 400 μm" example sits at the boundary of claim 13's "100 to <400 μm," and its stated goal of area minimization points directly at the claimed range.
• US 6,422,676 / US 6,478,404 (HP, "Compact ink jet printhead" / "Ink jet printhead," 2001 filings) — disclose a "compact" thin-film substructure/die with FET drive circuits (FIG. 7), primitive-select/addressing traces, heater resistors, and a composite SiN/SiC + tantalum passivation stack, driven by the need for "a compact ink jet printhead that has a large number of ink drop generators" without increased "substrate size and/or substrate fragility."
• US 6,302,504 (Canon), WO 00/61372 (Olivetti Lexikon), US 6,592,207 (Silverbrook), US 2002/0125511 (liquid jet apparatus) — additional evidence that on-chip driver + logic (shift registers/latches/decoders selecting driver gates per nozzle, as in '012's FIG. 4 NAND/inverter arrangement) and power distribution on printhead substrates were conventional by 2003.
• US 6,239,8347 / US 6,488,363 / US 6,523,935 (HP, energy-balanced / narrow printheads) and US 5,085,473 (Xerox, MOS driver with temperature control) — density- and area-driven design work in the same field.
• US 4,308,549 (Xerox high-voltage FET), US 5,010,355 (ionic passivation), US 6,365,917 / US 2001/0035863 (Semiconductor Energy Lab devices), US 5,913,111 (Canon, insulated-gate transistor process), US 4,472,875 (Teletype, IC manufacturing) — background MOS processing/scaling and passivation art, useful for the sub-3-micron-gate and passivation limitations.

Combinability evidence in the art itself: '528's background explicitly situates itself against '192, '355, 5,159,353, and '549; ITRI '545 cites '528 as its closest U.S. reference; HP '676 and '404 share a common specification. The references are cumulative improvements on the same chip architecture, which strongly supports a finding that a POSITA would treat them as a single body of knowledge.

4. Element-by-element mapping for independent claim 1

Claim 13 adds a cartridge body, nozzle plate, and the driver "active-area width 100 to <400 μm." Cartridge + nozzle-plate assemblies are ubiquitous in the art (HP '676's orifice plate; Canon '504; Lexmark's own commercial cartridges). The 100–400 μm width range again follows from laying out a '528/'545-style driver strip behind heaters at a 10–84 μm pitch (the '012 specification's own FIG. 11 range) — arithmetic consequence of the density targets the prior art already pursued.

Claim 22 swaps "fluid ejection actuators" for "heater resistors having a DLC protective layer 1,000–3,000 Å." Every element except DLC maps as above. The DLC limitation is the one genuinely hard-to-map feature on this record (see § 7).

5. Specific combinations that render the claims obvious

Combination A — Primary case against claims 1, 5–11, 13–21 (all but the DLC claims)

US 6,102,528 (Xerox) in view of US 4,947,192 / US 5,075,250 (Xerox), further in view of US 6,666,545 (ITRI) and/or US 6,422,676 or US 6,478,404 (HP).

• Claim 1: '192 and '528 give the monolithic chip with heater resistors, MOS power drivers, and on-chip addressing logic. '528 supplies the reason and the mechanism for compact drivers (pocket implant → reduced source-drain spacing → smaller silicon area at 600–1200 spi). '545 supplies body-contacts-in-source to cut further driver area and "minimizing the inkjet print head chip." HP '676/'404 supplies the compact-die design context (many drop generators on a small substrate). A POSITA combining them arrives at drivers sized within the claimed 1,000–<15,000 μm² window as a matter of course, with conventional sub-3 μm logic gates (see § 6).
• Dependent claims: LDD drain (4) and LDD source+drain (8): '250 expressly forms n− drift "lightly doped drain structures in the logic and driver sections"; '528's graded drift/pocket implant is the same concept for the power device. On-resistance <20 Ω (7): routine sizing for a 70–150 Ω heater (3) at 8–12 V — the '012 specification itself defines driver resistance as "less than 10% of total resistance," i.e., a design target, not an invention. Driver gate/channel length 0.1 to <3 μm (9, 10): '528's 3 μm gate scaled down under its own punch-through solution. Logic "selects a gate" of the drivers (6): the '012 FIG. 4 NAND + inverter per nozzle is the standard multiplexed-address architecture of WO 00/61372, Canon '504, and HP '676's primitive select.

Combination B — Independent-support case against claims 1, 13

US 4,947,192 and/or US 5,075,250 as primary (monolithic logic + drivers + heaters), in view of US 6,102,528 (density/area-driven compact drivers) and US 6,666,545 (driver area minimization). Even if a challenger prefers the older Xerox chip as the anchor, the combination yields the same result. Note the art's own cross-citation: '528's background reviews '192, so a POSITA reads them together as a matter of course.

Combination C — For claim 13's cartridge context

HP US 6,422,676 or US 6,478,404 (compact printhead/cartridge with FET drive array, orifice plate, passivation) in view of Xerox '528 + '192/'250. HP's compact-head references already sit inside a cartridge environment (they are HP print-cartridge patents), supplying the "nozzle plate attached to the substrate" and cartridge-body context with the same driver/logic density motivation.

Combination D — For claim 22 (with the DLC caveat below)

The Combination A references, plus HP '676/'404 (heater passivation stack over the resistors) and/or US 5,010,355 (passivation of printhead circuitry). The structure of claim 22 — DLC-protected heaters + compact drivers + sub-3 μm logic — is the same combination as A. Only the specific choice of DLC as the protective material needs separate support, which is not supplied by the four corners of the cited art (see § 7).

6. Why a POSITA would have been motivated to combine — and why the numeric ranges are obvious

The prior art contains an express, documented motivation. '528's background, quoted above, is essentially a confession of the problem the '012 patent addresses: fitting MOSFET drivers into shrinking per-nozzle space at high resolution without enlarging the substrate, because substrate area drives manufacturing cost. '545 says the same for driver area. HP '676 says the same for the die overall. The claimed dimensions are not a new goal — they are the metric of a goal the cited art already pursued.

Predictable application of known techniques (KSR, 550 U.S. 398 (2007)). The combination does not change the function of any component: transistors still switch current, resistors still nucleate bubbles, logic still demultiplexes address lines. A POSITA would combine '528's compact high-voltage driver with '192/'250's monolithic logic integration and '545's area-saving layout "according to known methods" and "with a reasonable expectation of success," yielding "predictable results." Post-KSR, no teaching-suggestion-motivation test requires a reference to point at another reference.

Obvious-to-try / result-effective variable. The active-area range (1,000 to <15,000 μm²), the width range (100 to <400 μm), the pitch (10–84 μm in the '012 specification), and the sub-3 μm logic gate length are all dimension choices bounded by (i) nozzle pitch at the resolutions the art already targeted (600–1200 spi per '528) and (ii) the MOS process generations available in 2003. The Federal Circuit has long treated "a range of a result-effective variable" as obvious where the art supplies a reason to optimize (see, e.g., In re Applied Materials, 692 F.2d 1289 (Fed. Cir. 1982); In re Aller, 220 F.2d 454 (CCPA 1955)); the record here has far more — an explicit cost-driven design incentive.

No evidence of criticality or unexpected results. The '012 specification discloses no comparative data, no examples showing that 15,000 μm² (vs., say, 20,000) or a 3.0 μm logic gate (vs. 2.9 μm) makes any functional difference. "About 1,000 to less than about 15,000 μm²" and "0.1 to less than about 3 microns" read like ceiling values chosen to encompass the density targets and process nodes of the day. On this record, a patentee defending these ranges would bear the burden of showing criticality — a burden the specification never attempts.

The sub-3 μm logic-gate limitation is especially weak as a differentiator. Claim 1 does not require sub-3 μm driver gates — only logic gates, which operate at low voltage and were fabricated at sub-micron-to-2-micron geometries as a matter of course in 2003-era ASICs. Even for the dependent claims that extend the range to the drivers (9, 21, 29), '528's pocket-implant/graded-drain solution expressly permits shorter gates without breakdown loss at >65 V, and its 3 μm working example sits at the claimed boundary, trivially scaled below it. The 0.1 μm floor is far below anything a printhead power device needs and reads as a conventional "catch-all" lower bound.

The references are in the same field, address the same problem, and are complementary rather than conflicting. Combining them requires no modification of any reference's principle of operation: '528's driver fits behind a '192-style heater; '545's body contacts shrink that driver further; HP's compact die packages the result. There is no teaching away in any retrieved text (e.g., no reference discourages shrinking logic gates or embedding body contacts). Cross-citation among '528, '192, and '545 affirmatively shows the art developed as a chain of area-reduction improvements.

7. Relative strength of the case, claim by claim

Candid caveats on reference content. I verified the substance of US 6,102,528, US 4,947,192, US 5,075,250, US 6,666,545, US 6,422,676, and US 6,478,404 from full-text sources (Google Patents / FreePatentsOnline / USPTO PDFs). For WO 00/61372, US 6,302,504, US 6,523,935, US 6,488,363, US 6,592,207, US 6,365,917, US 5,913,111, US 2002/0125511, and the Japanese/Chinese references, I relied on titles and bibliographic data; a formal opinion should pull each full text before relying on the specific mapping I've assigned. None of my conclusions depends on an unverified reference — the core case rests on '528, '192/'250, and '545, whose relevant content I verified directly.

8. Secondary considerations (weak on this record)

• No litigation-developed indicia exist: the patent was never IPR-challenged, never claim-construed, and the only assertion (Slingshot v. HP) settled before any validity finding. There is no finding of long-felt need, copying, commercial success with proven nexus to the claims, or industry skepticism — and equally no record of the contrary.
• Commercial success nexus problem: any Lexmark-era commercial success of printheads embodying the claims would face a weak nexus argument because the claimed ranges are unproven as the driver of consumer demand versus price, resolution, and reliability.
• The examiner allowed the claims, which is evidence of no obviousness at the time of examination, but the cited art — particularly '528 (2000) and '545 (published 2003-12-23, just after the 2003-11-14 priority date) — is precisely the kind of compact-driver art that makes the claims vulnerable now. The absence of any IPR despite years of high-stakes litigation is most plausibly explained by settlement economics, not by claim strength (as the earlier sections of this file noted).

9. Conclusion

On the cited record, US 7,018,012's core contribution — a monolithic microfluid ejection head whose per-nozzle MOS drivers occupy ~1,000 to <15,000 μm² and whose logic transistors use 0.1-to-<3 μm gates to cut silicon area — would have been obvious under § 103 over:

1. US 6,102,528 (compact high-voltage drivers behind high-resolution heaters, expressly to reduce substrate area), in view of
2. US 4,947,192 and/or US 5,075,250 (monolithic integration of logic, drivers, and heaters with LDD-type structures), and
3. US 6,666,545 and/or US 6,422,676 / US 6,478,404 (further driver-area and die-area minimization in the same art line).

The motivation is documented in the art itself (per-nozzle space limits at 600–1200 spi; die area ⇒ manufacturing cost; body-contact and pocket-implant techniques to reclaim area), and the claimed numbers are unremarkable optimization of result-effective variables with no showing of criticality. Claims 1–21 (except the DLC-dependent claims 12 and 20) face a strong obviousness case. Claim 22 and its DLC-dependent claims stand or fall on whether the challenger can supply DLC-overcoat art beyond the four corners of the cited list — the cited references do not, on this record, name DLC.

Key grounding references:

• US 6,102,528 full text (background and claims): https://patents.google.com/patent/US6102528
• US 4,947,192 full text: https://www.freepatentsonline.com/[4947192](/patent/4947192).html
• US 6,666,545 full text: https://www.freepatentsonline.com/[6666545](/patent/6666545).html
• US 6,422,676 full text: https://patents.google.com/patent/US6422676
• US 6,478,404 full text: https://patents.google.com/patent/[US6478404B2](/patent/US6478404B2)/en