US 4308549

I'll verify the patent against live sources before summarizing.

Verification performed

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Bibliographic data (from the authoritative text)

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Abstract (verbatim)

"A circular high voltage field effect transistor suitable for inclusion in LSI circuits, and the process for making said transistor, are described. The transistor comprises a central drain and concentric circular field plate, gate and source. Alternate embodiments include an intermediate gate and resistive gate. Implantation and diffusion techniques are described for producing the source and channel regions, and various device dimensions may be varied to improve either current or voltage handling capability or speed capability."

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Independent claims in plain language

Claim 1 — the "intermediate gate" device (FIG. 4 family).
A high-voltage FET whose elements are laid out as complete concentric circles on the surface of a p-type semiconductor substrate, ordered from the center radially outward as: n-type drain → first thick oxide layer → thin oxide layer → n-type source. A conducting gate covers at least part of the thin oxide; a conducting field plate covers at least part of the thick oxide. The substrate beneath the thin oxide is defined as the channel region, and beneath the thick oxide as the drift region. The claim then adds an intermediate gate that is electrically isolated from the rest of the transistor elements and sits on the thick oxide layer between the field plate and the gate. (In the spec this is element 40, typically biased to an intermediate voltage — e.g., ~200 V for a 400 V drain — to spread the equipotential lines and cut series resistance. Note claim 1 does not require the field plate to be tied to the drain; the spec expressly says the field plate "may be isolated from the drain 22 and supplied with an independent voltage.")

Claim 2 — the resistive-gate variant (FIG. 5).
The device of claim 1, further including a concentric resistive layer continuously connecting the gate and the intermediate gate. This is the spec's resistive polysilicon layer 50 / resistive gate contact 51; it lets the surface potential rise smoothly from ~0 V at the gate up to (and beyond) the high drain voltage, so no extra power supply is needed.

Claim 3 — the short-drift / high-current variant (FIG. 3).
A high-voltage FET with the same concentric-circle architecture — center n-type drain, thick oxide, thin oxide, n-type source; conducting gate over part of the thin oxide; conducting field plate over part of the thick oxide; channel region defined under the thin oxide and drift region under the thick oxide — but characterized solely by the relative lateral geometry: the radial length of the channel region is greater than the radial length of the drift region, which the claim states "allow[s] a higher current handling capability."

Dependent claim 2 is the only non-independent claim.

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Technical thrust (one paragraph)

The patent's stated problem is that high-voltage output amplifiers could not practically be integrated into an LSI chip because (a) each device consumed too much substrate area, and (b) high-voltage devices cross-talked with neighbors and with low-voltage logic. The claimed fix is the closed, concentric geometry: because the source (normally at ground) forms the outer ring, it shields each device's switched high-voltage drain from adjacent circuitry, enabling dense packing. High-voltage withstand is aided by the split-oxide topography (thin gate oxide for gate control; thick field oxide under the field plate), the field plate itself, and — in the claimed variants — the intermediate gate or resistive gate.

Not claimed, but described

The drawing-level and process subject matter is not in the claims: the raised drain bonding pad over thick oxide 33 (FIG. 2A/2B), the buried polysilicon field-plate-to-drain conductor 38 (FIG. 2C), the implanted vs. double-diffused channel P region 25 (FIG. 2D vs. FIG. 2E), the 8-mask fabrication sequence (FIGS. 6–13), and the continuous metal joining of field plate 24 to drain 22 (metal 35). The method of making was pursued in the separate divisional US 4,333,225 A.

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Litigation status / uncertainty — stated explicitly

• I found no CAFC 2026 docket, district court case, ITC investigation, or PTAB proceeding naming US 4,308,549. I did not have access to a dedicated litigation docket database in this session; my conclusion rests on web searches of the patent number plus relevant terms, and it is possible a proceeding exists in a database not indexed by those queries. Treat this as "no evidence found," not as a certified negative.
• Independent of searching, the patent's term expired 1998-12-29 (21-year term from the 1978-12-18 filing, consistent with Google's "Anticipated expiration" entry). A live 2026 CAFC appeal on this patent is therefore highly improbable for infringement purposes; the practical consequence is that any 2026 docket hit on this number would more likely be an unrelated-artifact match than a live dispute.
• Dimensions given in the specification (thick oxide 1.2–2 µm, thin oxide ~2,000 Å, drain depth 5–10 µm, source depth ~1 µm, substrate resistivity ≥50 Ω·cm, insulator ≥1.5 µm) are expressly stated to "describe the chip presently being produced" and "not intended to limit the attached claims." They should not be read as claim limitations.
• I cannot confirm from primary sources whether any post-1998 assignee record (e.g., a Xerox-related spin-off) exists for this specific patent; Google's listed "current assignee" is a database field, not a legal conclusion.

Primary source: US 4,308,549 A, https://patents.google.com/patent/US4308549/en

I'll search litigation databases and court records for US patent 4308549.

Initial searches returned only false positives. Let me search more targeted litigation sources.

The searches so far return irrelevant results. Let me query litigation-specific databases directly.

Litigation Search Report — U.S. Patent No. 4308549

Patent identified (literally): U.S. Patent No. 4,308,549 — "High voltage field effect transistor"

• Inventor: Keming W. Yeh
• Assignee: Xerox Corp (original assignee)
• Application No. US05/970,679; filed 1978‑12‑18; granted 1981‑12‑29
• Related child: US06/215,288 → U.S. Pat. No. 4,333,225 ("Method of making a circular high voltage field effect transistor"); JP counterpart JPS5583269A
• Legal status: Expired – Lifetime (anticipated expiration 1998‑12‑29)

Result: No litigation found

No court case, ITC investigation, or other adjudicated proceeding asserting U.S. Patent No. 4,308,549 was located. The patent appears in the record only as a patent document and as a cited reference in later patents — never as an asserted patent in any docket I could identify.

Fields requested (plaintiff, defendant, jurisdiction, case number, filing date, outcome): not applicable — no case identified.

What the searches actually returned (and why they are not this patent)

All hits were false positives for the number string, not for this patent:

1. EP‑4308549‑A4 — "Nitrogen-containing heterocyclic ketones…" (Hansoh Bio / ShangHai Hansoh), a 2021‑priority European pharmaceutical application. Completely unrelated. (pubchem.ncbi.nlm.nih.gov/patent/EP-4308549-A4)
2. US 430/8549‑type numbers appearing inside unrelated opinions — e.g., "the '430 patent" in Verinata Health, Inc. v. Ariosa Diagnostics, Inc. (Illumina/Roche fetal-aneuploidy patents), the '430 patent in a SanDisk reexamination dispute, and the '430 patent in a DSM/paed. § 112 best‑mode case. In each instance "'430" refers to a different patent in the 4,3xx,xxx series, not No. 4,308,549.
3. Indian trademark application 4308549 ("Pain Kill"), Argentine INPI acta 4308549, and a Korean USPTO case‑law compilation — none are U.S. patent litigation.
4. A cluster of European high‑voltage thin‑film‑transistor patents (EP 0156528, EP 0399737, EP 0403279, EP 0410799) that cite Xerox HVTFT art. These are prosecution citations in a related technical field (thin‑film high‑voltage transistors), not litigation over the '549 patent.

Important caveats on this conclusion

• Search coverage was limited. I was unable to directly load the Unified Patents litigation portal (https://portal.unifiedpatents.com/litigation/caselist), PACER, Docket Alarm, or CourtListener's docket search; those are paywalled, login‑gated, or not fully indexed by the search tool available to me. This report is therefore based on open‑web indexing only, and negative results from such a search are not conclusive.
• No IPR/PGR is possible against this patent — it expired in 1998, long before the AIA's post‑grant review regimes took effect, and it was never eligible for those proceedings. It likewise appears in no "Cited By" invalidity/PTAB context as an asserted patent.
• The number was interpreted literally, per instruction. I did not treat "'549," "4,308,549," or "US4308549" as shorthand for any neighboring patent, and I did not fold in results for US4333225, JPS5583269A, or the '-430 patents appearing in the unrelated opinions above.

Why the absence is plausible (context, not evidence)

US 4,308,549 issued to Xerox in 1981 and expired in 1998. It describes a circular high‑voltage field‑effect transistor intended for integration into LSI chips driving electrostatic printers, and it became technically relevant to later thermal‑ink‑jet printhead driver developments (note the downstream Xerox/HP/Lexmark printhead patents citing this family in the "Cited By" list: US4947192, US6102528, EP0909649, US6977185, etc.). If any dispute in this family existed, it would most plausibly concern those later printhead‑driver patents rather than the expired '549 patent itself — but I did not find any docket asserting the '549 patent, so I am not representing that such litigation exists.

Recommended verification steps (to reach an authoritative answer)

1. Unified Patents litigation portal — search "4308549" / "4,308,549" at https://portal.unifiedpatents.com/litigation/caselist.
2. CourtListener RECAP / PACER — full‑text docket search for "4,308,549" and "4308549," including the 1981–1998 enforcement window (PRE‑PACER cases from the 1980s–90s may not be electronically indexed, which is the most likely reason no hits appear).
3. Westlaw / LexisNexis / Bloomberg Law — patent‑number litigation search, which covers older paper dockets.
4. USPTO Patent Assignment / Global Dossier for this patent, to see whether any assignments coincide with a transfer‑driven suit.
5. ITC EDIS — Section 337 investigations involving Xerox high‑voltage/printhead technology.

Bottom line: Based on the sources I could reach, there is no known litigation involving U.S. Patent No. 4,308,549. I cannot rule out a pre‑PACER suit in the 1980s–90s that is not captured by open web indexing, and I flag that limitation explicitly rather than asserting a definitive negative.

I'll verify the canonical "no proceedings" signal against public sources before writing this up.

Let me run two more targeted checks before concluding.

Proceedings overview

Zero AIA trial proceedings on file. The USPTO Open Data Portal structured block reports no AIA trial proceedings for US 4,308,549, and my independent web checks surfaced none either — so the count is 0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution-denied. The defensive posture this gives a defendant is not "hardened patent" and not "claims canceled" — it is "nothing to fight at the PTAB, because there is no PTAB fight to have." The bottom line is that the patent itself is dead on the calendar: filed 1978-12-18, granted 1981-12-29, and its anticipated expiration date is 1998-12-29 (Google Patents legal-status entry: "Anticipated expiration"). Any demand letter asserting this patent is more likely a records/assignment artifact or a portfolio-propagation error than a live infringement theory.

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No proceedings to itemize

The template calls for one ### {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} block per proceeding. There are none to write. I am explicitly not populating that section with invented IPR numbers, and I am not repurposing the nearby hits my searches returned — those belong to unrelated patents:

Note the trap here: this patent is commonly abbreviated "the '549 patent," and the Xerox-assignee hit list is full of Xerox-owned patents, so both shortcut heuristics produce false positives. None of them involve US 4,308,549.

Why the absence is structural, not accidental

Three independent reasons no AIA trial exists or could practicably exist:

1. Timing. AIA trials (IPR/PGR/CBM) became available 2012-09-16. This patent expired 1998-12-29 — roughly fourteen years earlier. There is no commercial activity left to deter.
2. Damages runway. Under 35 U.S.C. § 286 there is a six-year lookback from the date a complaint is filed. With expiration in 1998, a complaint filed today reaches back only to 2020 — well after the patent's term ended. Nothing is recoverable.
3. Eligible regime mismatch. PGR requires a post-AIA filing; CBM requires a "covered business method" financial-services patent. This is a 1978-filed circular high-voltage FET for electrostatic printers/inkjet drivers. Neither regime fits even in principle.

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Strategic summary

Claim status: all UNTESTED, and all EXPIRED. The patent has three claims. Claim 1 is a concentric high-voltage FET with an n-type drain at center proceeding radially outward through a first thick oxide layer, a thin oxide layer, and an n-type source, plus a gate over the thin oxide, a field plate over the thick oxide, and an intermediate gate on the thick oxide between the field plate and the gate. Claim 2 adds a concentric resistive layer continuously connecting the gate and the intermediate gate. Claim 3 is the same concentric structure with the channel region radial length greater than the drift region length for higher current handling. The PTAB has never construed or ruled on any of the three. There is no cancelation, no affirmance, no claim-level outcome to report — because no petition was ever filed. If your adversary's letter cites claims 1, 2, or 3, none of them has been tested at the Board, and none of them is enforceable going forward.

Estoppel landscape: clean slate, but also nothing to gain. Because no IPR or PGR ever reached a final written decision, § 315(e)(2) estoppel never attached to anyone — no petitioner, no privy, no real party in interest. Every prior-art ground is theoretically "available." That is a hollow victory: the same is true of every § 102/§ 103 ground you could raise in district court, and the patent's expiration makes invalidity of claims 1–3 a moot question in most postures. Conversely, if you were considering an IPR as a defensive counterpunch, note the statutory 1-year § 315(b) bar clock and the futility of paying petition fees to invalidate a claim whose term ended in 1998.

Pattern signals: none. No repeat petitioner, no serial IPR filer, no defensive aggregator (no Unified Patents, RPX, or similar entity appears anywhere in the record), and no patent-owner appeal activity — there being no adverse decision to appeal. The patent appears once in the public record as asserted art rather than asserted right: it is cited in the international search reports for WO 1999/034449 A3 (Philips, high-voltage thin-film transistor) and WO 2002/078961 A1 (Hewlett-Packard, printhead integrated circuit). Its family is small and equally quiet: the Japanese counterpart JP S55-83269 A and the divisional U.S. 4,333,225 A ("Method of making a circular high voltage field effect transistor," filed 1980-12-11 as a division of this application). Four pre-AIA U.S. patents were cited against it during prosecution, the earliest being U.S. 3,845,495 (Signetics) — nothing that has been litigated.

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Recommended next steps

• If you are a defendant: the dispositive defense is not a PTAB argument — it is expiration plus § 286. Confirm the file-wrapper status directly at Google Patents US4308549A (expiration 1998-12-29) and pull the certified file wrapper via USPTO PatentCenter. There is no FWD to quote, because there is none; do not let opposing counsel imply otherwise.
• Verify against the primary source before relying on the empty set. The ODP structured block is authoritative for AIA trials, but run your own check at the USPTO PTAB Center (https://ptacts.uspto.gov/ptacts/) and via the PTAB Open Data / API (https://developer.uspto.gov/ptab-api) under patent number 4308549 and application 05/970,679. Confirm the zero count and archive a screenshot with a timestamp.
• Check the two adjacent risks the PTAB record does not cover. (a) Ex parte reexamination is not an AIA trial and would not appear in the ODP trial block — I did not independently verify reexamination certificates for this patent. (b) The divisional U.S. 4,333,225 and the JP counterpart JP S55-83269 A share the 1978-12-18 priority date and the same 1998-era term; treat them as expired too, but confirm the JP term separately (Japanese law, not U.S. law, controls).
• If active assertion genuinely exists, the likely explanation is a defective demand. Ask the asserting party in writing to (i) identify the specific claims asserted, and (ii) state the date of first infringement and the § 286 damages window. An expired-patent assertion usually resolves at that step.
• Do not budget for an IPR. With no PTAB activity to piggyback on, no estoppel leverage to exploit, and a patent whose term ended in 1998, an IPR petition would be money spent to invalidate a patent that has already ceased to exist.

Caveat on sourcing: I could not locate any PTAB E2E docket, Final Written Decision, or Federal Circuit opinion for US 4,308,549, and I have not asserted one exists. The statements above about claim scope come from the patent's own claim text as published on Google Patents; the expiration date comes from the Google Patents legal-status field, which is a derived record and should be confirmed in PatentCenter.

I'll start by checking what assignment data is actually retrievable for this patent before building the record.

Let me probe for any post-issuance transfers, litigation, or reassignment activity.

Let me check the inventor's background and whether any assignment records are indexed at all.

Verification caveat up front

I was not able to retrieve any assignment record for US 4308549. My tooling does not include a browser session against assignmentcenter.uspto.gov, and keyword searches for the patent's assignment reel/frame, correspondent, or any post-issuance transfer returned nothing. The Google Patents legal-events table in the authoritative text I was given lists only two events:

There is no ASG / assignment event of any kind in that record — not even the routine inventor→Xerox assignment that would normally exist for a 1978 corporate filing. So I cannot say "the Assignment Center has no records." I can only say I did not retrieve any. Treat the section below as unverified rather than as a confirmed null finding. To close this out, query assignmentcenter.uspto.gov and assignment.uspto.gov/patent/index.html directly by patent number 4308549, and separately pull the application's file wrapper via Patent Center (application 05/970,679) to find the recorded assignment of the invention from Yeh to Xerox.

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Inventors

Keming W. Yeh (also rendered Keming Wayne Yeh) — sole named inventor. Filed 1978-12-18 per the patent's own priority data.

Employer at time of filing: Xerox Corporation. This is well-grounded rather than inferred: Yeh's contemporaneous applications in the same period are all front-page-assigned to Xerox Corporation, Stamford, Conn. — e.g. US 4,193,079 (MESFET with non-uniform doping, filed 1978-01-30, inventor address Westchester, Calif.) and US 4,206,005 (Method of making split gate LSI VMOSFET, filed 1978-11-27, inventor address Los Angeles). A biographical entry places him as "Manager technical, Xerox Corporation, El Segundo, California, 1976—1982." So: Xerox, El Segundo / southern California facility, which is consistent with the Los Angeles–area inventor addresses on the parallel filings.

Unusual patterns: None of the fire-sale precursor type. He did not depart within 12 months of filing — he remained at Xerox through roughly 1982 and continued filing Xerox-assigned applications (e.g. the self-aligned MESFET line). One loose thread I could not resolve: a Keming W. Yeh appears on 1992–1996 patents covering palmtop computers, IC memory cards and docking stations. Whether that is the same person post-Xerox or a namesake is unverified — I am not asserting either.

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Original assignee

Xerox Corporation, Stamford, Connecticut (per the issued patent's front page). Note that Google Patents renders this as "Xerox Corp," and Unified Patents' record for the sibling divisional US 4,333,225 lists "Parent Company: Xerox Holdings Corp."

• Primary line of business at the time: xerographic copiers and duplicators; the patent's own background section names the electrostatic printer as the target application, needing 200 V+ drive on a low-voltage LSI logic chip.
• Did they ship a product embodying the claims? The circumstantial evidence points yes, but I want to be precise about what it proves. All three Xerox-family forward citations to this patent are thermal ink jet drive/printhead patents — US 4,947,192 (Monolithic silicon integrated circuit chip for a thermal ink jet printer, 1990), EP 0909649 A2 / US 6,102,528 (Drive transistor for an ink jet printhead, 1999–2000). That is a strong indication that the HIFET/drive-transistor lineage was carried into Xerox's ink jet products. Citation lineage is not proof of embodiment, and the patent had already expired by the time the 1999–2000 citations issued. Treat "shipped a product" as likely-but-not-documented here.
• Current status: Operating company. Xerox remains a public operating enterprise (restructured under a holding company, Xerox Holdings Corporation, in 2019). It has never, to my knowledge, been in Chapter 7/11 in any window relevant to this patent. I have not verified current-year corporate events and won't assert them.

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Assignment timeline

No recorded assignment was retrieved for this patent. No reel/frame, no conveyance type, no assignor, no assignee and — critically for your correspondent analysis — no correspondent of record. I will not construct plausible entries.

For completeness, what the record does show, and what it does not:

• 1980-12-11 — US 06/215,288 filed (divisional), issuing as US 4,333,225, "Method of making a circular high voltage field effect transistor." This is a prosecution-family relationship (division), not an assignment conveyance. Do not count it as a chain link.
• 1979-12-12 — JP 16139979 filed, publishing as JPS5583269A. Foreign filing, not an assignment.
• No litigation naming US 4,308,549 surfaced in any of my searches.

One cross-reference worth recording, clearly flagged as not confirmed for this patent: a search hit showed that Xerox recorded security interests over its patent portfolio with Bank One, NA as administrative agent — executed 2002-06-21, recorded 2002-06-28 at Reel 013153/0001 — and a further security agreement at Reel 015134/0476. Those appeared in a record for a different Xerox patent (US 5,608,023). US 4,308,549 expired 1998-12-29, so it could not have been collateral in a 2002 security agreement. Do not extend those reels to this patent.

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Timeline diagram

timeline
    title Ownership of US 4308549
    1978 : Application filed 18 Dec
         : Inventor Keming W Yeh
         : Assignee of record Xerox Corp
    1979 : Japan counterpart filed 12 Dec
    1980 : Divisional filed 11 Dec
         : US 4333225
    1981 : Patent granted 29 Dec
    1982 : Grant event recorded 08 Jan
    1998 : Patent expired 29 Dec

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NPE / troll-pattern signals

Because the assignment chain is unretrieved, most of these are unclear on the evidence, not "not present." I am distinguishing the two deliberately.

1. Shell-entity transfer — unclear (leans not present). No post-issuance assignment surfaced to any IP/Holdings/Ventures/Licensing entity. The assignee of record on the patent and on Google Patents remains Xerox Corp. But I have no reel/frame-level confirmation, so I won't call it affirmatively absent.
2. Known asserter in the chain — not present. Xerox Corporation appears on no NPE list (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, Spangenberg entities), and no such entity appears anywhere in the patent's cited-by or citation record.
3. Repeat correspondent across the chain — unclear / no data. The correspondent of record is exactly the field I could not retrieve, so this signal is untestable. Flagging: for a single-link chain (inventor→Xerox), a repeat-correspondent finding would require comparison against your broader tracked set — I have no name to compare.
4. Cascading transfers — not present. No chained LLC transfers; no assignments at all in the retrieved record.
5. Pre-litigation transfer — not present. No infringement suit naming this patent was found, so there is no assertion to precede.
6. Bankruptcy fire-sale — not present. Xerox did not enter Chapter 7/11 in this patent's live window (1978–1998), and the patent expired before any later Xerox restructuring activity.
7. Privateering — unclear. The forward-citation pattern (Xerox's own thermal ink jet printhead patents citing this disclosure) is consistent with in-house commercialization rather than privateering, but I found no SEC 10-K/8-K or Patent Progress / EFF coverage tying this patent to an NPE assertion campaign. If your thesis is Xerox privateering, this patent is not your exemplar on current evidence.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents or OIN.

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Verdict

Insufficient data.

The patent's record as I can retrieve it shows a single corporate assignee — Xerox Corporation — from filing through expiry on 1998-12-29, with no ASG event in the Google Patents legal-events table and no reel/frame, assignee, or correspondent retrievable from any source I could reach. There is therefore no evidenced basis for any NPE finding, and equally no evidenced basis for clearing the patent. Every one of the eight signals resolves to "not present" only where independent facts support it (no litigation, no bankruptcy, no aggregator) and to "unclear, no data" where the missing assignment record is dispositive — notably signal 3, the correspondent test, which is the whole point of this exercise.

To upgrade this verdict, run two queries I could not: (a) patent number 4308549 in USPTO Assignment Center to capture reel/frame, conveyance and correspondent of record; (b) the file wrapper for application 05/970,679 in USPTO Patent Center for the original Yeh→Xerox assignment, dated on or around the 1978-12-18 filing. If (a) returns an empty result set, the correct and defensible conclusion becomes: original assignee still holds title, no NPE pattern.

I'll verify the patent number and each face citation against live sources before analyzing.

Prior-Art Analysis — US 4,308,549 A ("High voltage field effect transistor")

Analyst note on the number: I searched literally for 4308549 and only for that number. Google Patents returns exactly one US document — US 4,308,549 A, High voltage field effect transistor, Keming W. Yeh, Xerox Corp. (https://patents.google.com/patent/US4308549/en). No sibling/nearby numbers (e.g. 4,288,801 / 4,288,802) were substituted. Corroboration from third-party records: US 6,102,528 (Xerox) recites "U.S. Pat. No. 4,308,549 … discloses a circular high voltage field effect transistor … central drain and concentric annular field plate, gate, and source," and EP 0,909,649 A2 lists "US 4308549 A 19811229 - YEH KEMING W" under Citation (applicant). This is consistent with the previously generated bibliography; no contradiction found. The only flag: my earlier section's caution about a "possible 2026 docket" remains unchanged — this patent expired 1998‑12‑29.

Pre-AIA framework. Because the application was filed 1978‑12‑18, pre-AIA 35 U.S.C. §§ 102/103 govern. Anticipation requires a single reference disclosing every element arranged as claimed. All four face citations are US patents; three issued more than one year before the filing date (available under pre-AIA § 102(b)), and US 4,115,709 issued within that year (available under § 102(a), and as § 102(e) art via its earlier US filing).

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1. The prior art of record — US 4,308,549 "Patent Citations (4)"

Date note (not auto-corrected): the record of US 4,115,709 shows the earlier 1974‑07‑16 priority alongside a 1977‑02‑15 US filing of Ser. No. 768,897 — i.e. a foreign-priority case. The US filing date controls for § 102(e) purposes.

Also in the family record (not on the US face): Google's "Family Cites Families (2)" lists JPS 53‑980 A, Hitachi, Field-effect transistor of high dielectric strength (priority 1977‑07‑13; published 1978‑01‑07) — a genuine, material HV-FET reference cited in the JP counterpart. The companion entry JPS 58‑49210 B2 (priority 1977‑03‑14, published 1983‑11‑02) carries the title "Shutter of poultry feeding equipment" and is plainly unrelated to this subject matter; I treat it as a database mis-mapping and expressly flag it rather than adopting it as prior art.

References that are not prior art: the 15 "Cited By" documents and the two members of the "Similar Documents" list (including the divisional US 4,333,225 A, filed 1980‑12‑11) all post-date the 1978‑12‑18 filing/priority and cannot be § 102 art against this patent. Likewise the 1981 IEDM paper "Integrated high-voltage/Low-voltage MOS devices" (Xerox "HiVID": circular drain radius 100 µm inside a circular source of 230 µm interior radius, resistive polysilicon field plate, 8‑mask flow) corroborates the disclosure but is the inventor's later publication — not prior art. I mention it only because it independently confirms the circular/field-plate architecture the prior-art search is trying to place.

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2. § 102 element chart vs. the independent claims

Claim 1 elements: (1‑a) complete concentric circles; (1‑b) radial order center→out: n-drain → thick oxide → thin oxide → n-source; (1‑c) gate on thin oxide; (1‑d) field plate on thick oxide; (1‑e) channel = substrate under thin oxide, drift = substrate under thick oxide; (1‑f) intermediate gate on the thick oxide, between field plate and gate, electrically isolated from the remaining elements.
Claim 2 = claim 1 + (2‑a) concentric resistive layer continuously connecting gate and intermediate gate.
Claim 3 = 1‑a through 1‑e only, plus (3‑f) radial channel length > radial drift length.

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3. Per-reference conclusions

A. US 3,845,495 (Signetics) — § 102: does not anticipate claims 1, 2 or 3; strongest § 103 art against claim 3's preamble.
It discloses every topological element of the claim 3 preamble — thin gate oxide over a diffused channel, thick oxide over the drain/depletion region, and a field plate over that thick oxide — and even the optional gate-to-field-plate interconnection. But it discloses no closed/concentric geometry, gives no center-drain geometry, and expressly teaches that high-voltage capability is decoupled from channel length. The claim 3 requirement that the channel be longer than the drift region is therefore not only absent but contradicted. Its natural role is as the § 103 starting reference, especially in view of a circular-layout teaching such as US 4,058,822 or the 1968 closed-loop dual-gate FET discussed below.

B. US 3,996,655 (TI) — § 102: does not anticipate any claim.
This is a process/isolation patent. It supplies the "short channel + extended drift region" architecture (element 1‑e) and a competing isolation philosophy (encircling p-type isolation rather than grounded-source shielding), but it has no gate/field-plate/thick-thin-oxide stack, no circular layout, and no intermediate gate. The extended drift region is longer than the 1 µm channel — the inverse of claim 3. Relevant as § 103 background on integrating HV devices into an IC, and as evidence of the general level of skill (isolation was the recognized obstacle to HV/LSI integration, the same problem the '549 solves by grounded-source shielding).

C. US 4,058,822 (Sharp) — § 102: does not anticipate any claim, but is the single most relevant reference on the merits.
It is the only reference of record that comes close to the whole disclosed architecture: circular electrode layout (FIG. 3), split insulation (thick 18 / thin 40 at 800–1000 Å), a lightly doped drift/channel region 16 under the thick oxide, and a drain-connected metal extension acting as a field plate. It therefore reads on substantial parts of both claim 1 and claim 3 preambles. It nevertheless fails as an anticipation reference for each claim as issued:

• Claim 1 — no intermediate gate that is electrically isolated from the other elements and located on the thick oxide between the field plate and the gate; its drain metal extension is drain-connected, not an independently biased intermediate gate.
• Claim 2 — no concentric resistive layer bridging gate and intermediate gate.
• Claim 3 — the disclosed channel (0.5–1.5 µm) is shorter than the drift region it feeds; the claim's "channel radial length greater than drift region length" is absent.
  Unverified point I will not assert: I could not, from the excerpts retrieved, establish with certainty that the drain of '822 sits at the circle's center with the source at the circumference in the exact radial order claim 1 requires (the FIG. 3 text identifies a circular source/gate/drain configuration and gate/source bonding pads, with 5–10 µm source-to-gate spacing, but not the full radial stack). Any anticipation theory would have to be proven on the full FIG. 3 geometry.

D. US 4,115,709 (NEC) — § 102: does not anticipate any claim; § 103 relevance is peripheral.
It is directed to preventing drain-voltage-induced gate-oxide destruction by a parallel gate-controlled diode, and its claims are about protection-device breakdown-voltage relations, bonding pads, and gate/drain isolation — not about a concentric HV-FET cell. Its only point of contact with the '549 subject matter is the recognition (shared with the '549 specification) that high drain voltage threatens the gate insulator, and its incidental recitation of a gate insulator thinner than ~1000 Å. As an anticipation reference for claims 1–3 it is deficient in essentially every element.

Bottom line on § 102: No reference of record anticipates claim 1, claim 2 or claim 3. Each independent claim contains at least one element absent from every citation — for claim 1 and claim 2 the isolated intermediate gate and the concentric resistive gate layer; for claim 3 the channel-longer-than-drift radial geometry. The prior art of record instead appears to have been cited for § 103 purposes: (A) and (C) for the split-oxide/field-plate concept, (B) for sub-micron-channel HV device integration, and (D) for drain-junction/gate-oxide breakdown at high drain voltage.

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4. Highly material art not on the face of US 4,308,549 that a searcher should add

I found this while reading a citing-family document, so it is reported as a lead, not as a verified face citation:

• Closed-loop FET with inner gate on thick oxide and outer gate on thin oxide, apparently in IEEE Transactions on Electron Devices, Vol. ED‑15, No. 10, Oct. 1968, pp. 717–728, and DE‑A‑2 740 702, discussed in the background of EP 0 020 164 B1: a "field effect transistor … having two gate electrodes in closed loops around a drain electrode, with the inner gate electrode being positioned on a thick layer of metal oxide, and the outer gate electrode being positioned on a thin layer of metal oxide contiguous with the thick layer" (source text at patentimages for EP0020164B1). The same document describes a "concentric grounded periphery HVMOSFET" with annular gate electrodes 70/80 on a stepped oxide. If the 1968 citation is accurate as quoted, it is materially closer to claim 1 than any of the four US face citations (closed-loop geometry + inner conductor on thick oxide + outer conductor on thin oxide), and it is the reference I would most want examined against claim 1 in a validity challenge. Caveat: I am relying on the quoting document's characterization, not on the 1968 paper itself, which I did not retrieve in this session.
• IBM Technical Disclosure Bulletin, Vol. 21, No. 8, Jan. 1979, p. 3368 — also cited in EP 0 020 164 B1 — "an FET having a floating field plate disposed between a gate electrode and the substrate." Its January 1979 date is after the '549 filing date (1978‑12‑18), so on its face it is not § 102 art against US 4,308,549; it would matter only for the later divisional/JP family or as evidence of contemporaneous thinking.
• JPS 53‑980 A (Hitachi, Field-effect transistor of high dielectric strength, pub. 1978‑01‑07): predates the filing by ~11 months; cited in the JP counterpart. Language barrier prevented content verification here — worth obtaining a translation if claim 1 is challenged.
• DE‑A‑2 740 702 — flagged above as the EP examiner's starting reference; not verified in this session.

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5. Verification limits (stated explicitly)

Primary source for the patent: US 4,308,549 A, https://patents.google.com/patent/US4308549/en

I'll verify what the cited prior-art references actually disclose before building the obviousness combinations.

The Signetics and Sharp references turn out to be highly material. Let me probe the remaining technical elements — concentric geometry, resistive field plate, and the Japanese family citation.

Obviousness analysis — US 4,308,549 A under 35 U.S.C. § 103

0. Governing law and framing

This patent was filed 1978‑12‑18 and issued 1981‑12‑29, so pre‑AIA § 103 governs (no AIA 102/103 effective‑date issues). The analysis follows Graham v. John Deere Co., 383 U.S. 1 (1966) — scope/content of the prior art, differences from the claims, level of ordinary skill, and secondary considerations — with the KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) refinements (predictable variation; design incentives; "known technique to improve a similar device in the same way"). Because the patent is presumed valid under 35 U.S.C. § 282, invalidation requires clear and convincing evidence in litigation (preponderance in a reexam).

I build on the previously generated claim constructions rather than repeating them. The three claims decompose into four potentially separable technical elements:

A, B and E are the only limitations of independent claim 3; claim 1 = A+B+C; claim 2 = A+B+C+D.

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1. Level of ordinary skill

Circa 1978, a POSITA is a semiconductor device engineer with a B.S./M.S. in EE or applied physics and roughly 2–5 years' experience designing high‑voltage/lateral MOS devices and their IC fabrication sequences — conversant with junction breakdown and curvature effects, field‑plate (metal overlay) field shaping, double‑diffusion/DSA (diffusion‑self‑alignment) structures, ion‑implantation channel formation, and masking economics. This is a modestly sophisticated but not extraordinary level of skill; the field was small, literature‑driven, and the relevant concepts were actively published (see the references below).

Field of the invention: all four references cited on the face of '549 are insulated‑gate field‑effect devices, and three of the four are expressly directed to high‑voltage / low‑on‑resistance operation. They are therefore analogous art a fortiori — reasonably pertinent to the problem the inventor faced (raising breakdown voltage while keeping on‑resistance, area and integration cost low).

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2. Scope and content of the prior art (verified disclosures)

2.1 US 3,845,495 — Signetics Corp., issued 1974‑10‑29 ("High voltage, high frequency double diffused metal oxide semiconductor device")

Source: https://patents.google.com/patent/[US3845495A](/patent/US3845495A)/en ; full text at https://uspto.report/patent/grant/[3845495](/patent/3845495)

This is the most dangerous reference because it discloses element A almost verbatim, and much of the function the '549 claims attribute to the field plate and drift region:

"An insulating layer is formed on the surface. The insulating layer is relatively thin where it overlies the region in which the channel extends to the surface and is relatively thick throughout the remaining portions."

"Additional metallization is disposed on the insulating layer adjacent the gate metallization and extends outwardly towards the drain metallization so that it overlies substantially all of the depletion region in the drain region. In certain embodiments, the gate metallization and the additional metallization are interconnected."

"…by the use of the metal overlay or field plate whose length is at least as great as a maximum depletion width spreading an extremely high voltage capability obtainable. … The drain is the high resistivity region; therefore, most of the depletion width associated with the reverse biased drain junction is on the drain side. Consequently, breakdown voltage limitations are to a large extent removed from the channel geometry to the drain."

"The gate in the device performs the dual role of forming an inversion layer in the channel and also maintains a high voltage across the drain junction."

Its FIGS. 9/10 show "another embodiment … in which the gate metallization and field plate metallization are separate."

What that gives the challenger: thin oxide over the gate‑controlled channel + thick oxide over the high‑resistivity drain/drift region + gate on the thin oxide + field plate on the thick oxide + the channel/drift functional division + field plate electrically tied to the drain + a separate‑gate‑and‑field‑plate embodiment. That is element A, and it is the express raison d'être of the Reference — the same problem ('549's stated 200–1,000 V requirement) approached the same way.

What it does not give: any concentric/circular geometry, any intermediate gate, any resistive layer, and any channel‑longer‑than‑drift ratio (Signetics' stated object is a "high voltage capability independent of the channel length," with an extremely short channel).

2.2 US 4,058,822 — Sharp K.K., issued 1977‑11‑15 ("High voltage, low on‑resistance diffusion‑self‑alignment metal oxide semiconductor device")

Source: https://patents.google.com/patent/[US4058822A](/patent/US4058822A)/en

Verified disclosure:

"The N‑type ion implanted layer 16 (the drift channel region) is formed on the surface of the silicon body 10 to extend between the drain N⁺ region 30 and the channel region 36… The drain metallization 48 extends toward the gate metallization 50 to cover the drift channel region 16 via the thick insulating layer 18. Moreover, the gate metallization 50 is also slightly extended toward the drain metallization 48 to reach over the thick insulating layer 18."

"The electric field in the lateral direction is relaxed by the provision of the drift channel region 16. The electric field in the vertical direction is relaxed near the boundary area of the drain contact region because of the provision of the extended metallization or the field plate 481."

"The device shows the avalanche breakdown voltage of 500 to 700 V when L' is 50 to 80 µm, FP is 10 to 45 µm, and S is 15 to 25 µm."

Two things matter enormously here:

1. The gate is extended over the thick oxide toward the drain. That is precisely the geometric move the '549 specification describes for its FIG. 3 embodiment ("the thick thermal oxide layer 27 … is shortened considerably, while the gate 23 is correspondingly lengthened"), with the same consequence the patent touts — lower on‑resistance / higher current.
2. Sharp expressly parameterizes the design space in terms of the drift‑region length L', the field‑plate overlap FP, and the gate‑to‑drain spacing S, against the resulting breakdown voltage. It teaches, in other words, that the relative lateral lengths of the gate‑controlled region and the drift region are selection variables traded against breakdown/on‑resistance.

2.3 US 4,115,709 — Nippon Electric Co., issued 1978‑09‑19 ("Gate controlled diode protection for drain of IGFET")

Source: https://patents.google.com/patent/[US4115709A](/patent/US4115709A)/en

Verified disclosure: a gate electrode over a gate insulator spanning a p‑n junction, where

"The breakdown voltage of a p‑n junction primarily depends upon the impurity concentrations of the regions on both sides of the junction. Where the insulating film on the exposed edge of the junction is thin, it also depends on the thickness of the insulating film. Moreover, the breakdown voltage further depends on the gate voltage applied to the gate electrode on the thin gate‑insulating film… The breakdown voltage of the p‑n junction of the gate‑controlled diode can be made lower than that of the drain junction of the transistor by controlling at least one factor of impurity concentration …, thickness of the gate insulator, and polarity and amplitude of a voltage applied to the gate electrode…"

Claim 3 of '709 adds that the gate is "electrically isolated from said drain."

This is the teaching that a separately biased, isolated electrode over an insulating layer that spans the high‑field junction directly and controllably modifies that junction's breakdown voltage. Functionally, that is the "intermediate gate" of '549 claim 1 (which the specification says is "connected to an intermediate voltage of about 200 volts for a drain voltage of 400 v"). NEC uses it to lower a diode's breakdown deliberately; the principle it states is fully symmetric and immediately recognizable to a POSITA as usable to grade/raise the field at a drain‑channel corner.

2.4 US 3,996,655 — Texas Instruments, issued 1976‑12‑14 (1‑micron‑channel isolated IGFETs)

Source: https://patents.google.com/patent/US3996655

Verified: the D/MOS process "forms the required source diffusion. This provides a narrow p‑type channel adjacent to the source with an extended drift region in the substrate material to the drain, thereby providing a 1‑micron or less channel length," and the driver/load combination "is isolated from other components in the substrate by the large p‑type region surrounding both of the drain regions." Cumulative art on (i) the short‑channel + long‑drift architecture and (ii) isolation of an individual high‑voltage device by a surrounding region — the latter being the functional seed of '549's source‑ring shielding rationale.

2.5 JPS53980A — Hitachi Ltd., published 1978‑01‑07 (JP app. 82967/1977, filed 1977‑07‑13), "Field‑effect transistor of high dielectric strength"

Source: https://patents.google.com/patent/JPS53980A/en (surfaced via https://patents.google.com/patent/JPS5436465B2/en)

Explicit gap: I retrieved only the bibliographic record (title, assignee, dates) — not the disclosure. Because it published 1978‑01‑07, less than one year before the 1978‑12‑18 filing, it is citable only as pre‑AIA § 102(a) art (subject to swearing behind by the inventor), not as a § 102(b) statutory bar. I cannot presently state what it teaches. It is flagged here as the single highest‑value unexamined lead for a claim‑1/claim‑3 challenge on the concentric layout, given its title and its repeated citation in high‑withstand‑voltage FET families.

Also flag (contradiction check): the "Family Cites Families" listing on the Google Patents page includes JPS5849210B2 — "Shutter of poultry feeding equipment" (Nakajima Seisakusho). On its face that is a citation‑mapping artifact and irrelevant prior art; it should not be used. It does not contradict the earlier bibliographic section, but any analyst working from that table should exclude it.

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3. Differences between the claims and the art

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4. The § 103 combinations

Combination 1 — US 3,845,495 + US 4,058,822 → claim 3

Elements addressed: A + E. Claim 3 does not require the intermediate gate (C) or the resistive layer (D), so this two‑reference combination reaches the entire claim.

What the combination teaches. Signetics supplies the split‑oxide, gate‑over‑thin‑oxide, field‑plate‑over‑thick‑oxide architecture and, critically, the express functional account that the drain/high‑resistivity region absorbs the depletion spread while the field plate spans it — i.e., '549's "channel region" and "drift region" as claimed. Signetics moreover teaches that the gate and the field‑plate metallization may be separate (FIGS. 9/10). Sharp supplies the disclosed refinement of exactly that structure in which the gate metallization is deliberately extended over the thick oxide toward the drain and in which the length of the drift region, the field‑plate overlap and the gate‑to‑drain spacing are quantified (L′ = 50–80 µm; FP = 10–45 µm; S = 15–25 µm) against a 500–700 V breakdown.

Why a POSITA would combine them. Both references are in the same field, address the same two‑way tradeoff (§ junction breakdown vs. on‑resistance/speed), and describe the same physical stack (thin gate oxide, thick field oxide, gate metal, field‑plate metal tied to drain). Signetics even states its own limitation indirectly — its high‑voltage design is deliberately independent of channel length and its long depletion overlay increases series resistance; Sharp expressly claims "low on‑resistance" as its object. A designer asked to make a driver that both withstands ~200–1,000 V (Signetics' problem) and pulls its output low during conduction (Sharp's problem) would predictably do what Sharp already did: extend the gate‑controlled channel and shorten the thick‑oxide drift span. KSR ("known technique to improve a similar device in the same way"), In re Keller, 642 F.2d 413 (CCPA 1981).

Why the claim's "higher current handling capability" language adds nothing. Claim 3 recites no structure beyond a relative dimension, with a stated result — and the specification itself concedes both the modification and its consequence:

"The device of FIG. 3 is a modification of the device of FIG. 1A to allow for higher current conducting capability… The thick thermal oxide layer 27 in the FIG. 3 version is shortened considerably, while the gate 23 is correspondingly lengthened. The result is a much smaller drift area L5 … and a much larger channel area L2 under control of the gate 23."

"The result is that the FIG. 3 embodiment has a higher current conducting capability but a lower voltage handling capability. The actual device is limited to a maximum drain 22 voltage of somewhat more than 400 volts."

Tradeoff claims of this kind are the paradigm of In re Aller, 220 F.2d 454 (CCPA 1955) ("the optimization of… parameters… is well within the ordinary skill of the art"), and KSR's "a court must ask whether the improvement is more than the predictable use of prior art elements according to their established functions." The longer gate‑controlled region reduces series resistance; the claim recites no departure from that expectation. Also relevant: US 3,996,655 establishes that the channel/drift proportion is a process‑controlled knob (narrow diffused channel + extended drift, <1 µm), removing any argument that the ratio was unavailable or unexpected.

Anticipated counter‑argument (teaching away) and its weakness. Applicant could argue Signetics states an object of "high voltage capability independent of the channel length," so lengthening the channel is contrary to its teaching. That is a Gurley-type argument, 27 F.3d 551 (Fed. Cir. 1994), but Signetics addresses only the high‑voltage design point; it does not disparage longer channels or criticality of the ratio. And Sharp — same field, later, and citing into the same art — teaches the very structure. At most Signetics gives a reason to prefer the FIG. 1A geometry for maximum voltage, which is precisely the tradeoff the applicant conceded.

Assessment: Claim 3 is a strong invalidity candidate with clear and convincing evidence. It is a claim to a design optimum, the optimum is disclosed as a design parameter by Sharp, and the specification supplies the admission.

Combination 2 — US 3,845,495 + US 4,058,822 + US 4,115,709 → claims 1 and 2

Elements addressed: A + C (+ D via the resistive‑field‑plate reasoning discussed below).

The intermediate gate (C). Once the architecture of Combination 1 is assumed, the remaining difference of claim 1 is a second isolated conductive segment on the same thick oxide between the gate and the field plate, biased at an intermediate potential. NEC '709 supplies the operative principle with unusual clarity: the breakdown voltage at a junction is a direct function of the voltage on a gate electrode over the insulator covering that junction ("polarity and amplitude of a voltage applied to the gate electrode"), and NEC's own claim 3 requires that electrode to be "electrically isolated from said drain" — the isolation limitation of '549 claim 1. Sharp supplies the complementary teaching that extending an electrode (gate metal) over the thick field oxide "relaxes the electric field at the boundary area of the channel region," i.e., that adding/grading metal coverage over the thick oxide improves the voltage‑withstand at the field‑crowded boundary.

Why a POSITA would combine them. '549's own specification states the mechanism and the motivation, which is itself evidence of what the skilled artisan would have thought obvious — the intermediate gate is described as a compromise between the FIG. 1A and FIG. 3 designs, i.e., a routine partition of the surface potential along the thick oxide:

"This intermediate gate 40 is connected to an intermediate voltage of about 200 volts for a drain voltage of 400 v… the electrical field gradient lines do not bend as sharply nor are they as concentrated near the drain‑channel junction… On the other hand, the provision of intermediate gate 40 reduces the series resistance… The corresponding disadvantage of this configuration is that a separate and additional voltage must be provided to the device."

Where a reference teaches that (i) any point in a drift region can be biased to grade the local field (NEC), (ii) metal over thick oxide is already used for exactly that purpose and is a known parameter (Sharp's FP and gate extension; Signetics' separate field‑plate embodiment), and (iii) the only cost of adding one more segment is an extra bias tap — a known technique used to improve a similar device in the same way — the addition of the isolated intermediate gate is within the ordinary skill. The claimed "electrical isolation" is a design choice that NEC expressly claims.

The concentric layout (B) — the real battleground. None of the four face‑cited references discloses a complete concentric arrangement with the source as the outer ring. Two independent rationales make that geometry an obvious design choice for the stated purpose:

• Junction curvature. The '549 specification itself identifies the failure site as "point 26, the sharp corner of the junction between the drain 22 and the L3 portion of the channel," where "the lines of equal potential … bend upward into the thermal oxide layer 27 and crowd around point 26." A closed circular junction has no such exposed corner. Eliminating junction curvature by using circular/annular junction geometries was standard planar‑junction practice (field‑limiting rings and closed geometries around high‑voltage junctions), so the geometry is a predictable solution to an expressly recognized mechanism. I did not verify a specific pre‑1978 reference on this in this session — see §5.
• Shielding / cross‑talk. The applicant's own stated problem is device‑to‑device interaction on a shared LSI substrate, and the applicant's own stated solution is that "the source of each device shields the high voltage transients produced at each drain from the adjacent circuits." That is a functional, result‑oriented motivation supplied by the problem itself — a classic KSR "design incentive" — and the claimed radial ordering (source outermost) is the necessary consequence, not a new structure. Note that the claim does not quantify any shielding parameter, so it covers every closed geometry that happens to put the source outside the gate.

Assessment: Combos 1+2 make claim 1 contestable but far from automatic. A challenger must establish two things a court may not simply assume: that a complete concentric arrangement (specifically, a ring gate and a ring source enclosing a center drain, with the field plate and intermediate gate as concentric rings) was an obvious choice, and that the isolated intermediate gate's placement between the field plate and gate (rather than NEC's separate protection‑diode site) follows from the combined teachings. NEC is arguably an alternative architectural path to the same goal (divert breakdown to a sacrificial diode rather than grade the drift region), which weakens the motivation case somewhat — though under In re Fulton, 391 F.3d 1195 (Fed. Cir. 2004), disclosure of a competing alternative is not teaching away. Without the Hitachi JPS53980A disclosure or additional concentric‑geometry art, I would put claim 1 at roughly a coin flip in litigation.

Combination 3 — the above + prevailing art on resistive / semi‑insulating surface grading films → claim 2

Element addressed: D.

Claim 2 depends from claim 1, so it falls if claim 1 falls. If claim 1 survives, claim 2's additional limitation is a concentric resistive layer continuously connecting the gate and the intermediate gate, which the specification explains is nothing more than a voltage divider built into the device surface:

"…the substrate 21 sees a voltage at the other side of the thick thermal oxide layer 27 which rises smoothly from approximately zero volts at the gate 23 to a high voltage at the resistive gate contact 51 and the field plate 24… One advantage of this configuration over the embodiment shown in FIG. 4 is that an additional power supply is not necessary since contact 51 can use the same voltage used for the drain 22 voltage."

Replacing a discrete bias tap with a resistive divider is the definition of an obvious substitution of a known electrical expedient (KSR factor B; In re Boesch), and the reference is within the same structure — a resistive film spanning an oxide over a high‑field region is the "resistive field plate" concept, now formally recognized in the classification scheme (CPC H10D64/115 — "Resistive field plates, e.g. semi‑insulating field plates"; note also H10D64/112 — "Field plates comprising multiple field plate segments," which corresponds to the intermediate‑gate feature of claim 1).

Caveat: the claimant's resistive layer must be concentric and must join the gate to the intermediate gate, whereas the specification's own fabrication narrative shows the resistive polysilicon segment (50) being formed as a masked portion of the same polysilicon layer that forms gate 24/field plate 24/contact 51, and the resistive property is obtained by shielding that region from the n‑type doping drive‑in with silicon nitride (FIGS. 10A–11). This is a materials/process choice squarely within the skill of the art and, per In re Boesch, the recitation of the layer's function adds nothing.

Assessment: claim 2's validity tracks claim 1's. If claim 1 is held obvious, claim 2 falls on the known‑expedient rationale above; if claim 1 survives, claim 2 likely survives with it.

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5. Motivation summary table

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6. Secondary considerations the patentee would raise

1. Long‑felt need / commercial success. High‑voltage output drivers could not previously be integrated with LSI logic (the specification's own 16‑discrete‑amplifier narrative), and the '549/4,333,225 family sits at the root of a substantial later commercial lineage — Xerox's monolithic thermal‑ink‑jet driver chip (US 4,947,192, "Monolithic silicon integrated circuit chip for a thermal ink jet printer," listed among the "Cited By" documents for '549) and a chain of HP/Lexmark printhead‑driver patents (US 6,887,894; US 6,977,185; EP0909649A2) that cite '549. This is the applicant's best Graham argument. Weakness: nexus. The success must be attributable to the claimed concentric + intermediate‑gate combination rather than to Xerox's overall electrostatic/ink‑jet system, imaging architecture, or the separate divisional method claims. And the "long‑felt need" must be shown to have been unsolved by the art, which is precisely what Sharp and Signetics undercut in the 400–700 V range (Sharp reports 500–700 V).
2. The claimed radial ordering is functional, not decorative. Because claim 1 requires the source outside the gate, the patentee can argue no reference suggests that inversion of the conventional planar order. This is a real point, but it is answered by the applicant's own stipulated reason (shielding), which is a design incentive, not an inventive contribution.
3. No express suggestion to combine. Under KSR, an express TSM is not required; the motivation may come from the problem, the art's own teachings, or ordinary creativity. The art here is unusually explicit — three of the four references discuss field plating and field relaxation in the same terms.

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7. Bottom line

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8. Explicit limitations of this analysis

• I did not retrieve the prosecution history (file wrapper) for US 4,308,549. The examiner allowed three claims; which of B, C, D or E was treated as the point of novelty is unknown, and that materially affects how a challenger should frame the combination.
• JPS53980A (Hitachi) is unexamined. I obtained only its bibliographic record (published 1978‑01‑07; JP app. 82967/1977, filed 1977‑07‑13). Any challenge to the concentric limitation, and to claim 1 generally, should begin there. Note its pre‑AIA § 102(a) status only (published less than one year before the 1978‑12‑18 filing), which means it is subject to being sworn behind.
• I found no pre‑1978 reference for (a) a complete concentric drain/field‑plate/gate/source MOSFET layout, or (b) a resistive or semi‑insulating field plate. My search budget for this session was exhausted by a tool step limit before I could pursue them. Their existence is strongly implied by the modern classification scheme (H10D62/126 "top‑view geometrical layouts"; H10D64/112 "multiple field plate segments"; H10D64/115 "resistive field plates, e.g. semi‑insulating field plates"), but I did not verify a citable document, and I will not assert one. Treat these two topics as open leads, not findings.
• Disregard JPS5849210B2 (Nakajima Seisakusho, "Shutter of poultry feeding equipment") from the family‑citation table; it is a mapping artifact.
• Because the patent's term expired 1998‑12‑29, this analysis is of retrospective/portfolio‑relative significance (e.g., for the validity of later Xerox/HP/Lexmark patents that cite '549 as background art), not for any current infringement exposure.

Primary sources: US 4,308,549 A — https://patents.google.com/patent/US4308549/en · US 3,845,495 — https://patents.google.com/patent/US3845495A/en · US 4,058,822 — https://patents.google.com/patent/US4058822A/en · US 4,115,709 — https://patents.google.com/patent/US4115709A/en · US 3,996,655 — https://patents.google.com/patent/US3996655 · JPS53980A — https://patents.google.com/patent/JPS53980A/en