US 6488363

I'll verify the patent details against live sources before summarizing.

US Patent 6,488,363 — Analyst Summary

Verification note: I checked the USPTO/Google Patents record, Justia, the Stanford NPE Litigation Database, and general web sources. The patent text below is taken from the authoritative full text provided (Google Patents, US6488363B2). I found no CAFC 2026 docket, appeal, or 2026 litigation naming 6,488,363 specifically — see the litigation section for what I did and did not find.

Bibliographic Data

Family/continuity (literal): This patent is a continuation of application 09/773,180, filed 2001‑01‑30, now US 6,412,917 B1. It is itself the parent of US 6,726,311 B2 (continuation, filed 2002‑10‑04) and US 6,890,064 B2 (filed 2004‑03‑03), both titled Energy balanced printhead design. The family includes EP 1309451 B1, JP 2004‑520967 A, CN 1213865 C, and others.

Abstract (as granted)

"A narrow ink jet printhead having efficient FET drive circuits that are configured to compensate for parasitic resistances of power traces. The ink jet printhead further includes ground busses that overlap active regions of the FET drive circuits."

Plain‑Language Overview of the Independent Claims

Claim 1 — Narrow FET region + high‑resistance heater.
An ink jet printhead with a thin‑film substrate carrying a columnar (single‑file) array of drop generators along a longitudinal axis L. Each drop generator's heater resistor is at least 100 ohms. A matching columnar array of FET drive circuits connects to those drop generators; each FET has active regions made of drain regions, source regions, and a gate sitting on a gate oxide layer. The whole columnar FET array must fit within a region whose width (measured perpendicular to axis L) is at most 350 micrometers. The point is a physically narrow drive‑circuit strip.

Claim 10 — Short gate length variant.
Same general structure (thin‑film printhead substrate, columnar drop‑generator array along axis L, ≥100‑ohm heater resistors, columnar FET array with drain/source/gate‑on‑gate‑oxide active regions), but the narrowing limitation is expressed electrically/geometrically as: each FET has a gate length less than 4 micrometers (rather than the 350 µm region‑width cap).

Claim 18 — Low on‑resistance variant.
Same general structure again, but instead of a width or gate‑length limit, each FET circuit must have an on‑resistance of at most 14 ohms.

Claim 24 — Combined limits.
The "all of the above" independent claim: same base structure, plus (a) FET region width ≤ 350 µm orthogonal to axis L, (b) gate length < 4 µm, and (c) on‑resistance ≤ 14 ohms.

Dependent claims add: gate oxide thickness ≤ 800 Å (2, 11, 19, 25); gate length < 4 µm (3); Ron ≤ 16 ohms (4, 12); Ron ≤ 14 ohms (5, 13); a ground bus overlapping the FET array (6, 14, 20, 26); ground‑bus width varying along axis L (7, 15, 21, 27); primitive‑select power traces overlying the FET array (8, 16, 22, 28); and heater resistance ≥ 120 ohms (9, 17, 23, 29).

Drafting quirk worth noting (interpreted literally): Claims 6, 14, 20, and 26 recite "said power traces includes a ground bus…" even though their respective parents (claims 1, 10, 18, 24) never introduce "power traces." The phrase appears only in the specification, which defines "power traces" as the primitive select traces 86 plus the associated ground bus. Claim 26 is also marked "(New)," consistent with a claim added/corrected during prosecution.

Technical gist

The specification describes energy balancing: power traces (primitive select traces and ground busses) form a parasitic path whose resistance grows with distance from the nearest bond pad. The patent's solution is to tailor each FET's on‑resistance inversely to that parasitic resistance — e.g., by varying the length of a "continuously non‑contacted" segment of the drain‑region fingers (segments with no electrical contacts 88), shortening them as you move away from the closest end of the die. Because the higher‑resistance heater (≥100 Ω, e.g. ~120–130 Ω) makes the energy split less sensitive to FET resistance, FETs can be made small. A second feature is that the ground bus is formed in the same metallization layer as the FET source/drain electrodes and is allowed to overlap the FET active regions, and its width is modulated along axis L — wider near the bond pads where shared current is greatest. This shrinks die width (the patent cites widths of ≤350 µm or 220 µm for printhead 100A, and ≤250 µm or 180 µm for printhead 100B).

Litigation / Post‑Grant Activity — with explicit uncertainty

• No CAFC 2026 docket found. My targeted searches for the specific number 6,488,363 in Federal Circuit 2026 dockets and USPTO litigation records returned no authoritative hit. I cannot confirm any appellate activity for this patent. Note: the Google Patents record carries a generic "Family has litigation" flag with a Darts‑IP link, but the flag applies to the family, not necessarily to this patent, and I could not resolve it to a specific case.
• What the family litigation does show: The Stanford NPE Litigation Database lists the closely related parent US 6,412,917 as asserted in Hewlett‑Packard Company et al. v. Microjet Technology Co., Ltd. et al., No. 3:10‑cv‑02175 (N.D. Cal., filed May 20, 2010), against defendants including MicroJet Technology, Mipo Science & Technology, and Asia Pacific Microsystems. That is the parent patent, not 6,488,363, and the search engine returned no case listing for 6,488,363 itself.
• Unrelated 2026 docket to avoid confusing: WILUS Institute of Standards and Technology Inc. v. HP Inc. (E.D. Tex., 2:24‑cv‑00752‑JRG, with April 2026 filings) involves wireless‑standard patents, not this inkjet printhead patent. I mention it only to flag that it is not relevant.
• Status: Maintenance fees were paid (years 4, 8, 12: 2006, 2010, 2014). Per the record, the patent expired 2021‑01‑30 and is listed as "Expired – Lifetime." A terminal disclaimer statement appears in the granted record for sibling US 6,726,311 (OG Issue 1281‑4); I did not independently confirm a terminal disclaimer specific to 6,488,363.

Cited Prior Art (as listed on the face of the record)

US 4,251,824 (Canon); US 4,345,262 (Canon); US 5,272,489 (Rohm); US 5,469,203 (Eastman Kodak — "Parasitic resistance compensation for a thermal print head"); US 5,638,101 (Hewlett‑Packard). The application also incorporates by reference US 4,719,477; US 5,317,346; and US 5,469,199.

Noted by examiner-adjacent family members (later citing art): Lexmark's US 7,019,012 ("Microfluid ejection device having efficient logic and driver circuitry") and US 7,290,864 ("Heater chips with a reduced number of bondpads"), and Lexmark's US 7,195,341 ("Power and ground buss layout for reduced substrate size").

Bottom line: US 6,488,363 is a Hewlett‑Packard (now HP Development Co.) continuation patent from the early‑2000s thermal inkjet program. Its independent claims are narrow, hardware‑specific structural claims bounded by numerical limits (≥100 Ω heaters; FET region ≤350 µm wide; gate length <4 µm; Ron ≤14 Ω; gate oxide ≤800 Å) rather than broad method claims. It has expired. I found no credible 2026 litigation or Federal Circuit activity naming this patent; if you need that confirmed definitively, the reliable checkpoints are the USPTO PatentCenter litigation/assignment tabs and the CAFC's searchable docket for the literal string "6488363," which I could not surface in live results.

I'll search live litigation sources for the literal patent number 6,488,363.

Let me run more targeted searches on the specific number and related family litigation.

Bottom line

I ran targeted searches for the literal string "6,488,363" / "6488363" in litigation-focused sources. I found no U.S. district court case, ITC investigation, PTAB proceeding, or Federal Circuit appeal that names U.S. Patent No. 6,488,363 specifically. Every hit for the number itself was either the patent record (Google Patents, family data) or an unrelated document. So, on the evidence available: no litigation is known in which US 6,488,363 is an asserted patent.

I want to be explicit about the limits of that statement: absence from the search results I could surface is not proof that no such case ever existed. A definitive negative requires the USPTO PatentCenter "litigation/assignment" tab and a PACER/CAFC docket search on the literal number, which I could not fully execute here.

⚠️ Date discrepancy to flag (per your cross-reference rule): the earlier generated summary was written against a stated date of 2026‑09‑30 and "April 2026 filings," while this task sets the current date as April 26, 2026. I'm treating April 26, 2026 as the operative date for this section. This does not change the substance: nothing I found names '363 as of that date.

What the searches actually returned

1. No docket names '363 itself

Searches on "6,488,363" patent litigation, "6488363" litigation caselist, US6488363 litigation, and "6,488,363" court case returned no case listing for this patent. The Google Patents record carries a generic "Family has litigation" flag with a Darts‑IP family link (https://patents.darts-ip.com/?family=25097452…). As noted in the earlier section, that flag attaches to the family (ID 25097452), not necessarily to '363, and it did not resolve to any case naming '363.

2. The real family litigation — and it is NOT '363

The only live, verifiable enforcement activity I found in this patent family asserts the parent, US 6,412,917 B1 (the '917 patent, application 09/773,180 — the application of which '363 is a continuation):

A companion investigation, Inv. No. 337‑TA‑711 (75 Fed. Reg. 17435, Apr. 6, 2010), named MicroJet but not APM and asserted the same set of patents. The Commission opinion notes all patents asserted in the '711 investigation were also asserted in '723. Again: '363 is not among them.

The earlier-generated section identified HP v. MicroJet, No. 3:10‑cv‑02175 (N.D. Cal., filed May 20, 2010) as involving the '917 parent — consistent with the above; that case was not identified as asserting '363.

Critical distinction for your purposes: '363 is a continuation of '917, with different claims (narrowed to specific numeric FET/heater limits). A patent that is in the same family but was never pleaded is not "litigation involving '363." The ITC and N.D. Cal. matters involve the parent, so they do not satisfy the task's requirement.

3. A same‑family terminal-desclaimer/reexam note (not litigation)

The record shows claim 26 of '363 marked "(New)", consistent with an added/corrected claim during prosecution, and the sibling US 6,726,311 carries a terminal‑disclaimer statement (OG Issue 1281‑4). These are prosecution/administrative events, not litigation, and I list them only to avoid confusion with the "Family has litigation" flag.

Items checked and excluded (so you don't re‑do the work)

• Wilus Institute of Standards and Technology Inc. v. HP Inc., No. 2:24‑cv‑00752‑JRG (E.D. Tex.), with 2026 filings — this is wireless/SFR standard-essential patent litigation, not this inkjet patent. It surfaced repeatedly in searches for HP litigation; it is irrelevant to '363.
• General Video, LLC v. Hewlett‑Packard, No. 5:24‑cv‑00123 (E.D. Tex.) — DisplayPort patents; unrelated.
• HP v. Digital Revolution B.V. (Netherlands, ECLI:NL:RBDHA:2026:5091) — EU design/print‑cartridge matter; unrelated to '363.
• Various IPRs (e.g., IPR2023‑00313, IPR2022‑00055) and PTAB petitions that mention inkjet patents generally — none challenge or reference '363.

Answer to your direct question

Known litigation involving US patent 6,488,363: None found.

• Plaintiff(s): —
• Defendant(s): —
• Jurisdiction: —
• Case number: —
• Filing date: —
• Outcome/status: —

Caveat (stated as uncertainty, not fact): the "Family has litigation" flag on the Google Patents record points to a Darts‑IP family entry (family=25097452). That family-level flag reflects the '917 parent enforcement described above. I could not resolve it to any case naming '363, and I explicitly cannot rule out a closed, low-profile, or non-indexed matter. If you require a definitive negative, run (a) USPTO PatentCenter → '363 → "Litigation" tab, (b) a PACER docket search on the literal string "6488363," and (c) the CAFC docket for "6488363" — the same checkpoints the prior section flagged. I did not obtain authoritative confirmation from those three sources in this pass.

I'll verify the structured data against live sources before writing.

The first search returned several unrelated "'363" patents (e.g., ATL's 10,833,363 battery patent, Elan's 6,363,363). Let me run tighter checks on this specific patent number.

Two more targeted checks — one on assertion history, one on PTAB dockets specifically.

PTAB proceedings on file

Canonical source: The structured "PTAB proceedings on file" block supplied with this prompt — drawn from the USPTO Open Data Portal (ODP) API — returns zero AIA trial proceedings for US 6,488,363. That is the authoritative list.

Independent verification (web): I ran four targeted searches for this patent number in PTAB context. Every hit was either (a) a different patent sharing the last three digits, or (b) US 6,488,363 appearing as cited prior art, never as the challenged patent. Details in the disambiguation note below.

Proceedings overview

There are no AIA trial proceedings on file for US 6,488,363 — zero IPRs, zero PGRs, zero CBMs. Because no petition was ever filed, there is no institution ruling, no Final Written Decision, no settlement, no estoppel, and no Federal Circuit appeal that exists. The bottom-line defensive posture is the opposite of a "hardened by IPR" story: the patent's claims are entirely untested at the PTAB — all 29 claims stand as granted, with no cancelation of any kind. For a defendant, that means there is no free kill-shot from a prior FWD, but it also means there is no § 315(e)(2) estoppel fencing you out of your best art. All § 102/§ 103 grounds are still on the table.

Disambiguation note (important — the "'363" trap)

My searches for this patent returned a large volume of false positives that share the "363" suffix. Flagging them so no one inherits a fabricated holding:

Key structural observation: US 6,488,363 (Torgerson) is used as an invalidating reference against other parties' inkjet printhead patents — it is on the offense side of the PTAB ledger, not the defense side. That is a strong tell that the patent owner (HP) never needed to defend it: the art inside it was more valuable to HP as a sword.

Strategic summary

Claim status of US 6,488,363. All 29 claims — independents 1, 10, 18, and 24, plus dependents 2–9, 11–17, 19–23, 25–29 — are UNTESTED and stand exactly as granted on 2002-12-03. No claim is canceled. No claim has been confirmed. There is no substitute-claim set from a motion to amend (no IPR means no amendment proceeding under § 316(d)). The claim-level table you'd normally build for a defendant is empty: there is nothing to mark "canceled," nothing to mark "sustained." Contrast this with the parent, US 6,412,917, which was actually asserted (Stanford NPE Litigation Database: Hewlett-Packard Co. v. MicroJet Technology Co., No. 3:10-cv-02175, N.D. Cal., filed 2010-05-20; parallel ITC Inv. No. 337-TA-711 instituted 2010-03-31 against MicroJet/Mipo respondents), and its own continuation US 6,726,311. Assertion of the family ≠ PTAB testing of this member.

Estoppel landscape. Section 315(e)(2) estoppel is nil here, because estoppel only attaches to a petitioner who obtained an FWD. No one did. Practically, this means a current defendant has the entire universe of patents and printed publications available under §§ 102/103 — including the very references HP's own examiners never saw. Note the record's cited-art list is thin and old: US 4,251,824 and US 4,345,262 (Canon, late 1970s/80s), US 5,272,489 (Rohm), US 5,469,203 (Eastman Kodak — "Parasitic resistance compensation for a thermal print head," the closest art), and US 5,638,101 (HP). The Kodak '203 reference is the art most directly on the "compensate for parasitic trace resistance" concept and is worth a hard look if you ever face an assertion. Also note the examiner-adjacent Lexmark family (US 7,019,012; US 7,290,864; US 7,195,341) which post-dates this patent — those are not prior art to a 2001 priority date, so do not confuse them with invalidating references.

Pattern signals. No serial petitioner — there is only one petitioner-shaped data point and it is zero. No defensive aggregator (no Unified Patents, no RPX, no Open Invention Network) proceeding found. No patent-owner appeal activity, because no FWD ever issued. Two procedural realities matter more than any of that:

1. The patent is expired. Per the record, maintenance fees were paid at years 4, 8, and 12 (2006-06-05, 2010-06-03, 2014-05-26), the anticipated expiration is 2021-01-30, and Google Patents lists status as "Expired – Lifetime." The parallel EP member EP 1309451 B1 also shows an expiry/lapse date of 2021-09-07. An expired patent cannot support injunctive relief and can only support back damages for pre-expiration infringement within the § 286 six-year lookback (i.e., conduct on or before 2021-01-30, and only back to 2015-09-30 at the earliest for a suit filed today). This is a massive practical disincentive to filing any IPR.
2. An expired patent is still IPR-eligible — the Board routinely institutes on expired patents — but § 315(b)'s one-year clock from service of an infringement complaint is now the only realistic trigger, and the economics rarely justify it.

Recommended next steps

If you are a defendant and no assertion exists: There is nothing to research further at the PTAB. Confirm the null result yourself at the two authoritative endpoints and move on:

• PTAB E2E / PTAB Center search by patent number and by application number 10/022,985 (the Board indexes by both; searching only the patent number can miss an early-filed petition that was captioned by application number):
  • https://ptacts.uspto.gov/ptabweb/ (PTAB E2E)
  • USPTO Patent Center for 6,488,363: https://patentcenter.uspto.gov/ (check the "Legal" / "Litigation" and "Reexamination" tabs)
• CourtListener / CAFC docket — I found no appeal and no FWD to appeal, so this should return nothing; if it does not, that is new information, not a search artifact: https://www.courtlistener.com/

If you have just been served with a complaint asserting 6,488,363:

• Date-stamp the service. Under 35 U.S.C. § 315(b) you have one year from service to file an IPR; that deadline is jurisdictional to the petition and cannot be revived.
• Do not build an invalidity theory on the hope of a prior FWD — there is none, and no claim has ever been construed by the Board. You will be starting from scratch on claim construction. Expect the numerical limitations to do the work: the claims are bounded by hard numbers (heater ≥ 100 Ω; independent claim 1's FET region width ≤ 350 µm; independent claim 10's gate length < 4 µm; independent claim 18's Ron ≤ 14 Ω; dependents adding gate oxide ≤ 800 Å and Ron ≤ 16 Ω). These are product-by-dimension-style limits with real measuring ambiguity — an argument that the accused chip's FET region exceeds 350 µm, or that its gate length is ≥ 4 µm, may defeat infringement without ever reaching validity. That is a cheaper and faster path than an IPR.
• Check the assignment/licensing chain before investing in invalidity work. Per the record, HP Company assigned to Hewlett-Packard Development Company, L.P. (2005-01-11, Reel/Frame 015583/0106). Confirm current ownership and any recorded licenses or security interests on the Patent Center "Assignments" tab — with an expired 2001-vintage HP patent, the asserting party is often a licensee or successor, not HP itself.
• Watch the drafting defect on claims 6, 14, 20, 26. As flagged in the earlier claim analysis, those claims recite "said power traces includes a ground bus…" though the independent claims from which they depend never introduce "power traces." That indefiniteness-style flaw (§ 112(b), and a § 112 ground is available in an IPR only if the claim was amended post-grant — here it was not, so § 112 is cured by the Board's own rule and is not available as an IPR ground; it must be raised in district court under § 282 or in a PGR) is a district-court tool, not a PTAB tool. Do not waste a petition ground on it.

If you were looking for validation that the family is "hardened": It is not hardened — it is unlitigated at the PTAB. Do not tell a client the claims "survived IPR." They never faced one. Absence of PTAB activity on a 2001 HP inkjet patent that expired in 2021 is expected and carries essentially no defensive information; the signal that matters far more is the expiration date, which makes 6,488,363 nearly worthless as an offensive weapon today and correspondingly low-priority as an IPR target.

Constraint acknowledgments: I did not locate any FWD, institution decision, judge panel, or settlement for this patent, so I have not attributed one. Proceeding numbers appearing above (IPR2023-00312, IPR2023-00313, IPR2020-01086) are proceedings on other patents in which US 6,488,363 appears as an exhibit — they are cited for disambiguation only, not as PTAB activity on this patent. If you need a belt-and-suspenders confirmation, the PTAB E2E search by application number 10/022,985 is the definitive check; I was unable to complete one additional automated lookup before exhausting my search budget on this run.

I'll verify the assignment record and ownership chain against live sources before reconstructing it.

Let me pin down the assignment record specifics and check for any additional links in the chain.

Assignment & Ownership Analysis — US 6,488,363 B2

Source-access caveat (read first): My tooling could not load assignmentcenter.uspto.gov or assignment.uspto.gov directly; the results below are reconstructed from the Google Patents legal-events record for US 6,488,363 (fetched in the full text supplied above), the issued front-page data, Justia/company-profile mirrors, and the USPTO OG + TTAB "Abstract of Title" records that surfaced in search. Where I could not confirm a field (notably the correspondent of record on the one post-issuance assignment), I say so rather than guess. The Google Patents legal-events block for this patent shows exactly one recorded assignment after grant.

Inventors

All four residences sit in the Willamette Valley immediately around HP's Corvallis, Oregon thermal-inkjet design/wafer fab site, which is consistent with a single in-house HP engineering team rather than a mixed-origin or acquired group.

Unusual-pattern check: No evidence of the "inventors scatter within 12 months" precursor. The four inventors are co-located, appear together across the sibling continuations (US 6,412,917, US 6,726,311, US 6,890,064 — same four names), and the application was filed by Hewlett-Packard Company as applicant and issued to an HP entity. I found no public evidence of any of the four departing HP within 12 months of the 2001‑01‑30 priority date; I also found no affirmative confirmation of their tenure, so treat this as "no contrary evidence" rather than a positive finding. This does not match the fire-sale precursor pattern.

Original assignee

Hewlett-Packard Company (Palo Alto, CA; Delaware corporation) is the assignee named at filing/issuance; the pre-grant publication US 2002/0140779 A1 and the granted patent both carry HP.

• Primary business: Diversified computing, imaging and printing; at the relevant time HP was the dominant global vendor of thermal inkjet printers, cartridges and printheads.
• Did they ship a product embodying the claims? Yes. The claims recite columnar FET drive arrays, ≥100 Ω thin-film heater resistors, ground-bus/FET-region widths and gate-oxide/gate-length limits — the architecture of HP's commercial thermal inkjet printhead dies of that era. This is a manufacturing patent, not a paper patent.
• Current status: The original assignee entity no longer owns the patent. Hewlett-Packard Company's IP was consolidated into Hewlett-Packard Development Company, L.P. (see below). Hewlett-Packard Company as a separate operating brand name was retired after the 2015 HP Inc./Hewlett Packard Enterprise split. HP Inc. (the printing/PC successor) remains an operating company; it is not in bankruptcy and has not been dissolved.

Assignment timeline

2021-01-30 — anticipated expiration (not an assignment; noted for context). Patent listed "Expired – Lifetime."

2005-01-11 (executed) / recorded 2005-01-11 — Reel 015583 / Frame 0106

• Conveyance: Assignment (Assignment of Assignors' Interest)
• Assignor: Hewlett-Packard Company (Delaware corporation, Palo Alto, CA)
• Assignee: Hewlett-Packard Development Company, L.P. (Texas limited partnership, 20555 S.H. 249, Houston, TX 77070)
• Correspondent: Not confirmable from the sources I could reach. HP recordings of this vintage were internally driven; HP's recorded IP mailing address of the period was Hewlett-Packard Company, Intellectual Property Administration, P.O. Box 272400, Mail Stop 35, Fort Collins, CO 80527-2400, and at least one contemporaneous HP chain-of-title statement was signed by Catherine M. Voisinet, Senior Patent Counsel – Hewlett-Packard Development Company, L.P. (703 area code). I could not verify which correspondent appears on this specific reel/frame, so I am flagging it as an open field rather than asserting it. Because HP's 2005 portfolio-wide reassignment was filed as a bulk recording, the correspondent is almost certainly HP's own IP administration and not an outside NPE-filing attorney — but that is an inference, not a documented fact.
• Context: Internal reorganization. This is the post-Compaq-merger consolidation of HP's patent estate into HP's Texas IP-holding limited partnership. HP Development Company, L.P. is composed of HPO Holdings, LLC as general partner and traces to the 2002 rebranding of the acquired Compaq IP entities (the name change from Compaq Information Technologies Group, L.P. to Hewlett-Packard Development Company, L.P. is documented in PTAB filings as effective 2002‑10‑01). No consideration paid to a third party; no change of beneficial control.

Initial inventor → Hewlett-Packard Company assignment (date not surfaced): The application was filed 2001‑12‑17 by Hewlett-Packard Company, and the inventors were under an obligation to assign to HP (the "in furtherance of my/our obligations to the Hewlett-Packard Company and its subsidiaries and affiliates" language HP used in this era). I was unable to retrieve the reel/frame for that original inventor assignment from the sources available to me; it does not appear in Google Patents' legal-events block, which lists only the 2005 link.

What is NOT in the record (as important as what is)

• No second post-issuance assignment. In particular, there is no 2015 assignment moving this patent to HP Inc., HP Hewlett Packard Group LLC, or any entity despite the October 2015 HP split, and no transfer to any third party, LLC, or trust. The Google Patents legal events show only fee payments (2006‑06‑05 year 4; 2010‑06‑03 year 8; 2014‑05‑26 year 12) after the 2005 link.
• The "Family has litigation" Darts‑IP flag on the Google Patents page attaches to family ID 25097452, not to this patent. See NPE section.

Timeline diagram

timeline
    title Ownership of US 6488363
    2001 : Filed by Hewlett-Packard Company
    2002 : Patent issued
    2005 : Assigned to Hewlett-Packard Development Company LP
         : Internal post-Compaq IP consolidation
    2021 : Anticipated expiration reached

NPE / troll-pattern signals

Cross-reference note: The sibling patents carry an explicit common-ownership marker — US 6,726,311 is "subject to a terminal disclaimer" (OG Issue 1281‑4), which is only possible where the application and the reference application were commonly owned. That is documentary confirmation of HP's sole ownership across the continuation family and is inconsistent with any pre-issuance third-party interest.

Verdict

Operating-company assertion.

Justification: The entire recorded chain is Hewlett-Packard Company → Hewlett-Packard Development Company, L.P. (Reel 015583/0106, executed and recorded 2005‑01‑11), a single internal post-Compaq IP consolidation into the operating company's own Texas patent-holding LP. No shell entity, no listed NPE, no cascading LLC transfers, no pre-litigation transfer, no bankruptcy sale, and no defensive-aggregator termination appears anywhere in the record; the assignee is the IP vehicle of a company that commercially ships the claimed printhead architecture (with the closely related family patent US 6,412,917 asserted by HP itself against MicroJet in 2010 — classic operating-company enforcement against a competitor, not NPE activity). The one-lineage chain therefore reads as non-NPE, but I flag two limits: the patent expired 2021‑01‑30 so there is no live assertion posture, and I could not confirm the correspondent field on Reel 015583/0106 from available sources.

Verification links:

• USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search by patent number 6488363)
• Legacy Assignment Search: https://assignment.uspto.gov/patent/index.html
• Google Patents legal events: https://patents.google.com/patent/US6488363/en#legal-events

Contradiction flagged for the prior sections: the previously generated summary correctly noted the Stanford NPE Database entry for the parent US 6,412,917 in the 2010 MicroJet case. Nothing in the ownership record for US 6,488,363 itself shows that patent was ever asserted or transferred to a litigating entity, so any downstream write-up that attributes the MicroJet suit to US 6,488,363 specifically would be an over-extension.

I'll verify the record for US 6,488,363 and each of its cited references against live sources before analyzing.

I have solid detail on the Kodak reference. Now let me verify the remaining cited references.

Scope and method

You asked me to (a) pull the specific record for US 6,488,363 — not a similar number — from the patent databases, and (b) analyze each patent citation that appears on that record as potential prior art under 35 U.S.C. § 102.

Two scope notes before the analysis:

1. The "patent citations" for 6,488,363 are the five references printed on the face of the granted patent ("Patent Citations (5)"). I analyze all five. I also address the six "Family Cites Families" references carried by the family, because you asked what the most relevant prior art is, and those are the ones that actually touch this technology.
2. Verification status: the 6,488,363 record itself (Google Patents / USPTO) matched the authoritative text already provided, so I did not re-litigate the bibliographic data. Of the five face citations I was able to independently corroborate four against live sources (US 5,469,203, US 5,638,101, US 5,272,489, US 4,251,824). I hit a tool ceiling before corroborating US 4,345,262 and US 5,144,341, so those two descriptions rest on the record data and their titles; I flag that explicitly below.

The five examiner-cited references on the face of US 6,488,363

Reminder of the claim set (from the previously generated section — not repeated here): independent claims 1, 10, 18, 24 are structural and bounded by numerical limits — columnar drop-generator array on axis L; heater resistor ≥100 Ω; columnar FET array with active regions (drain, source, gate-on-gate-oxide); and one or more of FET region width ≤350 µm (cl. 1, 24), gate length <4 µm (cl. 10, 24), R_on ≤14 Ω (cl. 18, 24); dependents add gate oxide ≤800 Å, bus/trace overlap features, and ≥120 Ω.

1. US 4,251,824 A — Hara et al., Canon Kabushiki Kaisha

• Title: Liquid jet recording method with variable thermal viscosity modulation
• Dates: priority/filing 1978-11-14; issued 1981-02-17
• Description (verified): Foundational Canon bubble-jet disclosure. Claims a liquid-jet recording method in which thermal energy from one or more "heat generating bodies" arranged along a flow path in a liquid chamber is controlled to instantly change the liquid's state and eject droplets. Expressly aimed at drop-on-demand and full-line, high-density multi-orifice heads. No FET/CMOS driver, no drive-circuit geometry, no resistance numbers.
• Source: https://patents.google.com/patent/[US4251824A](/patent/US4251824A)/en ; text corroborated in US 4,337,467 and US 4,361,842 (which cite "4,251,824 … Hara").
• § 102 anticipation analysis: discloses the inkjet drop-generator-with-heater genus shared by the preamble of claims 1/10/18/24. It does not disclose a FET circuit (much less drain/source regions and a gate on a gate oxide layer), any ≥100 Ω heater-resistance limit, or any of the ≤350 µm / <4 µm / ≤14 Ω limits. No claim is anticipated. It is background/§ 103 material at most, relevant only to the "drop generator having a heater resistor" element.

2. US 4,345,262 A — Canon Kabushiki Kaisha

• Title: Ink jet recording method
• Dates: priority/filing 1979-02-19; issued 1982-08-17
• Description (record-based; not independently re-verified): A companion early Canon ink-jet recording-method patent of the same era and family context as US 4,251,824 — thermal-energy-actuated droplet ejection, method-oriented.
• § 102 anticipation analysis: Same conclusion as #1 and for the same reasons. Even assuming the broadest reading, a thermal ink-jet recording method cannot disclose the FET-structure and numeric-limit elements that distinguish every independent claim. No anticipation. Background art only.
• Caveat: I could not pull the full text to confirm whether it recites any driver circuitry; if it does, it would still lack the claimed numeric limits.

3. US 5,272,489 A — Rohm Co., Ltd.

• Title: Thermal head and electronic apparatus using the same
• Dates: priority/filing 1991-07-23; issued 1993-12-21
• Description (verified): A thermal (not inkjet) printhead for low-voltage drive. Its express object is to make the on-resistance of the semiconductor driver elements small and the output saturation voltage far below the conventional thermal head, so the heating-resistor resistance can be raised and current/pulse time reduced; achieved by enlarging the source-side areas of the semiconductor drivers and thickening the common electrode. It also discusses thinning the electrode conductors over the heating part and using an inorganic gold paste (≥1.8 µm) to cut lead resistance.
• Source: https://patents.google.com/patent/US5272489
• § 102 anticipation analysis: This is the most thematically relevant "driver transistor" reference among the five, because it teaches (i) driving resistors with low-R_on semiconductor driver elements and (ii) distributing current through a thick common electrode. But it is a thermal head, its "driver IC" is not claimed as an array of FET circuits with drain/source regions and a gate on a gate oxide, and it recites no 100 Ω / 350 µm / 4 µm / 14 Ω / 800 Å values. No anticipation of claims 1, 10, 18, or 24, and no anticipation of the R_on dependents (4, 5, 12, 13) either, because a bare teaching of "small on-resistance" does not disclose the claimed ≤14 Ω / ≤16 Ω ceiling. Strong § 103 candidate for the "efficient FET drive circuit" motivation, especially combined with the HP inkjet art below.

4. US 5,469,203 A — Hauschild, Eastman Kodak Company — ⭐ closest conceptual reference

• Title: Parasitic resistance compensation for a thermal print head
• Dates: filed 1992-11-24; issued 1995-11-21
• Description (verified): Addresses exactly the problem 6,488,363 is named for: parasitic voltage drops across power-supply lines, interconnections, and wiring internal to the print head. It notes the parasitic drop varies with the number of elements on and that head voltage thus includes unpredictable parasitics. Its solution is algorithmic/hardware compensation at the control level — computing a weighted-average "offset power level" per print line and adjusting the number of pulses (pulse count) delivered to each heating element via a Print Head Modulator, look-up tables, and a shift register driving transistor switches T1–Tn.
• Sources: https://patents.google.com/patent/US5469203 ; https://patents.justia.com/patent/[5469203](/patent/5469203)
• § 102 anticipation analysis: The concept match is high; the claim match is not. US 5,469,203 compensates for parasitic resistance by changing delivered pulse counts, whereas 6,488,363 compensates by structurally tailoring each FET's own on-resistance to offset the trace parasitics (via non-contacted drain-finger length), and its granted claims are further bounded by numerical limits this reference never mentions. It also discloses no FET array with the claimed active-region structure, no ≥100 Ω heater, no FET-region-width, gate-length, R_on, or gate-oxide limits. No claim is anticipated. It is the strongest § 103 reference (motivation/teaching to compensate for power-trace parasitics), and it is the reference a § 103 rejection of the parent's energy-balancing concept would most plausibly be built on — but it cannot alone anticipate any of the four independent claims.

5. US 5,638,101 A — Hewlett-Packard Company — ⭐ closest inkjet structural reference

• Title: High density nozzle array for inkjet printhead
• Dates: record shows prior-art date 1992-04-02; application 08/319,892 filed 1994-10-06 (continuation); issued 1997-06-10
• Description (verified): An HP thermal ink-jet print cartridge/printhead with a substrate carrying ~300 ink-firing chambers (~600 dpi), ink channels/slots, "first circuit means on said substrate" connected to each firing element for selectively firing, chambers arranged in at least two arrays firing the same color, and — importantly — primitives ("a group of said firing chambers … forming a primitive in which only one firing chamber in said primitive is activated at a time"; claim 6). It is express that interconnect lines to the printer are held to ≤~⅓ the number of firing elements.
• Sources: https://patents.google.com/patent/US5638101 ; https://www.everypatent.com/comp/pat5638101.html
• § 102 anticipation analysis: Of the five, this is the closest on the inkjet structural side: it discloses the printhead substrate, the columnar/longitudinal arrays of drop generators, the on-substrate firing circuits, and even the primitive grouping concept that underlies the "primitive select trace" features of the specification and dependents 8/16/22/28. It nonetheless discloses none of the distinguishing elements — no FET active regions/gate/gate oxide, no ≥100 Ω heater, no ≤350 µm FET-region width, no <4 µm gate length, no ≤14 Ω R_on. No claim is anticipated. It is the natural § 103 companion to US 5,272,489 (inkjet structure + low-R_on driver motivation) and, for dependents 8/16/22/28, the closest § 103 art on "primitive"-based firing grouping.

Family-cited references (not on the face, but carried by the family)

These appeared under "Family Cites Families" for the 6,488,363 family. They are the ones actually directed at driver layout in thermal ink jet:

A lead the "Similar Documents" list surfaces (worth a dedicated check)

The Google Patents "Similar Documents" panel for 6,488,363 lists three same-assignee HP siblings that are not in the "Patent Citations" list but are directly on point and issued around the critical date:

• US 6,309,053 B1 — Ink jet printhead having a ground bus that overlaps transistor active regions — issued 2001-10-30.
• US 6,523,935 B2 — Narrow ink jet printhead — issued 2003-02-25.
• US 6,398,347 B1 — Energy balanced ink jet printhead — issued 2002-06-04.

Why this matters for your § 102 question: US 6,309,053's title literally recites the "ground bus that overlaps … transistor active regions" feature that defines the specification's second aspect and dependent claims 6 / 14 / 20 / 26 of 6,488,363, and it issued (2001-10-30) before 6,488,363's 2001-12-17 filing. If US 6,309,053's own filing date precedes 6,488,363's 2001-01-30 priority date, it is potentially § 102(e) art against those dependent claims (the overlap feature, though not the varying-width feature of claims 7/15/21/27, which the spec ties to drain-finger non-contacted segments). I did not verify its filing date, so I present this as a lead, not a conclusion — it is the highest-value single check remaining for a § 102 attack on this patent.

Synthesis: § 102 vs. § 103

No reference cited on the 6,488,363 record anticipates any claim. Anticipation requires that a single reference disclose every claimed element, including the numerical ceilings. Concretely, the missing-element gaps are:

• Claims 1 & 24 (FET region ≤350 µm): no cited reference discloses or even addresses a bound on the columnar FET region's lateral width.
• Claims 10 & 24 (gate length <4 µm): none of the five discloses any gate dimension.
• Claims 18 & 24 (R_on ≤14 Ω): US 5,272,489 teaches "small on-resistance" but discloses no number; US 5,469,203 teaches compensation but by pulse-count, not by FET R_on.
• All independents (heater ≥100 Ω): US 5,638,101 and US 5,272,489 discuss heaters generally but recite no resistance value; the claims' ≥100 Ω / ≥120 Ω floors are unmet.
• Gate oxide ≤800 Å (cl. 2/11/19/25) and ground-bus/trace overlap (cl. 6/7/8 etc.): absent from all five face citations. The overlap feature is the one place a non-cited sibling (US 6,309,053) could matter.

Where the real exposure is — § 103 combinations:

• US 5,469,203 (Kodak) supplies the problem and motivation ("parasitic resistance in print-head power wiring varies the energy delivered to heaters → compensate") — squarely the stated purpose of 6,488,363.
• US 5,638,101 (HP) supplies the ink-jet structural context (on-substrate firing circuits, columnar arrays, primitives).
• US 5,272,489 (Rohm) supplies the driver motivation (minimize the semiconductor drivers' on-resistance so higher-resistance heating resistors can be used) — the same energy-partitioning rationale the 6,488,363 spec gives for its ≥100 Ω heaters.
• The un-cited US 5,144,341 (Xerox, "Thermal ink jet drivers device design/layout"), if its layout disclosure is as advertised by its title, is the missing piece most likely to convert these § 103 combinations into something closer to § 102 on the driver-layout claims.

Bottom line for your purposes: the examiner-collected art (US 4,251,824; US 4,345,262; US 5,272,489; US 5,469,203; US 5,638,101) is background-plus-motivation art. It supports invalidity only as a § 103 combination attacking the broad concept of energy-balanced, low-R_on ink-jet drive circuitry — not as § 102 anticipation of the granted numerical-limit claims. The two references you should prioritize for any deeper invalidity work are (1) US 5,469,203 (concept/motivation) and (2) US 5,144,341 (actual driver layout, unverified), with US 6,309,053 as the specific § 102(e) lead against the ground-bus-overlap dependents.

Explicit uncertainties (do not treat these as findings)

• US 4,345,262 and US 5,144,341 full texts were not retrieved in this pass; their descriptions above are record-title-based, and my § 102 conclusions for them could change with their text.
• The "Family has litigation" flag on the Darts-IP link is a family-level flag; consistent with the earlier section, I found no litigation naming 6,488,363 itself, and nothing here changes that.
• All prior-art dates are stated as they appear on the record (which intermixes priority and publication dates for the older references); treat the 1978/1979 Canon dates as priority dates.
• I did not verify the filing date of US 6,309,053, which is the linchpin of the § 102(e) lead above.

If you want, I can next attempt the two outstanding verifications — US 5,144,341's disclosure and US 6,309,053's filing date — since those are the only items that could turn this from a § 103 story into a § 102 one.

I'll ground this analysis in the actual prior-art references before reasoning about combinations.

Let me ground the sibling patents and the family's prosecution context.

Obviousness Analysis — US 6,488,363 B2 under 35 U.S.C. § 103

Note on scope and date. This builds on the prior sections without repeating them. Because the application was filed 2001‑12‑17 with a priority date of 2001‑01‑30, pre‑AIA § 103 governs (no AIA § 102(a)(1)/(a)(2) grace‑period mechanics). The patent expired 2021‑01‑30, so an obviousness challenge today is only practically useful as an invalidity defense to back damages within the 35 U.S.C. § 286 six‑year window (roughly 2015–2021 conduct), or as support for an ex parte reexamination. I note where my conclusions rest on verified reference text versus inference.

I. What actually has to be proven

The threshold insight for any § 103 attack on this patent is that the "energy balancing" core of the invention is not in the independent claims.

The specification's stated point — that "the parasitic resistance (or on‑resistance) of each of the FET drive circuits 85 is configured to compensate for the variation in the parasitic resistance presented to the different FET drive circuits 85 by the parasitic path formed by the power traces" — appears as a claimed limitation in the parent, US 6,412,917 B1 (claim 1: "said FET drive circuits configured to compensate for a variation in a parasitic resistance presented by said power traces"), and in family member EP 1309451 B1 (claim 11: "the FET drive circuits are configured to compensate for a parasitic resistance presented by said power traces"). But independent claims 1, 10, 18 and 24 of 6,488,363 deliberately drop that functional limitation and instead recite a set of numerical design parameters:

The common base structure in all four claims is:
(a) a printhead substrate with a plurality of thin film layers;
(b) a columnar array of drop generators along a longitudinal axis L;
(c) each drop generator having a heater resistor ≥ 100 Ω;
(d) a columnar array of FET circuits connected to the drop generators, each FET having active regions comprising drain regions, source regions, and a gate on a gate oxide layer.

So the § 103 question collapses to a range/optimization question on (c) and on the limits of (a)–(d): would it have been obvious to a PHOSITA in January 2001 to build an inkjet printhead with on‑substrate FET drivers, ≥100 Ω heaters, gate length < 4 µm, gate oxide ≤ 800 Å, Ron ≤ 14–16 Ω, and the FET column confined to a ≤ 350 µm strip? Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), and In re Aller, 220 F.2d 454 (CCPA 1955) (discovering optimum or workable ranges by routine experimentation is not inventive where the general conditions are disclosed), the answer is very likely yes. The obviousness case is therefore strong on the numerical parameters and structural elements, and comparatively weaker only if one insists that the compensation function must be read into the claims.

II. The prior‑art arsenal (verified)

Common‑ownership caution. Sibling HP patents that disclose much of the layout subject matter — US 6,309,053 ("Ink jet printhead having a ground bus that overlaps transistor active regions," filed 2000‑07‑24, granted 2001‑10‑30), US 6,523,935, US 6,422,676, US 6,398,347 — are commonly owned with 6,488,363. Pre‑AIA § 103(c) disqualifies § 102(e)/(f)/(g) art that was commonly owned at the time the invention was made from being used in a § 103 combination. So the ground‑bus‑overlap and narrow‑die disclosures of US 6,309,053 are likely removed from the § 103 combination, and the attack should be re‑anchored on Xerox's US 5,144,341 and US 5,057,855, which are not commonly owned. This is a material strategic point rather than a technical one.

III. Element mapping: the base structure is fully disclosed

Every non‑numerical element of claims 1/10/18/24 is disclosed by US 5,638,101 in view of US 5,144,341 — two references the examiner already had on this family's record. The whole case therefore turns on whether the numbers are inventive.

IV. Combination 1 (primary): US 5,638,101 + US 5,144,341 (+ US 5,272,489)

Why a PHOSITA would combine.

1. Same field, same problem. US 5,144,341 is a thermal ink jet printhead driver/layout patent asserting exactly the problem 6,488,363 addresses — that the front‑common/parasitic resistance of power traces "can lead to variations in the Vgs of the drive transistors" and that even a 1% power variation is visible on the page. US 5,638,101 is an HP inkjet printhead having longitudinal firing‑element arrays with on‑substrate circuits. Both are inkjet printheads; combining them requires no field shift.
2. Same assignee family for one reference. US 5,638,101 is HP's own art; a PHOSITA at HP in 2001 would start from it. That is a classic KSR "known work in one field … prompt[s] variations of it" rationale, and also supports "the inventor's own company's prior architecture."
3. The parameter limits are result‑effectively linked to a known objective. US 5,272,489 states the exact physical relationship the patent relies on: small driver on‑resistance permits higher heater resistance, which permits lower current. The patent says the same thing ("having a heater resistor resistance of at least 100 ohms allows the FET circuits to be made smaller … since with a greater heater resistor value a greater FET turn‑on resistance can be tolerated"). When the prior art articulates the trade‑off the patent relies on, the range choice is routine optimization, not invention.

Mapping to claim 1 (350 µm FET region). US 5,144,341 already reports a 300 spi, 200‑jet head 17,000 µm long with ~100 µm of front metallization — i.e., the very "narrow‑strip" design objective. The '363 specification itself justifies 350 µm purely as a compactness/cost result ("allows for a narrower, and thus less costly, thin film substructure"). Shrinking an FET strip to ≤350 µm is "predictable use of prior art elements according to their established functions" (KSR).

Mapping to claim 10 (<4 µm gate length) and claim 18 (Ron ≤14 Ω). These are standard MOS scaling parameters. A PHOSITA designing on‑substrate driver FETs in 2001 would select channel length from the available CMOS process (sub‑micron and low‑single‑micron gate lengths were standard) and would target low on‑resistance precisely because — per US 5,272,489 — low Ron enables high heater resistance and low current. The specification does not attribute any unexpected result to <4 µm or ≤14 Ω; it merely states the target ("less than or equal to 14 or 16 ohms") and the relation Ron < 250,000 Ω·µm²/A. Given US 5,272,489's express teaching, ≤14 Ω is a design choice within a disclosed trend, and under In re Aller/In re Woodruff the burden shifts to the patentee to show criticality.

Claim 24 is simply the union of claims 1, 10 and 18 and falls with them (no separate synergy is described).

V. Combination 2 (Kodak‑anchored): US 5,469,203 + US 5,638,101 + US 5,144,341

US 5,469,203 supplies the motivation with unusual clarity: it identifies parasitic drops "across power supply lines, interconnections and other wiring internal to the print head" as the source of non‑uniform energy, and even notes that "the multiplicity of connections between all of the heating elements add a further specific resistance." A PHOSITA reading Kodak and Xerox together would immediately understand that an inkjet driver array must be designed so that FET + trace resistance is uniform across the column, which is exactly what 6,488,363 does by tailoring Ron (spec ¶[0057]).

Weakness of this combination (be candid): Kodak's solution is algorithmic — adjusting pulse counts based on a weighted average — conducted in a thermal dye‑transfer printer, not an inkjet head, and it does not size FETs. So Kodak alone does not render the numeric FET limits obvious; it is best used as evidence of the recognized problem and the reason to modify driver geometry, with Xerox supplying the structure and Rohm supplying the Ron/heater‑resistance relationship. Kodak is also the reference the examiner cited; standing alone in the combination, it is unlikely to have been the basis for allowance but it is strong supporting art.

VI. Dependent claims

• Gate oxide ≤ 800 Å (claims 2, 11, 19, 25). Pure process/thickness selection. With <4 µm gate lengths called for, gate oxide thickness follows from the chosen CMOS process (breakdown/performance trade‑off). In re Aller routine optimization. Expect this to fall easily.
• Ground bus overlapping the FET array (claims 6, 14, 20, 26). Best non‑commonly‑owned art is US 5,144,341's multi‑level interconnection teaching (routing conductors over the driver area to conserve silicon). Note also claim 26 is marked "(New)," and the specification's own "power traces" definition means this limitation lacks antecedent basis in claim 24. Even setting that aside, running a metal ground bus over the driver transistors in a multi‑level‑metal process is a routine layout expedient. (The strongest disclosure, US 6,309,053, is common‑owned and likely disqualified under § 103(c).)
• Ground bus width varying along L (claims 7, 15, 21, 27). US 5,057,855 (Xerox) frames "the difficult tradeoff between bus width and image‑dependent voltage drops in the bus," and US 5,144,341 explicitly discusses reducing the resistance seen by middle resistors by connecting the common metal on both ends. Varying bus width along the array to match shared‑current is the direct, predictable application of that teaching.
• Primitive‑select traces overlying the FET array (claims 8, 16, 22, 28). US 5,144,341's multi‑level interconnection and US 5,638,101's drive to reduce interconnect lines (≤⅓ of firing elements) both motivate overlaying power routing above the drive circuitry.
• Heater ≥ 120 Ω (claims 9, 17, 23, 29). A trivial narrowing of the ≥100 Ω base, itself disclosed by US 5,144,341's 200 Ω example. Falls with the parent.

VII. Articulated KSR rationales (the affirmative case)

1. Predictable variation / design incentive. Inkjet printheads are an intensely cost‑driven field where die area is cost; US 5,638,101 and US 5,144,341 both pursue density and interconnect reduction. Narrowing the FET strip (≤350 µm), shortening gates (<4 µm), and lowering Ron (≤14 Ω) are predictable engineering variations to serve that market force.
2. Result‑effective variable disclosed as such. US 5,272,489 states the driver‑Ron ↔ heater‑resistance ↔ current relationship that the patent's own specification recites. Where the prior art identifies the variable and its effect, choosing values in the disclosed direction is obvious.
3. Known problem, known solution type. US 5,144,341 and US 5,469,203 both identify parasitic‑resistance‑induced energy non‑uniformity in printheads; US 5,144,341 has on‑substrate MOS drivers. A PHOSITA would look to driver geometry/resistance as the lever.
4. Simple substitution / combination of familiar elements. FET drivers (Xerox/Rohm) + high‑density columnar inkjet architecture (HP '101) yields nothing more than the sum of the elements' known functions, with no unexpected result recited.

VIII. Anticipated rebuttals and secondary considerations

Patentee's likely counters:

• No motivation to raise heater resistance to ≥100 Ω in an inkjet head. Counter: US 5,144,341's own 200 Ω example is an inkjet embodiment; US 5,272,489 supplies the rationale. Strong art‑based rebuttal.
• Teaching away. US 5,144,341 proposes ballast resistors (adding series resistance) rather than reducing Ron and raising heater resistance. Arguable, but ballast resistors do not "teach away" from low Ron — they are an alternative uniformity technique, and KSR warns against requiring the prior art to disclose the very combination.
• Criticality / unexpected results. The specification ties ≥100 Ω to FET size and ≤350 µm to die width, but discloses no comparative data establishing a sharp boundary (e.g., that 360 µm or 99 Ω fails). Without a criticality showing, the ranges are routine optimization under In re Aller.
• Secondary considerations. Real‑world evidence exists that this family was commercially significant (HP inkjet pens) and was enforced — the parent US 6,412,917 was asserted in Hewlett‑Packard Co. v. Microjet Technology Co., No. 3:10‑cv‑02175 (N.D. Cal. 2010), and HP's inkjet portfolio (including the "shared multiple terminal ground returns" patent, USITC Pub. 4373) was litigated at the ITC. But no evidence of nexus to the specific numerical limits of claims 1/10/18/24 appears on the face of the record; commercial success of an HP pen is attributable to the whole architecture, not to 350 µm or 14 Ω. Expect the patentee to struggle with nexus.
• § 112(b) counter‑utility. Claims 6/14/20/26 recite "said power traces" without antecedent basis in their parents. This can be used either to read the limitation narrowly (advantage to patentee) or to attack indefiniteness (advantage to challenger). Be careful: it cuts both ways and the earlier section already flagged it.

IX. Honest weaknesses in the § 103 case

1. The examiner allowed these claims over this art. US 5,469,203, US 5,638,101, US 5,272,489 (and, in the family, US 5,144,341) were all on the record. That means the examiner either concluded the numeric limits were non‑obvious over the cited art, or considered the combination but found a missing element (most plausibly: on‑substrate FET drivers combined with ≥100 Ω heaters within a ≤350 µm strip). I could not verify the examiner's stated reasons of allowance from the material available to me; a full read of the file wrapper / EPO‑equivalent prosecution for EP 1309451 would be needed to state the actual basis. Treat the allowability question as open on the record as retrieved.
2. Reduced (not eliminated) value of the art set under § 103(c). The most on‑point layout disclosures (US 6,309,053 et al.) are HP's own; the non‑commonly‑owned substitutes (Xerox '341/'855) are older and framed for a different driver scale, so the mapping of "≤350 µm" and "≤14 Ω" is by inference/optimization rather than express disclosure. That is a KSR argument, not a clean anticipation.
3. No verified claim of a "single reference" anticipation. None of the five cited references alone discloses all elements; this is a combination case, and combination cases turn on motivation, which here is good but not overwhelming (Kodak's is a different printing modality and different solution type).
4. Do not overstate the litigation overlay. As flagged previously, no 2026 Federal Circuit activity on this literal patent number was located. The IPR petitions that recite "Torgerson" (e.g., the PTAB filings surfaced at ptacts.uspto.gov, pet. nos. 1550157 / 1550313, referencing "ground bus 181 of Torgerson" combined with "Bruce's teaching of ground portion 8") treat this family as prior art against later HP patents, which is useful context showing the family is citable art, but it is not a validity ruling on 6,488,363 itself.

X. Bottom line

• Claims 10, 18 and 24 (and all their dependents) are the most vulnerable. Gate length < 4 µm, gate oxide ≤ 800 Å and Ron ≤ 14 Ω are classic result‑effective design parameters of MOS driver design; US 5,272,489 expressly links low driver on‑resistance to high heater resistance, and US 5,144,341 discloses (i) a thermal inkjet head with on‑substrate MOS drivers and (ii) a 200 Ω heater — i.e., >100 Ω. The combination supplies every element, and the § 103 rationale is straightforward KSR predictable‑variation/routine‑optimization. Expect a strong prima facie case with the burden shifting to the patentee to show criticality.
• Claim 1 (≤350 µm FET region) is somewhat stronger for the patentee, because the width limit is the most "layout‑specific" of the three and the specification offers a concrete compactness/cost rationale. But the rationale the patent gives is the recognized design driver in US 5,638,101 and US 5,144,341, so even this claim is exposed to the "predictable use of known elements for their established function" argument.
• The dependent ground‑bus claims (6–8, 14–16, 20–22, 26–28) are best attacked with US 5,144,341's multi‑level interconnection and US 5,057,855's bus‑width/voltage‑drop trade‑off, not with the common‑owned US 6,309,053, which pre‑AIA § 103(c) likely disqualifies from a § 103 combination.
• Overall: the strongest § 103 theory is US 5,638,101 + US 5,144,341 in view of US 5,272,489, optionally with US 5,469,203 for the motivation, targeting the numerical limits. It is likely sufficient for claims 10/18/24 and their dependents, and litigable (though not a certainty) for claim 1.

What I could not verify and would need before relying on this: the examiner's specific reasons for allowance in US 6,488,363's file wrapper, the full text of US 5,144,341 and US 5,057,855 beyond the passages retrieved, and any applicant remarks distinguishing the numeric ranges. Those documents would determine whether the patentee already rebutted this combination during prosecution.

Sources cited: