US 4947192

I'll search for this specific patent number and any related 2026 litigation activity.

Let me run a couple more targeted checks for any litigation or post-grant proceedings involving this number.

Search scope and what I actually found

I ran targeted searches for the literal number 4947192 (US 4,947,192) against the Google Patents/legacy-USPTO record, EPO family records, PTAB document databases, and public 2026 Federal Circuit docket material.

No CAFC 2026 docket, district-court case, or PTAB proceeding involving US 4,947,192 was found. I want to be explicit that this is a negative search result from general web sources, not a certified PACER/CAFC docket query — I do not have direct authenticated access to those systems here, so treat the "no litigation" conclusion as no evidence found rather than proof of none. Relevant supporting facts: the record shows the patent reached its anticipated expiration on 2008-03-07 and its status is "Expired – Lifetime," which makes active 2026 assertion litigation highly unlikely. The only 2026-era hit was an unrelated N.D. Cal./E.D. Tex. Headwater appeal (USCA No. 26-1884), and the only textual hit for "4947192" was a prior-art search string inside a Canon IPR2023-00313 exhibit (a USOCR boolean query listing "4947192" alongside "5030971") — that is a search log, not a challenge or suit against the patent.

⚠️ Two search results contradict my training-data priors and I flag them per your rule:

1. Google Patents lists the current assignee as Samsung Electronics Co., Ltd., whereas the patent issued to Xerox Corp. The record shows a 2005-02-18 assignment from Xerox to Samsung, followed by several security-interest releases running back in favor of Xerox. I have not independently verified which entry governs "current" ownership, and Google Patents itself disclaims accuracy of the assignee list.
2. The search surfaced a related Xerox family application, EP 0 494 076 A3 (US priority 636826, filed 1992-01-02, inventors Hawkins and Burke), which cites US 4,947,192 as prior art — i.e., a later Hawkins/Burke Xerox filing in the same technical lineage. Do not conflate it with the patent you asked about.

US 4,947,192 — verified bibliographic data

Abstract (as issued): "A thermal jet ink printing system is provided with an improved printhead. The printhead is formed by monolithic integration of MOS transistors switches onto the same silicon substrate containing the resistive elements. In a preferred embodiment, the transistor switches and resistive elements are formed from a single layer of polysilicon with the resistive element formed on a thermally grown field oxide layer having a thickness ranging from about one to four microns. The integrated circuit chips are formed by MOS technology, are thermally stable and can be operated at higher voltages."

Plain-language overview of the independent claim

Claim 1 — the only independent claim — is drafted as a thermal ink jet printing module (an apparatus that combines the fluidics and the chip), not merely as a chip. In plain terms it requires:

1. A mechanical/fluid assembly: an ink channel structure with nozzles at one end and an ink supply at the other, fixedly joined to an integrated circuit.
2. A monolithic silicon circuit on a common wafer carrying both driver logic and resistive ink-heating elements. Structural elements recited:
   • a p-type silicon substrate with a patterned field oxide layer, followed by gate oxide growth;
   • at least one transistor switch with source and drain regions, where the drain specifically comprises a lightly doped n-type drift region and a separate n⁺ implanted region laterally displaced from the drift region (this is the high-voltage, extended-drain concept — the "drift" region spreads the field);
   • an n-type polysilicon gate on the gate oxide, in close physical proximity to the source and drain;
   • conductive vias making contact to source and drain at the n⁺ regions, which also provide the electrical connection between the transistor switch and the resistive elements.
3. The functional result clause: applying input signals to the vias causes the n⁺ region in at least the drain to create a carrier depletion region, which reduces the electric field at the gate–drain p-n junction.

The point of that last element is the stated benefit: by depleting the drain, the gate/drain junction field is softened so the device survives higher voltages before breakdown (the specification reports breakdown voltages >75 V versus ~20 V for the conventional device).

Dependent claims (not independent, summarized for completeness):

• Claim 2 (dep. 1): gate layer and resistive elements are made from a single polysilicon deposition (the FIG. 3 embodiment).
• Claim 3 (dep. 1): two polysilicon layers — a first for the gate, a second for the resistive elements (the FIG. 4 embodiment).
• Claim 4 (dep. 3): the first polysilicon layer doubles as a field plate for the carrier-depletion layer formed beneath the gate when signals are applied (the grounded-field-plate/drift-layer pinch-off structure of FIG. 4).

Notable claim-drafting observations (with confidence levels)

• Claim 1 does not recite the 1–4 µm field-oxide thickness. That limitation appears in the abstract and specification ("a thermally grown field oxide layer... ranging from about 1 to 4 microns") and in the description's summary-form paragraph, but it is absent from the granted claim set. High confidence — I read all four granted claims in the supplied text. If you are analyzing scope or validity, the thermal-efficiency thickness range is unclaimed subject matter.
• Claim 1 is a "module" claim with a result-oriented functional limitation ("creates a carrier depletion region... resulting in a reduction in the electric field"). The specification does not appear to supply a separate detailed test for that field reduction, which is the kind of language that historically invites §112 written-description/enablement attention. Flagging as an observation, medium confidence — I am reasoning from the specification text provided, not from any litigation record.
• My confidence in the technical content above (title, dates, inventors, claim language, abstract) is high, because it is drawn from the full authoritative patent text supplied via Google Patents and cross-corroborated by the EPO record for EP 0 401 440. My confidence in the "no 2026 litigation" point is moderate (public-search-derived), and my confidence in the current ownership entry is low, given the conflicting Xerox↔Samsung assignment chain and Google's own disclaimer.

Sources: https://patents.google.com/patent/US4947192/en (full text, claims, assignments, legal events); https://patentimages.storage.googleapis.com/f0/69/4e/643390a0705237/US4947192.pdf (granted PDF); http://data.epo.org/pise-server/rest/collections/lgpi/EP0401440B1.pdf (EPO family member); https://www.docketalarm.com/cases/PTAB/IPR2023-00313/ (source of the "4947192" prior-art search-string hit); https://archive.org/download/gov.uscourts.txed.[224022](/patent/224022)/ (2026 E.D. Tex. docket excerpt, unrelated case).

I'll search for litigation involving US patent 4947192 across multiple sources.

Initial searches returned noise. Let me search more targeted sources.

Let me try more specific litigation databases and queries.

Litigation Search Report — U.S. Patent No. 4,947,192

Prepared: April 26, 2026
Patent: U.S. 4,947,192 — "Monolithic silicon integrated circuit chip for a thermal ink jet printer"
Patentee of record (original): Xerox Corporation | Inventors: William G. Hawkins, Cathie J. Burke
Priority: March 7, 1988 · Filed: April 7, 1989 (continuation of Ser. No. 07/164,669) · Granted: August 7, 1990
Status: Expired – Lifetime (anticipated expiration March 7, 2008)

Bottom line

I found no litigation — no district court action, ITC Section 337 investigation, or Federal Circuit appeal — in which U.S. 4,947,192 is identified as an asserted patent.

I want to be explicit about the limits of this conclusion: it is a negative finding based on the searches described below, not a certified clearance. I could not complete a full run of PACER/Docket Alarm/CourtListener queries within this session, and I did not retrieve a Docket Navigator or Unified Patents litigation report for this specific number. My searches were substantially polluted by false positives (detailed below), which is a known hazard when searching short numeric patent IDs. Treat this as "no litigation located," not "no litigation exists."

Search methodology and results

Material findings on the one document that did surface the number

The only substantive document referencing 4947192 was an exhibit (Exhibit 1003) filed by Canon U.S.A., Inc. in IPR2023-00313 (PTAB), available via Docket Alarm. In that exhibit, "4947192" appears inside a prior-art search string — a logged USPTO/OCR database query of the form ("4630076" | "5638101" | ... | "4947192").PN. OR ("5030971")... dated 2009/05/18. This is a search-history artifact, i.e., a third party ran a patent-number search that happened to include '192. It is not an assertion of '192, not an IPR of '192, and not litigation. (Note that IPR2023-00313 itself concerns Canon and a different set of patents.)

False positives expressly rejected (per your "do not auto-correct / do not return similar numbers" instruction)

• 4947192 appearing in a Brazilian JUCIS-RS corporate filing (Sarwey Indústria e Comércio de Confecções Ltda.) — a registry entry, not a patent.
• 4947192 appearing in a Lithuanian company registry notice (Klaipėdos apygardos teismas insolvency) — a notice number, not a patent.
• JP Patent No. 4947192 (J-GLOBAL) — a Japanese patent number for an unrelated "情報再生装置" (information reproducing apparatus), wholly distinct from US 4,947,192. Different jurisdiction, different subject matter.

These are exactly the "similar number" confusions you asked me not to conflate. I have excluded them.

Context that bears on the (absence of) litigation

Two structural facts from the record make the absence of litigation plausible rather than surprising:

1. Term/expiry. The patent expired no later than March 7, 2008, with maintenance fees paid at the 4-, 8-, and 12-year intervals (1993, 1997, 2001). Pre-URAA patents like this one expired 17 years from grant (August 7, 2007) or 20 years from the earliest U.S. filing date (March 7, 2008); the file reflects the March 7, 2008 date. A substantial damages window closed almost two decades ago.

2. Ownership transfer to a competitor. A February 18, 2005 assignment transferred the patent from Xerox Corporation to Samsung Electronics Co., Ltd. (recorded REEL/FRAME 015687/0884, effective 2005-01-13). The chain also includes the 2002 Bank One security interest, the 2003 JPMorgan Chase collateral agreement, and later releases (2005–2022). This means the most likely enforcement candidate post-2005 is Samsung — and the residual term (roughly three years) was short. I found no Samsung assertion of '192 either.

3. Disclosure in later Xerox patents. The Google Patents "Similar Documents"/citation data reflect that Xerox's own later work — e.g., U.S. 5,010,355 (ionic passivation), U.S. 5,075,250 ("Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead"), U.S. 5,081,473 (temperature-control transducer and MOS driver), and U.S. 5,257,042 (transducer protection) — cites/relates to this disclosure. These are prosecution and citation relationships, not adversarial proceedings.

What I could not verify (and recommend as follow-up)

If you need a report suitable for a validity/enforcement opinion or an IPR/DFA analysis, the following should be run on paid databases, which I could not complete here:

• Docket Alarm / Docket Navigator — "Patent Litigation" filter by patent number (covers E.D. Tex. and all districts from the mid-1990s forward).
• PACER — case search (not generally searchable by patent number without knowing the case; requires a party/litigation list).
• Westlaw/Lexis Litigation Analytics and Derwent LitAlert — the best sources for 1988–2000-era infringement suits, which are poorly indexed on the free web and predate CourtListener's reliable coverage.
• USITC EDIS — Section 337 investigations (relevant given the inkjet industry's history of ITC actions, e.g., Canon/HP matters).
• PTAB P-TACTS — confirm no IPR/PGR/CBM/reexam naming '192 as the challenged patent.
• The European counterpart EP 0 401 440 B1 ("Monolithic silicon integrated circuit chip for a thermal ink jet printer"), which appears in the "Similar Documents" list — relevant to any international validity/enforcement picture, though also long expired.

Cited sources

• Google Patents, US4947192A (full text, classification, citation, and assignment records): https://patents.google.com/patent/US4947192/en
• Docket Alarm, PTAB IPR2023-00313, Canon U.S.A. Inc., Exhibit 1003 (reference to "4947192" in a logged search string only): https://www.docketalarm.com/cases/PTAB/IPR2023-00313/Canon_U.S.A._Inc/docs/01-21-2023-Petitioner/Exhibit-1003-Exhibit_1003.pdf
• J-GLOBAL, Japanese Patent No. 4947192 (unrelated subject matter — excluded as a false positive): https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=201303096325930905
• Xerox SEC disclosures reviewed for any mention of '192 (none found; concern unrelated matters): https://xerox.gcs-web.com/static-files/6783d186-d804-4437-843e-5a28d77e81df

Conclusion: No known litigation involving U.S. Patent No. 4,947,192. Please confirm with the paid litigation databases listed above before relying on this for any legal purpose.

I'll verify the canonical (empty) list against public sources before writing anything up.

Let me run a few more targeted checks, including the PTAB E2E-style docket and any litigation/opposition history.

One more round of verification — CourtListener docket and any PTAB-specific docket listing.

Proceedings overview

Zero AIA trial proceedings are on file for US 4,947,192 — total count 0; active 0, claims invalidated 0, claims sustained 0, settled 0, institution denied 0. The structured PTAB block supplied with this task (USPTO Open Data Portal) returns no AIA trial proceedings, and my independent web verification likewise surfaced none; the correct defensive read is therefore not "the patent has been hardened by surviving IPRs" but rather the far stronger one for a defendant — no claim of this patent has ever been tested at the PTAB, because the patent expired on 2008-03-07, more than four years before the current IPR regime took effect on 2012-09-16, and any assertion of it today is barred by expiration alone, independent of validity.

No proceedings to report — candidate hits checked and cleared

Because there is no proceeding to name, the required per-proceeding entries (petitioner, grounds, institution decision, FWD claim-level disposition, settlement, appeal) have no content. I did not manufacture proceeding numbers to fill the template. The following artifacts surfaced in search and were positively excluded:

Search caveat (stated plainly): my two final verification queries (a CourtListener docket sweep and a PTAB E2E trial-number sweep) were truncated by a tool-step limit and did not return results. My "no proceedings" conclusion rests on the canonical ODP block plus the completed searches, not on a fully exhaustive docket crawl. No Federal Circuit appeal of any FWD exists, because no FWD exists.

Strategic summary

Claim status: everything is untested, nothing is canceled or sustained. All four claims stand as issued — claim 1 (the independent module claim reciting the p-type substrate, the patterned field oxide, the n⁻ drift drain with laterally displaced n⁺ implant, the n-type polysilicon gate, and the vias creating a carrier-depletion region reducing gate–drain junction field), claim 2 (single-polysilicon-layer gate + resistors), claim 3 (two-polysilicon-layer gate/resistor split), and claim 4 (first polysilicon layer as field plate over the depletion layer). There is no narrowing certificate, no disclaimer, and no claim-level validity ruling from any tribunal. Treat "claims 1–5" or any claim-level invalidation in a demand letter as fabrication — this patent has only claims 1–4. The genuine, and dispositive, fact about this patent is temporal: the register shows an anticipated expiration of 2008-03-07, status Expired - Lifetime, with maintenance fees paid (4th, 8th, and 12th year payments recorded through 2001-12-20) and no lapse-based termination. Under 35 U.S.C. § 286 a damages action carries only a six-year lookback; from any 2026 filing date that window opens in 2020, long after expiration. There is no act of infringement available to plead.

Estoppel landscape: empty, but that is cold comfort for the other side too. Because no IPR, PGR, or CBM ever reached institution, no party is burdened by 35 U.S.C. § 315(e)(2) estoppel — every prior-art ground, including the twelve references cited on the face of the patent (US 4,111,776; 4,251,824; 4,308,549; 4,463,359; 4,399,451; 4,410,899; 4,429,321; 4,412,224; 4,595,821; 4,532,530; 4,601,777; 4,719,477) and the two non-patent publications (Martin et al., IEEE IEDM 1984, pp. 266–269; Yamaguchi et al., IEEE IEDM 1981, pp. 255–258), remains available to any future challenger, subject only to § 325(d) discretion and the ordinary IPR eligibility limits. But note the statutory ceiling on how that challenge could ever be brought: PGR is unavailable (the '192 patent has an effective filing date of 1989-04-07, far before the 2011-03-16 AIA threshold), and CBM is unavailable and sunset (not a covered business method patent; program ended 2020-09-16). IPR was and is the only vehicle — and it was never used.

Pattern signals: none of the usual tells. No petitioner has filed serially against this patent, so there is no repeat-player/joinder story. The patent owner never litigated to an appeal through the PTAB, so there is no aggressive-appeals pattern to price in. No defensive aggregator appears anywhere in the chain — no Unified Patents, RPX, or similar filing. The ownership trail is the only movement of note: original assignee Xerox Corp; a 2005-02-18 assignment of interest to Samsung Electronics Co., Ltd. (reel 015687/0884, effective 2005-01-13) with later release-of-security instruments back to Xerox in 2014 and 2022, and Google's "Current Assignee" field lists [Samsung Electronics Co Ltd](/litigations/by-plaintiff/Samsung%20Electronics%20Co%20Ltd) — treat that register field as an assumption, not a legal conclusion, and confirm ownership before relying on it. The clean reading of the record is that this patent simply aged out before the AIA trial regime matured; the absence of IPRs here is not evidence of patent strength, and the absence of any assertion campaign is consistent with a patent that has been expired since 2008.

Recommended next steps

• If you are a defendant being asserted against: do not research invalidity first — research expiration. The patent expired 2008-03-07 and its legal status is Expired - Lifetime. Any conduct you could be accused of occurred after the patent's death; the six-year damages lookback of 35 U.S.C. § 286 cannot reach a single pre-expiration act. Respond with the expiration date and the Patent Center status printout rather than a merits defense, and refuse to engage on claim construction. Primary links: US 4,947,192 on Google Patents (status: Expired - Lifetime) and USPTO Patent Center.
• If opposing counsel cites claim-level PTAB outcomes: there are none to cite. There is no Final Written Decision for this patent, so there is nothing to link to at USPTO PTAB Decisions or PTAB E2E, and no Federal Circuit docket number to check on CourtListener. Any representation that "claims were canceled" or that "the patent survived IPRs" is false in both directions.
• If the number is being cited as prior art against you in your own matter (the IPR2023-00313-style scenario): that is a legitimate use and is worth taking seriously. The '192 patent is a 1990-08-07 publication with a 1988-03-07 priority date and is a well-known foundational reference in monolithic thermal-inkjet driver circuitry; treat it as § 102(b) art with a date certain rather than as an assertion risk.
• If you are clearing a design for freedom to operate: the relevant live question is not the '192 patent but its family and descendants — Xerox's US 5,075,250 ("Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead," issued 1991-12-24) and the EP family members EP 0 401 440 and EP 0 494 076. Check the expiration status of those individually; do not assume they share the '192 patent's term.
• If you want to close the verification gap: run the PTAB API directly — https://developer.uspto.gov/ptab-api/proceedings?patentNumber=4947192 — and confirm on PTAB E2E that the proceedings list is empty. Confirm also that the structured ODP status field still reads "Expired - Lifetime," since that single field, not any invalidity ruling, is what defeats an assertion of this patent.

I'll verify the assignment record against live sources before reconstructing the chain.

Assignment & Ownership Reconstruction — US 4,947,192

Patent: Monolithic silicon integrated circuit chip for a thermal ink jet printer
App. 07/336,624 (continuation of 07/164,669, filed 1988‑03‑07) · filed 1989‑04‑07 · issued 1990‑08‑07 · expired 2008‑03‑07 (anticipated expiration, per Google Patents legal events)
Primary source reviewed: https://patents.google.com/patent/US4947192/en (legal-events tab mirrors the USPTO Assignment Center records and exposes reel/frame numbers)
Verification entry points: https://assignmentcenter.uspto.gov/ · https://assignment.uspto.gov/patent/index.html (search US4947192)

Two limitations stated up front, because they affect two of the eight signals:

1. The correspondent field is not present in any source I could retrieve. The Google Patents legal-events feed carries reel/frame, conveyance type, assignor/assignee and dates, but not the recording attorney or firm. My tool access returned no way to query the Assignment Center's correspondent field directly, so any correspondent name I supplied would be fabricated. Signal 3 is therefore unclear (data not retrievable) — not "not present."
2. The original inventor→Xerox assignment is not surfaced. No reel/frame for a 1988/1989 inventors-assignment appears in the legal-events feed. I am not inventing one; it is reported below as "recorded, reel/frame not surfaced in sources reviewed," and the task is to confirm it directly in the Assignment Center.

Inventors

Unusual-pattern check — not evidenced. There is no record of either inventor departing Xerox within 12 months of filing, and no post‑1990 inventor-side assignment (e.g., a quitclaim or nunc pro tunc correction) appears in the records. Two related observations, neither of which is a finding of unusual inventor behavior:

• A continuation/divisional lineage exists — US 5,075,250 (Xerox, issued 1991‑12‑24, "Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead") claims priority to this family. That is normal corporate prosecution practice, not attrition.
• The prosecution stayed inside Xerox: every recorded conveyance names Xerox as assignor or as the beneficiary of a release.

Original assignee

Xerox Corporation (original assignee of record; Google Patents lists current assignee as Samsung Electronics Co., Ltd.).

• Primary line of business: document management — copiers, printers, and printing supplies; a practicing OEM, not an IP-holding vehicle.
• Product embodying the claims: Yes, in the ordinary sense — the patent's own disclosure is directed at a commercial carriage‑type bubble‑jet printing device (FIG. 1–2) built for ~300 spi operation, and Xerox commercialized thermal ink jet printheads and printers of this generation. The module of claim 1 (channel structure + nozzles + ink supply fixedly adjoined to the monolithic driver/resistor chip) is the device Xerox was building; that is why the assignee bothered to file it and why the family was extended to EP (EP0401440B1, same title, listed in Google Patents "Similar Documents").
• Current status: Operating. Xerox has restructured (Xerox Holdings Corporation as the public parent from 2019; business‑process‑outsourcing spun into Conduent in 2017) but has never filed Chapter 7 or Chapter 11 that would put this portfolio into a bankruptcy sale. Note the 2002–2003 IP security interests below are ordinary secured corporate financing, not a bankruptcy proceeding.

Assignment timeline

Chronological. All entries below are recorded documents with reel/frame as exposed by the source; the parent-application entry at the top is the one gap.

• executed ~1988–1989 (date not surfaced) / recorded date not surfaced — Reel not surfaced

  • Conveyance: Assignment (inventors → company)
  • Assignor: William G. Hawkins; Cathie J. Burke
  • Assignee: Xerox Corporation
  • Correspondent: not retrievable (see limitation 1) — flag as a gap to close
  • Context: ordinary pre-issuance employee assignment; no reel/frame appears in the legal-events feed reviewed, so confirm directly at the Assignment Center.

• 2002‑06‑21 (executed) / recorded 2002‑06‑28 — Reel 013153/0001

  • Conveyance: Security Interest
  • Assignor: Xerox Corporation
  • Assignee: Bank One, NA, as Administrative Agent
  • Correspondent: not retrievable (see limitation 1)
  • Context: securitization — collateral pledge over the Xerox US patent portfolio under a corporate credit facility, not a change of ownership.

• 2003‑06‑25 (executed) / recorded 2003‑10‑31 — Reel 015134/0476

  • Conveyance: Security Agreement
  • Assignor: Xerox Corporation
  • Assignee: JPMorgan Chase Bank, as Collateral Agent
  • Correspondent: not retrievable (see limitation 1)
  • Context: securitization — second collateral pledge, same financing structure, again not a transfer of title.

• 2005‑01‑13 (executed) / recorded 2005‑02‑18 — Reel 015687/0884

  • Conveyance: Assignment of Interest
  • Assignor: Xerox Corporation
  • Assignee: [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.
  • Correspondent: not retrievable (see limitation 1)
  • Context: portfolio sale of Xerox ink‑jet assets to a practicing OEM — the only ownership transfer in the chain. Corroborated for the same Xerox→Samsung transaction in the EP counterpart family: "registered as Applicant/Proprietor in place of XEROX CORPORATION … by virtue of deed of assignment dated 01.04.2005" (https://www.search-for-intellectual-property.service.gov.uk/EP89312194.7/history).

• 2005‑03‑30 (executed) / recorded 2005‑04‑01 — Reel 016408/0016

  • Conveyance: Release of Patents
  • Assignor: JP Morgan Chase Bank, N.A.
  • Assignee: Xerox Corporation
  • Correspondent: not retrievable (see limitation 1)
  • Context: release of the 2003 collateral pledge; Xerox booked as "assignee" is a recording artifact of a release, not an acquisition.

• effective 2003‑06‑25 (executed) / recorded 2014‑06‑06 — Reel 033098/0737

  • Conveyance: Release of Security Interest
  • Assignor: Bank One, NA
  • Assignee: Xerox Corporation
  • Correspondent: not retrievable (see limitation 1)
  • Context: late-recorded release — an 11‑year lag between effective date and recording (2014). Housekeeping/chain‑of‑title cleanup, not a transaction.

• effective 2006‑12‑04 (executed) / recorded 2014‑11‑24 — Reel 034435/0817

  • Conveyance: Release by Secured Party
  • Assignor: JPMorgan Chase Bank, N.A.
  • Assignee: Xerox Corporation
  • Correspondent: not retrievable (see limitation 1)
  • Context: second late-recorded release, again cleanup of the 2002–2003 financing liens.

• effective 2022‑08‑22 (executed) / recorded 2022‑09‑07 — Reel 066728/0193

  • Conveyance: Release by Secured Party
  • Assignor: JPMorgan Chase Bank, N.A., as successor‑in‑interest administrative agent and collateral agent to JPMorgan Chase Bank
  • Assignee: Xerox Corporation
  • Correspondent: not retrievable (see limitation 1)
  • Context: third, very late release-layer recording, 14 years after the patent expired; administrative cleanup tied to successor‑agent paperwork, no economic effect on this patent.

No post‑2005 ownership assignment is recorded — there is no reel/frame moving US 4,947,192 off Samsung. Ownership therefore ends at Samsung Electronics Co., Ltd., and the patent is in the public domain as of 2008‑03‑07.

Timeline diagram

timeline
    title Ownership of US 4947192
    1990 : Issued to Xerox Corporation
    2002 : Bank One security interest recorded
    2003 : JPMorgan security agreement recorded
    2005 : Assigned to Samsung Electronics Co Ltd
         : Security interests released
    2008 : Patent expires
    2014 : Two old releases recorded late
    2022 : JPMorgan successor release recorded

NPE / troll-pattern signals

1. Shell-entity transfer — not present.
Every recorded assignee is either the original operating OEM (Xerox) or a solvent financial institution acting as collateral agent (Bank One, NA, reel 013153/0001; JPMorgan Chase Bank, reel 015134/0476), and the sole title transfer runs to Samsung Electronics Co., Ltd., an operating manufacturer (reel 015687/0884, executed 2005‑01‑13). No "IP / Holdings / Licensing / Ventures" assignee appears anywhere in the chain. There is no registered-agent address, single-member LLC, or Texas/Delaware shell in the record.

2. Known asserter in the chain — not present.
No assignee matches any of the listed asserters (Acacia, Marathon, IV, IPNav, Wi‑LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, Spangenberg entities) and none appears in the Unified Patents / RPX high-frequency plaintiff directories reviewed for this chain.
Deliberate non-finding: searches surfaced Monument Peak Ventures, LLC — a Dominion Harbor entity flagged by Unified Patents as an NPE — litigating against Xerox in E.D. Tex. and W.D.N.Y. (https://www.unifiedpatents.com/insights/2023/7/28/2000-awarded-for-dominion-harbor-entity-monument-peak-ventures-photography-patent-prior-art ; https://www.docketalarm.com/cases/[PTAB](/ptab)/IPR2022-00318/Xerox_Corporation/docs/12-15-2021-Petitioner/Exhibit-1030-30-WDNY_Complaint.pdf). That is a different chain. MPV's asserted patents originate with Kodak via Intellectual Ventures, not with Xerox, and US 4,947,192 is not among the patents-in-suit. Naming alone is not evidence; I am recording this as a name-proximity trap, not as a signal.

3. Repeat correspondent across the chain — unclear (evidence not retrievable).
The correspondent of record is not exposed in any source I could query, so I cannot state whether one attorney/firm handled reels 013153/0001, 015134/0476, 015687/0884, 016408/0016, 033098/0737, 034435/0817 and 066728/0193. This is the single highest-value open item for the assignment-record exercise: the reels span 2002–2022 and two corporate identities (Xerox, then Samsung-controlled), so a recurring recording attorney would be informative either way. Recommended next step: open each reel/frame PDF at assignmentcenter.uspto.gov (the site now exposes downloadable conveyance PDFs with the recording cover sheet) and pull the "correspondent" block for all seven reels.

4. Cascading transfers — not present.
There is one ownership transfer in 20 years of record (Xerox → Samsung, reel 015687/0884). The remaining seven entries are two liens (2002, 2003) and five releases (2005, 2014 ×2, 2022) — financing paperwork, not a chained-LLC sequence. No two consecutive assignments share a correspondent address because no consecutive assignments exist.

5. Pre-litigation transfer — not present / moot.
No infringement suit naming US 4,947,192 surfaced in searches, and the patent expired 2008‑03‑07, so there is no assertion window and no "assignment within 6 months of suit" to assess. The 2005 transfer occurred three years before expiration and is unaccompanied by any asserted litigation.

6. Bankruptcy fire-sale — not present.
Xerox has no Chapter 7/11 in the record. The 2002–2003 security interests (reels 013153/0001, 015134/0476) are secured corporate financing, not a bankruptcy disposition, and were released (reels 016408/0016; 033098/0737; 034435/0817) rather than foreclosed. The 2005 transfer was a negotiated commercial sale, evidenced by the parallel EP filing dating the same Xerox→Samsung deed ("deed of assignment dated 01.04.2005").

7. Privateering — not present.
The 2005 transferee is a practicing competitor/OEM (Samsung), not an NPE, and there is no evidence Samsung ever asserted this patent — let alone asserted it on Xerox's behalf. No SEC filing or Patent Progress/EFF coverage connecting this patent to a privateering arrangement was found.

8. Defensive aggregator (anti-NPE) — not present.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. Termination is by expiration (2008‑03‑07), not by defensive acquisition. The practical effect (patent neutralized, cannot be asserted) resembles the defensive-aggregator outcome, but the mechanism is different and should not be reported as if it were a defensive purchase.

Verdict

Defensive / non-asserting — with a documented deviation from the category definition.

The literal criterion for this verdict is "chain terminates at a defensive aggregator," and that is not what happened: the chain terminates at Samsung Electronics Co., Ltd., an operating company, and the patent was never transferred to RPX, AST, LOT, or Unified. I select this verdict because it is the only one that is substantively true of the record — no NPE ever held this patent, no shell LLCC appears, no litigation asserting it was found, and it has been unassertable since 2008‑03‑07. The two alternative verdicts are affirmatively wrong: "NPE — high/moderate confidence" fails because zero NPE signals are present, and "operating-company assertion" fails because its defining condition (current assignee suing actual competitors on this patent) is unmet — Samsung is an operating manufacturer, but no suit naming US 4,947,192 exists, and the patent expired 14 years before the Samsung portfolio moved on to HP-adjacent hands. The chain is, in full: Xerox (operating, 1990) → two financing liens (reels 013153/0001 and 015134/0476) → Xerox → Samsung Electronics, reel 015687/0884, executed 2005‑01‑13 → releases through 2022. Insufficient data is not appropriate because seven recorded conveyances exist and the ownership outcome is clear; the only genuine gap is the correspondent field (signal 3), which does not affect the verdict.

Verify at: https://assignmentcenter.uspto.gov/ (search "4947192") — pull reels 013153/0001, 015134/0476, 015687/0884, 016408/0016, 033098/0737, 034435/0817, 066728/0193, and request the correspondent block on each to close signal 3.

I'll ground this analysis with live searches before giving you per-reference findings.

Prior-Art Analysis — US 4,947,192

1. Target patent: identification and verification

Search-scope caveat (stated explicitly, per your rules): I ran live searches, but I could not pull the USPTO PatentCenter/pair record for 07/336,624 directly in the tool results returned. What I did retrieve were the authoritative full text you supplied (Google Patents mirror of the USPTO grant, fetched 2026-09-24) plus corroborating EPO/Google mirrors for the references. Where a fact below is not confirmed in the sources actually returned, I say so rather than fill the gap. Per your rule, all numbers are reproduced literally as they appear in the record — including the one internal inconsistency flagged in §4 below.

2. Critical-date framework (this determines whether §102 can even apply)

Because US 4,947,192 is a continuation of application 07/164,669 filed 1988-03-07, the effective date against which the cited art is measured is 1988-03-07 (for subject matter carried over from the parent).

• §102(b) — available against any reference published more than one year before 1988-03-07, i.e. before 1987-03-07. Statutory bar; applies regardless of who the author/inventor is.
• §102(a) — publications before the applicant's invention date (presumptively on/before 1988-03-07).
• §102(e) — US patents/published applications as of their US filing date, but only if "by another."

Applying this to the 12 cited US patents:

3. The 12 cited references — full citations, dates, disclosures, and §102 claim mapping

The grant's front page lists 12 "Patent Citations (12) — cited by examiner." I take these as the complete cited art set.

(1) US 4,110,776

• Citation: Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer; inventors G. R. Mohan Rao, John S. Stanczak, Jih-chang Lien, Shyam Bhatia; assignee Texas Instruments Incorporated.
• Dates: US filing 1976-09-27; issued 1978-08-29.
• Description: Ion-implanted resistor formed in a polysilicon strip that also serves as the MOS transistor gate and as interconnection over the field oxide; resistor resistivity set by phosphorus implant dose (≈5×10¹³–1×10¹⁴/cm²); resistor capped with a grown oxide. Expressly a static-RAM load device, not a printer.
• Potential §102 target: Claim 2 (single polysilicon layer forming both gate layer and resistive elements) — this is the single closest element-level match in the whole cited set. It does not reach claims 1, 3 or 4.
• Assessment: Cannot anticipate claim 2 as a whole, because claim 2 incorporates all of claim 1 (no ink jet module, no n⁻ drift drain, no ink-heater vias in '776). Best use is §103, not §102.
• Note: the grant cites only '776; the closely related divisional US 4,208,781 (same title; two-level poly resistor) appears in the record only as a self-citation inside other documents, not on this front page.

(2) US 4,251,824

• Citation: Liquid jet recording method with variable thermal viscosity modulation; assignee Canon Kabushiki Kaisha.
• Dates: US filing 1978-11-14; issued 1981-02-17.
• Description: Canon thermal/liquid-jet recording method — the drop-on-demand thermal ink jet background art cited by the applicants themselves in the "Background and Information Disclosure Statement."
• Potential §102 target: the preamble of claim 1 only (thermal ink jet printing module; ink channels/nozzles/resistors; drive circuitry on the same chip). The applicants themselves use it to introduce bipolar drive circuitry as the prior art.
• Assessment: No anticipation of any of claims 1–4 (bipolar drive; no p-type substrate/field-oxide/lateral n⁺-displaced-from-n⁻ geometry).

(3) US 4,308,549

• Citation: High voltage field effect transistor; assignee Xerox Corporation.
• Dates: US filing 1978-12-18; issued 1981-12-29.
• Description: The "HIFET" — a high-voltage field-effect transistor in a radial/closed geometry that "occupies little space on a substrate and minimizes cross conduction between devices," and is "suitable for inclusion in LSI designs requiring high voltage outputs."
• Potential §102 target: the high-breakdown-voltage MOS switch concept in claim 1; also structurally adjacent to claim 4's field-plate/field-relief concept.
• Assessment: This is the most technically pertinent of the 12 to the breakdown-voltage inventive aspect, but it is an LSI/electrographic device, not an ink jet module, and its high-voltage mechanism is geometric/field-relief rather than the claimed "lightly doped n-type drift region and an n⁺ ion implanted region laterally displaced from the drift region." No anticipation of claims 1–4; §103 material.

(4) US 4,463,359

• Citation: Droplet generating method and apparatus thereof; assignee Canon Kabushiki Kaisha.
• Dates: US filing 1979-04-02; issued 1984-07-31.
• Description: Cited by the applicants as foundational thermal ink jet prior art ("Thermal ink jet printers are well known in the prior art as exemplified by U.S. Pat. Nos. 4,463,359 and 4,601,777").
• Potential §102 target: claim 1 preamble only.
• Assessment: No anticipation; background art for the bubble-generating system.

(5) US 4,399,451

• Citation: Semiconductor device and method for production thereof; assignee Fujitsu Limited.
• Dates: US filing 1979-12-30; issued 1983-08-16.
• Description: Semiconductor device/production method. In the sources I retrieved, this reference appears only as a bibliographic front-page citation; I did not obtain its disclosure text, so I will not characterize its teaching beyond its title. Flagged as unverified.
• Potential §102 target: cannot responsibly assign one. On the title alone it is a general semiconductor device reference; at most it touches claim 1's facilitator elements (substrate/gate/film) and cannot reach the claimed combination.
• Assessment: No anticipation of claims 1–4.

(6) US 4,410,899

• Citation: Method for forming liquid droplets; assignee Canon Kabushiki Kaisha.
• Dates: US filing 1980-04-01; issued 1983-10-18.
• Description: Named by the applicants as one of the printheads using bipolar drive circuits combined on the same chip as the resistors (with US 4,251,824 and US 4,412,224).
• Potential §102 target: claim 1 preamble ("integrated circuit which contains driver logic and resistive ink heating elements formed on the surface of a common silicon wafer").
• Assessment: Addresses the co-location idea only, expressly with bipolar (the specification criticizes the bipolar approach for cost and thermal runaway). No anticipation.

(7) US 4,429,321

• Citation: Liquid jet recording device; assignee Canon Kabushiki Kaisha.
• Dates: US filing 1980-10-23; issued 1984-01-31.
• Description: In the record, this is the reference that a later Xerox case (EP 0 494 076 A3) characterizes as disclosing a monolithic arrangement in which "a control unit and a transducer on a single substrate" are combined, with the control unit being a bipolar transistor and various implants used to create the resistor. That characterization originates from the later Xerox filing, not from the '192 grant itself, but it is instructive.
• Potential §102 target: claim 1 preamble (monolithic control unit + transducer on one substrate).
• Assessment: Closest of the Canon group on integration, but bipolar; lacks the n⁻ drift/n⁺ laterally displaced drain, the vias-to-n⁺ contact scheme, and the depletion/electric-field-reduction limitation. No anticipation of claims 1–4.

(8) US 4,412,224

• Citation: Method of forming an ink-jet head; assignee Canon Kabushiki Kaisha.
• Dates: US filing 1980-12-18; issued 1983-10-25.
• Description: Named by the applicants alongside US 4,251,824 and US 4,410,899 as a bipolar-drive printhead with resistors on the same chip.
• Potential §102 target: claim 1 preamble.
• Assessment: No anticipation; same reasoning as items (2), (6).

(9) US 4,595,821

• Citation: Semiconductor device for use with a thermal print head; as listed on the grant's front page, assignee Seikosha Instruments & Electronics Ltd. The specification text, however, calls this "the Matsuera patent" ("U.S. Pat. No. 4,595,821 to Matsuera"), and the applicants' own discussion states it discloses "a thermal printhead … in which a CMOS control circuit is mounted on a ceramic substrate upon which is also mounted the resistor element," which "is not suitable for thermal ink jet printing applications."
• Dates: US filing 1982-09-27; issued 1986-06-17.
• Potential §102 target: claim 1's MOS-driver-with-resistor concept — but on the applicants' own reading it is a ceramic substrate with a separately mounted resistor, i.e. not the claimed "common silicon wafer."
• Assessment: No anticipation of claims 1–4. Its evidentiary value runs against the claims, and the applicants affirmatively distinguished it in the background.
• Discrepancy note: I flag the Seikosha/Matsuera naming discrepancy rather than reconciling it, as required.

(10) US 4,532,530

• Citation: Bubble jet printing device; inventor William Gregg Hawkins; assignee Xerox Corporation. (Confirmed: application 06/588,166, priority 1984-03-09; EP counterpart EP 0154515 A3 names Hawkins.)
• Dates: US filing 1984-03-09; issued 1985-07-30.
• Description (from the record): Heavily doped polycrystalline silicon bubble-generating resistors formable "on the same process lines with those for integrated circuits"; glass mesas thermally isolate the active resistor region from the silicon substrate and from the electrode connection points; a thermally grown dielectric layer under a tantalum ink-interfacing layer. The applicants' own characterization: "A polycrystalline silicon is simultaneously used to form the resistor and the associated drive circuitry. This configuration requires that each resistor element be attached to a bonding pad by a separate utilization contact process," which is a "disadvantage … for moderate and high speed printing applications and for printing at a density near or above 300 spi."
• Potential §102 target: Claim 2 and, on the two-layer question, claim 3 — this is the closest item in the set to "single polysilicon layer used for both the gate of the driver transistor and the resistive element."
• Assessment: The most dangerous of the 12, but still not an anticipation of any claim: it (a) uses glass mesas rather than a 1–4 µm thermally grown field oxide as the thermal barrier (the stated point of novelty in the specification and in claim 1), (b) contemplates per-resistor bonding pads (the very thing the '192 combination eliminates), and (c) does not show the n⁻ drift/n⁺ laterally displaced drain or the depletion-field-reduction limitation. §103 material against claims 2–3 in combination with, e.g., US 4,110,776.

(11) US 4,601,777

• Citation: Thermal ink jet printhead and process therefor; assignee Xerox Corporation.
• Dates: US filing 1985-04-03; issued 1986-07-22.
• Description: The basic thermal ink jet printhead/process background reference, cited by the applicants with US 4,463,359.
• Potential §102 target: claim 1 preamble (channel structure, nozzles, supply, resistors).
• Assessment: No anticipation. Caveat: I did not verify the listed inventive entity of '777; if Hawkins appears as an inventor, note that a same-entity US patent is not a §102(a)/(e) "by another" reference for this application (the §102(b) publication bar, however, still applies since it issued >1 yr before 1988-03-07).

(12) US 4,719,477

• Citation: Integrated thermal ink jet printhead and method of manufacture; assignee Hewlett-Packard Company (front-page listing: priority 1986-01-17; application 06/820,754).
• Dates: US filing 1986-01-17; issued 1988-01-12.
• Description: An integrated thermal ink jet printhead in which the orifice plate, a first barrier layer, heater resistors (thin-film, e.g. TaAl), a second barrier layer and an ink-reservoir-defining layer are built up in sequence on a reusable ("dummy") substrate and then self-aligned by stripping the dummy substrate away; lead-in conductors are formed integral with the resistors by controlling cross-sectional areas. Drive electronics are attached externally (e.g., TAB/flex), not monolithically integrated.
• Potential §102 target: the "printhead formed by monolithic integration"/integrated-TIJ concept running through claim 1's preamble.
• Dates/status point: it is the only cited reference that is not §102(b) — issued 1988-01-12, less than one year before the 1988-03-07 priority date. Its teeth come from §102(a) (if it predates the applicant's invention date) and §102(e), where it is prior art as of its 1986-01-17 filing date.
• Assessment: No anticipation of claims 1–4: it is a thin-film resistor build-up on a removable substrate with off-chip drive circuitry, expressly contrasted with the claimed on-substrate MOS transistor switches and field-oxide thermal barrier.

4. The two non-patent citations

The grant lists 4 non-patent entries, which are the same two documents recorded twice (with an en-dash variant in the page ranges):

Honest limitation: the sources I retrieved did not include the text of these two IEDM papers. I will not invent their titles or holdings. Two observations I can support from what I did retrieve:

• Both are examiner-cited printed publications comfortably more than one year before the 1988-03-07 priority date, so they are unambiguously available under §102(b) (and, being non-patent publications, they are not subject to the "by another" qualifier in the same way).
• I did retrieve a different Xerox IEDM 1981 paper in the immediately adjacent pages — "Integrated high-voltage/Low-voltage MOS devices," Buhler, Heald, Ronen, Gannon and Elkins (Xerox Microelectronics Center), IEDM 81, pp. 259–262. That paper discloses a high-voltage polysilicon field-plate ("highly resistive polysilicon") NMOS structure integrable with low-voltage NMOS logic. That is not the Yamaguchi paper at pp. 255–258 and I am not asserting it is; I flag it only because it shows the cited IEDM 1981 session was the high-voltage/field-plate MOS session, which is consistent with these non-patent citations being the vehicle for the high-breakdown-voltage MOS teaching. Treat that as an inference, not a verified fact.

5. Bottom line on §102

Reading the four issued claims literally:

1. Claim 1 requires a specific combination: a thermal ink jet module (ink channel structure + nozzles + supply) adjoined to an IC on a common silicon wafer; a p-type substrate with patterned field oxide and a gate oxide; a transistor whose drain comprises a lightly doped n-type drift region and an n⁺ ion-implanted region laterally displaced from the drift region; an n-type polysilicon gate on the gate oxide; conductive vias contacting source and drain at the n⁺ region and tying the transistor to the resistive heaters; and the functional consequence that the n⁺ region creates a carrier depletion region reducing the electric field at the gate–drain p-n junction.
2. Claim 2 = + single-polysilicon gate/resistor.
3. Claim 3 = + two-polysilicon (gate / resistor).
4. Claim 4 = + first poly layer as a field plate for the carrier-depletion layer under the gate.

No single reference in the cited set discloses every element of any of claims 1–4. The strongest element-level readings are:

• Claim 2 → US 4,110,776 and US 4,532,530 (single poly serving gate + resistor).
• Claim 3 → US 4,110,776's family (e.g., the two-level-poly division US 4,208,781, which is not cited) and US 4,532,530.
• Claim 1's high-voltage switch element → US 4,308,549, and the IEDM 1981/1984 non-patent items.
• Claim 4's field plate → US 4,308,549 (and the adjacent IEDM 1981 field-plate work), plus US 4,110,776's polysilicon-over-field-oxide structure.
• Claim 1's module preamble → US 4,463,359, US 4,601,777, US 4,251,824, US 4,410,899, US 4,412,224, US 4,429,321, US 4,719,477.

So for §102 specifically: the only references one could even attempt an anticipation argument with are the ones aimed at the narrower dependent claims (US 4,110,776 vs. claim 2), and those attempts fail because claim 2 carries claim 1's limitations forward. Every other mapping in §3 is properly a §103 combination argument, not §102 — most plausibly US 4,532,530 (or US 4,110,776) in view of US 4,308,549, optionally with one of the Canon module references (e.g., US 4,429,321), to attack claim 1.

Two record observations worth carrying forward:

• US 4,719,477 is the timing outlier. It is the only cited item that cannot be a §102(b) reference; it is prior art only under §102(a) and/or §102(e) as of 1986-01-17. If an invention date earlier than 1988-01-12 could be established for the applicants, it drops out as §102(a) art and survives only in the §102(e) role.
• US 4,532,530, US 4,601,777 and US 4,308,549 are all Xerox references, and '530 names Hawkins, a named inventor here. That matters for which subsection of §102 is even available: same-inventive-entity US patents are not §102(a)/(e) "by another" art, whereas §102(b) is a bar regardless of authorship.

I'll ground this analysis in the actual cited art. Let me verify the key references.

Let me verify the remaining key references.

Obviousness Analysis — US 4,947,192 A

"Monolithic silicon integrated circuit chip for a thermal ink jet printer"
Inventors: William G. Hawkins; Cathie J. Burke · Original assignee: Xerox Corp. · Priority: 1988-03-07 · Filed: 1989-04-07 · Granted: 1990-08-07 · Status: Expired – Lifetime (anticipated expiration 2008-03-07)
Source: https://patents.google.com/patent/US4947192/en

1. Threshold observations that frame the analysis

(a) The patent's headline feature is not claimed. The specification and abstract emphasize a thermally grown field oxide of 1–4 µm as the central advance (and identify ~2.0 µm as the minimum-dissipation point for 3 µsec pulses). No claim recites any field-oxide thickness. Claim 1 requires only "a patterned field oxide layer grown on said substrate, followed by gate oxide growth." Claims 2–4 add nothing about thickness. Similarly, the asserted life extension ("10⁶ cycles" → "10⁸ cycles") is attributed to "composite layer 79" over the resistors — also unclaimed. Any obviousness analysis must therefore be run against the claims as written, not the specification's commercial story.

(b) Applicable law. Priority is 1988-03-07, so pre-AIA 35 U.S.C. § 103(a) governs, evaluated under Graham v. John Deere Co., 383 U.S. 1 (1966), and Federal Circuit precedent on motivation to combine (In re Kerkhoven, In re Nilssen, In re Kemps). If the claims were tested today, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), would also apply. Because the patent expired 2008-03-07, § 103 is now of defensive/prior-art significance only — the claims are unenforceable, but the disclosure remains citable art against later filings.

(c) Level of ordinary skill. A person with a B.S. in electrical engineering, materials science, or applied physics and roughly 2–5 years of experience in MOS integrated-circuit fabrication, or equivalent, with working familiarity with LOCOS isolation, self-aligned polysilicon gate NMOS, and thin-film thermal printing heads.

(d) A claim-drafting defect worth flagging. Claim 1 recites that "said n⁺ ion implanted region in at least the drain region creates a carrier depletion region." Per the specification (col. 3), depletion in fact occurs in the lightly doped n⁻ drift region 82, not the n⁺ contact implant 90. The claim appears to mislabel the operative region. Read literally, claim 1 may not read on the inventors' own FIG. 3 embodiment; read in light of the specification (Phillips v. AWH; In re Packard), it should be construed as the n⁻ drift region. This ambiguity affects which prior-art structures anticipate or render obvious the claim.

2. The prior art of record, and what each supplies

Supplementary but highly material art discovered during verification (not on the face of US 4,947,192):

• US 4,288,802 (Ronen, Xerox, issued 1981-09-08) — HVMOSFET driver with single-poly gate: "closed geometry grounded peripheries … DMOS-like structures with separate channel and drift regions, … split oxide topography having relatively thin oxide under a control gate and over a channel region, and relatively thick oxide under a field plate and over a drift region … The … HVMOSFET with single polysilicon layers for non-overlapping gates is operative to bend field lines away from the drain … thereby increasing the available breakdown voltage adjacent to the drain area." This is, in substance, the FIG. 3/FIG. 4 architecture of US 4,947,192, published seven years earlier and assigned to the same company. It is § 102(b) art and would be devastating on claims 1, 2, and 4.
• US 4,209,716 / US 4,247,697 / US 4,360,571 / US 4,367,580 (Texas Instruments) — second-level polysilicon resistors over first-level polysilicon gates, masking/defining the resistor with the second-level poly. Directly supplies claim 3's two-poly architecture.
• US 4,208,781 / US 4,110,776 (TI) — same family, confirming the single-poly gate-and-resistor process.

⚠️ Note on the page's "Similar Documents" list: several entries there (e.g., JPH09174851A — "Printhead with field oxide as thermal barrier in chip", EP0574911B1 — "Semiconductor device for driving heat generator", EP0401440B1 / DE68929075T2) post-date or mirror this patent and are not prior art to it; they should not be used in a § 103 rejection. JPH09174851A is nonetheless useful evidence of what a PHOSITA understood about field oxide as a thermal barrier.

3. Claim charts and combinations

Combination A — Claim 1 (primary rejection)

Motivation to combine. Hawkins '530 expressly frames the problem the patent purports to solve — resistor material "formed on the same process lines with those of integrated circuits to reduce equipment costs and achieve higher yields" — and the '192 background itself concedes that "the drive circuitry should be formed on the same chip as the resistive elements." The remaining gap is the high-voltage switching capability of an MOS driver. Yamaguchi IEDM 1981 and Xerox '308,549 both teach, in the same field and for the same purpose (driving arrays of high-voltage transducers), that a drift-drain/field-plate MOS structure raises breakdown voltage; Yamaguchi additionally teaches co-integrating such devices with low-voltage NMOS logic. A PHOSITA seeking to shrink a TIJ driver chip (the '192 specification's own TABLE demonstrates that raising breakdown from 15 V to 60 V shrinks chip area from 140 mils to 80 mils and "at least halves the chip cost") would have been strongly motivated to substitute the known drift-drain driver for the conventional self-aligned n⁺ drain in Hawkins' monolithic printhead. In re Kemps; In re Nilssen (motivation may arise from "the nature of the problem to be solved").

Result would be predictable. The claimed "whereby" clause is not a separate inventive step; it is the inherent, well-understood mechanism by which a lightly doped drift region reduces peak field at the gate–drain junction. In re Best / In re Boesch (inherent properties of a disclosed composition are not patentable); In re Kerkhoven.

Combination B — Claim 2 (single polysilicon layer for gate and resistor)

Hawkins '530 in view of Rao '776. Rao '776's abstract states verbatim: "The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide." Hawkins '530 already teaches doped polysilicon bubble-generating resistors. Substituting Hawkins' resistor material into Rao's single-poly gate level is a design choice between two known alternatives (one poly level vs. two) with predictable results. Claim 2 is the most clearly obvious of the four.

Combination C — Claim 3 (two polysilicon levels: one for gates, one for resistors)

Hawkins '530 / Rao '776 in view of Raymond US 4,209,716 (or TI's 4,247,697 / 4,360,571 / 4,360,758), each teaching an implanted resistor in a second-level polysilicon overlying first-level poly transistor gates — and teaching that this requires no additional masks beyond a standard double-poly process. Where the disclosed single-poly approach forces a compromise between gate doping and resistor sheet resistance, providing a second poly level for the resistor is the obvious design alternative, expressly taught in the same art for the same purpose (decoupling resistor resistivity from gate doping).

Combination D — Claim 4 (first poly layer as field plate over the depletion layer)

Yamaguchi IEDM 1981 and Xerox '308,549 (or Ronen '288,802) in view of Rao '776. Yamaguchi expressly teaches a resistive polysilicon field plate over a thick field oxide over the n⁻ drift layer, with the drift layer "pinched between the wafer, which is grounded, and the grounded field plate" — i.e., a field plate that creates and controls a carrier depletion layer. The claim adds only the limitation that this field plate be formed in the first poly layer. That is a layout choice, not a structural advance.

⚠️ Note the internal tension: claim 3 requires the first poly to form the gate; claim 4 (depending from claim 3) requires the first poly to form the field plate. The claim set therefore contemplates the same first-poly level serving as gate over the channel and as field plate over the drift region — which is exactly what Ronen '288,802 ("single polysilicon layers for non-overlapping gates … bend field lines away from the drain") discloses. The combination is not merely obvious; the art anticipates the architecture.

4. Secondary considerations (Graham factor 4)

The specification's asserted advantages do not rescue the claims:

1. Thermal efficiency (21% / 37% improvements for 3 µsec and 5 µsec pulses) is tied exclusively to field-oxide thickness of 1–4 µm — which appears in no claim. Even if the data are credited, there is no nexus to the claimed subject matter (Ormco Corp. v. Align Tech.).
2. Extended resistor life (10⁶ → 10⁸ cycles) is attributed to the composite capping layer 79 over the polysilicon resistors, also unclaimed. Moreover, Hawkins '530 already discloses a thermally grown dielectric layer between the resistor and the protective tantalum ink-interface layer, i.e., the same capping concept.
3. Chip-size/cost reduction is a recognized, predictable benefit of higher breakdown voltage; it is evidence of motivation to combine (see the patent's own TABLE), not of non-obviousness.
4. Long-felt need / commercial success could theoretically be argued, but requires (i) proof the need was long-felt and unmet by Hawkins '530, Xerox '308,549, and Yamaguchi, and (ii) a nexus to claim scope. Neither is available for the field-oxide and capping-layer features, since they are unclaimed. The patent's own background also concedes the prior art already contained MOS-based thermal printheads (Hawkins '530; "Matsuera" / Seikosha '821).
5. Teaching away is weak. The '192 background asserts bipolar drive circuits were preferred and MOS was inefficient, but that is the applicant's characterization of a different prior-art branch. Hawkins '530 and Yamaguchi both point toward MOS/polysilicon integration, and a reference's criticism of a different approach does not teach away from the disclosed improvement (In re Lintner; In re Rinehart).

5. Expected rejections and where the analysis is soft

Strong (probably 2-references, no declaration needed): Claims 2 (Hawkins '530 + Rao '776) and 3 (add Raymond '209,716).

Strong: Claim 1 over Hawkins '530 + Yamaguchi IEDM 1981 + Rao '776. The only potentially surviving feature is the "whereby" clause; if construed literally as depletion within the n⁺ region, a rejection would require a factual showing, but under the specification-consistent construction (depletion in the n⁻ drift) Yamaguchi is squarely on point.

Strong, if the reference is properly of record: All of claims 1, 2, and 4 over US 4,288,802 (Ronen) alone or in view of Hawkins '530 — a single Xerox reference from the same decade that discloses separate channel and drift regions, split thick/thin oxide with a field plate over the drift region, and a single-poly non-overlapping gate.

Soft spots / things I cannot verify:

• Martin et al., IEDM 1984, pp. 266–269 — content unverified; I would not build a rejection on it without the paper.
• US 4,595,821 (Seikosha) — title and assignee confirmed from the patent's citation table; specification not retrieved. Also note the '192 specification calls this reference "to Matsuera," which the citation table does not corroborate; the identifier is used literally here and the attribution should not be relied on.
• Yamaguchi IEDM 1981 — content verified in relevant part (Xerox HiVID, 2 µm field oxide, resistive polysilicon field plate, co-integrated NMOS shift register); exact page range 255–258 not confirmed.

Bottom line. US 4,947,192 claims a combination of known elements: a bubble-jet channel/nosepiece module on a substrate (Xerox '777); polysilicon resistors co-fabricated with MOS circuitry on the same wafer (Hawkins '530); a self-aligned polysilicon-gated NMOS with a lightly doped drift drain extending breakdown voltage (Yamaguchi IEDM 1981; Xerox '308,549); and one- or two-level polysilicon resistors with metal vias (Rao '776; Raymond '209,716). Each reference is in the same field, addresses the same problem (a compact, low-cost, high-voltage-switching monolithic thermal printhead), and the combination yields no more than the predictable sum of the known functions. Claims 1–4 would be obvious under § 103(a). The features that appear genuinely novel and beneficial in the specification — the 1–4 µm thermal field oxide and the resistor capping layer — were left out of the claims, and are therefore available as prior art or unclaimed disclosure rather than as a basis for validity.