US 11894098

US Patent 11894098, titled "Dynamic random access memory applied to an embedded display port," was issued on February 6, 2024. The application was filed on March 25, 2021, under application number US17/213,133. The inventors are Der-Min Yuan, Yen-An Chang, and Wei-Ming Huang. The current assignee of record is Wecrevention Inc, following reassignments from Etron Technology Inc and VALUECREATION TECHNOLOGY, INC.

Abstract:
The patent describes a dynamic random access memory (DRAM) designed for use with an embedded display port. This DRAM comprises a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit operates at a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit and operates at a second predetermined voltage, which is specified to be lower than 1.1V. Similarly, the input/output unit is electrically connected to both the peripheral circuit unit and the memory core unit, operating at a third predetermined voltage that is also lower than 1.1V.

Independent Claims Overview:

• Claim 1: This claim describes a DRAM with a volatile DRAM core cell and a peripheral circuit, both formed on a single chip. The DRAM core cell operates at a first voltage that is lower than 1.1V. The peripheral circuit, which is external to the core cell and electrically connected to it, operates at a second voltage that is also lower than 1.1V. A key aspect is that the first and second voltages are different from each other.

• Claim 2: This claim is similar to Claim 1, detailing a DRAM with a volatile DRAM core cell and a peripheral circuit. Both the core cell and the peripheral circuit operate at voltages lower than 1.1V. Specifically, the first voltage supplied to the DRAM core cell is explicitly stated to be greater than the second voltage supplied to the peripheral circuit.

• Claim 3: This claim introduces an input/output circuit in addition to the DRAM core cell and peripheral circuit. All three components are comprised within the DRAM, with the core cell and input/output circuit formed on a single chip. The input/output circuit and the peripheral circuit are both electrically connected to the DRAM core cell and operate at a third and second voltage, respectively, both of which are lower than 1.1V. The input/output circuit is external to the DRAM core cell. The claim emphasizes that the first voltage (for the core cell) is different from the second voltage (for the peripheral circuit), and also different from the third voltage (for the input/output circuit).

• Claim 6: This claim describes a DRAM comprising a volatile DRAM core cell and an input/output circuit, both operating at specified voltages. The input/output circuit is electrically connected to the DRAM core cell and operates at a third voltage lower than 1.1V. A key feature is that the first voltage (for the core cell) is greater than the third voltage (for the input/output circuit). The DRAM, operating with these specified voltages, is capable of being applied to an embedded display port (eDP).

Docket Information (as of April 26, 2026):
The patent family is involved in litigation. As of the patent document's last update, multiple US cases were filed in the Texas Western District Court and Texas Eastern District Court in 2025. Additionally, a PTAB case, IPR2026-00242, was filed and is currently pending in 2026.