US 9281314

US Patent 9281314, titled "Non-volatile storage having oxide/nitride sidewall," was filed on October 10, 2014, and granted on March 8, 2016. The original assignee was SanDisk Technologies LLC, and the current assignee is Palisade Technologies LLP, as of August 15, 2024. The inventors are Takashi Kashimura, Xiaolong Hu, Sayako Nagamine, Yusuke Yoshida, Hiroaki Iuchi, Akira Nakada, and Kazutaka Yoshizawa.

Abstract:
The patent describes non-volatile storage devices and their fabrication methods. It details how the sidewalls of memory cells and their associated word lines are covered with silicon oxide. Silicon nitride is specifically placed over the silicon oxide adjacent to the word lines to offer protection during fabrication. Crucially, this silicon nitride does not cover the silicon oxide adjacent to the charge storage regions of the memory cells. This selective placement is designed to prevent charge trapping in the silicon nitride near the charge storage regions, which can otherwise degrade device operation, such as reducing memory cell current. The disclosed methods include using a sacrificial material to precisely control the formation of the silicon nitride layer.

Plain-Language Overview of Independent Claims:

The patent outlines four primary independent claims, two for methods of formation and two for the resulting memory devices:

1. Method of Forming a Memory Device: This claim describes a manufacturing process where lines of memory cells (each having a charge storage region and a control gate) and parallel word lines are formed. Oxide is applied to cover the sidewalls of both the charge storage regions and the word lines. Subsequently, a nitride region is formed adjacent to the oxide covering the word lines, but not adjacent to the oxide covering the charge storage regions. The method further includes forming air gaps between adjacent word lines, with a portion of these air gaps being next to the oxide that covers the charge storage regions.
2. Memory Device (Structure): This claim defines a memory device comprising lines of memory cells (each with a charge storage region and a control gate) and associated word lines. The device includes first oxide regions covering the sidewalls of the charge storage regions and second oxide regions covering the sidewalls of the word lines. Nitride regions are present, covering these second oxide regions (those adjacent to the word lines). Importantly, the device also features electrical isolation regions (other than silicon nitride) adjacent to the first oxide regions, which are the ones covering the sidewalls of the charge storage regions.
3. Method of Forming a Memory Array (Detailed): This claim details a fabrication method for a memory array. It involves forming lines of memory cell stacks, each containing memory cells and a tungsten word line. Silicon oxide is formed on the sidewalls of these stacks. A sacrificial material is then deposited between the stacks, such that its top surface is below the word lines but above the charge storage regions. This leaves a specific portion of the silicon oxide exposed. Silicon nitride is then formed on the sidewalls of this exposed silicon oxide. The sacrificial material is subsequently removed, ensuring the silicon oxide remains on the stack sidewalls and the silicon nitride stays only on the silicon oxide adjacent to the word lines. Finally, air gaps are created between neighboring memory cell stacks.
4. Memory Device (Detailed Structure): This claim describes a memory device structured with multiple lines of memory cell stacks. Each line comprises memory cells and a tungsten word line, with individual memory cells having a charge storage region. The device includes silicon oxide that covers the sidewalls of the memory cell stacks. Crucially, silicon nitride covers only those portions of the silicon oxide that are adjacent to the tungsten word lines. Furthermore, the device incorporates word line air gaps between neighboring pairs of the memory cell stacks, with these air gaps being adjacent to the portions of silicon oxide that are themselves adjacent to the charge storage regions.

Legal Status and Litigation:
The patent is currently Active, with an anticipated expiration date of October 10, 2034. It is involved in multiple litigation proceedings as of the current date (April 26, 2026):

• A PTAB case, IPR2025-01009, was filed but not instituted due to procedural reasons.
• A US case has been filed in the Texas Western District Court (case number 7:24-cv-00262).
• Another US case has been filed in the Texas Eastern District Court (case number 2:25-cv-01170).
• The first worldwide family litigation has also been filed.