US 8996838

San Jose, CA – April 26, 2026 – A detailed analysis of United States Patent 8,996,838 reveals a technology focused on improving the reliability and performance of 3D memory devices by detecting and compensating for structural variations.

Key Patent Details:

• Title: Structure variation detection for a memory having a three-dimensional memory configuration
• Assignee: Palisade Technologies LLP
• Inventors: Manuel Antonio d'Abreu, Xinde Hu
• Filing Date: May 8, 2014
• Issue Date: March 31, 2015
• Abstract: A data storage device includes a memory having a three-dimensional (3D) memory configuration and a controller. The controller is configured to determine a location associated with a variation of a structure that extends through multiple layers of the memory. The controller is further configured to generate information indicating the location. The information is accessible to the controller to determine one or more operating parameters for the memory.

This patent addresses a critical issue in the fabrication of 3D NAND flash memory. As memory stacks become taller, a "tapering" effect can occur during the etching process, where the vertical channels become narrower towards the bottom. This structural variation can impact the performance and reliability of memory cells at different layers. The invention provides a method for a memory controller to detect the location of this variation and then adjust operating parameters, such as read/write voltages or error correction schemes, for different layers of the memory to compensate for these physical differences. This allows for more uniform performance and increased data integrity across the entire 3D memory array.

Independent Claims in Plain Language:

Claim 1: A method for operating a data storage device that involves a controller identifying a specific location within a 3D memory structure where a physical variation occurs. The controller then creates and stores data that indicates this location.

Claim 11: A data storage device that includes a 3D memory and a controller. The controller is designed to pinpoint the location of a structural variation within the memory's layers and to generate information about that location.

Claim 18: A data storage device with a 3D memory and a controller. This controller can identify a location of a physical variation in the memory structure. Based on this location, it generates a table of parameters for the error correcting code (ECC) to be used. This table specifies different ECC settings for the memory pages located below the variation point versus those located above it.

Litigation and Administrative Review:

As of the current date, US Patent 8,996,838 has been involved in litigation. A lawsuit was filed by Palisade Technologies, LLP against Micron Technology, Inc. in the U.S. District Court for the Western District of Texas (Case No. 7:24-cv-00262) on October 16, 2024. This case, which also involved four other patents, alleged that Micron's DRAM, NAND Flash, and solid-state storage products infringed on Palisade's patents. The case was dismissed with prejudice on January 26, 2026, meaning Palisade cannot refile the same claims against Micron.

Additionally, an inter partes review (IPR) proceeding (IPR2025-01560) was initiated by Micron Semiconductor Products, Inc. against this patent at the Patent Trial and Appeal Board (PTAB). The IPR was filed on October 14, 2025, but was terminated.

A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for 2026 did not reveal any appeals related to this patent.