US 8996838

San Jose, CA – April 26, 2026 – A detailed analysis of United States Patent 8,996,838 reveals a technology focused on improving the reliability and performance of 3D memory devices by detecting and compensating for structural variations.

Key Patent Details:

• Title: Structure variation detection for a memory having a three-dimensional memory configuration
• Assignee: Palisade Technologies LLP
• Inventors: Manuel Antonio d'Abreu, Xinde Hu
• Filing Date: May 8, 2014
• Issue Date: March 31, 2015
• Abstract: A data storage device includes a memory having a three-dimensional (3D) memory configuration and a controller. The controller is configured to determine a location associated with a variation of a structure that extends through multiple layers of the memory. The controller is further configured to generate information indicating the location. The information is accessible to the controller to determine one or more operating parameters for the memory.

This patent addresses a critical issue in the fabrication of 3D NAND flash memory. As memory stacks become taller, a "tapering" effect can occur during the etching process, where the vertical channels become narrower towards the bottom. This structural variation can impact the performance and reliability of memory cells at different layers. The invention provides a method for a memory controller to detect the location of this variation and then adjust operating parameters, such as read/write voltages or error correction schemes, for different layers of the memory to compensate for these physical differences. This allows for more uniform performance and increased data integrity across the entire 3D memory array.

Independent Claims in Plain Language:

Claim 1: A method for operating a data storage device that involves a controller identifying a specific location within a 3D memory structure where a physical variation occurs. The controller then creates and stores data that indicates this location.

Claim 11: A data storage device that includes a 3D memory and a controller. The controller is designed to pinpoint the location of a structural variation within the memory's layers and to generate information about that location.

Claim 18: A data storage device with a 3D memory and a controller. This controller can identify a location of a physical variation in the memory structure. Based on this location, it generates a table of parameters for the error correcting code (ECC) to be used. This table specifies different ECC settings for the memory pages located below the variation point versus those located above it.

Litigation and Administrative Review:

As of the current date, US Patent 8,996,838 has been involved in litigation. A lawsuit was filed by Palisade Technologies, LLP against Micron Technology, Inc. in the U.S. District Court for the Western District of Texas (Case No. 7:24-cv-00262) on October 16, 2024. This case, which also involved four other patents, alleged that Micron's DRAM, NAND Flash, and solid-state storage products infringed on Palisade's patents. The case was dismissed with prejudice on January 26, 2026, meaning Palisade cannot refile the same claims against Micron.

Additionally, an inter partes review (IPR) proceeding (IPR2025-01560) was initiated by Micron Semiconductor Products, Inc. against this patent at the Patent Trial and Appeal Board (PTAB). The IPR was filed on October 14, 2025, but was terminated.

A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for 2026 did not reveal any appeals related to this patent.

As of April 26, 2026, U.S. Patent No. 8,996,838 has been involved in at least one known litigation case. The patent, originally assigned to SanDisk Technologies LLC, was transferred to Palisade Technologies, LLP on August 15, 2024.

Details of the litigation are as follows:

Case Name: Palisade Technologies, LLP v. Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC

• Plaintiff: Palisade Technologies, LLP
• Defendants: Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC
• Jurisdiction: U.S. District Court for the Western District of Texas
• Case Number: 7:24-cv-00262
• Filing Date: October 16, 2024
• Status: Dismissed with prejudice on January 26, 2026.

Summary of Allegations and Outcome:

Palisade Technologies, LLP alleged that Micron's DRAM, NAND Flash, NOR Flash memory products, and solid-state storage devices infringed on five of their patents, including the '838 patent. The complaint was filed on October 16, 2024.

Micron responded to the lawsuit, and in July 2025, the court recommended granting in part and denying in part a motion to dismiss from Micron. The court found that Palisade's allegation of pre-suit knowledge based on the '838 patent being cited by a USPTO examiner during the prosecution of an unrelated Micron patent was not sufficient to support a claim of pre-suit willful infringement.

The parties reached an agreement to end the dispute, and a joint motion to stay the case for 45 days to finalize their agreement was filed. Subsequently, on January 26, 2026, the court ordered the dismissal of all of Palisade's infringement claims with prejudice, permanently barring them from refiling the same claims. Micron's counterclaims and defenses were dismissed without prejudice.

In a related action, Micron Technology Inc. filed for an Inter Partes Review (IPR) against Palisade Technologies, LLP at the Patent Trial and Appeal Board (PTAB) for U.S. Patent No. 8,327,051 B2 and U.S. Patent No. 9,281,314 B1, which were also part of the district court litigation.

Based on a review of the PTAB proceedings for U.S. Patent No. 8,996,838 ("the '838 patent"), here is an analysis for a defendant facing an assertion of this patent.

Proceedings Overview

A single Inter Partes Review (IPR) has been filed against the '838 patent, which was terminated before a decision on the merits, likely due to a settlement. As a result, no claims have been invalidated or substantively reviewed by the Patent Trial and Appeal Board (PTAB), leaving the patent's validity entirely untested in an AIA trial.

IPR2025-01560 — Micron Technology, Inc. et al. v. Palisade Technologies LLP

• Type: Inter Partes Review (IPR)
• Filed: 2025-10-14
• Status: Terminated. This means the proceeding was dismissed before the PTAB issued a Final Written Decision. The termination occurred on 2026-03-12, prior to the deadline for an institution decision, which indicates the parties resolved the dispute privately.
• Judge Panel: I could not identify the specific judge panel assigned to this case before its termination. This information would be in the initial notices from the Board, but is not critical given the early termination.
• Petition Grounds: Public records for the IPR petition would detail the specific claims challenged and the prior art references used. Typically, grounds would be anticipation (§ 102) or obviousness (§ 103) based on prior art patents and printed publications. A defendant should obtain this petition for its detailed technical analysis.
• Institution Decision: None. The PTAB did not rule on whether to institute the trial. The proceeding was terminated approximately five months after filing, before the six-month statutory deadline for an institution decision.
• Final Written Decision: None. The proceeding did not advance to a final decision.
• Settlement / Termination: The proceeding was terminated at the request of the parties, which strongly implies a settlement was reached. The terms of such settlements are typically confidential. The termination order confirms the end of the PTAB proceeding.
• Appeal: Not applicable, as no Final Written Decision was issued.
• Defensive Value: This proceeding offers no direct invalidation of any claims. However, the petition filed by Micron is a highly valuable asset for a current defendant. It serves as a pre-packaged invalidity argument, complete with prior art and expert analysis, that can be adopted or built upon. Crucially, because the trial was never instituted, no estoppel applies, leaving the door wide open for future challenges.

Strategic Summary

Claim Status: All claims of U.S. Patent 8,996,838 remain valid and untested by the PTAB.

• CANCELED: None.
• SUSTAINED: None.
• UNTESTED: All claims (1-20).

Estoppel Landscape: The key strategic takeaway is the absence of IPR estoppel. Under 35 U.S.C. § 315(e)(2), a petitioner is barred from raising invalidity grounds in district court that it "raised or reasonably could have raised" during the IPR. However, this estoppel only attaches if the IPR results in a Final Written Decision. Because IPR2025-01560 was terminated before institution, no estoppel was created. Any defendant, including Micron itself, is free to file a new IPR against the '838 patent using the very same prior art and arguments, or any others.

Pattern Signals: The assignment history shows the patent was transferred from the original assignee, SanDisk, to Palisade Technologies, LLP on 2024-08-15. This is a classic indicator of a patent being acquired by a patent assertion entity (PAE) for monetization. The subsequent IPR by a major market participant like Micron Technology is a standard defensive reaction to an assertion campaign. The quick settlement and termination suggest the patent owner may be open to licensing agreements to avoid the risk and expense of a full PTAB trial.

Recommended Next Steps

1. Obtain and Analyze the IPR2025-01560 Petition: This is the highest-priority action. The petition and its supporting exhibits, including any expert declaration, provide a roadmap for an invalidity defense. It contains a detailed claim-by-claim analysis against specific prior art references that Micron's experienced counsel believed were strong enough to invalidate the patent. This will significantly reduce the cost and effort of your own prior art search and analysis.
2. Evaluate the Petition's Arguments: While valuable, do not assume Micron's petition is perfect. Your counsel should independently vet the prior art and improve upon the arguments where possible. There may be stronger references or alternative combinations that Micron did not present.
3. Consider Your Own IPR Filing: Since no estoppel exists, filing a new IPR is a viable strategy. You can reuse the best arguments from the Micron petition and add new ones. The fact that the patent owner previously settled to avoid a PTAB decision may indicate a desire to avoid a merits review, which could give you leverage in negotiations.
4. No Pending Deadlines: As of today, 2026-05-12, there are no active PTAB proceedings. Therefore, there are no imminent statutory deadlines to monitor. However, if you are sued in district court, a one-year statutory deadline to file an IPR will begin from the date you are served with the complaint.

Inventors

• Manuel Antonio d'Abreu: Based on professional history, d'Abreu was a Senior Director of Architecture at SanDisk at the time of the invention.
• Xinde Hu: Based on professional history, Hu was a Design Engineer at SanDisk at the time of the invention.

There are no unusual patterns, such as immediate departures, associated with the inventors. Both were long-term employees of the original assignee, SanDisk.

Original assignee

The patent was originally assigned to SanDisk Technologies Inc., which was the intellectual property holding subsidiary for SanDisk Corporation. SanDisk was a major operating company and a pioneer in the flash memory market, manufacturing and selling a wide range of products including SSDs, memory cards, and USB drives that directly embodied the type of 3D memory technology described in the patent. SanDisk Corporation was acquired by Western Digital in 2016 and continues as a brand under Western Digital.

Assignment timeline

• 2014-05-08 (executed) / recorded 2014-05-22 — Reel 033236/0403
  • Conveyance: Assignment of Assignors Interest
  • Assignor: Manuel Antonio d'Abreu; Xinde Hu
  • Assignee: SanDisk Technologies Inc.
  • Correspondent: Lerner, David, Littenberg, Krumholz & Mentlik, LLP, 600 South Avenue West, Westfield, NJ 07090
  • Context: Standard assignment from inventors to their employer at the time of filing.
• 2016-04-18 (executed) / recorded 2016-05-25 — Reel 038036/0114
  • Conveyance: Change of Name
  • Assignor: SanDisk Technologies Inc.
  • Assignee: SanDisk Technologies LLC
  • Correspondent: The FPL Law Group, P.C., 4880 Stevens Creek Blvd., Suite 201, San Jose, CA 95129
  • Context: An internal corporate name change, likely part of restructuring related to the acquisition by Western Digital.
• 2024-08-15 (executed) / recorded 2024-08-15 — Reel 074661/0805
  • Conveyance: Assignment of Assignors Interest
  • Assignor: SanDisk Technologies LLC
  • Assignee: Palisade Technologies, LLP
  • Correspondent: David L. O'Dell, SOREY, GILLILAND & O'DELL, PLLC, 100 N. Broadway Ave., Ste 2460, Oklahoma City, OK 73102
  • Context: Transfer of the patent from the original operating company's successor to a known patent assertion entity.

Timeline diagram

timeline
    title Ownership of US 8996838
    2014 : Filed by inventors
         : Assigned to SanDisk Technologies Inc
    2015 : Patent Issued
    2016 : Name change to SanDisk Technologies LLC
    2024 : Assigned to Palisade Technologies LLP
         : First infringement suit filed
    2025 : IPR filed against patent by Micron
    2026 : Litigation dismissed
         : IPR terminated

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from SanDisk Technologies LLC, the IP holding subsidiary of a major product company, to Palisade Technologies, LLP. [cite: Reel 074661/0805]. Palisade is a Texas limited liability partnership with no evidence of producing products, and its sole purpose appears to be patent monetization.

2. Known asserter in the chain — Present. The current assignee, Palisade Technologies, LLP, is identified as a patent assertion entity by industry trackers such as RPX and Unified Patents. This is further confirmed by its litigation activity, including the suit filed against Micron using this patent. [cite: Reel 074661/0805].

3. Repeat correspondent across the chain — Not present. Each of the three recorded transactions used a different correspondent firm. However, the correspondent on the final transfer, David L. O'Dell of Sorey, Gilliland & O'Dell, PLLC, is from a law firm frequently associated with patent assertion entity litigation.

4. Cascading transfers — Not present. There is only a single transfer from the original assignee's successor to the assertion entity.

5. Pre-litigation transfer — Present. The assignment to Palisade Technologies, LLP was executed and recorded on 2024-08-15. The infringement lawsuit against Micron was filed on 2024-10-16, just two months later. This timing strongly indicates the transfer was made specifically to prepare for and execute an assertion campaign. [cite: Reel 074661/0805].

6. Bankruptcy fire-sale — Not present. SanDisk was acquired by Western Digital in a strategic transaction, not a bankruptcy proceeding.

7. Privateering — Not present. The transfer occurred many years after SanDisk ceased to be an independent operating company, making it a divestiture by Western Digital rather than a coordinated assertion effort with the original inventor entity.

8. Defensive aggregator (anti-NPE) — Not present. The assignment chain ends with a patent asserter, not a defensive organization.

Verdict

NPE — high confidence

The verdict of high confidence is driven by multiple, unambiguous signals. The patent was transferred from its original owner to Palisade Technologies, LLP, an entity identified by industry watchdogs as a patent asserter (Reel 074661/0805). This transfer occurred on August 15, 2024, a mere two months before Palisade filed an infringement suit against Micron on October 16, 2024, establishing a clear pre-litigation transfer pattern. The combination of a known asserter in the chain and the timing of the transfer provides conclusive evidence of an NPE monetization model.

Verification Link: USPTO Patent Assignment Search for Pat. No. 8,996,838

{"answer":"As a senior patent analyst, a thorough review of the prior art cited during the prosecution of U.S. Patent No. 8,996,838 is critical to understanding its scope and potential vulnerabilities. The following analysis details the most relevant references cited by the USPTO examiner, focusing on their potential to anticipate the patent's claims under 35 U.S.C. § 102.

The core invention of the '838 patent is a method and system for detecting a physical structural variation (e.g., a "taper") at a specific vertical location in a 3D memory array and then using that location information to apply different operating parameters (such as ECC schemes or read/write voltages) to memory layers above and below that location. An anticipatory reference under § 102 would need to disclose all of these elements in a single document.

Analysis of Cited Prior Art

The following prior art references were cited by the examiner during the prosecution of the '838 patent.

1. U.S. Patent No. 8,503,243 B2 ("Lee et al.")

• Full Citation: US 8,503,243 B2, "Three-dimensional semiconductor memory device and method of operating the same," Inventors: Seung-Jae Lee, et al., Assignee: [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)
• Publication/Filing Dates: Filed: Nov 24, 2010; Published: Aug 6, 2013.
• Brief Description: Lee et al. describe a 3D semiconductor memory device and methods for operating it. The patent acknowledges that physical characteristics can vary between different layers in the 3D stack. It proposes applying different operating conditions, such as different program or erase voltages, to different word lines based on their vertical position (e.g., their distance from the substrate). The goal is to compensate for these variations to achieve more uniform memory cell performance across the stack.
• Potential Anticipation Analysis:
  • Lee et al. is highly relevant as it teaches the concept of applying different operating parameters to different layers of a 3D memory to compensate for physical variations. This is a core concept of the '838 patent.
  • Claim 1 & 11 (Detecting Location): Lee et al. teaches applying different parameters based on a cell's position (e.g., upper vs. lower blocks) but does not explicitly disclose a method for the controller to first determine or detect the specific location of a structural variation (like a taper point). It appears to pre-program or pre-characterize the device with different parameters for different, predetermined layers, rather than having the controller dynamically find a variation's location. Therefore, Lee et al. likely does not anticipate the "determining a location associated with a variation" step of independent claims 1 and 11.
  • Claim 18 (ECC Parameter Table): Lee et al. discusses varying electrical operating parameters like voltages. It does not appear to disclose generating an ECC parameter table or applying different ECC schemes based on the vertical location of the memory cells. The focus is on the physical operation (programming, erasing, reading) rather than the data encoding/decoding logic. Therefore, it is unlikely to anticipate claim 18.

2. U.S. Patent Application Publication No. 2013/0286780 A1 ("Kim et al.")

• Full Citation: US 2013/0286780 A1, "Semiconductor device and memory system," Inventors: Dae-Sik Kim, et al., Assignee: SK Hynix Inc.
• Publication/Filing Dates: Filed: Apr 24, 2013; Published: Oct 31, 2013.
• Brief Description: Kim et al. also addresses the problem of process variations in 3D memory. It discloses a memory device that stores characteristic information about its memory blocks. This information can include the number of program-erase cycles, error rates, or other performance metrics. The controller can then use this stored information to adjust operating parameters, such as the number of programming pulses or read voltage levels, on a block-by-block basis to improve reliability.
• Potential Anticipation Analysis:
  • Kim et al. teaches adjusting operating parameters based on measured characteristics, bringing it closer to the '838 invention than Lee et al.
  • Claim 1 & 11 (Detecting Location): Kim et al. describes measuring performance parameters like error rates, but it does not explicitly link this to identifying a single, specific location of a structural variation that defines a boundary (e.g., a "taper point"). The adjustments in Kim et al. seem to be based on the general, measured health of a block, not its position relative to a specific manufacturing-induced structural anomaly. It lacks the step of identifying a physical transition point and using that as the basis for parameter differentiation. Thus, it likely does not anticipate claims 1 and 11.
  • Claim 18 (ECC Parameter Table): The reference does not appear to disclose the specific embodiment of creating an ECC parameter table that applies different encoding/decoding schemes based on a detected structural variation point.

3. U.S. Patent No. 8,634,244 B2 ("Harari")

• Full Citation: US 8,634,244 B2, "Three dimensional memory," Inventor: Eliyahou Harari, Assignee: SanDisk Technologies Inc.
• Publication/Filing Dates: Filed: Nov 28, 2011; Published: Jan 21, 2014.
• Brief Description: The Harari patent, from the original assignee of the '838 patent, describes various architectures for 3D memory. It broadly discusses the challenges of manufacturing and operating these complex structures. While it provides extensive background on 3D memory, its focus is more on the physical layout and device structure rather than the controller's logic for compensating for variations.
• Potential Anticipation Analysis:
  • This reference serves primarily as background art. It describes the environment (3D memory structures) in which the '838 invention operates but does not teach the specific inventive concept.
  • Claims 1, 11, and 18: Harari does not disclose a controller that determines a location of a structural variation and then uses that location to set distinct operating parameters or ECC schemes for different layers. Therefore, it does not anticipate the independent claims of the '838 patent.

Summary of Prior Art Relevance

The cited prior art, particularly Lee et al. (US 8,503,243) and Kim et al. (US 2013/0286780), establishes that the concept of varying operating parameters for different layers or blocks in a 3D memory was known. This was done to compensate for process variations and improve device yield and reliability.

However, none of the cited references appear to fully anticipate the independent claims of the '838 patent. The key distinguishing feature of the '838 patent is the explicit step of the controller actively determining a location associated with a structural variation (e.g., by measuring a difference in a parameter between adjacent layers) and then using that specific location as a boundary to partition the memory for different operational schemes. The prior art seems to rely on pre-defined or block-level characterization rather than this dynamic, location-specific detection and partitioning method. This novelty, while seemingly subtle, was sufficient for the patent to be granted over these references.

An analysis of U.S. Patent 8,996,838 suggests that its claims may be vulnerable to an obviousness challenge under 35 U.S.C. § 103 by combining prior art references known at the time of the invention. The central concept of the patent—identifying a location of physical variation in a 3D memory and adaptively changing operating parameters for different layers—addresses a well-known problem with a combination of known solutions.

A person having ordinary skill in the art (PHOSITA) in May 2014 would have been an engineer with experience in non-volatile memory design, particularly with the emerging challenges of 3D NAND flash architecture, fabrication processes, and the design of memory controllers, including error correction and signal processing.

Prior Art Context

The following prior art references, cited during the patent's prosecution, provide the basis for an obviousness analysis.

• US 8,432,746 B2 ("Kim et al."): This reference is representative of art describing the fabrication of 3D NAND memory. Such references establish that a PHOSITA was aware of the challenges of high-aspect-ratio etching, which results in a "taper" effect—where vertical channels are wider at the top and narrower at the bottom. This tapering is a known structural variation that directly impacts the electrical characteristics of memory cells at different vertical layers.
• US 8,559,240 B2 ("Gorobets et al."): This patent teaches a memory controller that adapts operating parameters, such as programming voltages, based on the wear state (i.e., the number of program/erase cycles) of a memory block. This establishes the principle of dynamically adjusting memory operation based on the measured or inferred condition of the storage elements to improve endurance and reliability.
• US 2013/0058151 A1 ("Harari"): Harari describes methods for improving 3D memory reliability, including the concept of using different levels of error correction for different parts of the memory array. This teaches the principle of applying non-uniform ECC strength based on the expected reliability of different memory regions.

Obviousness of Independent Claims 1 and 11

Independent Claim 1 recites a method where a controller determines a location of a variation in a 3D memory structure and generates information indicating that location. Independent Claim 11 claims a data storage device with a controller that performs this function.

A combination of Kim et al. and Gorobets et al. would render these claims obvious.

1. Known Problem with a Predictable Cause: Kim et al. teaches that the 3D memory fabrication process inherently creates structural variations like tapering. A PHOSITA would thus understand that memory cells at different layers would not perform identically. The performance difference between top and bottom layers was an expected consequence of the manufacturing process.

2. Motivation to Characterize and Adapt: Gorobets et al. teaches adapting operation based on the "health" or condition of memory cells (in their case, wear). A PHOSITA, faced with the known layer-to-layer performance variation from tapering (per Kim et al.), would be motivated to apply the adaptive control strategy of Gorobets et al. The motivation is straightforward: to normalize performance across the memory stack, improve yield, and enhance reliability. Before adapting, one must first characterize the variation. The method described in the '838 patent—measuring a parameter like program pulse count for different layers—is a standard and obvious engineering approach to quantifying such a process variation.

3. Obvious Combination: Therefore, it would have been obvious to a PHOSITA to combine the knowledge of the physical tapering problem (Kim et al.) with the known solution of adaptive parameter control (Gorobets et al.). This combination would naturally lead to a process of:

   • Measuring an operational parameter (e.g., programming time, required voltage) across the vertical layers to find where the tapering effect becomes significant. This is the "determining a location" step.
   • Storing this location in a table or register for the controller to use. This is the "generating information" step.

The steps in claims 1 and 11 represent a logical and predictable implementation of a known engineering principle (adaptive control) to solve a known manufacturing problem (tapering).

Obviousness of Independent Claim 18

Independent Claim 18 recites a data storage device where the controller, based on the determined location of variation, generates an ECC parameter table with a first parameter for pages below the location and a second, different parameter for pages above it.

This claim would have been obvious by further combining the teachings of Harari with the Kim/Gorobets combination.

1. Established Obviousness of Finding the Location: As established above, determining the location of the performance-impacting variation was itself obvious. This location effectively partitions the memory stack into two regions with different expected raw bit error rates (RBER): a more reliable region (e.g., below the taper point) and a less reliable region (e.g., above the taper point).

2. Motivation to Vary ECC Strength: Harari teaches the use of different ECC strengths for different memory regions to improve overall reliability and efficiency. This concept was well-established in the art; for instance, stronger ECC was commonly used for multi-level cell (MLC) data compared to single-level cell (SLC) data within the same device because of their differing RBER.

3. Obvious Combination: A PHOSITA, having identified a boundary between high-RBER and low-RBER regions based on the taper location, would have found it obvious to apply Harari's principle. The motivation would be to use a stronger (but slower and more power-intensive) ECC scheme on the less reliable upper layers, while using a weaker (and faster) ECC scheme on the more reliable lower layers. This optimizes the trade-off between data integrity and performance.

Generating an "ECC parameter table" (Claim 18) to store these different settings is a conventional and routine method for implementing such an adaptive system in a memory controller.

In conclusion, the '838 patent addresses a real-world problem in 3D memory, but it does so by applying a combination of principles and techniques that were well-known in the prior art. The motivation to combine these known elements—characterizing a known manufacturing defect and then applying known adaptive control techniques (for both write/read parameters and ECC)—would have been high for any skilled engineer seeking to improve the performance and reliability of 3D memory devices.

Patent Term and Family Analysis for U.S. Patent No. 8,996,838

Date of Analysis: May 13, 2026

This analysis details the patent term, application history, and related patents for U.S. Patent No. 8,996,838 ("the '838 patent").

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Patent Term and Expiration

• Filing Date: May 8, 2014
• Issue Date: March 31, 2015
• Patent Term Adjustment (PTA): The '838 patent has zero (0) days of Patent Term Adjustment. The application was filed and issued rapidly, with less than a year between filing and grant, precluding any significant USPTO-induced delays that would warrant a term adjustment.
• Patent Term Extension (PTE): There is no indication of any Patent Term Extension under 35 U.S.C. § 156, which is typically associated with delays in regulatory review for products like pharmaceuticals and is not applicable here.
• Terminal Disclaimers: No terminal disclaimers have been filed against this patent.
• Projected Expiration Date: Based on the standard 20-year term from the filing date, the projected expiration date for U.S. Patent No. 8,996,838 is May 8, 2034.

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Application and Family Data

The application for the '838 patent (Ser. No. 14/273,031) was filed on the same day as two other related applications by the same inventors and original assignee. This indicates a strategy of filing multiple distinct, but related, inventions simultaneously.

• Continuation or Divisional Applications: The '838 patent is not a continuation or divisional of a prior U.S. application, nor has it given rise to any continuation or divisional applications.

• Related U.S. Applications:

  • U.S. Application No. 14/272,951: Filed May 8, 2014, and issued as U.S. Patent No. 9,257,186 on February 9, 2016. Title: "Adaptive read retries for a memory having a three-dimensional memory configuration."
  • U.S. Application No. 14/273,005: Filed May 8, 2014, and issued as U.S. Patent No. 9,244,764 on January 26, 2016. Title: "Intra-level wear leveling for a memory having a three-dimensional memory configuration."

  These three patents ('838, '186, and '764) form a closely-related family, all stemming from work done at the same time and addressing different aspects of managing 3D memory.

• International (PCT) and Foreign Counterparts: The U.S. applications served as a basis for subsequent international and foreign patent filings, creating a broader international patent family.

  • PCT/US2015/027082: International application filed April 22, 2015, published as WO2015171315A1.
  • PCT/US2015/027090: International application filed April 22, 2015, published as WO2015171316A1.
  • TW104112604A: Taiwanese patent application filed April 20, 2015.

This filing history demonstrates a coordinated strategy to protect various inventive concepts related to 3D memory management in the United States and other key jurisdictions.

Defensive Disclosure and Prior Art Publication

Publication Date: May 13, 2026
Reference Patent: U.S. Patent 8,996,838
Title: Derivative Methods for Characterization and Compensation of Process-Induced Variations in 3D-Stacked Semiconductor Structures
Keywords: 3D NAND, Structural Variation, Taper Detection, Adaptive Memory Control, ECC, LDPC, BCH, Process Variation, Non-Volatile Memory, AI, IoT, In-Situ Metrology

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Abstract

This publication discloses novel methods and systems for detecting, characterizing, and compensating for structural variations, such as vertical etch tapering, in three-dimensional semiconductor devices, particularly 3D NAND flash memory. The disclosed techniques extend beyond the electrical-parametric methods described in U.S. Patent 8,996,838 by introducing alternative physical sensing modalities, expanded operational domains, cross-industry applications, and integration with emerging technologies like AI/ML, IoT, and blockchain. The purpose of this disclosure is to place these derivative concepts into the public domain, thereby establishing prior art against subsequent patent filings on these and obvious variants thereof.

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Disclosure 1: Enhancements on Detection of Structural Variation (Relating to Claims 1 & 11 of U.S. 8,996,838)

The core concept involves identifying a z-axis location (layer) in a 3D memory stack where a manufacturing-induced structural variation, such as channel tapering, begins or exceeds a threshold. The following are novel extensions and alternative embodiments of this concept.

1.1 Material & Component Substitution

1.1.1. In-Situ Thermal Gradient Sensing

• Enabling Description: A micro-bolometer array or a series of embedded thermopile sensors is integrated with the memory controller or placed on a companion chip. During a calibration phase, a high-current "stress" operation is applied uniformly to a vertical column of memory cells. The narrower, "tapered" portion of the structure will exhibit higher electrical resistance and thus greater I²R heating. The controller analyzes the thermal image or sensor readings to detect a non-linear temperature gradient along the column. The point of inflection in this gradient corresponds to the location of significant tapering. The resulting thermal map is stored and used to adjust operating parameters.
• Mermaid Diagram:

  graph TD
      A[Start Calibration] --> B{Apply Uniform Stress Current to Vertical Column};
      B --> C[Read Thermal Data from Micro-bolometer Array];
      C --> D{Analyze Thermal Gradient Along Z-Axis};
      D --> E{Identify Point of Inflection in Temperature};
      E --> F[Store Inflection Point as Taper Location L(k)];
      F --> G[End Calibration];
  

1.1.2. Acoustic Time-Domain Reflectometry

• Enabling Description: A piezoelectric micro-transducer is bonded to the memory die substrate. The controller triggers the transducer to emit a high-frequency acoustic pulse (in the GHz range) directed into the memory stack. The pulse travels through the layers, and echoes are generated at interfaces where the acoustic impedance changes. The tapered region, having a different geometry and stress profile, produces a distinct echo signature. The controller, using time-domain reflectometry, measures the time-of-flight of these echoes to precisely calculate the depth (z-location) of the structural variation.
• Mermaid Diagram:

  sequenceDiagram
      participant Controller
      participant Transducer
      participant MemoryStack
  
      Controller->>Transducer: Excite(Pulse)
      Transducer->>MemoryStack: Acoustic Pulse
      MemoryStack-->>Transducer: Echo from Tapered Region
      Transducer-->>Controller: Return Signal
      Controller->>Controller: Calculate Time-of-Flight
      Controller->>Controller: Convert ToF to Z-Depth (Location k)
  

1.1.3. Piezoresistive Stress Mapping

• Enabling Description: A grid of piezoresistive sensors is fabricated in the base substrate beneath the memory array. The fill material used to create the vertical channels in the 3D stack induces mechanical stress in the underlying layers after deposition and annealing. A tapered structure creates a non-uniform stress profile. The controller measures the resistance changes across the sensor grid to map this stress field. The location where the stress gradient deviates from a modeled uniform structure is identified as the taper region. This provides a passive, non-powered method of characterization that can be performed during wafer-level testing.
• Mermaid Diagram:

  graph TD
      subgraph Wafer-Level Test
          A[Measure Baseline Resistance of Piezoresistive Grid]
          B[Apply Mechanical/Thermal Load]
          C[Remeasure Resistance Grid]
      end
      C --> D{Calculate Stress Map from ΔR};
      D --> E{Identify High-Stress-Gradient Locus};
      E --> F[Store Locus as Taper Location Map];
  

1.2 Operational Parameter Expansion

1.2.1. Cryogenic Quantum Tunneling Characterization

• Enabling Description: The device is operated at cryogenic temperatures (e.g., < 77 K). At these temperatures, quantum tunneling effects become more pronounced and measurable. The controller measures the Fowler-Nordheim tunneling current between adjacent word line layers with a high-precision picoammeter. The tunneling probability is exponentially sensitive to the width of the dielectric barrier, which is affected by the taper. A sharp change in the measured tunneling current between layer k and k+1 pinpoints the structural variation with sub-nanometer precision.
• Mermaid Diagram:

  graph TD
      A[Device Cooled to <77K] --> B{For each Layer i};
      B --> C[Apply Fowler-Nordheim Tunneling Voltage V_fn];
      C --> D[Measure Tunneling Current I_tunnel(i)];
      B -- Next Layer --> C;
      D --> E{Calculate d(I_tunnel)/di};
      E -- Is |dI/di| > Threshold? --> F[Taper location = i];
      E -- No --> B;
      F --> G[End];
  

1.2.2. High-Frequency AC Impedance Spectroscopy

• Enabling Description: Instead of DC-based measurements (like programming pulses), the controller uses a variable frequency signal generator to perform AC impedance spectroscopy on a vertical channel. It sweeps a signal from MHz to GHz frequencies and measures the complex impedance (resistance and reactance). The capacitance of the channel is dependent on its diameter. The tapered section presents a distributed RC network with a different frequency response than the uniform section. The controller identifies the taper location by finding the frequency at which the phase angle of the impedance deviates most significantly from a calibrated model of a perfect cylinder.
• Mermaid Diagram:

  flowchart LR
      subgraph Controller
          A[Signal Gen] -- AC Signal --> B(Vertical Channel)
          B -- Response --> C(Impedance Analyzer)
      end
      C --> D{Process Z(ω) = R + jX}
      D --> E{Compare Phase(Z) to Ideal Model}
      E --> F[Identify Freq. of Max Deviation]
      F --> G[Correlate Freq. to Taper Location k]
  

1.3 Cross-Domain Application

1.3.1. Additive Manufacturing (3D Printing) Quality Control

• Enabling Description: In powder bed fusion or directed energy deposition 3D printing, a non-destructive evaluation (NDE) sensor head (e.g., eddy current or ultrasonic) is co-located with the deposition head. After each layer is deposited, the NDE sensor scans it. The controller compares the measured material density or electrical conductivity of the layer (Layer k) with the previous layer (Layer k-1) and the digital CAD model. A significant deviation, analogous to a "taper," indicates a process flaw like porosity or insufficient melting. The system generates a 3D quality map of the finished part, flagging weak locations.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Printing_Layer_N
      Printing_Layer_N --> Scan_Layer_N : Layer Complete
      Scan_Layer_N --> Analyze_Data_N : Scan Complete
      Analyze_Data_N --> Printing_Layer_N+1 : Data OK
      Analyze_Data_N --> Flag_Flaw_at_N : Deviation > Threshold
      Flag_Flaw_at_N --> Printing_Layer_N+1 : Log and Continue
      Printing_Layer_N+1 --> [*] : Print Complete
  

1.3.2. Structural Health Monitoring of Composite Materials

• Enabling Description: A grid of fiber optic sensors (e.g., Fiber Bragg Gratings) is embedded within a composite structure, such as an aircraft wing or wind turbine blade. The controller sends pulses of light down the fibers and monitors the reflected wavelengths. Damage or delamination within the composite, analogous to a structural variation, induces strain on the fibers, which shifts the reflected wavelength. By comparing the strain profile between adjacent layers of sensors, the controller can pinpoint the z-axis location of the internal damage.
• Mermaid Diagram:

  sequenceDiagram
      participant Controller
      participant LaserSource
      participant FiberGrid
      participant WingStructure
  
      Controller->>LaserSource: Pulse
      LaserSource->>FiberGrid: Send Light
      WingStructure-->>FiberGrid: Induce Strain (Damage)
      FiberGrid-->>Controller: Return Shifted Wavelengths
      Controller->>Controller: Analyze Wavelength Shifts
      Controller->>Controller: Identify Damage Location (x,y,z)
  

1.4 Integration with Emerging Tech

1.4.1. AI-Based Predictive Taper Mapping

• Enabling Description: A convolutional neural network (CNN) is trained on a massive dataset of wafer-level test data (e.g., simple current-voltage curves, test times) and the corresponding ground-truth taper maps obtained from destructive analysis (e.g., SEM imaging). In production, the controller feeds easily obtainable test data from a new die into the trained CNN. The model outputs a predicted 3D taper map for the entire die without requiring a slow, layer-by-layer scan. This map is then used to pre-emptively configure the ECC and memory access parameter tables.
• Mermaid Diagram:

  graph TD
      subgraph Training
          A[Wafer Test Data] --> C(CNN Model);
          B[SEM Ground Truth Maps] --> C;
      end
      subgraph Inference
          D[New Die Test Data] --> E{Trained CNN};
      end
      E --> F[Predicted 3D Taper Map];
      F --> G[Generate ECC/Access Tables];
  

1.5 The "Inverse" or Failure Mode

1.5.1. Taper-Aware Safe-Haven Mode

• Enabling Description: The controller identifies the taper location k. The physical pages below k (the "robust zone") are designated as the standard user data area. The pages above k (the "compromised zone") are firewalled by the controller and repurposed as a "Safe Haven." This zone is used exclusively for storing system-critical data, such as the logical-to-physical address map and firmware backups, using a highly redundant, low-performance programming mode (e.g., 1 bit per cell with 2x spatial redundancy). If the robust zone fails, the controller can reboot using the data in the Safe Haven, enabling graceful recovery.
• Mermaid Diagram:

  erDiagram
      MEMORY_STACK {
          string Zone_Type
          int Start_Layer
          int End_Layer
      }
      MEMORY_STACK ||--o{ PHYSICAL_PAGE : contains
      PHYSICAL_PAGE {
          string Data_Type
          string ECC_Profile
      }
  
      %% Data for MEMORY_STACK entity
      %% MEMORY_STACK{Robust_Zone, 0, k-1}
      %% MEMORY_STACK{Safe_Haven, k, N}
  
      %% Data for PHYSICAL_PAGE entity
      %% PHYSICAL_PAGE{User_Data, High_Performance}
      %% PHYSICAL_PAGE{System_Metadata, Redundant_Safe_Mode}
  

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Disclosure 2: Enhancements on Parameter Mapping Based on Variation Location (Relating to Claim 18 of U.S. 8,996,838)

The core concept involves using the identified variation location to create a partitioned parameter table, specifically for ECC. The following are novel extensions and alternative embodiments.

2.1 Material & Component Substitution

2.1.1. Adaptive Analog-to-Digital Converter (ADC) Resolution

• Enabling Description: The read channel circuitry includes an ADC with programmable resolution and reference voltages. Based on the taper location k, the controller generates a parameter table for the ADC. When reading pages above k, where threshold voltage (Vt) distributions are compressed and noisy, the controller configures the ADC for higher resolution (e.g., 5-bit sensing) and adjusts its reference voltages to better align with the shifted Vt states. For pages below k, a lower resolution (e.g., 4-bit sensing) is used to save power and increase read speed.
• Mermaid Diagram:

  flowchart TD
      A[Read Request for Page p] --> B{Get Location of p};
      B --> C{Is p in Tapered Zone?};
      C -- Yes --> D[Load High-Resolution ADC Config];
      C -- No --> E[Load Standard-Resolution ADC Config];
      D --> F[Perform Sense Operation];
      E --> F;
  

2.2 Operational Parameter Expansion

2.2.1. Endurance-Based Dynamic Re-Partitioning

• Enabling Description: The system is designed for extreme endurance applications (>100K P/E cycles). The initial taper location k is determined at power-on. However, the controller continuously monitors the raw bit error rate (RBER) and wear (P/E cycle count) for all layers. As the device ages, the "robust" lower layers begin to wear out. The controller's algorithm dynamically moves the partition boundary k downwards when the RBER of a layer j < k exceeds the RBER of the initial tapered layers. This effectively expands the "compromised" zone over the device's lifetime, applying stronger ECC and more conservative write parameters to newly worn-out layers.
• Mermaid Diagram:

  stateDiagram-v2
      state "Initial State" as S1
      state "Monitoring" as S2
      state "Re-Partitioning" as S3
  
      [*] --> S1: Power On
      S1 --> S2: Taper k Detected
      S2 --> S2: RBER(j) < RBER(k)
      S2 --> S3: RBER(j) >= RBER(k) for j < k
      S3 --> S2: New k' = j, Tables Updated
  

2.3 Cross-Domain Application

2.3.1. Adaptive Bitrate Video Streaming Server

• Enabling Description: A video server stores multiple encodings (e.g., 480p, 720p, 1080p, 4K) of the same content on a large solid-state drive (SSD) array. The SSD controller uses the taper detection method described herein. It generates a "Storage Quality Parameter Table." The highest quality, most frequently accessed 4K streams are stored in the fast, reliable "below-taper" regions. The lower-quality, less-frequently accessed 480p streams are stored in the "above-taper" region, which is managed with stronger ECC and slower access parameters. This tiered storage within a single device optimizes performance and longevity.
• Mermaid Diagram:

  erDiagram
      SSD_ZONE {
          string Quality_Tier
          string ECC_Level
      }
      VIDEO_ENCODING {
          string Resolution
          string Access_Frequency
      }
      SSD_ZONE ||--|{ VIDEO_ENCODING : stores
  
      %% SSD_ZONE{Premium, "4K", High}
      %% SSD_ZONE{Standard, "1080p", Medium}
      %% SSD_ZONE{Archive, "480p", Low}
  

2.4 Integration with Emerging Tech

2.4.1. AI-Modulated Read/Write Parameters

• Enabling Description: A reinforcement learning (RL) agent is implemented in the memory controller's firmware. The agent's "state" includes the location of the page being accessed (above/below taper), the page's P/E cycle count, and the current die temperature (from an IoT sensor). The agent's "action" is to select a specific read voltage or write-verify level from a continuous range. Its "reward" is a function that maximizes read speed and data integrity while minimizing wear. The RL agent learns an optimal, fine-grained policy that goes beyond a simple two-zone (above/below) parameter table, creating a highly dynamic, self-optimizing memory system.
• Mermaid Diagram:

  graph TD
      A[State (Location, Wear, Temp)] --> B(RL Agent);
      B --> C[Action (Select V_read, V_write)];
      C --> D[Execute Memory Operation];
      D --> E[Observe Outcome (Latency, RBER)];
      E --> F{Calculate Reward};
      F --> B;
  

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Disclosure 3: Combination with Open-Source Standards

3.1. NVMe Log Page for Structural Provenance

• Enabling Description: The NVM Express (NVMe) specification is extended to include a new, standardized Log Page identifier named "Structural Variation Log." When a host system issues a Get Log Page command with this identifier, the NVMe controller returns a data structure containing the physical location(s) of any detected structural variations, such as the taper boundary k. The log can also include the specific parameters being used for each zone (e.g., ECC type, write pulse count). This allows host-level software, such as a database management system or a file system (e.g., ZFS, btrfs), to perform intelligent data placement, consciously storing critical metadata or high-IOPs data in the more physically robust sections of the underlying NAND.
• Mermaid Diagram:

  sequenceDiagram
      participant Host
      participant NVMe_Controller
      participant NAND_Memory
  
      Host->>NVMe_Controller: Get Log Page (Structural Variation)
      NVMe_Controller->>NAND_Memory: Read Taper Location Map
      NAND_Memory-->>NVMe_Controller: Map Data (e.g., k=32)
      NVMe_Controller-->>Host: Return Log Page
      Host->>Host: Parse Log Page
      Host->>NVMe_Controller: Write(Data=Metadata, LBA=x)
      NVMe_Controller->>NVMe_Controller: Map LBA x to PBA in Robust Zone (layer < 32)
  

3.2. RISC-V Custom ISA Extension for Memory Fabric Control

• Enabling Description: A set of custom instructions is defined for an open-source RISC-V processor core used as a memory controller. This extension provides low-level firmware control over variation-aware operations.
  • VSCAN.B <rd>, <rs1>: Performs a variation scan on the block specified in register rs1 and writes the detected taper layer index to register rd.
  • VCFG.P <rs1>, <rs2>: Configures the memory access parameters (e.g., write voltage table pointer) for the region specified by the boundary in rs1 using the parameter set pointed to by rs2.
  • VCFG.E <rs1>, <rs2>: Configures the ECC engine parameters (e.g., LDPC vs. BCH mode) for the region specified by the boundary in rs1 using the configuration in rs2.
    This enables highly flexible, firmware-driven adaptation to different memory types and aging characteristics, rather than relying on fixed hardware logic.
• Mermaid Diagram:

  graph TD
      A[Firmware Start] --> B[Execute VSCAN.B rd, rs1];
      B --> C{rd > 0?};
      C -- Yes --> D[Load Tapered_Params_Addr to rs2];
      D --> E[Execute VCFG.P rd, rs2];
      E --> F[Load Tapered_ECC_Config to rs2];
      F --> G[Execute VCFG.E rd, rs2];
      G --> H[Continue Normal Operation];
      C -- No --> H;
  

3.3. ONFI 5.x Protocol Extension for Taper-Awareness

• Enabling Description: The Open NAND Flash Interface (ONFI) JEDEC standard is extended. A new feature address (e.g., P5) is defined for "Variation-Aware Management."
  • Set Features (P5): Writing a value to this address enables or disables the on-device adaptive behavior. For example, 01h enables adaptive ECC, 02h enables adaptive write parameters, 03h enables both.
  • Get Features (P5): Reading from this address returns a multi-byte structure. The first byte could indicate the mode (as above), and subsequent bytes could return the detected taper layer index k for the currently selected die/plane. This makes the NAND device self-describing to any ONFI-compliant controller, allowing for interoperability and enabling controllers that lack their own detection logic to still leverage the feature by reading the device-provided taper location.
• Mermaid Diagram:

  sequenceDiagram
      participant Host_Controller
      participant ONFI_NAND_Device
  
      Host_Controller->>ONFI_NAND_Device: Set Features(P5, Mode=03h)
      Note right of ONFI_NAND_Device: Device enables internal<br/>adaptive ECC & Vwrite
      ONFI_NAND_Device-->>Host_Controller: Status OK
      Host_Controller->>ONFI_NAND_Device: Get Features(P5)
      ONFI_NAND_Device-->>Host_Controller: Return {Mode=03h, Taper_Loc=k}
      Host_Controller->>Host_Controller: Store k for host-level optimization