Derivative works — US Patent 8996838

Defensive Disclosure and Prior Art Publication

Publication Date: May 13, 2026
Reference Patent: U.S. Patent 8,996,838
Title: Derivative Methods for Characterization and Compensation of Process-Induced Variations in 3D-Stacked Semiconductor Structures
Keywords: 3D NAND, Structural Variation, Taper Detection, Adaptive Memory Control, ECC, LDPC, BCH, Process Variation, Non-Volatile Memory, AI, IoT, In-Situ Metrology

Abstract

This publication discloses novel methods and systems for detecting, characterizing, and compensating for structural variations, such as vertical etch tapering, in three-dimensional semiconductor devices, particularly 3D NAND flash memory. The disclosed techniques extend beyond the electrical-parametric methods described in U.S. Patent 8,996,838 by introducing alternative physical sensing modalities, expanded operational domains, cross-industry applications, and integration with emerging technologies like AI/ML, IoT, and blockchain. The purpose of this disclosure is to place these derivative concepts into the public domain, thereby establishing prior art against subsequent patent filings on these and obvious variants thereof.

Disclosure 1: Enhancements on Detection of Structural Variation (Relating to Claims 1 & 11 of U.S. 8,996,838)

The core concept involves identifying a z-axis location (layer) in a 3D memory stack where a manufacturing-induced structural variation, such as channel tapering, begins or exceeds a threshold. The following are novel extensions and alternative embodiments of this concept.

1.1 Material & Component Substitution

1.1.1. In-Situ Thermal Gradient Sensing

Enabling Description: A micro-bolometer array or a series of embedded thermopile sensors is integrated with the memory controller or placed on a companion chip. During a calibration phase, a high-current "stress" operation is applied uniformly to a vertical column of memory cells. The narrower, "tapered" portion of the structure will exhibit higher electrical resistance and thus greater I²R heating. The controller analyzes the thermal image or sensor readings to detect a non-linear temperature gradient along the column. The point of inflection in this gradient corresponds to the location of significant tapering. The resulting thermal map is stored and used to adjust operating parameters.

Mermaid Diagram:

graph TD
    A[Start Calibration] --> B{Apply Uniform Stress Current to Vertical Column};
    B --> C[Read Thermal Data from Micro-bolometer Array];
    C --> D{Analyze Thermal Gradient Along Z-Axis};
    D --> E{Identify Point of Inflection in Temperature};
    E --> F[Store Inflection Point as Taper Location L(k)];
    F --> G[End Calibration];

1.1.2. Acoustic Time-Domain Reflectometry

Enabling Description: A piezoelectric micro-transducer is bonded to the memory die substrate. The controller triggers the transducer to emit a high-frequency acoustic pulse (in the GHz range) directed into the memory stack. The pulse travels through the layers, and echoes are generated at interfaces where the acoustic impedance changes. The tapered region, having a different geometry and stress profile, produces a distinct echo signature. The controller, using time-domain reflectometry, measures the time-of-flight of these echoes to precisely calculate the depth (z-location) of the structural variation.

Mermaid Diagram:

sequenceDiagram
    participant Controller
    participant Transducer
    participant MemoryStack

    Controller->>Transducer: Excite(Pulse)
    Transducer->>MemoryStack: Acoustic Pulse
    MemoryStack-->>Transducer: Echo from Tapered Region
    Transducer-->>Controller: Return Signal
    Controller->>Controller: Calculate Time-of-Flight
    Controller->>Controller: Convert ToF to Z-Depth (Location k)

1.1.3. Piezoresistive Stress Mapping

Enabling Description: A grid of piezoresistive sensors is fabricated in the base substrate beneath the memory array. The fill material used to create the vertical channels in the 3D stack induces mechanical stress in the underlying layers after deposition and annealing. A tapered structure creates a non-uniform stress profile. The controller measures the resistance changes across the sensor grid to map this stress field. The location where the stress gradient deviates from a modeled uniform structure is identified as the taper region. This provides a passive, non-powered method of characterization that can be performed during wafer-level testing.

Mermaid Diagram:

graph TD
    subgraph Wafer-Level Test
        A[Measure Baseline Resistance of Piezoresistive Grid]
        B[Apply Mechanical/Thermal Load]
        C[Remeasure Resistance Grid]
    end
    C --> D{Calculate Stress Map from ΔR};
    D --> E{Identify High-Stress-Gradient Locus};
    E --> F[Store Locus as Taper Location Map];

1.2 Operational Parameter Expansion

1.2.1. Cryogenic Quantum Tunneling Characterization

Enabling Description: The device is operated at cryogenic temperatures (e.g., < 77 K). At these temperatures, quantum tunneling effects become more pronounced and measurable. The controller measures the Fowler-Nordheim tunneling current between adjacent word line layers with a high-precision picoammeter. The tunneling probability is exponentially sensitive to the width of the dielectric barrier, which is affected by the taper. A sharp change in the measured tunneling current between layer k and k+1 pinpoints the structural variation with sub-nanometer precision.

Mermaid Diagram:

graph TD
    A[Device Cooled to <77K] --> B{For each Layer i};
    B --> C[Apply Fowler-Nordheim Tunneling Voltage V_fn];
    C --> D[Measure Tunneling Current I_tunnel(i)];
    B -- Next Layer --> C;
    D --> E{Calculate d(I_tunnel)/di};
    E -- Is |dI/di| > Threshold? --> F[Taper location = i];
    E -- No --> B;
    F --> G[End];

1.2.2. High-Frequency AC Impedance Spectroscopy

Enabling Description: Instead of DC-based measurements (like programming pulses), the controller uses a variable frequency signal generator to perform AC impedance spectroscopy on a vertical channel. It sweeps a signal from MHz to GHz frequencies and measures the complex impedance (resistance and reactance). The capacitance of the channel is dependent on its diameter. The tapered section presents a distributed RC network with a different frequency response than the uniform section. The controller identifies the taper location by finding the frequency at which the phase angle of the impedance deviates most significantly from a calibrated model of a perfect cylinder.

Mermaid Diagram:

flowchart LR
    subgraph Controller
        A[Signal Gen] -- AC Signal --> B(Vertical Channel)
        B -- Response --> C(Impedance Analyzer)
    end
    C --> D{Process Z(ω) = R + jX}
    D --> E{Compare Phase(Z) to Ideal Model}
    E --> F[Identify Freq. of Max Deviation]
    F --> G[Correlate Freq. to Taper Location k]

1.3 Cross-Domain Application

1.3.1. Additive Manufacturing (3D Printing) Quality Control

Enabling Description: In powder bed fusion or directed energy deposition 3D printing, a non-destructive evaluation (NDE) sensor head (e.g., eddy current or ultrasonic) is co-located with the deposition head. After each layer is deposited, the NDE sensor scans it. The controller compares the measured material density or electrical conductivity of the layer (Layer k) with the previous layer (Layer k-1) and the digital CAD model. A significant deviation, analogous to a "taper," indicates a process flaw like porosity or insufficient melting. The system generates a 3D quality map of the finished part, flagging weak locations.

Mermaid Diagram:

stateDiagram-v2
    [*] --> Printing_Layer_N
    Printing_Layer_N --> Scan_Layer_N : Layer Complete
    Scan_Layer_N --> Analyze_Data_N : Scan Complete
    Analyze_Data_N --> Printing_Layer_N+1 : Data OK
    Analyze_Data_N --> Flag_Flaw_at_N : Deviation > Threshold
    Flag_Flaw_at_N --> Printing_Layer_N+1 : Log and Continue
    Printing_Layer_N+1 --> [*] : Print Complete

1.3.2. Structural Health Monitoring of Composite Materials

Enabling Description: A grid of fiber optic sensors (e.g., Fiber Bragg Gratings) is embedded within a composite structure, such as an aircraft wing or wind turbine blade. The controller sends pulses of light down the fibers and monitors the reflected wavelengths. Damage or delamination within the composite, analogous to a structural variation, induces strain on the fibers, which shifts the reflected wavelength. By comparing the strain profile between adjacent layers of sensors, the controller can pinpoint the z-axis location of the internal damage.

Mermaid Diagram:

sequenceDiagram
    participant Controller
    participant LaserSource
    participant FiberGrid
    participant WingStructure

    Controller->>LaserSource: Pulse
    LaserSource->>FiberGrid: Send Light
    WingStructure-->>FiberGrid: Induce Strain (Damage)
    FiberGrid-->>Controller: Return Shifted Wavelengths
    Controller->>Controller: Analyze Wavelength Shifts
    Controller->>Controller: Identify Damage Location (x,y,z)

1.4 Integration with Emerging Tech

1.4.1. AI-Based Predictive Taper Mapping

Enabling Description: A convolutional neural network (CNN) is trained on a massive dataset of wafer-level test data (e.g., simple current-voltage curves, test times) and the corresponding ground-truth taper maps obtained from destructive analysis (e.g., SEM imaging). In production, the controller feeds easily obtainable test data from a new die into the trained CNN. The model outputs a predicted 3D taper map for the entire die without requiring a slow, layer-by-layer scan. This map is then used to pre-emptively configure the ECC and memory access parameter tables.

Mermaid Diagram:

graph TD
    subgraph Training
        A[Wafer Test Data] --> C(CNN Model);
        B[SEM Ground Truth Maps] --> C;
    end
    subgraph Inference
        D[New Die Test Data] --> E{Trained CNN};
    end
    E --> F[Predicted 3D Taper Map];
    F --> G[Generate ECC/Access Tables];

1.5 The "Inverse" or Failure Mode

1.5.1. Taper-Aware Safe-Haven Mode

Enabling Description: The controller identifies the taper location k. The physical pages below k (the "robust zone") are designated as the standard user data area. The pages above k (the "compromised zone") are firewalled by the controller and repurposed as a "Safe Haven." This zone is used exclusively for storing system-critical data, such as the logical-to-physical address map and firmware backups, using a highly redundant, low-performance programming mode (e.g., 1 bit per cell with 2x spatial redundancy). If the robust zone fails, the controller can reboot using the data in the Safe Haven, enabling graceful recovery.

Mermaid Diagram:

erDiagram
    MEMORY_STACK {
        string Zone_Type
        int Start_Layer
        int End_Layer
    }
    MEMORY_STACK ||--o{ PHYSICAL_PAGE : contains
    PHYSICAL_PAGE {
        string Data_Type
        string ECC_Profile
    }

    %% Data for MEMORY_STACK entity
    %% MEMORY_STACK{Robust_Zone, 0, k-1}
    %% MEMORY_STACK{Safe_Haven, k, N}

    %% Data for PHYSICAL_PAGE entity
    %% PHYSICAL_PAGE{User_Data, High_Performance}
    %% PHYSICAL_PAGE{System_Metadata, Redundant_Safe_Mode}

Disclosure 2: Enhancements on Parameter Mapping Based on Variation Location (Relating to Claim 18 of U.S. 8,996,838)

The core concept involves using the identified variation location to create a partitioned parameter table, specifically for ECC. The following are novel extensions and alternative embodiments.

2.1 Material & Component Substitution

2.1.1. Adaptive Analog-to-Digital Converter (ADC) Resolution

Enabling Description: The read channel circuitry includes an ADC with programmable resolution and reference voltages. Based on the taper location k, the controller generates a parameter table for the ADC. When reading pages above k, where threshold voltage (Vt) distributions are compressed and noisy, the controller configures the ADC for higher resolution (e.g., 5-bit sensing) and adjusts its reference voltages to better align with the shifted Vt states. For pages below k, a lower resolution (e.g., 4-bit sensing) is used to save power and increase read speed.

Mermaid Diagram:

flowchart TD
    A[Read Request for Page p] --> B{Get Location of p};
    B --> C{Is p in Tapered Zone?};
    C -- Yes --> D[Load High-Resolution ADC Config];
    C -- No --> E[Load Standard-Resolution ADC Config];
    D --> F[Perform Sense Operation];
    E --> F;

2.2 Operational Parameter Expansion

2.2.1. Endurance-Based Dynamic Re-Partitioning

Enabling Description: The system is designed for extreme endurance applications (>100K P/E cycles). The initial taper location k is determined at power-on. However, the controller continuously monitors the raw bit error rate (RBER) and wear (P/E cycle count) for all layers. As the device ages, the "robust" lower layers begin to wear out. The controller's algorithm dynamically moves the partition boundary k downwards when the RBER of a layer j < k exceeds the RBER of the initial tapered layers. This effectively expands the "compromised" zone over the device's lifetime, applying stronger ECC and more conservative write parameters to newly worn-out layers.

Mermaid Diagram:

stateDiagram-v2
    state "Initial State" as S1
    state "Monitoring" as S2
    state "Re-Partitioning" as S3

    [*] --> S1: Power On
    S1 --> S2: Taper k Detected
    S2 --> S2: RBER(j) < RBER(k)
    S2 --> S3: RBER(j) >= RBER(k) for j < k
    S3 --> S2: New k' = j, Tables Updated

2.3 Cross-Domain Application

2.3.1. Adaptive Bitrate Video Streaming Server

Enabling Description: A video server stores multiple encodings (e.g., 480p, 720p, 1080p, 4K) of the same content on a large solid-state drive (SSD) array. The SSD controller uses the taper detection method described herein. It generates a "Storage Quality Parameter Table." The highest quality, most frequently accessed 4K streams are stored in the fast, reliable "below-taper" regions. The lower-quality, less-frequently accessed 480p streams are stored in the "above-taper" region, which is managed with stronger ECC and slower access parameters. This tiered storage within a single device optimizes performance and longevity.

Mermaid Diagram:

erDiagram
    SSD_ZONE {
        string Quality_Tier
        string ECC_Level
    }
    VIDEO_ENCODING {
        string Resolution
        string Access_Frequency
    }
    SSD_ZONE ||--|{ VIDEO_ENCODING : stores

    %% SSD_ZONE{Premium, "4K", High}
    %% SSD_ZONE{Standard, "1080p", Medium}
    %% SSD_ZONE{Archive, "480p", Low}

2.4 Integration with Emerging Tech

2.4.1. AI-Modulated Read/Write Parameters

Enabling Description: A reinforcement learning (RL) agent is implemented in the memory controller's firmware. The agent's "state" includes the location of the page being accessed (above/below taper), the page's P/E cycle count, and the current die temperature (from an IoT sensor). The agent's "action" is to select a specific read voltage or write-verify level from a continuous range. Its "reward" is a function that maximizes read speed and data integrity while minimizing wear. The RL agent learns an optimal, fine-grained policy that goes beyond a simple two-zone (above/below) parameter table, creating a highly dynamic, self-optimizing memory system.

Mermaid Diagram:

graph TD
    A[State (Location, Wear, Temp)] --> B(RL Agent);
    B --> C[Action (Select V_read, V_write)];
    C --> D[Execute Memory Operation];
    D --> E[Observe Outcome (Latency, RBER)];
    E --> F{Calculate Reward};
    F --> B;

Disclosure 3: Combination with Open-Source Standards

3.1. NVMe Log Page for Structural Provenance

Enabling Description: The NVM Express (NVMe) specification is extended to include a new, standardized Log Page identifier named "Structural Variation Log." When a host system issues a Get Log Page command with this identifier, the NVMe controller returns a data structure containing the physical location(s) of any detected structural variations, such as the taper boundary k. The log can also include the specific parameters being used for each zone (e.g., ECC type, write pulse count). This allows host-level software, such as a database management system or a file system (e.g., ZFS, btrfs), to perform intelligent data placement, consciously storing critical metadata or high-IOPs data in the more physically robust sections of the underlying NAND.

Mermaid Diagram:

sequenceDiagram
    participant Host
    participant NVMe_Controller
    participant NAND_Memory

    Host->>NVMe_Controller: Get Log Page (Structural Variation)
    NVMe_Controller->>NAND_Memory: Read Taper Location Map
    NAND_Memory-->>NVMe_Controller: Map Data (e.g., k=32)
    NVMe_Controller-->>Host: Return Log Page
    Host->>Host: Parse Log Page
    Host->>NVMe_Controller: Write(Data=Metadata, LBA=x)
    NVMe_Controller->>NVMe_Controller: Map LBA x to PBA in Robust Zone (layer < 32)

3.2. RISC-V Custom ISA Extension for Memory Fabric Control

Enabling Description: A set of custom instructions is defined for an open-source RISC-V processor core used as a memory controller. This extension provides low-level firmware control over variation-aware operations.
- VSCAN.B <rd>, <rs1>: Performs a variation scan on the block specified in register rs1 and writes the detected taper layer index to register rd.
- VCFG.P <rs1>, <rs2>: Configures the memory access parameters (e.g., write voltage table pointer) for the region specified by the boundary in rs1 using the parameter set pointed to by rs2.
- VCFG.E <rs1>, <rs2>: Configures the ECC engine parameters (e.g., LDPC vs. BCH mode) for the region specified by the boundary in rs1 using the configuration in rs2.
  This enables highly flexible, firmware-driven adaptation to different memory types and aging characteristics, rather than relying on fixed hardware logic.

Mermaid Diagram:

graph TD
    A[Firmware Start] --> B[Execute VSCAN.B rd, rs1];
    B --> C{rd > 0?};
    C -- Yes --> D[Load Tapered_Params_Addr to rs2];
    D --> E[Execute VCFG.P rd, rs2];
    E --> F[Load Tapered_ECC_Config to rs2];
    F --> G[Execute VCFG.E rd, rs2];
    G --> H[Continue Normal Operation];
    C -- No --> H;

3.3. ONFI 5.x Protocol Extension for Taper-Awareness

Enabling Description: The Open NAND Flash Interface (ONFI) JEDEC standard is extended. A new feature address (e.g., P5) is defined for "Variation-Aware Management."
- Set Features (P5): Writing a value to this address enables or disables the on-device adaptive behavior. For example, 01h enables adaptive ECC, 02h enables adaptive write parameters, 03h enables both.
- Get Features (P5): Reading from this address returns a multi-byte structure. The first byte could indicate the mode (as above), and subsequent bytes could return the detected taper layer index k for the currently selected die/plane. This makes the NAND device self-describing to any ONFI-compliant controller, allowing for interoperability and enabling controllers that lack their own detection logic to still leverage the feature by reading the device-provided taper location.

Mermaid Diagram:

sequenceDiagram
    participant Host_Controller
    participant ONFI_NAND_Device

    Host_Controller->>ONFI_NAND_Device: Set Features(P5, Mode=03h)
    Note right of ONFI_NAND_Device: Device enables internal<br/>adaptive ECC & Vwrite
    ONFI_NAND_Device-->>Host_Controller: Status OK
    Host_Controller->>ONFI_NAND_Device: Get Features(P5)
    ONFI_NAND_Device-->>Host_Controller: Return {Mode=03h, Taper_Loc=k}
    Host_Controller->>Host_Controller: Store k for host-level optimization