Prior art

{"answer":"As a senior patent analyst, a thorough review of the prior art cited during the prosecution of U.S. Patent No. 8,996,838 is critical to understanding its scope and potential vulnerabilities. The following analysis details the most relevant references cited by the USPTO examiner, focusing on their potential to anticipate the patent's claims under 35 U.S.C. § 102.

The core invention of the '838 patent is a method and system for detecting a physical structural variation (e.g., a "taper") at a specific vertical location in a 3D memory array and then using that location information to apply different operating parameters (such as ECC schemes or read/write voltages) to memory layers above and below that location. An anticipatory reference under § 102 would need to disclose all of these elements in a single document.

Analysis of Cited Prior Art

The following prior art references were cited by the examiner during the prosecution of the '838 patent.

1. U.S. Patent No. 8,503,243 B2 ("Lee et al.")

• Full Citation: US 8,503,243 B2, "Three-dimensional semiconductor memory device and method of operating the same," Inventors: Seung-Jae Lee, et al., Assignee: Samsung Electronics Co., Ltd.
• Publication/Filing Dates: Filed: Nov 24, 2010; Published: Aug 6, 2013.
• Brief Description: Lee et al. describe a 3D semiconductor memory device and methods for operating it. The patent acknowledges that physical characteristics can vary between different layers in the 3D stack. It proposes applying different operating conditions, such as different program or erase voltages, to different word lines based on their vertical position (e.g., their distance from the substrate). The goal is to compensate for these variations to achieve more uniform memory cell performance across the stack.
• Potential Anticipation Analysis:
  • Lee et al. is highly relevant as it teaches the concept of applying different operating parameters to different layers of a 3D memory to compensate for physical variations. This is a core concept of the '838 patent.
  • Claim 1 & 11 (Detecting Location): Lee et al. teaches applying different parameters based on a cell's position (e.g., upper vs. lower blocks) but does not explicitly disclose a method for the controller to first determine or detect the specific location of a structural variation (like a taper point). It appears to pre-program or pre-characterize the device with different parameters for different, predetermined layers, rather than having the controller dynamically find a variation's location. Therefore, Lee et al. likely does not anticipate the "determining a location associated with a variation" step of independent claims 1 and 11.
  • Claim 18 (ECC Parameter Table): Lee et al. discusses varying electrical operating parameters like voltages. It does not appear to disclose generating an ECC parameter table or applying different ECC schemes based on the vertical location of the memory cells. The focus is on the physical operation (programming, erasing, reading) rather than the data encoding/decoding logic. Therefore, it is unlikely to anticipate claim 18.

2. U.S. Patent Application Publication No. 2013/0286780 A1 ("Kim et al.")

• Full Citation: US 2013/0286780 A1, "Semiconductor device and memory system," Inventors: Dae-Sik Kim, et al., Assignee: SK Hynix Inc.
• Publication/Filing Dates: Filed: Apr 24, 2013; Published: Oct 31, 2013.
• Brief Description: Kim et al. also addresses the problem of process variations in 3D memory. It discloses a memory device that stores characteristic information about its memory blocks. This information can include the number of program-erase cycles, error rates, or other performance metrics. The controller can then use this stored information to adjust operating parameters, such as the number of programming pulses or read voltage levels, on a block-by-block basis to improve reliability.
• Potential Anticipation Analysis:
  • Kim et al. teaches adjusting operating parameters based on measured characteristics, bringing it closer to the '838 invention than Lee et al.
  • Claim 1 & 11 (Detecting Location): Kim et al. describes measuring performance parameters like error rates, but it does not explicitly link this to identifying a single, specific location of a structural variation that defines a boundary (e.g., a "taper point"). The adjustments in Kim et al. seem to be based on the general, measured health of a block, not its position relative to a specific manufacturing-induced structural anomaly. It lacks the step of identifying a physical transition point and using that as the basis for parameter differentiation. Thus, it likely does not anticipate claims 1 and 11.
  • Claim 18 (ECC Parameter Table): The reference does not appear to disclose the specific embodiment of creating an ECC parameter table that applies different encoding/decoding schemes based on a detected structural variation point.

3. U.S. Patent No. 8,634,244 B2 ("Harari")

• Full Citation: US 8,634,244 B2, "Three dimensional memory," Inventor: Eliyahou Harari, Assignee: SanDisk Technologies Inc.
• Publication/Filing Dates: Filed: Nov 28, 2011; Published: Jan 21, 2014.
• Brief Description: The Harari patent, from the original assignee of the '838 patent, describes various architectures for 3D memory. It broadly discusses the challenges of manufacturing and operating these complex structures. While it provides extensive background on 3D memory, its focus is more on the physical layout and device structure rather than the controller's logic for compensating for variations.
• Potential Anticipation Analysis:
  • This reference serves primarily as background art. It describes the environment (3D memory structures) in which the '838 invention operates but does not teach the specific inventive concept.
  • Claims 1, 11, and 18: Harari does not disclose a controller that determines a location of a structural variation and then uses that location to set distinct operating parameters or ECC schemes for different layers. Therefore, it does not anticipate the independent claims of the '838 patent.

Summary of Prior Art Relevance

The cited prior art, particularly Lee et al. (US 8,503,243) and Kim et al. (US 2013/0286780), establishes that the concept of varying operating parameters for different layers or blocks in a 3D memory was known. This was done to compensate for process variations and improve device yield and reliability.

However, none of the cited references appear to fully anticipate the independent claims of the '838 patent. The key distinguishing feature of the '838 patent is the explicit step of the controller actively determining a location associated with a structural variation (e.g., by measuring a difference in a parameter between adjacent layers) and then using that specific location as a boundary to partition the memory for different operational schemes. The prior art seems to rely on pre-defined or block-level characterization rather than this dynamic, location-specific detection and partitioning method. This novelty, while seemingly subtle, was sufficient for the patent to be granted over these references.