Obviousness

An analysis of U.S. Patent 8,996,838 suggests that its claims may be vulnerable to an obviousness challenge under 35 U.S.C. § 103 by combining prior art references known at the time of the invention. The central concept of the patent—identifying a location of physical variation in a 3D memory and adaptively changing operating parameters for different layers—addresses a well-known problem with a combination of known solutions.

A person having ordinary skill in the art (PHOSITA) in May 2014 would have been an engineer with experience in non-volatile memory design, particularly with the emerging challenges of 3D NAND flash architecture, fabrication processes, and the design of memory controllers, including error correction and signal processing.

Prior Art Context

The following prior art references, cited during the patent's prosecution, provide the basis for an obviousness analysis.

• US 8,432,746 B2 ("Kim et al."): This reference is representative of art describing the fabrication of 3D NAND memory. Such references establish that a PHOSITA was aware of the challenges of high-aspect-ratio etching, which results in a "taper" effect—where vertical channels are wider at the top and narrower at the bottom. This tapering is a known structural variation that directly impacts the electrical characteristics of memory cells at different vertical layers.
• US 8,559,240 B2 ("Gorobets et al."): This patent teaches a memory controller that adapts operating parameters, such as programming voltages, based on the wear state (i.e., the number of program/erase cycles) of a memory block. This establishes the principle of dynamically adjusting memory operation based on the measured or inferred condition of the storage elements to improve endurance and reliability.
• US 2013/0058151 A1 ("Harari"): Harari describes methods for improving 3D memory reliability, including the concept of using different levels of error correction for different parts of the memory array. This teaches the principle of applying non-uniform ECC strength based on the expected reliability of different memory regions.

Obviousness of Independent Claims 1 and 11

Independent Claim 1 recites a method where a controller determines a location of a variation in a 3D memory structure and generates information indicating that location. Independent Claim 11 claims a data storage device with a controller that performs this function.

A combination of Kim et al. and Gorobets et al. would render these claims obvious.

1. Known Problem with a Predictable Cause: Kim et al. teaches that the 3D memory fabrication process inherently creates structural variations like tapering. A PHOSITA would thus understand that memory cells at different layers would not perform identically. The performance difference between top and bottom layers was an expected consequence of the manufacturing process.

2. Motivation to Characterize and Adapt: Gorobets et al. teaches adapting operation based on the "health" or condition of memory cells (in their case, wear). A PHOSITA, faced with the known layer-to-layer performance variation from tapering (per Kim et al.), would be motivated to apply the adaptive control strategy of Gorobets et al. The motivation is straightforward: to normalize performance across the memory stack, improve yield, and enhance reliability. Before adapting, one must first characterize the variation. The method described in the '838 patent—measuring a parameter like program pulse count for different layers—is a standard and obvious engineering approach to quantifying such a process variation.

3. Obvious Combination: Therefore, it would have been obvious to a PHOSITA to combine the knowledge of the physical tapering problem (Kim et al.) with the known solution of adaptive parameter control (Gorobets et al.). This combination would naturally lead to a process of:

   • Measuring an operational parameter (e.g., programming time, required voltage) across the vertical layers to find where the tapering effect becomes significant. This is the "determining a location" step.
   • Storing this location in a table or register for the controller to use. This is the "generating information" step.

The steps in claims 1 and 11 represent a logical and predictable implementation of a known engineering principle (adaptive control) to solve a known manufacturing problem (tapering).

Obviousness of Independent Claim 18

Independent Claim 18 recites a data storage device where the controller, based on the determined location of variation, generates an ECC parameter table with a first parameter for pages below the location and a second, different parameter for pages above it.

This claim would have been obvious by further combining the teachings of Harari with the Kim/Gorobets combination.

1. Established Obviousness of Finding the Location: As established above, determining the location of the performance-impacting variation was itself obvious. This location effectively partitions the memory stack into two regions with different expected raw bit error rates (RBER): a more reliable region (e.g., below the taper point) and a less reliable region (e.g., above the taper point).

2. Motivation to Vary ECC Strength: Harari teaches the use of different ECC strengths for different memory regions to improve overall reliability and efficiency. This concept was well-established in the art; for instance, stronger ECC was commonly used for multi-level cell (MLC) data compared to single-level cell (SLC) data within the same device because of their differing RBER.

3. Obvious Combination: A PHOSITA, having identified a boundary between high-RBER and low-RBER regions based on the taper location, would have found it obvious to apply Harari's principle. The motivation would be to use a stronger (but slower and more power-intensive) ECC scheme on the less reliable upper layers, while using a weaker (and faster) ECC scheme on the more reliable lower layers. This optimizes the trade-off between data integrity and performance.

Generating an "ECC parameter table" (Claim 18) to store these different settings is a conventional and routine method for implementing such an adaptive system in a memory controller.

In conclusion, the '838 patent addresses a real-world problem in 3D memory, but it does so by applying a combination of principles and techniques that were well-known in the prior art. The motivation to combine these known elements—characterizing a known manufacturing defect and then applying known adaptive control techniques (for both write/read parameters and ECC)—would have been high for any skilled engineer seeking to improve the performance and reliability of 3D memory devices.