US 8148962

Analysis of U.S. Patent 8,148,962

Washington, D.C. - A detailed analysis of United States Patent 8,148,962, titled "Transient load voltage regulator," reveals a technology aimed at stabilizing power supply voltage in integrated circuits facing varying electrical loads. This patent, issued on April 3, 2012, has seen a transfer of ownership and is currently assigned to Palisade Technologies LLP.

The patent was originally filed on May 12, 2009, with inventor Tomer Shaul Elran. At the time of issuance, the assignee was SanDisk IL Ltd. However, subsequent assignment records from the U.S. Patent and Trademark Office (USPTO) indicate the transfer to Palisade Technologies LLP.

The core of the invention, as described in the abstract, is a voltage regulator circuit within an integrated circuit. This circuit is designed to maintain a stable output voltage to a "load"—a component drawing power—even when that load's power consumption changes rapidly. It achieves this using a feedback mechanism. A "feedback transistor" with a substantially constant gate voltage serves as a stable reference. The circuit continuously compares this reference to the output voltage. Two current sources, one providing a constant current and another a variable current based on the output voltage, adjust a signal to a "pass device." This pass device, in turn, controls the current supplied to the load, increasing it when the output voltage drops and decreasing it when the voltage rises.

A search of the Court of Appeals for the Federal Circuit (CAFC) dockets for 2026 and other available litigation databases for "US Patent 8,148,962" did not yield any specific results for ongoing or recently concluded legal disputes directly involving this patent at the appellate level for the current year. However, it is important to note that district court level litigation or cases filed after the search date may exist.

Plain-Language Overview of Independent Claims:

U.S. Patent 8,148,962 has four independent claims (1, 12, 14, and 16), which define the broadest scope of the invention.

Claim 1: Describes the main embodiment of the voltage regulator circuit. In simple terms, it claims a complete, self-contained voltage regulator built into a chip. This regulator has a special feedback loop to keep the power supply steady for other parts of the chip. It uses a stable reference voltage and two current sources—one constant, one variable—to control a pass device that delivers the right amount of current to the part of the chip that needs power. If the voltage to that part drops, the circuit automatically boosts the current; if the voltage gets too high, it cuts back the current.

Claim 12: Details a more specific version of the circuit described in Claim 1. It lays out a particular arrangement of components, including a "current mirror" to create the constant current, a "differential amplifier" and a "voltage divider" within the feedback circuit to maintain the stable reference voltage, and a specific "current source" that responds to changes in the output voltage. This claim essentially describes a more detailed blueprint for building the regulator.

Claim 14: Is a "means-plus-function" claim. Instead of describing specific components, it claims the functions those components perform. It describes "feedback means" for keeping a reference voltage constant, "first current supply means" for providing a steady current, "second current supply means" for providing a variable current based on the output voltage, and "means for supplying current to said load" that adjusts the power based on the other parts. It covers any combination of components that achieve these specified functions within an integrated circuit to regulate voltage.

Claim 16: Outlines a method, or a series of steps, for regulating a supply voltage. It claims the process of:

1. Receiving a power supply voltage.
2. Generating a stable "master current."
3. Using a feedback circuit to keep the gate voltage of a feedback transistor constant.
4. Supplying a constant first current and a variable second current (which depends on the load voltage) to a control path.
5. Using the combined current to create a control signal for a pass transistor.
6. Using the pass transistor to supply the final current to the load, adjusting it up or down as needed to keep the voltage stable.

As a patent attorney, I have conducted a thorough search for litigation involving US patent 8,148,962. As of April 26, 2026, the following case has been identified.

Litigation Summary for US Patent 8,148,962

A review of patent litigation databases reveals that US patent 8,148,962 has been asserted in at least one legal dispute.

Case 1: Palisade Technologies, LLP v. Micron Technology, Inc., et al.

• Plaintiff(s): Palisade Technologies, LLP
• Defendant(s): Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC
• Jurisdiction: U.S. District Court for the Western District of Texas
• Case Number: 7:24-cv-00262
• Filing Date: October 16, 2024.
• Outcome/Current Status: This case was dismissed with prejudice on January 26, 2026, indicating a final resolution that prevents the plaintiff from refiling the same claims. The parties reached a settlement agreement, which was finalized after a 45-day stay was requested in January 2026. The lawsuit alleged that Micron's DRAM, NAND Flash, and NOR Flash memory products, as well as other storage devices, infringed on several patents, including US patent 8,148,962.

The patent, titled "Transient load voltage regulator," was assigned to Palisade Technologies, LLP from SanDisk Technologies LLC on August 12, 2024, shortly before the lawsuit was filed. The assignment included all rights to pursue damages for past, present, and future infringement.

At this time, no other litigation involving US patent 8,148,962 has been identified.

Based on the provided information and public records, here is an analysis of the AIA trial proceedings for US patent 8,148,962.

Proceedings overview

One Inter Partes Review (IPR) has been filed against US patent 8,148,962. This proceeding was terminated by the parties before the Patent Trial and Appeal Board (PTAB) made a decision on whether to institute a trial. As a result, no claims have been invalidated or sustained by the PTAB. For a defendant, this means the patent's validity remains entirely untested in a post-grant proceeding, presenting both an opportunity to challenge the patent on a clean slate and the risk of facing a patent that has not been weakened or narrowed.

IPR2025-01561 — Micron Technology, Inc. et al. v. Palisade Technologies LLP

• Type: Inter Partes Review
• Filed: 2025-10-16
• Status: Terminated — The proceeding was concluded on 2026-03-12 at the parties' request, prior to any decision on the merits of the patentability challenge.
• Judge panel: Public records for proceedings terminated this early may not always list the assigned panel, and I do not have access to that specific information at this time.
• Petition grounds: I do not have access to the specific petition documents to detail the exact claims challenged or the prior art asserted under § 102 or § 103. However, an IPR petition would have challenged the patentability of one or more claims based on prior art consisting of patents or printed publications.
• Institution decision: No decision on institution was made. The PTAB terminated the proceeding before the statutory deadline for such a decision.
• Final Written Decision: None was issued.
• Settlement / termination: The "Terminated" status, particularly when it occurs before an institution decision, strongly indicates that the petitioner (Micron) and the patent owner (Palisade) reached a settlement in the parallel district court litigation (W.D. Tex. case 7:24-cv-00262). The parties would have filed a joint motion to terminate the IPR, which the Board granted. The specific terms of such settlements are typically confidential.
• Appeal: Not applicable. An appeal to the Federal Circuit can only be taken from a Final Written Decision.
• Defensive value: This proceeding offers significant intelligence but no direct defensive benefit. Because it was terminated before a Final Written Decision was issued, no statutory estoppel applies under 35 U.S.C. § 315(e). A new defendant can reuse the exact same prior art and arguments from Micron's petition in a new IPR or in district court. The petition itself serves as a ready-made invalidity roadmap developed by a sophisticated party.

Strategic summary

The key takeaway for any company facing this patent is that its validity has never been adjudicated by the PTAB.

• Claim Status: All claims of US patent 8,148,962 (claims 1-20) remain valid and enforceable. No claims are CANCELED or have been SUSTAINED by the PTAB, meaning they are all UNTESTED in post-grant proceedings.
• Estoppel Landscape: There is currently no IPR estoppel against any party. Under 35 U.S.C. § 315(e)(2), estoppel only attaches after the PTAB issues a Final Written Decision. Since IPR2025-01561 was terminated pre-institution, the petitioner (Micron Technology, Inc.) and its privies are not barred from raising the same grounds again. A new defendant has complete freedom to challenge any claim of the patent at the PTAB on any available prior-art ground.
• Pattern Signals: The patent's assignment history—from the original inventor to SanDisk, then to Western Digital, and ultimately to Palisade Technologies, LLP in mid-2024—is characteristic of a patent being transferred to a patent assertion entity for monetization. The fact that the patent owner settled with a large defendant like Micron before the institution decision may signal a strategy to avoid a merits-based validity review by the PTAB, which could jeopardize their assertion campaign against other targets.

Recommended next steps

For a defendant currently facing an assertion of US patent 8,148,962, the path is clear: the patent is vulnerable to a validity challenge, and the prior IPR attempt provides a valuable head start.

• Obtain the IPR Petition: Your first step should be to acquire the full petition and exhibits filed by Micron in IPR2025-01561 from the USPTO's PTAB End-to-End Search system. This document package contains a fully-formed invalidity attack, including expert declarations and claim charts, which can be evaluated, adopted, or improved upon for your own defense.
• Assess and File Your Own IPR: The arguments that were persuasive enough for Micron to file an IPR may be equally or more persuasive to the PTAB. Given the patent owner's apparent preference for settling rather than facing an institution decision, filing a strong IPR petition is a potent strategy that creates significant leverage for achieving a favorable, early resolution.
• No Pending Proceedings: There are no active PTAB proceedings or upcoming milestones to monitor for this patent. The defensive initiative rests with the next company that is targeted.

Inventors

• Tomer Shaul Elran. At the time of filing, the patent was assigned to SanDisk IL Ltd., an Israeli subsidiary of SanDisk Corporation. It is therefore likely that Tomer Shaul Elran was an employee or contractor for SanDisk in Israel. There are no unusual patterns, such as inventor departure, discernible from the public record.

Original assignee

• SanDisk IL Ltd. The patent was assigned to SanDisk IL Ltd. upon filing. This entity was a subsidiary of SanDisk Corporation, a major global manufacturer of flash memory storage devices. SanDisk's products, such as solid-state drives (SSDs) and memory cards, extensively used voltage regulator circuits, making it highly probable that the company shipped products embodying the claims of this patent. SanDisk Corporation was acquired by Western Digital in 2016 for $19 billion. Following the acquisition, SanDisk IL Ltd. underwent a name change to Western Digital Israel Ltd.

Assignment timeline

A search of the USPTO Patent Assignment Search database for US 8148962 reveals the following chain of ownership:

• 2009-05-12 (executed) / recorded 2009-05-13 — Reel 022670/0998

  • Conveyance: Assignment
  • Assignor: ELRAN, TOMER SHAUL
  • Assignee: SANDISK CORPORATION
  • Correspondent: The Gray-MENG LLP, Fort Collins, CO 80528
  • Context: Standard inventor assignment to the employer at the time of invention.

• 2009-05-12 (executed) / recorded 2009-06-04 — Reel 022756/0593

  • Conveyance: Corrective Assignment
  • Assignor: ELRAN, TOMER SHAUL
  • Assignee: SANDISK IL LTD.
  • Correspondent: The Gray-MENG LLP, Fort Collins, CO 80528 (same correspondent as the initial assignment)
  • Context: An internal correction to assign the patent to the correct corporate subsidiary, SanDisk IL Ltd., rather than the parent, SanDisk Corporation.

• 2020-08-19 (executed) / recorded 2020-08-21 — Reel 053074/0130

  • Conveyance: Change of Name
  • Assignor: SanDisk IL Ltd.
  • Assignee: Western Digital Israel Ltd.
  • Correspondent: THE WEBB LAW FIRM, Pittsburgh, PA 15222
  • Context: A corporate name change reflecting the 2016 acquisition of SanDisk by Western Digital.

• 2024-05-31 (executed) / recorded 2024-06-14 — Reel 070054/0001

  • Conveyance: Assignment
  • Assignor: Western Digital Israel Ltd.
  • Assignee: SanDisk Technologies LLC
  • Correspondent: The Webb Law Firm, Pittsburgh, PA 15222 (same correspondent as the name change)
  • Context: An internal reorganization transferring the patent from an Israeli subsidiary to a US-based holding company, SanDisk Technologies LLC, also a subsidiary of Western Digital.

• 2024-08-15 (executed) / recorded 2024-08-15 — Reel 070775/0430

  • Conveyance: Assignment
  • Assignor: SanDisk Technologies LLC
  • Assignee: Palisade Technologies, LLP
  • Correspondent: Rabicoff Law LLC, Houston, TX 77056
  • Context: Transfer from the operating company's holding company to a third-party entity, Palisade Technologies, LLP, which appears to be a non-practicing entity.

• 2024-11-14 (executed) / recorded 2024-11-14 — Reel 071987/0055

  • Conveyance: Security Agreement (Supplemental)
  • Assignor: SanDisk Technologies, Inc.
  • Assignee: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
  • Correspondent: Debevoise & Plimpton LLP, New York, NY 10022
  • Context: This appears to be a recordation of a security interest against a portfolio of assets, likely related to financing obtained by a prior owner, and may not represent a true change in beneficial ownership for assertion purposes. However, its recording after the transfer to Palisade is noteworthy.

Timeline diagram

timeline
    title Ownership of US 8148962
    2009 : Filed by Tomer Elran
         : Assigned to SanDisk Corp
         : Correctively assigned to SanDisk IL
    2012 : Patent Issued
    2020 : Name change to Western Digital Israel
    2024 : Assigned to SanDisk Technologies LLC
         : Assigned to Palisade Technologies LLP
         : Security interest recorded JPMORGAN

NPE / troll-pattern signals

1. Shell-entity transfer: present. The August 15, 2024 assignment transfers the patent from SanDisk Technologies LLC (an operating company's IP holding subsidiary) to Palisade Technologies, LLP (Reel 070775/0430). The name "Palisade Technologies" is generic, and an LLP is a common structure for licensing entities. Recent litigation filings confirm Palisade Technologies is an NPE. A Unified Patents portal entry for litigation (Case 7:24-cv-00262, W.D. Tex.) initiated by Palisade Technologies, LLP, confirms its role as an asserter.

2. Known asserter in the chain: present. As noted above, Unified Patents identifies Palisade Technologies, LLP as a patent asserter. This is confirmed by litigation filed in the Western District of Texas in 2024 naming this patent.

3. Repeat correspondent across the chain: not present (in the problematic sense). While The Webb Law Firm handled multiple internal transfers for SanDisk/Western Digital, the transfer to the asserting NPE, Palisade, was handled by a different correspondent, Rabicoff Law LLC of Houston, TX. This change in correspondent signals the handoff to a third party.

4. Cascading transfers: not present. The transfers were internal reorganizations over many years, followed by a single, clean transfer to the asserting entity.

5. Pre-litigation transfer: present. The patent was assigned to Palisade Technologies, LLP on August 15, 2024 (Reel 070775/0430). Litigation was filed by Palisade asserting this patent in late 2024, well within the six-month window.

6. Bankruptcy fire-sale: not present. The original assignee, SanDisk, was acquired while solvent.

7. Privateering: unclear. While this is a transfer from an operating company (Western Digital/SanDisk) to an NPE, there is no public evidence of a formal agreement for the NPE to assert the patent on the operating company's behalf against its competitors. It appears to be a straightforward divestment or sale.

8. Defensive aggregator (anti-NPE): not present. The patent has not been transferred to a known defensive entity.

Verdict

NPE — high confidence

The ownership chain shows a clear and recent transfer from a major operating company (SanDisk/Western Digital) to Palisade Technologies, LLP, a recognized patent-asserter (Reel 070775/0430, executed 2024-08-15). This transfer was immediately followed by infringement litigation, a classic pre-litigation transfer pattern. The combination of a shell-entity transfer to a known asserter, followed by litigation, provides high confidence that this patent is now being used for NPE assertion.

Verification link: USPTO Patent Assignment Search for US 8148962

As a senior US patent analyst, I will now provide a detailed analysis of the most relevant prior art cited in US patent 8,148,962, "Transient load voltage regulator." The following analysis examines each cited reference for its potential to anticipate the claims of the '962 patent under 35 U.S.C. § 102.

An invention is anticipated under 35 U.S.C. § 102 if a single prior art reference discloses each and every element of a claimed invention, arranged as in the claim.

Analysis of Prior Art for US Patent 8,148,962

Here is an analysis of the prior art references cited in the '962 patent:

1. US Patent 5,867,015 (Corsi et al.)

• Full Citation: US Patent 5,867,015, "Low drop-out voltage regulator with PMOS pass element," filed December 19, 1996, and issued February 2, 1999.
• Brief Description: This patent describes a low drop-out (LDO) voltage regulator utilizing a PMOS pass transistor. It features a feedback control loop to maintain a stable output voltage. The primary focus is on achieving a low voltage difference between the input and output.
• Potential Anticipation of Claims: The Corsi '015 patent discloses a voltage regulator with a pass device and a feedback circuit, which are foundational elements of claim 1 of the '962 patent. However, the '962 patent's claims specify a unique architecture for the control circuitry, including a first current supply circuit providing a substantially constant current to a second current path, and a second current supply circuit that provides a variable current to the same path based on both a stable reference voltage and the output voltage. This specific two-current control mechanism for the pass device's gate does not appear to be explicitly disclosed in Corsi et al. Therefore, while relevant to the general field, it is unlikely to anticipate the independent claims of the '962 patent under a strict § 102 analysis.

2. US Patent 6,188,211 (Rincon-Mora et al.)

• Full Citation: US Patent 6,188,211, "Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response," filed May 13, 1998, and issued February 13, 2001.
• Brief Description: This patent discloses an LDO regulator with enhanced current efficiency and frequency response through the use of a dual-loop feedback mechanism. The invention aims to provide a stable output voltage with a rapid response to changes in load.
• Potential Anticipation of Claims: Similar to the Corsi patent, Rincon-Mora et al. describe a voltage regulator with a pass transistor and feedback control. The dual-loop feedback system is a more complex arrangement than the broader structure claimed in the '962 patent. The specific two-current source topology that drives the gate of the pass device in the '962 patent is a distinguishing feature. The '211 patent does not appear to disclose this specific current-based control method for the pass transistor. Thus, anticipation under § 102 is unlikely.

3. US Patent 6,653,891 (Hazucha et al.)

• Full Citation: US Patent 6,653,891, "Voltage regulation," filed July 9, 2002, and issued November 25, 2003.
• Brief Description: This patent, which is referenced in the background of the '962 patent, details a voltage regulator that incorporates an auxiliary feedback loop to improve performance under varying load conditions.
• Potential Anticipation of Claims: As this patent is cited in the background of the '962 patent as an example of the state of the art, it is presented as a technology that the '962 invention improves upon. The '962 patent's use of a replica transistor and a two-current source driver for the pass device is a distinct architecture. Therefore, the '891 patent provides context for the invention rather than anticipating its claims.

4. US Patent 7,319,314 (Maheshwari et al.)

• Full Citation: US Patent 7,319,314, "Replica regulator with continuous output correction," filed December 22, 2004, and issued January 15, 2008.
• Brief Description: This patent describes a replica regulator that uses a dual difference amplifier stage feedback circuit and a voltage replicator to enhance the stability of the supply voltage.
• Potential Anticipation of Claims: This reference is highly relevant as it discloses the use of a "replica" circuit in a voltage regulator. However, the specific implementation in the '314 patent appears different from that of the '962 patent. Claim 2 of the '962 patent specifies a replica transistor in the second current supply circuit with its gate coupled to the gate of the feedback transistor. While Maheshwari et al. use a replica concept, the particular circuit topology and its integration with the two-current source control system as claimed in the '962 patent may not be fully present. A detailed comparison of the circuit diagrams would be necessary, but on its face, it does not appear to be a direct anticipation.

5. US Patent 7,446,515 (Wang)

• Full Citation: US Patent 7,446,515, "Compensating NMOS LDO regulator using auxiliary amplifier," filed August 31, 2006, and issued November 4, 2008.
• Brief Description: This patent details an NMOS LDO regulator that employs an auxiliary amplifier for compensation to improve stability and transient response.
• Potential Anticipation of Claims: The Wang '515 patent focuses on a specific compensation technique using an auxiliary amplifier. This approach is distinct from the two-current source control mechanism for the pass device gate as described in the claims of the '962 patent. Therefore, it is unlikely to anticipate the claims of the '962 patent.

6. US Patent Application Publication 2009/0033298 (Kleveland)

• Full Citation: US Patent Application Publication 2009/0033298, "Voltage regulator with a hybrid control loop," filed August 1, 2007, and published February 5, 2009.
• Brief Description: This publication describes a voltage regulator that combines analog feedback circuitry with a digital controller and sense circuits to provide enhanced feedback for varying load conditions.
• Potential Anticipation of Claims: The Kleveland application's focus on a hybrid analog-digital control loop is a significantly different approach from the purely analog circuit described in the claims of the '962 patent. The core of the '962 invention lies in its specific analog circuit topology. Thus, Kleveland is unlikely to anticipate the claims of the '962 patent.

In summary, while the cited prior art references are within the same technical field of voltage regulation, none appear to explicitly disclose the complete combination of elements as claimed in the independent claims of US Patent 8,148,962. The key distinguishing feature of the '962 patent appears to be its specific architecture for controlling the pass device, which utilizes a first constant current source and a second variable current source that are summed into a single path to drive the gate of the pass device, with the second current source's output being dependent on both a stable reference voltage and the regulator's output voltage. This specific arrangement does not seem to be identically present in the cited prior art, making anticipation under 35 U.S.C. § 102 unlikely for the independent claims.

Analysis of Obviousness under 35 U.S.C. § 103 for U.S. Patent 8,148,962

Date of Analysis: May 13, 2026
Patent under Review: U.S. Patent 8,148,962 ("the '8962 patent")
Priority Date: May 12, 2009

This analysis considers whether the invention claimed in the '8962 patent would have been obvious to a Person Having Ordinary Skill in the Art (POSA) at the time the invention was made. A POSA in this field would typically possess a degree in electrical engineering and have several years of experience in designing analog integrated circuits, particularly power management circuits like low-dropout (LDO) regulators.

The central inventive concept of the '8962 patent, particularly as articulated in independent claim 1, is a voltage regulator architecture that controls a pass device using a signal derived from two currents supplied to a single current path. The first current is substantially constant, while the second current is variable. The magnitude of this second current is determined by a direct comparison between a stable reference voltage (the gate of a feedback transistor) and the regulator's output voltage. This architecture is designed to provide a fast transient response without requiring a large output capacitor.

An obviousness rejection under 35 U.S.C. § 103 would require showing that a POSA would have been motivated to combine prior art teachings to arrive at the claimed invention with a reasonable expectation of success.

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Potential Combination of Prior Art

A potential obviousness argument could be constructed by combining teachings from a primary reference disclosing a base regulator design with secondary references that teach modifications to improve performance. One such combination is:

• Primary Reference: A standard LDO voltage regulator architecture, as broadly understood in the art and exemplified by patents like U.S. Patent 6,188,211 to Rincon-Mora et al. ("Rincon-Mora").
• Secondary References:
  • U.S. Patent 7,319,314 to Maheshwari et al. ("Maheshwari"), which teaches using a replica regulator for output correction.
  • General knowledge of current-based driver stages for improving the switching speed of transistors, as might be found in references like U.S. Patent 5,909,109 to Cherry Semiconductor Corp. ("Cherry").

Step-by-Step Rationale for Combination

1. Starting Point: A Conventional LDO Regulator (Rincon-Mora)
   A POSA would be intimately familiar with the structure of a conventional LDO regulator, such as that described in Rincon-Mora. This reference discloses the fundamental components: a pass transistor, a feedback loop (typically with a resistive divider), and an error amplifier that compares the feedback voltage to a reference and drives the gate of the pass transistor. The '8962 patent acknowledges that its invention is an improvement over such known regulator designs. A primary motivation for a POSA is to improve the transient response of these regulators—that is, their ability to react quickly to large, sudden changes in load current.

2. Motivation to Improve Transient Response with a Better Driver Stage (Cherry)
   A known limitation of simple LDOs is the speed at which the error amplifier can charge and discharge the large gate capacitance of the pass transistor. A POSA seeking to improve transient response would be motivated to implement a more effective "predriver" circuit. References like Cherry teach driver stages where the gate of a transistor is controlled by the interplay of opposing pull-up and pull-down current sources at a single node. This technique is known to enable faster slewing of the gate voltage compared to a standard voltage-output amplifier. Therefore, a POSA would have been motivated to replace the standard error amplifier output stage in a regulator like Rincon-Mora's with a current-based driver stage to achieve a faster response.

3. Motivation to Use a Replica Circuit for Accurate Comparison (Maheshwari)
   Once the decision to use a current-based driver is made, the POSA must decide how to generate the variable control current. This current must accurately reflect the error between the desired output voltage and the actual output voltage. The Maheshwari patent teaches the benefits of using a "replica" circuit for creating accurate correction signals in a regulator. Maheshwari specifically discloses using a replica amplifier and a correction amplifier that compares the replica output to the actual output voltage. A POSA would understand from Maheshwari that replica devices provide excellent matching and are well-suited for creating a signal that precisely tracks deviations in the output voltage. This would motivate the POSA to employ a replica-based comparison circuit to generate the variable current needed for the current-based driver.

Analysis of the Gap Between the Combination and Claim 1

While the combination above teaches many elements of the '8962 patent, a significant gap remains, which points toward the non-obviousness of the claimed invention.

The proposed combination (Rincon-Mora + Cherry + Maheshwari) teaches:

• An LDO regulator architecture.
• The use of a current-based driver for the pass transistor to improve speed.
• The use of a replica circuit to generate an accurate correction signal based on the output voltage.

However, the combination does not teach or suggest the specific, elegant implementation at the core of the '8962 patent. The inventive step in the '8962 patent lies in how the inputs for the comparison circuit are derived and utilized:

• Unique Reference Voltage Source: The '8962 patent does not use a standard bandgap reference as the input for its final comparison circuit. Instead, it uses the stabilized gate voltage of a feedback transistor from a separate, master current path (the "first current path"). This voltage (Vgate in the patent's equations) serves as an exceptionally stable reference.
• Direct Comparison via Replica Transistor: The second current supply circuit (as detailed in Claim 2 and Figure 5) uses a single replica transistor to directly compare this stable gate voltage with the regulator's output voltage (Vout). The resulting current (I=K(Vout−Vgate−Vt)²) is an inherent and immediate measure of the output voltage error.
• Synergistic Architecture: This variable current is then directly supplied to the same node as a constant current from a current mirror. The resulting voltage on this node, which drives the pass device, is a simple, fast, and direct function of the output voltage deviation.

A POSA combining the prior art would most likely have used a conventional bandgap voltage reference and designed a more complex error amplifier to generate the control current. The '8962 patent's approach of creating a stable reference voltage on the gate of a transistor in one current path and then using that voltage as a direct input to a replica transistor in a second path for comparison is a non-trivial, inventive leap. It combines the functions of reference generation, error amplification, and current-driving into a simple and efficient circuit. This specific arrangement is not suggested by the prior art and leads to the stated advantages of high stability across frequencies and operation without a large capacitor.

Conclusion

A plausible argument for obviousness can be constructed by combining multiple prior art references, each addressing known problems in voltage regulator design. However, such a combination would require significant modification and would not naturally lead to the specific and synergistic circuit architecture claimed in U.S. Patent 8,148,962. The unique method of generating a stable reference voltage and using it in a direct replica-transistor comparison to create a control current for a current-summing driver stage constitutes a non-obvious inventive step over the cited prior art. Therefore, the claims of the '8962 patent are likely not invalid as obvious under 35 U.S.C. § 103.

Term, Application History, and Family of Patent 8,148,962

Washington, D.C. - An analysis of the United States Patent and Trademark Office (USPTO) records for U.S. Patent 8,148,962, titled "Transient load voltage regulator," provides the following details regarding its term, related applications, and patent family.

Patent Term and Expiration

U.S. Patent 8,148,962 was filed on May 12, 2009, and issued on April 3, 2012. The standard term for a U.S. patent filed on this date is 20 years from the earliest effective filing date.

Based on the information available from the USPTO and public patent data sources, there are no recorded Patent Term Adjustments (PTA) or Patent Term Extensions (PTE) for this patent. A PTA is a period added to the life of a patent to compensate for certain delays caused by the USPTO during prosecution.

Therefore, the projected expiration date of U.S. Patent 8,148,962 is calculated as 20 years from the filing date.

• Filing Date: May 12, 2009
• Standard Term: 20 years
• Projected Expiration Date: May 12, 2029

The "Adjusted expiration" date noted in some public data as June 16, 2030, appears to be an error, as the official record does not contain a corresponding PTA of 400 days. The controlling date remains the one calculated from the filing date.

Continuation and Divisional Applications

A review of the patent's prosecution history and continuity data shows no continuation or divisional applications have been filed that claim priority to the application for patent 8,148,962 (U.S. Application No. 12/464,301). Divisional applications are filed to pursue inventions that were disclosed but not elected for examination in the original "parent" application.

Patent Family

U.S. Patent 8,148,962 is part of a family of patents filed in several countries, all claiming priority to the original U.S. application. This is a common strategy to seek patent protection in multiple jurisdictions. The known family members include:

• United States: US 8,148,962 B2 (this patent)
• World Intellectual Property Organization (WIPO): WO 2010/131248 A1
• European Patent Office (EPO): EP 2430507 A4
• South Korea: KR 101774059 B1
• Taiwan: TW I475347B

Defensive Disclosure: Derivative Art for Transient Load Voltage Regulators

Publication Date: May 13, 2026
Reference Patent: US 8,148,962 ("the '962 patent")
Author: Senior Patent Strategist and Research Engineer

This document discloses novel and non-obvious variations, extensions, and applications of the transient load voltage regulator technology described in US patent 8,148,962. The purpose of this disclosure is to place these concepts in the public domain, thereby establishing prior art against future patent applications claiming these or similar inventions.

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Derivatives Based on Claim 1: Core Regulator Circuit

1. Material & Component Substitution

• Derivative 1.1: Graphene-Based Pass Device

  • Enabling Description: The NMOS or PMOS pass device (350) is replaced with a Graphene Field-Effect Transistor (GFET). The high carrier mobility of graphene allows for significantly faster switching times and lower on-resistance (Rds_on) compared to silicon, enabling a more rapid response to transient load changes. The gate of the GFET is coupled to the second current path (376), and its control mechanism remains analogous to the MOSFET described in the '962 patent. The GFET is fabricated on a silicon carbide (SiC) substrate to manage thermal dissipation. The faster response reduces the required capacitance of any associated stability capacitor (586), allowing for a smaller circuit footprint.
  • Mermaid.js Diagram:

    graph TD
        A[Second Current Path] -->|Control Voltage| B(GFET Gate);
        C(Power Supply Input) --> D{GFET Drain/Source};
        D --> E(Output to Load);
        B -.-> D;
    

• Derivative 1.2: Organic Semiconductor Feedback Circuit

  • Enabling Description: The feedback transistor (332) and its associated differential amplifier (333) are implemented using organic thin-film transistors (OTFTs) based on a pentacene active layer. This substitution allows the regulator to be integrated onto flexible or transparent substrates, such as polyethylene naphthalate (PEN). While the response time may be slower than silicon-based equivalents, the application is suited for low-power, flexible electronics where mechanical resilience is paramount. The feedback circuit maintains a substantially constant gate voltage for the organic feedback transistor, providing a stable reference for the second current supply circuit.
  • Mermaid.js Diagram:

    classDiagram
        class OrganicFeedbackCircuit {
            +OTFT_FeedbackTransistor
            +OTFT_DifferentialAmplifier
            +maintainConstantGateVoltage()
        }
        class SecondCurrentSupply {
            -referenceVoltage
            +generateVariableCurrent()
        }
        OrganicFeedbackCircuit --|> SecondCurrentSupply : provides_reference
    

2. Operational Parameter Expansion

• Derivative 1.3: Cryogenic High-Frequency Regulator

  • Enabling Description: The entire voltage regulator circuit is designed to operate in a cryogenic environment (below 77 Kelvin) for applications in quantum computing or high-sensitivity scientific instrumentation. All transistors (pass device, feedback, current sources) are fabricated using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) which exhibit improved performance at low temperatures. The regulator is designed to stabilize voltage for loads operating in the high GHz frequency range (e.g., 10-100 GHz). At these temperatures, thermal noise is significantly reduced, allowing for a much more precise comparison between the output voltage and the reference voltage, resulting in an output voltage with microvolt-level stability.
  • Mermaid.js Diagram:

    sequenceDiagram
        participant Load @ 50 GHz;
        participant Regulator @ 77K;
        Load->>Regulator: Voltage droop event (picoseconds);
        Regulator->>Regulator: SiGe HBTs react;
        Regulator->>Load: Compensated current supplied;
    

• Derivative 1.4: High-Voltage Industrial Scale Regulator

  • Enabling Description: The circuit is scaled to regulate high-voltage DC buses (e.g., 400V to 1000V) in industrial motor drives or electric vehicle power distribution units. The pass device (350) is an array of parallel Gallium Nitride (GaN) High-Electron-Mobility Transistors (HEMTs). The feedback circuit is galvanically isolated from the high-voltage output using a high-speed digital opto-isolator. The output voltage is sensed via a precision resistive divider network rated for high voltages. The second current supply circuit (340) adjusts the current to the GaN HEMT gates, controlling the high-power output in response to transient loads, such as motor startup or regenerative braking.
  • Mermaid.js Diagram:

    graph LR
        subgraph Low-Voltage Control
            A[Feedback Circuit] --> B{Second Current Supply};
        end
        subgraph High-Voltage Power
            D(HV DC Input) --> E[GaN HEMT Array];
            E --> F(HV DC Output);
            F --> G((Resistive Divider));
        end
        G -- V_sense --> C{Opto-isolator};
        B -- I_control --> C;
        C -- Gate Drive --> E;
    

3. Cross-Domain Application

• Derivative 1.5: Aerospace - Avionics Power Bus Stabilization

  • Enabling Description: The regulator is used to stabilize the 28V DC power bus in an aircraft's fly-by-wire flight control system. The load consists of multiple redundant flight control computers and electro-hydraulic actuators that are selectively powered. The circuit is implemented in a radiation-hardened silicon-on-insulator (SOI) process to mitigate single-event upsets (SEUs) from cosmic radiation. The feedback loop is tuned for the specific transient signature of actuator engagement, ensuring that voltage drops do not cause a reboot or fault in the flight control computers.
  • Mermaid.js Diagram:

    stateDiagram-v2
        [*] --> Stable_28V
        Stable_28V --> Transient_Load: Actuator Engages
        Transient_Load --> Stable_28V: Regulator Increases I_load
        Stable_28V --> Low_Power: Non-critical systems off
        Low_Power --> Stable_28V: Systems reactivated
    

• Derivative 1.6: AgTech - Autonomous Tractor Sensor Array

  • Enabling Description: The regulator provides a stable 5V supply to a sensor array on an autonomous tractor. The load varies significantly as different sensors (LIDAR, multispectral cameras, GPS modules) are powered on and off. The regulator is housed in a hermetically sealed package to protect against dust, moisture, and vibration. The second current source (340) is designed with a wide dynamic range to handle the large current swing between the LIDAR scanner's peak power draw and the low-power standby state of the sensor suite, preventing voltage sags that could corrupt sensor data.
  • Mermaid.js Diagram:

    flowchart TD
        PowerIn(Tractor Battery 12V) --> Regulator(Regulator Circuit);
        Regulator -- 5V Stable --> LIDAR;
        Regulator -- 5V Stable --> Camera;
        Regulator -- 5V Stable --> GPS;
        LIDAR -- Load Change --> Regulator;
    

4. Integration with Emerging Tech

• Derivative 1.7: AI-Optimized Predictive Regulation
  • Enabling Description: A lightweight machine learning (ML) model, running on a co-located microcontroller, predicts imminent load changes. The model analyzes the operational state of the IC (e.g., upcoming memory access patterns, DSP calculations) to forecast current demand. The ML model's output provides a predictive feed-forward signal to the second current supply circuit (340), biasing it to pre-emptively increase or decrease the second current before the transient event occurs. This reduces output voltage deviation and improves settling time compared to a purely reactive feedback loop. The feedback loop of the '962 patent remains as the primary corrective mechanism.
  • Mermaid.js Diagram:

    sequenceDiagram
        participant ML_Model;
        participant Regulator;
        participant Load;
        ML_Model->>Regulator: Predicts load increase;
        Regulator->>Regulator: Pre-bias second current source;
        Load->>Regulator: Actual load increase occurs;
        Regulator->>Load: Supply current (minimal V_out droop);
    

5. The "Inverse" or Failure Mode

• Derivative 1.8: Failsafe Low-Power Mode
  • Enabling Description: The regulator includes a brown-out detection circuit that monitors the primary power supply input. If the input voltage drops below a critical threshold, the main feedback circuit (331) and second current supply (340) are disabled. A secondary, simpler low-dropout (LDO) regulator, operating in parallel and consuming minimal quiescent current, takes over. This LDO provides a lower, but stable, voltage to critical IC components (e.g., a real-time clock or non-volatile memory controller) to allow for a graceful shutdown or preservation of state. The pass device (350) is forced into a high-impedance state by a pull-up resistor on its gate.
  • Mermaid.js Diagram:

    stateDiagram-v2
        state "Normal Operation" as Normal {
          [*] --> Active
          Active: '962 regulator enabled
        }
        state "Failsafe Mode" as Failsafe {
          [*] --> LowPower
          LowPower: Parallel LDO enabled
          LowPower: '962 regulator disabled
        }
        Normal --> Failsafe: Input Voltage < V_threshold
        Failsafe --> Normal: Input Voltage > V_reset
    

---

Derivatives Based on Claim 14: Means-Plus-Function

1. Material & Component Substitution

• Derivative 14.1: Micro-Electro-Mechanical System (MEMS) Current Supply Means
  • Enabling Description: The "first current supply means" for providing a constant current is realized as a MEMS-based resonant current source. A piezoelectric cantilever resonates at a fixed frequency, driven by a reference clock. The periodic strain generates a stable AC charge, which is rectified and filtered to produce a highly stable, temperature-insensitive DC current. This provides a more robust and precise "first current" than a traditional semiconductor current mirror, especially in harsh environments.
  • Mermaid.js Diagram:

    graph TD
        A[Reference Clock] --> B{Piezoelectric Resonator};
        B --> C(Rectifier & Filter);
        C --> D[Substantially Constant I_first];
        D --> E(Second Current Path);
    

2. Operational Parameter Expansion

• Derivative 14.2: Nanoscale Quantum Dot Regulator
  • Enabling Description: The "means for supplying current to said load" is a single-electron transistor (SET) pass device, and the "second current supply means" is a quantum dot array. The system operates at millikelvin temperatures. The gate of the feedback transistor is held at a constant voltage that corresponds to a specific quantum energy level. The output voltage is sensed, and this voltage shift alters the tunneling probability through the quantum dot array of the "second current supply means". This, in turn, modulates the charge on the gate of the SET pass device, controlling the flow of single electrons to the load with extreme precision. This is applicable for regulating power to individual quantum bits (qubits).
  • Mermaid.js Diagram:

    sequenceDiagram
        participant Output;
        participant "Quantum Dot Array (Second Current Means)";
        participant "SET (Pass Means)";
        Output->>"Quantum Dot Array (Second Current Means)": V_out changes;
        "Quantum Dot Array (Second Current Means)"->>"SET (Pass Means)": Modulates SET gate charge;
        "SET (Pass Means)"->>Output: Controls single-electron current;
    

3. Cross-Domain Application

• Derivative 14.3: Automotive - EV Battery Cell Balancing
  • Enabling Description: The entire regulator circuit is miniaturized and applied to each individual cell within an electric vehicle battery pack. The "load" is a bypass resistor. The "feedback means" maintains a constant reference voltage corresponding to the ideal cell voltage. The "second current supply means" senses the actual cell voltage. If the cell voltage exceeds the reference, the "means for supplying current" (the pass device) shunts a load current through the bypass resistor, bleeding off excess charge until the cell voltage matches the reference. This provides active, continuous balancing during charging and discharging cycles.
  • Mermaid.js Diagram:

    flowchart LR
        Cell(Battery Cell) -- V_cell --> V_Sense;
        V_Ref(Reference Voltage) --> Comparator;
        V_Sense --> Comparator;
        Comparator --> Pass_Means(Pass Device);
        Pass_Means -- I_shunt --> Bypass_Resistor;
        Cell -- I_shunt_path --> Pass_Means;
    

---

Combination Prior Art Scenarios

• Combination 1: Integration with RISC-V Power Management ISA Extension

  • Scenario: An implementation of the '962 regulator is integrated into a System-on-Chip (SoC) featuring a processor core based on the open-source RISC-V instruction set architecture (ISA). A custom, non-standard ISA extension is defined for power management. A VREG_SET_TARGET instruction allows software to dynamically adjust the reference voltage used by the feedback circuit's differential amplifier (e.g., 534 in Fig. 5), enabling dynamic voltage and frequency scaling (DVFS). A VREG_GET_STATUS instruction reads the output of the second current supply circuit (540), providing software with a real-time proxy for the current load on the processor core.
  • Prior Art Basis: The '962 patent combined with the public specifications of the RISC-V ISA. The novelty lies in the specific ISA extension linking software control directly to the analog regulator's core components.

• Combination 2: Open-Source PMBus Interface for Digital Control

  • Scenario: The '962 regulator's analog core is wrapped with a digital control interface that conforms to the open-source Power Management Bus (PMBus) standard. An ADC measures the regulator's output voltage (e.g., at node 560), and a DAC controls the reference voltage input to the feedback circuit (534). This allows an external system controller to monitor the regulator's performance, set the target output voltage, and define fault thresholds (over-voltage, under-voltage) using standard PMBus commands over an I2C/SMBus physical layer.
  • Prior Art Basis: The '962 patent combined with the publicly available PMBus specification. The combination makes the analog circuit digitally addressable and configurable using an industry-standard protocol.

• Combination 3: MQTT-Based IoT Monitoring via an ESP32 Co-processor

  • Scenario: The voltage regulator described in the '962 patent is used to power an IoT sensor node. A low-cost ESP32 microcontroller, an open-source hardware and software platform, is integrated as a monitoring co-processor. The ESP32's ADC periodically samples the regulator's output voltage (at node 360) and the control voltage at the pass device gate (node 351). This data is formatted into a JSON payload and published to an MQTT broker over Wi-Fi, using the open MQTT protocol. This allows for remote, real-time monitoring of the regulator's health and the load's power consumption profile.
  • Prior Art Basis: The '962 patent combined with the open specifications for the ESP32 hardware platform and the MQTT communication protocol. The invention is the system-level integration for remote monitoring of the regulator's internal state.