US 7547584

Patent Summary: US 7,547,584 B2

Date of Analysis: May 13, 2026

Title: Method of reducing charging damage to integrated circuits during semiconductor manufacturing

Assignee: The patent was originally assigned to United Microelectronics Corp. and is currently assigned to Marlin Semiconductor Ltd.

Inventors: Ko-Ting Chen, Wen-Bin Lu, Chao-Hu Liang

Filing Date: November 16, 2006

Issue Date: June 16, 2009

Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Plain-Language Summary of Independent Claims

This patent describes methods to prevent the buildup of electrical charge during the manufacturing of integrated circuits, which can damage the delicate components. The core idea is to create additional, non-functional "dummy" patterns on the semiconductor wafer. These dummy patterns provide a path for excess electrical charge to safely dissipate, rather than damaging the actual circuit components. This is particularly important during processes like plasma etching and ion implantation, which are known to cause charge accumulation.

Independent Claim 1:

This claim outlines a method for reducing charge damage during the creation of metal interconnects on a chip. The key steps are:

1. Start with a semiconductor wafer that has a dielectric (insulating) layer on top of it.
2. Use a mask to create a pattern on the dielectric layer. This mask has openings for both the actual "interconnect" wiring and for "dummy" non-interconnect features.
3. Etch trenches into the dielectric layer using a plasma process, following the pattern of the mask. This creates both the trenches for the real wiring and dummy trenches.
4. Fill both types of trenches with a conductive material (like copper). This forms the functional interconnects and the non-functional dummy features.

The crucial part of this claim is that the dummy features, which are either left electrically floating or are grounded, provide a path for electrical charge to spread out and dissipate during the plasma etching step. This prevents a localized buildup of charge that could otherwise damage the circuit. The claim also specifies that the total area of all the openings in the mask should be more than 5% of the total die area to ensure effective charge dissipation.