US 7547584

Patent Summary: US 7,547,584 B2

Date of Analysis: May 13, 2026

Title: Method of reducing charging damage to integrated circuits during semiconductor manufacturing

Assignee: The patent was originally assigned to United Microelectronics Corp. and is currently assigned to [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

Inventors: Ko-Ting Chen, Wen-Bin Lu, Chao-Hu Liang

Filing Date: November 16, 2006

Issue Date: June 16, 2009

Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Plain-Language Summary of Independent Claims

This patent describes methods to prevent the buildup of electrical charge during the manufacturing of integrated circuits, which can damage the delicate components. The core idea is to create additional, non-functional "dummy" patterns on the semiconductor wafer. These dummy patterns provide a path for excess electrical charge to safely dissipate, rather than damaging the actual circuit components. This is particularly important during processes like plasma etching and ion implantation, which are known to cause charge accumulation.

Independent Claim 1:

This claim outlines a method for reducing charge damage during the creation of metal interconnects on a chip. The key steps are:

1. Start with a semiconductor wafer that has a dielectric (insulating) layer on top of it.
2. Use a mask to create a pattern on the dielectric layer. This mask has openings for both the actual "interconnect" wiring and for "dummy" non-interconnect features.
3. Etch trenches into the dielectric layer using a plasma process, following the pattern of the mask. This creates both the trenches for the real wiring and dummy trenches.
4. Fill both types of trenches with a conductive material (like copper). This forms the functional interconnects and the non-functional dummy features.

The crucial part of this claim is that the dummy features, which are either left electrically floating or are grounded, provide a path for electrical charge to spread out and dissipate during the plasma etching step. This prevents a localized buildup of charge that could otherwise damage the circuit. The claim also specifies that the total area of all the openings in the mask should be more than 5% of the total die area to ensure effective charge dissipation.

Following a comprehensive search, here is a summary of known litigation involving U.S. Patent No. 7,547,584.

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Patent Trial and Appeal Board (PTAB) Proceedings

1. Inter Partes Review (IPR)

• Case Number: IPR2025-01444
• Parties:
  • Petitioner: Unified Patents, LLC
  • Patent Owner: [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)
• Jurisdiction: United States Patent and Trademark Office, Patent Trial and Appeal Board (PTAB)
• Filing Date: The case was filed recently, leading to its current status.
• Status: Pending - Instituted
• Summary: An Inter Partes Review (IPR) has been initiated by Unified Patents, LLC to challenge the validity of one or more claims of U.S. Patent 7,547,584. The PTAB has instituted the trial, which means it has found a reasonable likelihood that the petitioner will prevail in its challenge against at least one of the patent's claims.

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At present, this is the only litigation found for U.S. Patent 7,547,584 based on the available public records as of today's date.

Based on the patent data and publicly available records, here is an analysis of the PTAB proceedings for U.S. Patent No. 7,547,584.

Proceedings overview

There is one active inter partes review (IPR) filed against U.S. Patent 7,547,584. The Patent Trial and Appeal Board (PTAB) has instituted trial on all challenged claims, indicating that the petitioner has shown a reasonable likelihood of success in invalidating them. For a potential defendant, this active challenge provides a strong defensive position, as the patent's validity is currently under significant threat.

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IPR2025-01444 — Taiwan Semiconductor Manufacturing Company Ltd. v. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

• Type: Inter Partes Review
• Filed: 2025-09-19
• Status: Trial Instituted. This means the PTAB has reviewed the petition and determined there is a "reasonable likelihood" that the petitioner will prevail in showing the unpatentability of at least one of the challenged claims. The case is now in the trial phase.
• Judge panel: The panel assigned to this case has not yet been made public in the available records.
• Petition grounds: The petition asserts that claims 1-6 of the '584 patent are invalid as either anticipated under 35 U.S.C. § 102 or obvious under 35 U.S.C. § 103 based on prior art references. The specific art and detailed arguments would be contained within the petition document itself.
• Institution decision: The decision to institute trial was made on or around 2026-05-05. The PTAB agreed with the petitioner, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC), that the presented evidence and arguments established a reasonable likelihood of invalidating claims 1-6. This preliminary finding allows the full trial to proceed.
• Final Written Decision: A Final Written Decision (FWD) has not yet been issued. The statutory deadline for the PTAB to issue its FWD is one year from the date of institution, making the expected deadline approximately 2027-05-05.
• Settlement / termination: There is no public record of a settlement or termination at this time. The proceeding remains active.
• Appeal: Not applicable. An appeal to the U.S. Court of Appeals for the Federal Circuit can only be filed after the PTAB issues a Final Written Decision.
• Defensive value: This proceeding is highly valuable for a defendant. The institution of trial on all challenged claims (1-6) signifies that the invalidity arguments are strong. A defendant can leverage the petitioner's arguments and evidence, and a stay of any co-pending district court litigation may be granted pending the outcome of this IPR.

Strategic summary

• Claim Status: All claims of U.S. Patent 7,547,584 (claims 1-6) are currently being challenged in IPR2025-01444. No claims have been finally adjudicated as invalid or confirmed as patentable. All claims remain valid and enforceable until a Final Written Decision rules otherwise.

• Estoppel Landscape: Statutory estoppel under 35 U.S.C. § 315(e) has not yet attached. If the PTAB issues a Final Written Decision, the petitioner (TSMC) and its real parties-in-interest will be barred from challenging the patent claims in district court or the ITC on any invalidity grounds that they raised or reasonably could have raised in the IPR. This estoppel does not yet apply to any other potential defendants. For a defendant other than TSMC, all prior art grounds remain available for a new PTAB challenge or for use in district court litigation.

• Pattern Signals: The patent was transferred from its original assignee, United Microelectronics Corp., to Marlin Semiconductor Ltd. in 2021. Marlin Semiconductor is a patent assertion entity. The IPR was filed by TSMC, a major operating company in the semiconductor industry, which is a common pattern where an operating company proactively challenges a patent being asserted within its industry. This IPR represents a significant, well-funded challenge to the patent's validity.

Recommended next steps

For any company facing an assertion of U.S. Patent 7,547,584, the most critical next step is to monitor IPR2025-01444 closely.

• Obtain Key Documents: A defendant should immediately obtain and analyze the full IPR petition and the Board's Decision on Institution from the PTAB's public database (available via the PTAB E2E portal). These documents will provide the complete invalidity arguments and prior art, as well as the Board's reasoning for finding a likelihood of success.
• Track Case Milestones: The key date is the statutory deadline for the Final Written Decision, which is on or about May 5, 2027. Other important dates, such as the Patent Owner's Response and the oral hearing, will be set by the Board's Scheduling Order.
• Consider Litigation Strategy: The institution of this IPR provides significant leverage. If sued, a defendant has strong grounds to request a stay of the district court case pending the final outcome of the IPR, which could resolve the entire dispute without the expense of a full trial. The invalidity contentions from the IPR can form the basis of a defense in court.

Inventors

The inventors listed on US Patent 7,547,584 are Ko-Ting Chen, Wen-Bin Lu, and Chao-Hu Liang. At the time of the patent application in November 2006, all inventors assigned their rights to their employer, United Microelectronics Corp. There is no public information to suggest any unusual employment patterns following the patent filing.

Original assignee

The original assignee is United Microelectronics Corp. (UMC), a major global semiconductor foundry headquartered in Hsinchu, Taiwan. UMC is an operating company that manufactures integrated circuits for other companies and is one of the world's largest dedicated semiconductor foundries. As a manufacturer of semiconductor devices, UMC undoubtedly developed and shipped products embodying the manufacturing processes described in the patent. The company remains a major, publicly traded, and active entity.

Assignment timeline

• 2006-11-13 (executed) / recorded 2006-11-16 — Reel 018529/0795
  • Conveyance: Assignment
  • Assignor: Ko-Ting Chen, Wen-Bin Lu, Chao-Hu Liang (Inventors)
  • Assignee: United Microelectronics Corp.
  • Correspondent: MIKIO ISHIMARU, The Mclaughlin Law Group, P.C., 26521 Moulton Pkwy, Ste G302, Laguna Hills, CA 92653
  • Context: Standard assignment of invention from employees to their employer at the time of filing.
• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292
  • Conveyance: Assignment
  • Assignor: United Microelectronics Corporation
  • Assignee: Marlin Semiconductor Limited
  • Correspondent: James J. DeCarlo, Greenberg Traurig, LLP, 500 Campus Drive, Suite 400, Florham Park, NJ 07932
  • Context: Transfer of the patent from the original operating company to a third-party entity, likely for monetization or assertion purposes.

Timeline diagram

timeline
    title Ownership of US 7,547,584
    2006 : Inventors assign to UMC
    2009 : Patent issued
    2021 : UMC assigns to Marlin Semiconductor
    2025 : IPR filed against patent

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from an operating manufacturer (United Microelectronics Corp.) to Marlin Semiconductor Limited (Reel 056991/0292, recorded 2021-07-26). Public records identify Marlin Semiconductor as an Irish entity and associate it with Marlin Equity Partners, a private equity firm. It does not appear to be a product-manufacturing company, suggesting it is a special purpose entity for holding and asserting intellectual property.

2. Known asserter in the chain — Present. The current assignee, Marlin Semiconductor Ltd., is the patent owner of record in an inter partes review (IPR) proceeding, IPR2025-01444, initiated by Unified Patents. Unified Patents is an organization that challenges patents it believes are being asserted by non-practicing entities (NPEs). Being the subject of a Unified Patents IPR is a strong indicator that the patent owner is actively asserting the patent.

3. Repeat correspondent across the chain — Not present. The two assignments on record were handled by different law firms.

4. Cascading transfers — Not present. The public record shows a direct transfer from the original assignee to the current assignee.

5. Pre-litigation transfer — Present. The assignment to Marlin Semiconductor Ltd. was recorded on July 26, 2021. This transfer enabled the subsequent assertion activities that led to the filing of IPR2025-01444 in 2025. The transfer was a necessary step to move the patent into an assertion vehicle before any monetization campaign could begin.

6. Bankruptcy fire-sale — Not present. The original assignee, UMC, is a financially healthy, ongoing global enterprise.

7. Privateering — Unclear. The transfer from a major operating company (UMC) to a patent assertion entity (Marlin) fits a common privateering pattern, where the original owner may retain a financial interest in the assertion campaign against its competitors. However, without access to the terms of the sale agreement between UMC and Marlin, this cannot be definitively confirmed.

8. Defensive aggregator (anti-NPE) — Not present. The current assignee is an assertion entity, not a defensive aggregator.

Verdict

NPE — high confidence

The patent was transferred from its original creator, an active semiconductor manufacturer (UMC), to Marlin Semiconductor Ltd., an entity that does not produce products and is associated with a private equity firm (Reel 056991/0292). The patent is currently being challenged in an IPR proceeding (IPR2025-01444) brought by Unified Patents, a strong indicator of active assertion by a non-practicing entity. This combination of a transfer from a manufacturer to a non-operating entity, followed by litigation activity, provides high confidence that the patent is now held for assertion purposes.

A full record of these assignment events can be reviewed at the USPTO Patent Assignment Search database by searching for Patent Number 7547584.

Prior Art Analysis for U.S. Patent No. 7,547,584

This analysis details the prior art cited in the prosecution history of U.S. Patent No. 7,547,584. Each cited reference is examined for its potential to anticipate the claims of the '584 patent under 35 U.S.C. § 102.

Based on the patent's file wrapper, the following documents were cited as prior art during the examination process:

1. U.S. Patent No. 5,998,282 (Lukaszek)

• Full Citation: US Patent 5,998,282, "Method of reducing charging damage to integrated circuits in ion implant and plasma-based integrated circuit process equipment"
• Publication Date: December 7, 1999
• Filing Date: October 21, 1997
• Description: Lukaszek discloses a method to mitigate charging damage during ion implantation and plasma processing by modifying the scribe lanes between integrated circuit dies. It teaches creating conductive paths or "shunt paths" within these scribe lanes to dissipate accumulated electrical charge to the substrate, thereby protecting the active circuit areas on the die. The patent explicitly mentions that creating such shunt paths within the integrated circuit die itself is difficult due to layout constraints.
• Potential Anticipation of Claims: Lukaszek teaches the general concept of using shunt paths to mitigate charging damage. However, it focuses on modifying the scribe lanes, which are the non-functional areas between dies, rather than creating dummy features within the die area itself as claimed in the '584 patent. The method described in claim 1 of US 7,547,584 specifies forming "dummy, non-interconnect" features within each said integrated circuit die. Lukaszek's disclosure of creating shunt paths in the scribe lanes does not directly anticipate this specific in-die implementation. Therefore, it is unlikely that Lukaszek '282 anticipates the claims of US 7,547,584 on its own.

2. U.S. Patent No. 6,521,487 B1 (Tu et al.)

• Full Citation: US Patent 6,521,487 B1, "Method for making a thyristor"
• Publication Date: February 18, 2003
• Filing Date: December 5, 2001
• Assignee: United Microelectronics Corp.
• Description: Tu et al. describes a method for fabricating a thyristor, a type of semiconductor device. The process involves multiple ion implantation steps using photoresist masks to define P-wells, N-wells, and various doped regions. The focus is on the specific structure and formation of the thyristor and does not address the problem of charging damage during these implantation steps, nor does it teach the deliberate creation of dummy openings in the mask to increase the exposed surface area for charge dissipation.
• Potential Anticipation of Claims: This reference is cited as general background for semiconductor fabrication processes involving ion implantation and masking. It does not appear to disclose the key inventive concept of the '584 patent, which is the use of dummy openings in a mask to create a shunt path for charge dissipation during plasma etching or ion implantation. It does not teach forming dummy, non-interconnect openings or features within the die to reduce charging damage. Therefore, Tu et al. '487 does not anticipate the claims of US 7,547,584.

3. U.S. Patent Application Publication No. 2006/0006538 A1 (Cote et al.)

• Full Citation: US Patent Application Publication 2006/0006538 A1, "Extreme low-K interconnect structure and method"
• Publication Date: January 12, 2006
• Filing Date: July 2, 2004
• Description: Cote et al. describes a method for creating interconnect structures using low-dielectric constant (low-k) materials. It addresses the challenges of integrating these fragile materials, including preventing damage during processing. The application discusses damascene processes for forming metal lines and vias. While it involves plasma etching of dielectric materials to form trenches and vias, its primary focus is on the material properties and structural integrity of low-k dielectrics. It does not explicitly teach the use of dummy features to mitigate plasma-induced charging damage.
• Potential Anticipation of Claims: This reference is relevant to the damascene process described in the '584 patent (see FIGS. 7-10). However, it does not disclose the deliberate formation of dummy, non-interconnect openings in the mask to create shunt paths during the plasma etch process. The core of claim 1 of the '584 patent is the combination of forming both interconnect and dummy features simultaneously for the purpose of charge dissipation. Cote et al. '538 does not appear to teach this specific combination or its purpose. Therefore, it is unlikely to anticipate the claims of US 7,547,584.

4. U.S. Patent No. 7,176,051 B2 (Chen et al.)

• Full Citation: US Patent 7,176,051 B2, "Method of reducing charging damage to integrated circuits during semiconductor manufacturing"
• Publication Date: February 13, 2007
• Filing Date: May 27, 2005
• Assignee: United Microelectronics Corp.
• Description: This patent is the parent application from which US 7,547,584 B2 claims priority as a continuation-in-part. The disclosure is highly relevant and describes a similar method of reducing charging damage during ion implantation by using an implant mask with dummy openings. Specifically, it focuses on forming LDD (lightly doped drain) regions and discloses exposing a non-active "STI dummy region" during the implantation of a device region to increase the total exposed substrate area and reduce charging.
• Potential Anticipation of Claims: As the parent application, this document contains much of the foundational disclosure. The core concept of adding dummy openings to an implant mask to increase the exposed area and create a shunt path is present. However, the claims of the '584 patent are directed specifically to a method involving a plasma etching process to form interconnect and dummy recessed trenches, which are then filled with conductive material. The '051 patent's claims are focused on the ion implantation steps. While the specification is similar, the claims are directed to different manufacturing processes (plasma etching for interconnects vs. ion implantation for doping). Therefore, the '051 patent would not anticipate the specific method claimed in claim 1 of the '584 patent, which is directed at forming interconnects via plasma etching.

5. U.S. Patent No. 7,259,091 B2 (En et al.)

• Full Citation: US Patent 7,259,091 B2, "Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer"
• Publication Date: August 21, 2007
• Filing Date: July 30, 2004
• Description: En et al. describes a method for forming copper interconnects, focusing on the treatment of the etched dielectric surfaces before depositing the barrier layer and copper. The invention aims to improve the quality of the interface between the dielectric and the barrier metal. It describes plasma treatment steps within the context of a dual damascene process.
• Potential Anticipation of Claims: This reference relates to the general field of copper interconnect formation using damascene processes, which involves plasma etching. However, its inventive concept is centered on surface treatment and passivation, not on the layout of the etch mask to mitigate charge buildup. It does not teach the use of dummy, non-interconnect openings in the mask to create charge dissipation paths. Therefore, En et al. '091 does not anticipate the claims of US 7,547,584.

6. U.S. Patent Application Publication No. 2008/0174022 A1 (Lin et al.)

• Full Citation: US Patent Application Publication 2008/0174022 A1, "Semiconductor device and fabrication method thereof"
• Publication Date: July 24, 2008
• Filing Date: January 22, 2007
• Description: Lin et al. discloses a method for forming a semiconductor device with improved electrical performance by using dummy structures. The dummy structures are described as being formed in a metal layer and are intended to improve the uniformity of subsequent chemical-mechanical polishing (CMP) processes. The application discusses forming a metal interconnection and dummy metal patterns simultaneously.
• Potential Anticipation of Claims: This reference discloses the simultaneous formation of interconnect features and dummy features within a die. However, the stated purpose of these dummy features is to improve CMP planarity, not to reduce charging damage during a preceding plasma etch step. Claim 1 of the '584 patent explicitly states the function of the dummy opening is to "increase an in-die shunt path current flow during said plasma etching process, thereby reducing charge damage". Since Lin et al. '022 teaches the formation of dummy patterns for a different purpose (CMP uniformity), it does not explicitly teach or suggest their use for charge dissipation during etching. Therefore, it is unlikely to anticipate the claims of US 7,547,584.

Obviousness Analysis of U.S. Patent No. 7,547,584

An analysis of U.S. Patent No. 7,547,584 ("the '584 patent") in light of prior art reveals a strong case for obviousness under 35 U.S.C. § 103. The claims of the '584 patent are likely invalid as they represent an obvious combination of known techniques to solve a well-documented problem in the field of semiconductor manufacturing.

Summary of the Invention

The '584 patent, titled "Method of reducing charging damage to integrated circuits during semiconductor manufacturing," addresses the issue of electrical charge accumulation on a semiconductor wafer during processes like plasma etching and ion implantation. This charge buildup can damage sensitive components, particularly the thin gate oxides of transistors.

The core of the invention is to create additional "dummy" or non-functional patterns on the integrated circuit die. These dummy patterns, which are etched or implanted at the same time as the active device features, increase the exposed surface area of the wafer. This provides additional pathways for electrical charge to dissipate, preventing localized buildup and subsequent damage. The patent describes this for both creating metal interconnects (a dual damascene process) and for ion implantation steps (such as forming lightly doped drains or LDDs).

Analysis of Key Claims

Claim 1 is representative of the a key embodiment of the invention. It describes a method for reducing charging damage during plasma etching by:

1. Providing a semiconductor substrate with a dielectric layer.
2. Forming a mask over the dielectric layer that includes both an "interconnect opening" for the actual circuit wiring and a "dummy, non-interconnect opening" within the same die.
3. Performing plasma etching through both types of openings to create trenches.
4. Filling the trenches with a conductive material to form both the functional interconnect and a non-functional "dummy feature."
5. Stating the purpose: The dummy feature increases the "in-die shunt path current flow during said plasma etching process, thereby reducing charge damage."

Primary Prior Art and Motivation to Combine

A person of ordinary skill in the art (POSITA) at the time of the invention (priority date of May 27, 2005) would have found the invention to be an obvious solution to the known problem of charging damage. The primary prior art reference for this analysis is U.S. Patent No. 5,998,282 to Lukaszek ("Lukaszek").

1. Lukaszek (US 5,998,282 A): The Problem and a Partial Solution

The '584 patent itself cites Lukaszek as prior art, acknowledging that Lukaszek addresses the same problem. Lukaszek teaches a method for "reducing charging damage to integrated circuits during ion implantation and plasma processing." The core concept in Lukaszek is to create "shunt paths" for electrical current to flow to and from the wafer substrate, thereby preventing charge accumulation on isolated conductive features like transistor gates.

Crucially, Lukaszek proposes creating these shunt paths by processing the scribe lanes—the non-functional areas between individual dies on a wafer. The '584 patent's background section notes that Lukaszek "reveals that increasing shunt path current flow within the integrated circuit die is difficult due to circuit layout constraints." This statement is key: Lukaszek identified the problem and a solution principle (shunt paths) but suggested that implementing it within the die was challenging.

2. General Knowledge: Dummy Features for Process Uniformity

At the time of the invention, the use of "dummy" or "fill" patterns within an integrated circuit die was a standard and well-understood practice. These non-functional features were added to layouts to ensure a more uniform density of features across the die. This uniformity is critical for processes like Chemical Mechanical Planarization (CMP) and plasma etching, where "loading effects" (variations in etch rate based on the density of features) can degrade manufacturing yield. The '584 patent itself alludes to this, mentioning "STI dummy patterns used to reduce loading effect during the fabrication of STI" (Column 4, Lines 1-3).

3. The Obvious Combination

A POSITA, aware of the charging problem and Lukaszek's shunt path solution, would have been motivated to find more effective ways to implement such paths. While Lukaszek focused on scribe lanes, a skilled artisan would recognize that the most effective place to dissipate a localized charge buildup is near its source—within the die itself.

The '584 patent's claimed invention is essentially the application of Lukaszek's charge-dissipating shunt path concept to the well-known practice of using in-die dummy structures. The motivation to combine these two known elements is straightforward:

• Problem: Plasma etching and ion implantation cause damaging charge buildup.
• Known Solution Principle (Lukaszek): Create shunt paths to dissipate the charge.
• Known Technique (Industry Practice): Add dummy features within the die to improve process uniformity.

A POSITA would have recognized that the existing practice of adding dummy metal or polysilicon features for CMP or etch uniformity could be leveraged to solve the charging problem. By simply modifying the masks to include these dummy features during the etching or implantation steps, one could create precisely the in-die shunt paths Lukaszek theorized were "difficult" but desirable. This would be seen not as a new invention, but as a practical and obvious implementation of a known solution using standard industry techniques. The fact that these dummy features already existed on many designs for other purposes makes this combination particularly compelling.

Conclusion:

The method described in US 7,547,584 would have been obvious to a person of ordinary skill in the art. The patent combines the known concept of using shunt paths to mitigate charging damage (taught by Lukaszek) with the standard industry practice of using in-die dummy features for process control. The motivation to combine these elements is clear: to apply the charge dissipation principle directly within the active area of the die, where it is most needed, by leveraging existing and well-understood layout and masking techniques. Therefore, the claims of the '584 patent are likely invalid under 35 U.S.C. § 103.

Patent Term and Family Data for U.S. Patent No. 7,547,584

Analysis Date: May 13, 2026

This section details the patent term adjustments, related applications, and the projected expiration date for U.S. Patent No. 7,547,584 B2.

• Patent Term Adjustment (PTA) / Patent Term Extension (PTE):
  There is no information available in the provided patent documentation regarding any Patent Term Adjustments (PTA) or Patent Term Extensions (PTE). The listed expiration date appears to be calculated from the priority date.

• Continuation and Related Application History:
  This patent is a continuation-in-part of U.S. patent application Ser. No. 10/908,815, which was filed on May 27, 2005, and later issued as U.S. Patent No. 7,176,051. The subject patent, US 7,547,584 B2, claims priority to this earlier application.

• Patent Family:

  • Parent Application: US 10/908,815 (now US Patent 7,176,051), filed May 27, 2005.
  • This Application: US 11/560,831, filed November 16, 2006 (issued as US 7,547,584 B2).

• Projected Expiration Date:
  The legal status of the patent is listed as "Expired - Lifetime" with an adjusted expiration date of October 24, 2025. This date is based on the 20-year term from the earliest non-provisional priority date of May 27, 2005, established by the parent application (US 10/908,815). The expiration date appears to have been adjusted from the standard 20-year term, though the specific details of the adjustment are not provided in the source document.

Defensive Disclosure: US7547584B2

Publication Date: May 13, 2026
Reference Patent: US 7,547,584 B2 ("the '584 patent")
Subject: Advanced Methods for Mitigating Process-Induced Charging Damage in Micro and Nano-Fabrication

This document discloses a series of methods, materials, and applications that build upon, extend, or modify the core inventive concepts described in US Patent 7,547,584 B2. The purpose of this disclosure is to place these derivative concepts into the public domain, thereby establishing them as prior art.

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Analysis of Core Claim (based on Claim 1 of US 7,547,584)

The foundational concept involves creating dummy, non-interconnect openings in a mask alongside functional interconnect openings. During plasma etching, these dummy openings form recessed features that are subsequently filled with a conductive material. These dummy features act as in-die shunt paths, dissipating accumulated charge and preventing damage to active circuit elements. The following derivative inventions expand upon this principle.

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Axis 1: Material & Component Substitution

Derivative 1.1: Graphene-Based Charge Dissipation Grid

• Enabling Description: Instead of using standard conductive materials like copper or aluminum, the dummy recessed trenches are filled with a graphene-based conductive ink or grown via Chemical Vapor Deposition (CVD). Graphene's exceptional carrier mobility and atomic-scale thickness allow for the creation of a highly efficient, transparent, and minimally intrusive charge dissipation grid. The interconnect features are filled with a traditional metal (e.g., copper), while the dummy features form a continuous or semi-continuous graphene mesh. This mesh can be designed to have a specific sheet resistance to optimize the charge dissipation rate for a given plasma process, balancing discharge speed with the prevention of eddy currents during high-frequency operation.
• Mermaid Diagram:

  graph TD
      A[Start: Wafer with Dielectric Layer] --> B{Form Mask with Interconnect & Graphene Grid Patterns};
      B --> C{Plasma Etch Dielectric};
      C --> D[Selectively Deposit Graphene in Dummy Trenches];
      D --> E[Fill Interconnect Trenches with Copper/Tungsten];
      E --> F[Planarize Surface (CMP)];
      F --> G[Charge Dissipation via Graphene Grid];
      G --> H(End: Protected IC);
  

Derivative 1.2: Sacrificial Phase-Change Material in Dummy Vias

• Enabling Description: This method utilizes a phase-change material (PCM), such as a chalcogenide glass (e.g., Ge₂Sb₂Te₅), to fill the dummy recessed features. The PCM is deposited in its amorphous, high-resistance state. During a plasma process, localized charge accumulation and associated heating cause the PCM in the dummy features to crystallize into a low-resistance state, rapidly creating a conductive path to dissipate the charge. After the plasma process, a brief thermal anneal can reset the PCM to its high-resistance state, rendering the dummy features electrically invisible during normal device operation. This creates a "dynamic" or "on-demand" charge dissipation system.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Amorphous_High_R: Initial State
      Amorphous_High_R --> Crystalline_Low_R: Event: Plasma Charge/Heat Buildup
      Crystalline_Low_R --> Amorphous_High_R: Event: Post-Process Thermal Anneal
      Crystalline_Low_R: Charge Dissipation Active
      Amorphous_High_R: Electrically Dormant
  

Derivative 1.3: Porous Low-k Dielectric with In-Situ Conductive Pore Sealing

• Enabling Description: This method applies to processes using porous low-k dielectrics (e.g., SiOCH). The mask defines both interconnect trenches and dummy "zones" rather than discrete trenches. During the plasma etch, the exposed porous dielectric in the dummy zones is intentionally modified. Following the etch, a selective electroless plating or atomic layer deposition (ALD) process is used to deposit a conductive material (e.g., Cobalt, Ruthenium) that preferentially fills the pores of the dielectric within these dummy zones, without creating a solid plug. This transforms the porous insulator into a localized, semi-conductive or "leaky" dielectric, providing a distributed shunt path for charge to bleed off to the substrate. The interconnect trenches are then filled as usual.
• Mermaid Diagram:

  sequenceDiagram
      participant Wafer
      participant PlasmaEtcher
      participant PlatingBath
      Wafer->>PlasmaEtcher: Enter Etch Chamber
      PlasmaEtcher->>Wafer: Etch Interconnect and Dummy Zones
      Wafer->>PlatingBath: Immerse in Electroless Solution
      PlatingBath->>Wafer: Selectively Plate Conductive Material into Porous Dielectric in Dummy Zones
      Wafer-->>Wafer: Interconnect Trench Fill & CMP
  

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Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Plasma Etching Charge Control

• Enabling Description: This method adapts the '584 patent for cryogenic etching processes (<-100°C). At these temperatures, the resistivity of the semiconductor substrate increases significantly. To compensate, the dummy features are designed with much larger surface areas and are filled with a superconducting material (e.g., Niobium Nitride). The mask pattern for the dummy features is a dense, web-like structure covering 25-50% of the non-active die area. This extensive network ensures that a low-resistance discharge path to the cryo-cooled wafer chuck (ground) is maintained, preventing charge accumulation on the highly resistive substrate surface.
• Mermaid Diagram:

  graph TD
      subgraph Cryo-Chamber [-120°C]
          A[Wafer on Cryo-Chuck] --> B{Form Mask w/ Large-Area Dummy Web};
          B --> C{Cryo-Plasma Etch};
          C --> D[Charge Accumulates];
          D -- Dissipates via --> E(Superconducting NbN Dummy Web);
          E --> F[Ground Path via Chuck];
      end
      F --> G[Completed Etch];
  

Derivative 2.2: Micro-scale Atmospheric Plasma Jet Etching

• Enabling Description: This method applies the concept to atmospheric-pressure plasma jet systems used for large-area flexible electronics. The substrate is a flexible polymer (e.g., PET, Kapton). Dummy features are not trenches but rather surface-level conductive pads (e.g., screen-printed silver ink) placed strategically around the active device areas. As the plasma jet scans across the surface, these dummy pads act as localized charge sinks, intercepting ions and electrons that would otherwise build up on the insulating polymer substrate. The pads are interconnected by a thin, grounded conductive grid, providing a global discharge pathway across the large, flexible surface.
• Mermaid Diagram:

  flowchart LR
      subgraph Flexible Substrate
          A(Active Device Area 1)
          B(Active Device Area 2)
          C(Active Device Area 3)
          D1[Dummy Pad]
          D2[Dummy Pad]
          D3[Dummy Pad]
          D4[Dummy Pad]
          G[[Ground Plane]]
          A --- D1
          B --- D2 & D3
          C --- D4
          D1 --- G
          D2 --- G
          D3 --- G
          D4 --- G
      end
      PJ(Plasma Jet) -- Scans --> Substrate
  

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Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - MEMS Gyroscope & Accelerometer Fabrication

• Enabling Description: In the fabrication of high-precision MEMS gyroscopes and accelerometers, plasma etching processes are used to define microscopic moving masses and sensing combs. Uncontrolled charge buildup can cause these delicate structures to deflect and "stick" to adjacent surfaces (stiction), a primary failure mode. This invention applies the '584 method by creating an array of dummy, grounded trenches within the silicon substrate surrounding the active MEMS device. These trenches are etched and filled with a conductive polysilicon during the same process steps that form the device's electrical interconnects. This provides a localized equipotential plane during the high-aspect-ratio deep reactive-ion etching (DRIE) process, preventing electrostatic-induced stiction and improving device yield and reliability for aerospace applications.
• Mermaid Diagram:

  graph TD
      subgraph MEMS Die
          A[Proof Mass]
          B[Sensing Combs]
          C[Actuation Combs]
          D{Dummy Polysilicon-Filled Trenches}
      end
  
      P[Plasma Etch Process] -->|Charge Buildup| A & B & C
      P -->|Charge Dissipation| D
      D --> E[Substrate Ground]
  
      style D fill:#f9f,stroke:#333,stroke-width:2px
  

Derivative 3.2: Agricultural Technology (AgTech) - Microfluidic Soil Sensor Array

• Enabling Description: The method is adapted for fabricating microfluidic "lab-on-a-chip" devices for real-time soil analysis. These devices are made from polymers like PDMS or glass, which are highly insulating. Plasma etching is used to create micro-channels and electrode patterns. To prevent charge-induced damage to the delicate electrode sensors (e.g., ion-selective electrodes), dummy channels are etched alongside the functional fluidic channels. These dummy channels are then filled with an ionic conductive hydrogel that is connected to a common ground point on the chip's perimeter. During plasma bonding or surface treatment, this hydrogel-filled network safely shunts away static charge, preserving the integrity of the sensing electrodes.
• Mermaid Diagram:

  graph TD
      subgraph Soil Sensor Chip
          direction LR
          A[Sample Inlet] --> B(Microfluidic Channel);
          B --> C{Sensor Electrodes};
          B -- Proximity --> D(Dummy Channel - Hydrogel Filled);
          C -- Electrical Field --> D;
          D -- Shunts Charge --> E[Ground Contact];
          A --> D;
      end
  

Derivative 3.3: Consumer Electronics - Flexible OLED Display Manufacturing

• Enabling Description: In the roll-to-roll manufacturing of flexible OLED displays, thin-film transistor (TFT) backplanes are patterned on polymer substrates. Plasma-enhanced chemical vapor deposition (PECVD) and etching are key steps that can induce significant charging. The invention is applied by patterning a grid of dummy metal lines (using the same metal layer as the TFT source/drain contacts, e.g., aluminum or copper) in the non-pixel areas. These dummy lines are not part of the active pixel-driving circuitry but are connected to a grounding bar at the edge of the substrate roll. During plasma processes, this grid acts as a Faraday cage, shielding the sensitive TFTs from charge build-up and preventing threshold voltage shifts or gate oxide breakdown, thus improving display uniformity and lifespan.
• Mermaid Diagram:

  graph LR
      subgraph Flexible Display Substrate
          Pixel1[TFT & OLED]
          Pixel2[TFT & OLED]
          Pixel3[TFT & OLED]
          DummyGrid(Dummy Metal Grid)
      end
      
      Plasma[Plasma Processing Step]
      Plasma -- Generates Charge --> Substrate
      Substrate -- Charge Captured By --> DummyGrid
      DummyGrid --> Ground[Ground Connection]
      
      style DummyGrid fill:#ddd,stroke:#333,stroke-dasharray: 5 5
  

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Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Optimized Dummy Feature Generation

• Enabling Description: The fixed-pattern dummy structures of the '584 patent are replaced by a dynamic, AI-driven design methodology. A machine learning model (e.g., a Graph Neural Network) is trained on a dataset of IC layouts and corresponding wafer-level charge measurement data. For a new chip design (GDSII file), the model predicts the areas of highest probable charge accumulation during critical plasma etch steps. It then automatically generates an optimized, non-uniform pattern of dummy openings, varying their size, density, and proximity to sensitive gates, to create the most efficient shunt paths. This "charge-aware" layout is added to the mask set, creating a bespoke charge protection scheme for each unique IC design, superior to a one-size-fits-all approach.
• Mermaid Diagram:

  sequenceDiagram
      participant Designer
      participant AI_Model as AI Layout Optimizer
      participant Mask_Fab
      participant Plasma_Etcher
      Designer->>AI_Model: Submit GDSII Layout
      AI_Model->>AI_Model: Predict Charge Hotspots
      AI_Model->>AI_Model: Generate Optimal Dummy Pattern
      AI_Model->>Designer: Return Modified GDSII
      Designer->>Mask_Fab: Send Final Layout
      Mask_Fab->>Plasma_Etcher: Provide Fabricated Mask
      Plasma_Etcher->>Plasma_Etcher: Process Wafer with Optimized Charge Protection
  

Derivative 4.2: IoT-Enabled Real-Time Plasma Process Control

• Enabling Description: The dummy features are designed not just for passive charge dissipation but as active IoT sensors. A subset of the dummy structures are fabricated as charge-collection plates (antennas) connected to simple ring oscillator circuits located in the wafer's scribe lines. The oscillation frequency changes in direct proportion to the collected charge potential. An external, non-contact RF probe reads these frequencies during the plasma process, providing real-time, in-situ feedback on the wafer's surface charge distribution. This data stream is fed back to the plasma tool's controller, which can dynamically adjust parameters like RF power, gas pressure, or bias voltage to minimize charging on the fly, moving from a static damage prevention method to an active feedback control loop.
• Mermaid Diagram:

  graph TD
      A[Plasma Chamber] -- Generates Plasma --> B[Semiconductor Wafer];
      B -- Charge Accumulates on --> C{Dummy Antenna Structures};
      C -- Modulates Frequency --> D[Ring Oscillator Sensor in Scribe Line];
      D -- Emits RF Signal --> E(External RF Probe);
      E -- Feeds Data --> F[Process Controller];
      F -- Adjusts Parameters --> A;
      subgraph On-Wafer
          C
          D
      end
      subgraph Off-Wafer
          E
          F
      end
  

Derivative 4.3: Blockchain-Verified Manufacturing Process for High-Reliability ICs

• Enabling Description: For critical applications (e.g., automotive, defense), the integrity of the charge damage mitigation process is paramount. Each wafer is given a unique digital identity on a distributed ledger (blockchain). During manufacturing, data from the IoT charge sensors (as described in 4.2) is timestamped and written to the wafer's blockchain record as an immutable transaction. This creates a verifiable "birth certificate" for each die, proving that it was processed within safe charging limits. Customers can later query the blockchain to verify the manufacturing provenance and quality control of each specific chip, ensuring it wasn't exposed to potentially damaging electrostatic discharge events during fabrication.
• Mermaid Diagram:

  flowchart LR
      subgraph Fab
          Wafer[Wafer with Unique ID] --> Etch(Plasma Etch Step)
          Sensor[IoT Charge Sensor] -- Data --> Controller(Process Controller)
          Controller -- Log Data --> Blockchain(Append to Wafer's Block)
      end
      subgraph Supply_Chain
          Fab --> Distributor
          Distributor --> OEM(End Customer)
          OEM -- Scans Chip ID --> Query(Query Blockchain)
          Query --> Blockchain
          Blockchain -- Returns Process History --> OEM
      end
  

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Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Self-Destructing Charge-Fuses for Process Characterization

• Enabling Description: Instead of preventing damage, this method uses dummy features to precisely detect when and where damaging charge levels occur. The "dummy features" are designed as arrays of microscopic, electrically isolated fuses. Each fuse consists of a thin polysilicon gate over a deliberately thinned gate oxide. The "antenna ratio" (ratio of conductive collector area to gate area) of each fuse is varied systematically across the array. During a plasma process, when the local charge potential exceeds the breakdown voltage of a fuse's thin oxide, it ruptures permanently. By inspecting which fuses in the array have been blown after processing, engineers can create a detailed, high-resolution map of the wafer's charging profile. This diagnostic structure allows for rapid qualification of new plasma equipment and processes.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Intact
      Intact: V_collected < V_breakdown
      Ruptured: V_collected >= V_breakdown
      
      Intact --> Ruptured: Plasma Charging Event Exceeds Threshold
      
      note right of Ruptured
        Fuse is permanently open.
        Location and antenna ratio provide
        process characterization data.
      end note
  

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Combination with Open-Source Standards

1. Integration with KiCad EDA Suite: A plugin for the KiCad PCB layout software is developed to apply this charge-mitigation principle to printed circuit board fabrication. The plugin's script automatically populates unused board areas with a grid of non-functional "dummy pads" and "thieving traces" connected to the ground plane. This increases the exposed copper percentage during the plasma desmear and etch processes used in multilayer PCB manufacturing, ensuring uniform etching and preventing charge-induced damage to sensitive surface-mount components, leveraging the open-source KiCad platform for widespread adoption.

2. Application with RISC-V SoC Designs: A reference implementation is provided for a System-on-Chip (SoC) based on the open-source RISC-V instruction set architecture. The GDSII layout files for a standard RISC-V core (e.g., Rocket or BOOM) are modified to include a standardized library of dummy STI (Shallow Trench Isolation) and metal fill structures as described in the '584 patent. This "charge-hardened" open-source IP can be freely used by designers, ensuring that even low-cost or experimental RISC-V implementations are protected from common plasma-induced manufacturing defects without requiring proprietary layout solutions.

3. Use with Linux-based Equipment Control (EPICS): The IoT-based real-time charge monitoring system (Derivative 4.2) is integrated with the Experimental Physics and Industrial Control System (EPICS), an open-source framework used for controlling large-scale scientific and industrial equipment. A specific EPICS device driver and control module are developed to read data from the wafer charge sensors and interface with the mass flow controllers (MFCs) and RF generators of a plasma etcher. This allows any fabrication facility using the EPICS standard to implement a sophisticated, closed-loop charge control system using off-the-shelf hardware and open-source software, democratizing access to advanced process control.