Prior art

Prior Art Analysis for U.S. Patent No. 7,547,584

This analysis details the prior art cited in the prosecution history of U.S. Patent No. 7,547,584. Each cited reference is examined for its potential to anticipate the claims of the '584 patent under 35 U.S.C. § 102.

Based on the patent's file wrapper, the following documents were cited as prior art during the examination process:

1. U.S. Patent No. 5,998,282 (Lukaszek)

• Full Citation: US Patent 5,998,282, "Method of reducing charging damage to integrated circuits in ion implant and plasma-based integrated circuit process equipment"
• Publication Date: December 7, 1999
• Filing Date: October 21, 1997
• Description: Lukaszek discloses a method to mitigate charging damage during ion implantation and plasma processing by modifying the scribe lanes between integrated circuit dies. It teaches creating conductive paths or "shunt paths" within these scribe lanes to dissipate accumulated electrical charge to the substrate, thereby protecting the active circuit areas on the die. The patent explicitly mentions that creating such shunt paths within the integrated circuit die itself is difficult due to layout constraints.
• Potential Anticipation of Claims: Lukaszek teaches the general concept of using shunt paths to mitigate charging damage. However, it focuses on modifying the scribe lanes, which are the non-functional areas between dies, rather than creating dummy features within the die area itself as claimed in the '584 patent. The method described in claim 1 of US 7,547,584 specifies forming "dummy, non-interconnect" features within each said integrated circuit die. Lukaszek's disclosure of creating shunt paths in the scribe lanes does not directly anticipate this specific in-die implementation. Therefore, it is unlikely that Lukaszek '282 anticipates the claims of US 7,547,584 on its own.

2. U.S. Patent No. 6,521,487 B1 (Tu et al.)

• Full Citation: US Patent 6,521,487 B1, "Method for making a thyristor"
• Publication Date: February 18, 2003
• Filing Date: December 5, 2001
• Assignee: United Microelectronics Corp.
• Description: Tu et al. describes a method for fabricating a thyristor, a type of semiconductor device. The process involves multiple ion implantation steps using photoresist masks to define P-wells, N-wells, and various doped regions. The focus is on the specific structure and formation of the thyristor and does not address the problem of charging damage during these implantation steps, nor does it teach the deliberate creation of dummy openings in the mask to increase the exposed surface area for charge dissipation.
• Potential Anticipation of Claims: This reference is cited as general background for semiconductor fabrication processes involving ion implantation and masking. It does not appear to disclose the key inventive concept of the '584 patent, which is the use of dummy openings in a mask to create a shunt path for charge dissipation during plasma etching or ion implantation. It does not teach forming dummy, non-interconnect openings or features within the die to reduce charging damage. Therefore, Tu et al. '487 does not anticipate the claims of US 7,547,584.

3. U.S. Patent Application Publication No. 2006/0006538 A1 (Cote et al.)

• Full Citation: US Patent Application Publication 2006/0006538 A1, "Extreme low-K interconnect structure and method"
• Publication Date: January 12, 2006
• Filing Date: July 2, 2004
• Description: Cote et al. describes a method for creating interconnect structures using low-dielectric constant (low-k) materials. It addresses the challenges of integrating these fragile materials, including preventing damage during processing. The application discusses damascene processes for forming metal lines and vias. While it involves plasma etching of dielectric materials to form trenches and vias, its primary focus is on the material properties and structural integrity of low-k dielectrics. It does not explicitly teach the use of dummy features to mitigate plasma-induced charging damage.
• Potential Anticipation of Claims: This reference is relevant to the damascene process described in the '584 patent (see FIGS. 7-10). However, it does not disclose the deliberate formation of dummy, non-interconnect openings in the mask to create shunt paths during the plasma etch process. The core of claim 1 of the '584 patent is the combination of forming both interconnect and dummy features simultaneously for the purpose of charge dissipation. Cote et al. '538 does not appear to teach this specific combination or its purpose. Therefore, it is unlikely to anticipate the claims of US 7,547,584.

4. U.S. Patent No. 7,176,051 B2 (Chen et al.)

• Full Citation: US Patent 7,176,051 B2, "Method of reducing charging damage to integrated circuits during semiconductor manufacturing"
• Publication Date: February 13, 2007
• Filing Date: May 27, 2005
• Assignee: United Microelectronics Corp.
• Description: This patent is the parent application from which US 7,547,584 B2 claims priority as a continuation-in-part. The disclosure is highly relevant and describes a similar method of reducing charging damage during ion implantation by using an implant mask with dummy openings. Specifically, it focuses on forming LDD (lightly doped drain) regions and discloses exposing a non-active "STI dummy region" during the implantation of a device region to increase the total exposed substrate area and reduce charging.
• Potential Anticipation of Claims: As the parent application, this document contains much of the foundational disclosure. The core concept of adding dummy openings to an implant mask to increase the exposed area and create a shunt path is present. However, the claims of the '584 patent are directed specifically to a method involving a plasma etching process to form interconnect and dummy recessed trenches, which are then filled with conductive material. The '051 patent's claims are focused on the ion implantation steps. While the specification is similar, the claims are directed to different manufacturing processes (plasma etching for interconnects vs. ion implantation for doping). Therefore, the '051 patent would not anticipate the specific method claimed in claim 1 of the '584 patent, which is directed at forming interconnects via plasma etching.

5. U.S. Patent No. 7,259,091 B2 (En et al.)

• Full Citation: US Patent 7,259,091 B2, "Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer"
• Publication Date: August 21, 2007
• Filing Date: July 30, 2004
• Description: En et al. describes a method for forming copper interconnects, focusing on the treatment of the etched dielectric surfaces before depositing the barrier layer and copper. The invention aims to improve the quality of the interface between the dielectric and the barrier metal. It describes plasma treatment steps within the context of a dual damascene process.
• Potential Anticipation of Claims: This reference relates to the general field of copper interconnect formation using damascene processes, which involves plasma etching. However, its inventive concept is centered on surface treatment and passivation, not on the layout of the etch mask to mitigate charge buildup. It does not teach the use of dummy, non-interconnect openings in the mask to create charge dissipation paths. Therefore, En et al. '091 does not anticipate the claims of US 7,547,584.

6. U.S. Patent Application Publication No. 2008/0174022 A1 (Lin et al.)

• Full Citation: US Patent Application Publication 2008/0174022 A1, "Semiconductor device and fabrication method thereof"
• Publication Date: July 24, 2008
• Filing Date: January 22, 2007
• Description: Lin et al. discloses a method for forming a semiconductor device with improved electrical performance by using dummy structures. The dummy structures are described as being formed in a metal layer and are intended to improve the uniformity of subsequent chemical-mechanical polishing (CMP) processes. The application discusses forming a metal interconnection and dummy metal patterns simultaneously.
• Potential Anticipation of Claims: This reference discloses the simultaneous formation of interconnect features and dummy features within a die. However, the stated purpose of these dummy features is to improve CMP planarity, not to reduce charging damage during a preceding plasma etch step. Claim 1 of the '584 patent explicitly states the function of the dummy opening is to "increase an in-die shunt path current flow during said plasma etching process, thereby reducing charge damage". Since Lin et al. '022 teaches the formation of dummy patterns for a different purpose (CMP uniformity), it does not explicitly teach or suggest their use for charge dissipation during etching. Therefore, it is unlikely to anticipate the claims of US 7,547,584.