Derivative works — US Patent 7547584

Defensive Disclosure: US7547584B2

Publication Date: May 13, 2026
Reference Patent: US 7,547,584 B2 ("the '584 patent")
Subject: Advanced Methods for Mitigating Process-Induced Charging Damage in Micro and Nano-Fabrication

This document discloses a series of methods, materials, and applications that build upon, extend, or modify the core inventive concepts described in US Patent 7,547,584 B2. The purpose of this disclosure is to place these derivative concepts into the public domain, thereby establishing them as prior art.

Analysis of Core Claim (based on Claim 1 of US 7,547,584)

The foundational concept involves creating dummy, non-interconnect openings in a mask alongside functional interconnect openings. During plasma etching, these dummy openings form recessed features that are subsequently filled with a conductive material. These dummy features act as in-die shunt paths, dissipating accumulated charge and preventing damage to active circuit elements. The following derivative inventions expand upon this principle.

Axis 1: Material & Component Substitution

Derivative 1.1: Graphene-Based Charge Dissipation Grid

Enabling Description: Instead of using standard conductive materials like copper or aluminum, the dummy recessed trenches are filled with a graphene-based conductive ink or grown via Chemical Vapor Deposition (CVD). Graphene's exceptional carrier mobility and atomic-scale thickness allow for the creation of a highly efficient, transparent, and minimally intrusive charge dissipation grid. The interconnect features are filled with a traditional metal (e.g., copper), while the dummy features form a continuous or semi-continuous graphene mesh. This mesh can be designed to have a specific sheet resistance to optimize the charge dissipation rate for a given plasma process, balancing discharge speed with the prevention of eddy currents during high-frequency operation.

Mermaid Diagram:

graph TD
    A[Start: Wafer with Dielectric Layer] --> B{Form Mask with Interconnect & Graphene Grid Patterns};
    B --> C{Plasma Etch Dielectric};
    C --> D[Selectively Deposit Graphene in Dummy Trenches];
    D --> E[Fill Interconnect Trenches with Copper/Tungsten];
    E --> F[Planarize Surface (CMP)];
    F --> G[Charge Dissipation via Graphene Grid];
    G --> H(End: Protected IC);

Derivative 1.2: Sacrificial Phase-Change Material in Dummy Vias

Enabling Description: This method utilizes a phase-change material (PCM), such as a chalcogenide glass (e.g., Ge₂Sb₂Te₅), to fill the dummy recessed features. The PCM is deposited in its amorphous, high-resistance state. During a plasma process, localized charge accumulation and associated heating cause the PCM in the dummy features to crystallize into a low-resistance state, rapidly creating a conductive path to dissipate the charge. After the plasma process, a brief thermal anneal can reset the PCM to its high-resistance state, rendering the dummy features electrically invisible during normal device operation. This creates a "dynamic" or "on-demand" charge dissipation system.

Mermaid Diagram:

stateDiagram-v2
    [*] --> Amorphous_High_R: Initial State
    Amorphous_High_R --> Crystalline_Low_R: Event: Plasma Charge/Heat Buildup
    Crystalline_Low_R --> Amorphous_High_R: Event: Post-Process Thermal Anneal
    Crystalline_Low_R: Charge Dissipation Active
    Amorphous_High_R: Electrically Dormant

Derivative 1.3: Porous Low-k Dielectric with In-Situ Conductive Pore Sealing

Enabling Description: This method applies to processes using porous low-k dielectrics (e.g., SiOCH). The mask defines both interconnect trenches and dummy "zones" rather than discrete trenches. During the plasma etch, the exposed porous dielectric in the dummy zones is intentionally modified. Following the etch, a selective electroless plating or atomic layer deposition (ALD) process is used to deposit a conductive material (e.g., Cobalt, Ruthenium) that preferentially fills the pores of the dielectric within these dummy zones, without creating a solid plug. This transforms the porous insulator into a localized, semi-conductive or "leaky" dielectric, providing a distributed shunt path for charge to bleed off to the substrate. The interconnect trenches are then filled as usual.

Mermaid Diagram:

sequenceDiagram
    participant Wafer
    participant PlasmaEtcher
    participant PlatingBath
    Wafer->>PlasmaEtcher: Enter Etch Chamber
    PlasmaEtcher->>Wafer: Etch Interconnect and Dummy Zones
    Wafer->>PlatingBath: Immerse in Electroless Solution
    PlatingBath->>Wafer: Selectively Plate Conductive Material into Porous Dielectric in Dummy Zones
    Wafer-->>Wafer: Interconnect Trench Fill & CMP

Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Plasma Etching Charge Control

Enabling Description: This method adapts the '584 patent for cryogenic etching processes (<-100°C). At these temperatures, the resistivity of the semiconductor substrate increases significantly. To compensate, the dummy features are designed with much larger surface areas and are filled with a superconducting material (e.g., Niobium Nitride). The mask pattern for the dummy features is a dense, web-like structure covering 25-50% of the non-active die area. This extensive network ensures that a low-resistance discharge path to the cryo-cooled wafer chuck (ground) is maintained, preventing charge accumulation on the highly resistive substrate surface.

Mermaid Diagram:

graph TD
    subgraph Cryo-Chamber [-120°C]
        A[Wafer on Cryo-Chuck] --> B{Form Mask w/ Large-Area Dummy Web};
        B --> C{Cryo-Plasma Etch};
        C --> D[Charge Accumulates];
        D -- Dissipates via --> E(Superconducting NbN Dummy Web);
        E --> F[Ground Path via Chuck];
    end
    F --> G[Completed Etch];

Derivative 2.2: Micro-scale Atmospheric Plasma Jet Etching

Enabling Description: This method applies the concept to atmospheric-pressure plasma jet systems used for large-area flexible electronics. The substrate is a flexible polymer (e.g., PET, Kapton). Dummy features are not trenches but rather surface-level conductive pads (e.g., screen-printed silver ink) placed strategically around the active device areas. As the plasma jet scans across the surface, these dummy pads act as localized charge sinks, intercepting ions and electrons that would otherwise build up on the insulating polymer substrate. The pads are interconnected by a thin, grounded conductive grid, providing a global discharge pathway across the large, flexible surface.

Mermaid Diagram:

flowchart LR
    subgraph Flexible Substrate
        A(Active Device Area 1)
        B(Active Device Area 2)
        C(Active Device Area 3)
        D1[Dummy Pad]
        D2[Dummy Pad]
        D3[Dummy Pad]
        D4[Dummy Pad]
        G[[Ground Plane]]
        A --- D1
        B --- D2 & D3
        C --- D4
        D1 --- G
        D2 --- G
        D3 --- G
        D4 --- G
    end
    PJ(Plasma Jet) -- Scans --> Substrate

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - MEMS Gyroscope & Accelerometer Fabrication

Enabling Description: In the fabrication of high-precision MEMS gyroscopes and accelerometers, plasma etching processes are used to define microscopic moving masses and sensing combs. Uncontrolled charge buildup can cause these delicate structures to deflect and "stick" to adjacent surfaces (stiction), a primary failure mode. This invention applies the '584 method by creating an array of dummy, grounded trenches within the silicon substrate surrounding the active MEMS device. These trenches are etched and filled with a conductive polysilicon during the same process steps that form the device's electrical interconnects. This provides a localized equipotential plane during the high-aspect-ratio deep reactive-ion etching (DRIE) process, preventing electrostatic-induced stiction and improving device yield and reliability for aerospace applications.

Mermaid Diagram:

graph TD
    subgraph MEMS Die
        A[Proof Mass]
        B[Sensing Combs]
        C[Actuation Combs]
        D{Dummy Polysilicon-Filled Trenches}
    end

    P[Plasma Etch Process] -->|Charge Buildup| A & B & C
    P -->|Charge Dissipation| D
    D --> E[Substrate Ground]

    style D fill:#f9f,stroke:#333,stroke-width:2px

Derivative 3.2: Agricultural Technology (AgTech) - Microfluidic Soil Sensor Array

Enabling Description: The method is adapted for fabricating microfluidic "lab-on-a-chip" devices for real-time soil analysis. These devices are made from polymers like PDMS or glass, which are highly insulating. Plasma etching is used to create micro-channels and electrode patterns. To prevent charge-induced damage to the delicate electrode sensors (e.g., ion-selective electrodes), dummy channels are etched alongside the functional fluidic channels. These dummy channels are then filled with an ionic conductive hydrogel that is connected to a common ground point on the chip's perimeter. During plasma bonding or surface treatment, this hydrogel-filled network safely shunts away static charge, preserving the integrity of the sensing electrodes.

Mermaid Diagram:

graph TD
    subgraph Soil Sensor Chip
        direction LR
        A[Sample Inlet] --> B(Microfluidic Channel);
        B --> C{Sensor Electrodes};
        B -- Proximity --> D(Dummy Channel - Hydrogel Filled);
        C -- Electrical Field --> D;
        D -- Shunts Charge --> E[Ground Contact];
        A --> D;
    end

Derivative 3.3: Consumer Electronics - Flexible OLED Display Manufacturing

Enabling Description: In the roll-to-roll manufacturing of flexible OLED displays, thin-film transistor (TFT) backplanes are patterned on polymer substrates. Plasma-enhanced chemical vapor deposition (PECVD) and etching are key steps that can induce significant charging. The invention is applied by patterning a grid of dummy metal lines (using the same metal layer as the TFT source/drain contacts, e.g., aluminum or copper) in the non-pixel areas. These dummy lines are not part of the active pixel-driving circuitry but are connected to a grounding bar at the edge of the substrate roll. During plasma processes, this grid acts as a Faraday cage, shielding the sensitive TFTs from charge build-up and preventing threshold voltage shifts or gate oxide breakdown, thus improving display uniformity and lifespan.

Mermaid Diagram:

graph LR
    subgraph Flexible Display Substrate
        Pixel1[TFT & OLED]
        Pixel2[TFT & OLED]
        Pixel3[TFT & OLED]
        DummyGrid(Dummy Metal Grid)
    end
    
    Plasma[Plasma Processing Step]
    Plasma -- Generates Charge --> Substrate
    Substrate -- Charge Captured By --> DummyGrid
    DummyGrid --> Ground[Ground Connection]
    
    style DummyGrid fill:#ddd,stroke:#333,stroke-dasharray: 5 5

Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Optimized Dummy Feature Generation

Enabling Description: The fixed-pattern dummy structures of the '584 patent are replaced by a dynamic, AI-driven design methodology. A machine learning model (e.g., a Graph Neural Network) is trained on a dataset of IC layouts and corresponding wafer-level charge measurement data. For a new chip design (GDSII file), the model predicts the areas of highest probable charge accumulation during critical plasma etch steps. It then automatically generates an optimized, non-uniform pattern of dummy openings, varying their size, density, and proximity to sensitive gates, to create the most efficient shunt paths. This "charge-aware" layout is added to the mask set, creating a bespoke charge protection scheme for each unique IC design, superior to a one-size-fits-all approach.

Mermaid Diagram:

sequenceDiagram
    participant Designer
    participant AI_Model as AI Layout Optimizer
    participant Mask_Fab
    participant Plasma_Etcher
    Designer->>AI_Model: Submit GDSII Layout
    AI_Model->>AI_Model: Predict Charge Hotspots
    AI_Model->>AI_Model: Generate Optimal Dummy Pattern
    AI_Model->>Designer: Return Modified GDSII
    Designer->>Mask_Fab: Send Final Layout
    Mask_Fab->>Plasma_Etcher: Provide Fabricated Mask
    Plasma_Etcher->>Plasma_Etcher: Process Wafer with Optimized Charge Protection

Derivative 4.2: IoT-Enabled Real-Time Plasma Process Control

Enabling Description: The dummy features are designed not just for passive charge dissipation but as active IoT sensors. A subset of the dummy structures are fabricated as charge-collection plates (antennas) connected to simple ring oscillator circuits located in the wafer's scribe lines. The oscillation frequency changes in direct proportion to the collected charge potential. An external, non-contact RF probe reads these frequencies during the plasma process, providing real-time, in-situ feedback on the wafer's surface charge distribution. This data stream is fed back to the plasma tool's controller, which can dynamically adjust parameters like RF power, gas pressure, or bias voltage to minimize charging on the fly, moving from a static damage prevention method to an active feedback control loop.

Mermaid Diagram:

graph TD
    A[Plasma Chamber] -- Generates Plasma --> B[Semiconductor Wafer];
    B -- Charge Accumulates on --> C{Dummy Antenna Structures};
    C -- Modulates Frequency --> D[Ring Oscillator Sensor in Scribe Line];
    D -- Emits RF Signal --> E(External RF Probe);
    E -- Feeds Data --> F[Process Controller];
    F -- Adjusts Parameters --> A;
    subgraph On-Wafer
        C
        D
    end
    subgraph Off-Wafer
        E
        F
    end

Derivative 4.3: Blockchain-Verified Manufacturing Process for High-Reliability ICs

Enabling Description: For critical applications (e.g., automotive, defense), the integrity of the charge damage mitigation process is paramount. Each wafer is given a unique digital identity on a distributed ledger (blockchain). During manufacturing, data from the IoT charge sensors (as described in 4.2) is timestamped and written to the wafer's blockchain record as an immutable transaction. This creates a verifiable "birth certificate" for each die, proving that it was processed within safe charging limits. Customers can later query the blockchain to verify the manufacturing provenance and quality control of each specific chip, ensuring it wasn't exposed to potentially damaging electrostatic discharge events during fabrication.

Mermaid Diagram:

flowchart LR
    subgraph Fab
        Wafer[Wafer with Unique ID] --> Etch(Plasma Etch Step)
        Sensor[IoT Charge Sensor] -- Data --> Controller(Process Controller)
        Controller -- Log Data --> Blockchain(Append to Wafer's Block)
    end
    subgraph Supply_Chain
        Fab --> Distributor
        Distributor --> OEM(End Customer)
        OEM -- Scans Chip ID --> Query(Query Blockchain)
        Query --> Blockchain
        Blockchain -- Returns Process History --> OEM
    end

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Self-Destructing Charge-Fuses for Process Characterization

Enabling Description: Instead of preventing damage, this method uses dummy features to precisely detect when and where damaging charge levels occur. The "dummy features" are designed as arrays of microscopic, electrically isolated fuses. Each fuse consists of a thin polysilicon gate over a deliberately thinned gate oxide. The "antenna ratio" (ratio of conductive collector area to gate area) of each fuse is varied systematically across the array. During a plasma process, when the local charge potential exceeds the breakdown voltage of a fuse's thin oxide, it ruptures permanently. By inspecting which fuses in the array have been blown after processing, engineers can create a detailed, high-resolution map of the wafer's charging profile. This diagnostic structure allows for rapid qualification of new plasma equipment and processes.

Mermaid Diagram:

stateDiagram-v2
    [*] --> Intact
    Intact: V_collected < V_breakdown
    Ruptured: V_collected >= V_breakdown
    
    Intact --> Ruptured: Plasma Charging Event Exceeds Threshold
    
    note right of Ruptured
      Fuse is permanently open.
      Location and antenna ratio provide
      process characterization data.
    end note

Combination with Open-Source Standards

Integration with KiCad EDA Suite: A plugin for the KiCad PCB layout software is developed to apply this charge-mitigation principle to printed circuit board fabrication. The plugin's script automatically populates unused board areas with a grid of non-functional "dummy pads" and "thieving traces" connected to the ground plane. This increases the exposed copper percentage during the plasma desmear and etch processes used in multilayer PCB manufacturing, ensuring uniform etching and preventing charge-induced damage to sensitive surface-mount components, leveraging the open-source KiCad platform for widespread adoption.
Application with RISC-V SoC Designs: A reference implementation is provided for a System-on-Chip (SoC) based on the open-source RISC-V instruction set architecture. The GDSII layout files for a standard RISC-V core (e.g., Rocket or BOOM) are modified to include a standardized library of dummy STI (Shallow Trench Isolation) and metal fill structures as described in the '584 patent. This "charge-hardened" open-source IP can be freely used by designers, ensuring that even low-cost or experimental RISC-V implementations are protected from common plasma-induced manufacturing defects without requiring proprietary layout solutions.
Use with Linux-based Equipment Control (EPICS): The IoT-based real-time charge monitoring system (Derivative 4.2) is integrated with the Experimental Physics and Industrial Control System (EPICS), an open-source framework used for controlling large-scale scientific and industrial equipment. A specific EPICS device driver and control module are developed to read data from the wafer charge sensors and interface with the mass flow controllers (MFCs) and RF generators of a plasma etcher. This allows any fabrication facility using the EPICS standard to implement a sophisticated, closed-loop charge control system using off-the-shelf hardware and open-source software, democratizing access to advanced process control.