US 11568941

US Patent 11,568,941: Overview and Independent Claims

Title: Memory including a plurality of portions and used for reducing program disturbance and program method thereof

Assignee: Yangtze Memory Technologies Co Ltd

Inventors: Yali Song, XiangNan Zhao, Ying Cui

Filing Date: September 10, 2021

Issue Date: January 31, 2023

Abstract:
A memory device is described that includes a first portion, a second portion, and a controller. The first portion contains word lines WL1 to WLk, and the second portion, located above the first, contains word lines WL(k+1) to WLm. When a specific xth word line is being programmed, the controller applies different voltages to surrounding word lines to reduce program disturbance. Specifically, a first voltage is applied to word lines from WL1 to WL(x-2), a second voltage to WL(x-1), and a third voltage to WL(x+1). The parameters x, k, and m are positive integers.

Plain-Language Overview of Independent Claims:

Independent Claim 1 (Memory Apparatus):
This claim describes a memory device structured to reduce program disturbance. It consists of:

• A first memory portion containing word lines from (m+1)th to nth, ordered from bottom to top.
• A second memory portion located below the first portion, containing word lines from (k+1)th to mth, also from bottom to top.
• A controller that manages voltage application during a program operation of an xth word line. When programming the xth word line, the controller applies:
  • A first voltage to word lines from (x+2)th to nth.
  • A second voltage to the (x+1)th word line.
  • A third voltage to the (x-1)th word line.
  • A fourth voltage to word lines from the (m+1)th to (x-2)th.
  • A fifth voltage to word lines from the (k+1)th to mth.
    The claim specifies that x, k, and m are integers, with 0 ≤ k < m, and (m+2) < x < (n-1). A key distinction is that the fifth voltage is lower than the fourth voltage.

Independent Claim 5 (Program Method):
This claim outlines a method for operating a memory to reduce program disturbance. The memory includes a first portion (WL1 to WLk) and a second portion (WL(k+1) to WLm) stacked above it. The method involves:

• Applying a first voltage to word lines from the first word line (WL1) to the (x-2)th word line when an xth word line is being programmed.
• Applying a second voltage to the (x-1)th word line.
• Applying a third voltage to the (x+1)th word line.
  The parameters x, k, and m are positive integers, with 1 < k < m and 3 ≤ x.

Independent Claim 11 (Program Method with Graded Voltages):
This claim details another program method for a memory with a first portion (WL(m+1) to WLn) and a second portion (WL(k+1) to WLm) below it. During the program operation of an xth word line, the method comprises:

• Applying a first voltage to word lines from the (x+2)th to nth.
• Applying a second voltage to the (x+1)th word line.
• Applying a third voltage to the (x-1)th word line.
• Applying a fourth voltage to word lines from the (m+1)th to (x-2)th.
• Applying a fifth voltage to word lines from the (k+1)th to mth.
  Similar to Claim 1, x, k, and m are integers, with 0 ≤ k < m, and (m+2) < x < (n-1), and the fifth voltage is lower than the fourth voltage.

Litigation Status:

As of April 26, 2026, US Patent 11,568,941 is Active.
Publicly available information indicates that an Inter Partes Review (IPR) proceeding, IPR2025-00190, was filed against US11568941 by Micron Technology, Inc., and its subsidiaries, including Micron Consumer Products Group LLC. The requested date for this IPR was November 26, 2024. This IPR is currently listed as "Pending - Instituted" [cite: The provided patent text under "Legal status" and "PTAB case IPR2025-00190"].

The patent record also shows US cases filed in the California Eastern District Court (3:23-cv-05792) and the California Northern District Court (3:24-cv-04223 and 5:24-cv-04223), with the first worldwide family litigation filed in 2023 [cite: The provided patent text under "Family has litigation"].

Regarding CAFC 2026 dockets specifically for US11568941, no direct results indicating a CAFC appeal for 2026 were found in the current search. While an IPR has been instituted, an appeal to the CAFC would typically occur after a final written decision by the PTAB, and no such decision or subsequent appeal has been identified as of the current date.

As of April 26, 2026, the following litigation is known involving US patent 11568941:

PTAB Case:

• Case Number: IPR2025-00190 [cite: The legal status of the patent mentions "PTAB case IPR2025-00190 filed (Pending - Instituted)".]
• Plaintiff(s): Micron Technology, Inc., and its subsidiaries, including Micron Consumer Products Group LLC [cite: The legal status section of the patent lists "Petitioner: MICRON TECHNOLOGY, INC., AND ITS SUBSIDIARIES, INCLUDING MICRON CONSUMER PRODUCTS GROUP LLC".]
• Defendant(s): Yangtze Memory Technologies Co Ltd (as the assignee of the patent)
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Filing Date: February 18, 2025 [cite: The legal status section of the patent shows "2025-02-18 IPR Aia trial proceeding filed before the patent and appeal board: inter partes review".]
• Outcome/Current Status: Pending - Instituted. [cite: The legal status section of the patent indicates "PTAB case IPR2025-00190 filed (Pending - Instituted)".]

District Court Cases:

According to the provided information, US patent 11568941 has been involved in several district court cases in California. However, specific details such as plaintiffs, defendants, and filing dates are not fully provided in the provided text.

• Jurisdiction: California Eastern District Court
  • Case Number: 3:23-cv-05792 [cite: The legal status section of the patent states "US case filed in California Eastern District Court litigation https://portal.unifiedpatents.com/litigation/California%20Eastern%20District%20Court/case/3%3A23-cv-05792".]
  • Outcome/Current Status: Litigation [cite: The legal status section of the patent mentions "US case filed in California Eastern District Court litigation".]
• Jurisdiction: California Northern District Court
  • Case Number: 3:24-cv-04223 [cite: The legal status section of the patent mentions "US case filed in California Northern District Court litigation https://portal.unifiedpatents.com/litigation/California%20Northern%20District%20Court/case/3%3A24-cv-04223".]
  • Outcome/Current Status: Litigation [cite: The legal status section of the patent mentions "US case filed in California Northern District Court litigation".]
• Jurisdiction: California Northern District Court
  • Case Number: 5:24-cv-04223 [cite: The legal status section of the patent mentions "US case filed in California Northern District Court litigation https://portal.unifiedpatents.com/litigation/California%20Northern%20District%20Court/case/5%3A24-cv-04223".]
  • Outcome/Current Status: Litigation [cite: The legal status section of the patent mentions "US case filed in California Northern District Court litigation".]

Further details regarding the specific plaintiffs, defendants, and filing dates for these district court cases would require direct access to the court dockets (e.g., via PACER) or a more detailed patent litigation database than what is provided in the current context.

Proceedings overview

One AIA trial proceeding is on file for US patent 11568941, currently in an instituted but pending status. This means the patent has not yet been hardened or invalidated through PTAB review, and the outcome of the ongoing proceeding will be critical for any defendant.

IPR2025-00190 — Micron Technology, Inc., and its Subsidiaries, Including Micron Consumer Products Group LLC v. Yangtze Memory Technologies Co Ltd

• Type: Inter Partes Review
• Filed: 2024-11-26 (Effective date of IPR filing)
• Status: Pending - Instituted
• Judge panel: Not publicly available yet for this stage of the proceeding from the provided information.
• Petition grounds: Not publicly available yet from the provided information. IPRs typically challenge claims under 35 U.S.C. §§ 102 and/or 103 based on patents or printed publications.
• Institution decision: Instituted. The date of institution is not explicitly stated but the status indicates it has been instituted.
• Final Written Decision (if issued): Not yet issued as the case is pending.
• Settlement / termination: Not settled as the case is pending.
• Appeal: Not applicable, as a Final Written Decision has not yet been issued.
• Defensive value: An active IPR means that the patentability of some claims is under review. If claims relevant to an infringement allegation are ultimately canceled, this IPR could provide a strong defense. Conversely, if the claims are affirmed, it will strengthen the patent owner's position against future challenges.

Strategic summary

Currently, there is one active Inter Partes Review, IPR2025-00190, against US patent 11568941. This IPR was filed by Micron Technology, Inc., and its subsidiaries, including Micron Consumer Products Group LLC, and has been instituted by the PTAB. As the proceeding is still pending, no claims have been canceled or sustained yet through an IPR FWD. Therefore, all claims of US11568941 are currently considered untested by a final PTAB decision.

The estoppel landscape will become relevant after a Final Written Decision is issued. Under 35 U.S.C. § 315(e)(2), the petitioner (Micron Technology, Inc., and its privies) will be estopped from asserting in other proceedings that a claim is invalid on any ground that the petitioner raised or reasonably could have raised during the IPR. For a defendant facing assertion of this patent, prior-art grounds not raised or reasonably raisable by Micron in IPR2025-00190 would theoretically remain available for a separate challenge. The presence of a significant industry player like Micron as a petitioner signals potential concerns about the patent's validity within the semiconductor memory sector.

Recommended next steps

The IPR2025-00190 proceeding is currently active and instituted. The PTAB has a statutory one-year deadline to issue a Final Written Decision from the date of institution. Key upcoming milestones would include the patent owner's response, any petitioner reply, an oral hearing (if requested), and finally, the Final Written Decision. It is advisable to monitor the progress of IPR2025-00190 closely through the USPTO PTAB E2E system to understand the specific claims being challenged and the arguments being made.

Link to PTAB case: https://portal.unifiedpatents.com/ptab/case/IPR2025-00190

Inventors

• Yali Song
• XiangNan Zhao
• Ying Cui

Employer at time of filing: Yangtze Memory Technologies Co Ltd. All inventors appear to be still associated with the original assignee, and there are no immediate indications of their departure within 12 months of filing.

Original assignee

Yangtze Memory Technologies Co Ltd
Primary line of business: Semiconductor memory manufacturing, particularly 3D NAND flash memory.
Current status: Operating.

Assignment timeline

The USPTO Patent Assignment Search (https://assignmentcenter.uspto.gov/patent/index.html?id=[11568941](/patent/11568941)) indicates no recorded assignments for US Patent 11568941.

Timeline diagram

timeline
    title Ownership of US 11568941
    2021 : Filed by Yangtze Memory Technologies Co Ltd
    2023 : Issued to Yangtze Memory Technologies Co Ltd

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No assignment records found.
2. Known asserter in the chain — not present. No assignment records found.
3. Repeat correspondent across the chain — not present. No assignment records found.
4. Cascading transfers — not present. No assignment records found.
5. Pre-litigation transfer — unclear. While litigation exists for this patent (e.g., IPR2025-00190 was filed on 2025-02-18 by Micron Technology, Inc.), there are no recorded assignments to evaluate transfers relative to litigation dates.
6. Bankruptcy fire-sale — not present. No assignment records found, and the original assignee is currently operating.
7. Privateering — unclear. No assignment records found.
8. Defensive aggregator (anti-NPE) — not present. No assignment records found.

Verdict

Insufficient data. There are no recorded assignments for US Patent 11568941 on the USPTO Patent Assignment Search database (https://assignmentcenter.uspto.gov/patent/index.html?id=11568941). Therefore, it is not possible to assess NPE/troll-pattern signals based on assignment history. The patent remains with the original assignee, Yangtze Memory Technologies Co Ltd.

The USPTO offers tools for patent searching, including Patent Public Search for U.S. patents and published applications. The current analysis will rely on the provided Google Patents full text for US11568941B2, as it includes the necessary citation information.

US patent 11568941 (hereinafter '941 patent) describes a memory and a program method designed to reduce program disturbance and pass voltage disturbance in three-dimensional (3D) stack NAND flash memories. The invention achieves this by dividing the memory into multiple portions and applying different voltage levels to word lines within these portions during a program operation, depending on the location of the programmed word line (WLx). A key aspect involves applying progressively lower voltages to word lines in portions located further below the programmed word line.

The following are the most relevant prior art documents cited in US11568941B2, along with their details and potential anticipation of the '941 patent's claims:

Prior Art Analysis

1. US6061270A

• Full Citation: US6,061,270 A, "Method for programming a non-volatile memory device with program disturb control," issued to [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)
• Publication/Filing Date: Publication: May 9, 2000. Priority/Filing: December 31, 1997.
• Brief Description: This patent describes a method for programming a non-volatile memory device, such as a flash memory, which includes applying a pass voltage to unselected word lines during a program operation to prevent program disturb. The pass voltage is typically set to a level that does not program the unselected cells.
• Potential Anticipation: This patent generally addresses program disturb control in non-volatile memory by applying pass voltages. While it introduces the concept of preventing program disturb, it does not describe the multi-portion memory structure or the specific graduated voltage application scheme (e.g., V6 < V5 < V4) to different portions below the programmed word line as claimed in claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent. It also doesn't explicitly discuss 3D structures or varying pass voltages based on the WLx location within different portions/decks. Therefore, it might generally anticipate the broad concept of using pass voltages to prevent program disturb, but not the specific, detailed multi-level voltage control across divided memory portions of the '941 patent.

2. US20090257280A1

• Full Citation: US 2009/0257280 A1, "Nand flash memory device and method of operating same," published by Dong-Yean Oh.
• Publication/Filing Date: Publication: October 15, 2009. Filing: April 14, 2008.
• Brief Description: This application relates to a NAND flash memory device and its operating method, aiming to reduce program disturb by applying different pass voltages to unselected word lines. Specifically, it suggests applying a lower pass voltage to unselected word lines closer to the selected word line and a higher pass voltage to unselected word lines further away. This is primarily concerned with reducing program disturb in the selected string.
• Potential Anticipation: This reference discloses applying different pass voltages to unselected word lines based on their proximity to the selected word line. This concept of varying pass voltages is relevant. However, the '941 patent introduces a more complex scheme of dividing the memory into distinct "portions" (e.g., first, second, third portions) and applying different voltages to entire portions below the selected word line, where these voltages have a specific hierarchical relationship (e.g., V6 < V5 < V4). US20090257280A1 typically discusses voltages that increase with distance from WLx to mitigate GIDL (Gate-Induced Drain Leakage) related disturb, which is distinct from the '941 patent's approach for portions below WLx. Thus, while it broadly anticipates varying pass voltages, it doesn't clearly anticipate the multi-portion architecture and the specific graduated voltage reduction scheme described in claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent.

3. US20100124119A1

• Full Citation: US 2010/0124119 A1, "Nonvolatile Memory Device and Read Methods Thereof," published by Lee Changhyun.
• Publication/Filing Date: Publication: May 20, 2010. Filing: November 14, 2008.
• Brief Description: This patent application focuses on read methods for nonvolatile memory devices, particularly to overcome issues like read disturb and cell-to-cell interference by adjusting read voltages. It proposes varying read voltages based on the state of neighboring cells.
• Potential Anticipation: This reference primarily deals with read operations and read disturb, not program operations and program disturb as claimed in the '941 patent. The voltage application schemes described are for reading, not programming, and do not disclose the specific memory partitioning and program voltage differentiation claimed in the '941 patent (claims 1, 5, 11).

4. US20120163096A1

• Full Citation: US 2012/0163096 A1, "Nonvolatile semiconductor memory device and method for controlling the same," published by Kabushiki Kaisha Toshiba.
• Publication/Filing Date: Publication: June 28, 2012. Filing: December 28, 2010.
• Brief Description: This application describes a nonvolatile semiconductor memory device and control method that reduces program disturb by applying different pass voltages to unselected word lines. It suggests varying the pass voltage based on the distance from the selected word line or the program loop count. It aims to suppress unintentional programming of unselected memory cells.
• Potential Anticipation: Similar to US20090257280A1, this reference discloses varying pass voltages for unselected word lines to prevent program disturb. While it touches upon the core problem, it does not explicitly describe the "portions" concept (first, second, third portions) or the specific hierarchical voltage relationship (e.g., V6 < V5 < V4) across these distinct physical or logical portions below the programmed word line as detailed in claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent. Its focus is more on individual word line pass voltages rather than differentiated voltage application to pre-defined memory portions.

5. CN102789814A

• Full Citation: CN 102789814 A, "Program method of nonvolatile memory device," published by Hynix Semiconductor Inc.
• Publication/Filing Date: Publication: November 21, 2012. Filing: May 20, 2011.
• Brief Description: This patent describes a method for programming a nonvolatile memory device that involves adjusting program voltages and pass voltages to reduce program disturb. It may suggest optimizing voltage levels based on memory characteristics to improve programming reliability.
• Potential Anticipation: This general description indicates a method for reducing program disturb by adjusting program and pass voltages. Without more specific details, it is difficult to determine direct anticipation. However, based on the general description, it likely does not disclose the specific multi-portion architecture with progressively lower voltages in lower portions as defined in claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent.

6. US20130163326A1

• Full Citation: US 2013/0163326 A1, "Nonvolatile Memory Device and Program Method Thereof," published by Samsung Electronics Co., Ltd.
• Publication/Filing Date: Publication: June 27, 2013. Filing: December 26, 2011.
• Brief Description: This application describes a nonvolatile memory device and its programming method that applies different pass voltages to unselected word lines to mitigate program disturb. It suggests providing pass voltages that vary based on physical location or other criteria to protect unselected cells.
• Potential Anticipation: This reference, similar to others, broadly teaches applying different pass voltages to unselected word lines to mitigate program disturb. However, it does not clearly articulate the concept of dividing the entire memory into specific "portions" (e.g., first, second, third portions) with a distinct voltage hierarchy (e.g., V6 < V5 < V4) applied to these entire portions below the WLx, nor the condition-dependent variation of V1 based on WLx location as in claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent.

7. US20130272067A1

• Full Citation: US 2013/0272067 A1, "Non-boosting program inhibit scheme in nand design," published by Aplus Flash Technology, Inc.
• Publication/Filing Date: Publication: October 17, 2013. Filing: April 11, 2012.
• Brief Description: This application discloses a program inhibit scheme for NAND flash memory that aims to prevent program disturb by inhibiting boosting of unselected word lines, thereby maintaining a lower voltage. This method is an alternative to traditional boosting techniques.
• Potential Anticipation: This patent focuses on a "non-boosting program inhibit scheme" rather than a differential voltage application across distinct memory portions. While it addresses program inhibit, its mechanism and the specific voltage relationships for sections below WLx as claimed in the '941 patent (claims 1, 2, 5, 8, 9, 11, 12) are not clearly anticipated.

8. CN104916319A

• Full Citation: CN 104916319 A, "Semiconductor storage device," published by Kabushiki Kaisha Toshiba.
• Publication/Filing Date: Publication: September 16, 2015. Filing: March 14, 2014.
• Brief Description: This application describes a semiconductor storage device, potentially a NAND flash memory, that aims to control program operations to improve reliability. The description focuses on general aspects of semiconductor memory.
• Potential Anticipation: The provided description is very general and does not offer sufficient detail to assess anticipation. Without further information about its specific program disturb mitigation techniques, it cannot be determined if it anticipates the multi-portion voltage application scheme of the '941 patent (claims 1, 2, 5, 8, 9, 11, 12).

9. US20160071595A1

• Full Citation: US 2016/0071595 A1, "Controlling Pass Voltages To Minimize Program Disturb In Charge-Trapping Memory," published by Sandisk Technologies Inc.
• Publication/Filing Date: Publication: March 10, 2016. Filing: September 9, 2014.
• Brief Description: This application discloses controlling pass voltages in charge-trapping memory to minimize program disturb. It may involve adjusting pass voltages to unselected word lines in a string or block to prevent unintentional programming.
• Potential Anticipation: This reference broadly addresses controlling pass voltages for program disturb. However, without specific details on whether it employs a "portion-based" architecture with hierarchical voltage relationships for portions below WLx, and variable V1 based on WLx location, it is unlikely to anticipate claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent.

10. US20160099060A1

• Full Citation: US 2016/0099060 A1, "Semiconductor memory device including a dummy memory cell and method of programming the same," published by SK Hynix Inc.
• Publication/Filing Date: Publication: April 7, 2016. Filing: October 2, 2014.
• Brief Description: This application describes a semiconductor memory device including dummy memory cells and a programming method for them. Dummy cells are often used at the edges of a memory block or string to manage voltage distributions or reduce edge effects.
• Potential Anticipation: This patent mentions dummy memory cells. Claim 4 and Claim 10 of the '941 patent disclose the inclusion of "dummy word lines" and a "two-deck structure." While US20160099060A1 mentions dummy cells in a programming context, it does not clearly describe the specific "upper dummy word line," "lower dummy word line," and "joint oxide layer" configuration in a two-deck structure as defined in claims 4 and 10 of the '941 patent. Furthermore, its primary focus is on dummy cells rather than the multi-portion voltage application for program disturb.

11. US20160343414A1

• Full Citation: US 2016/0343414 A1, "Semiconductor memory device and operating method thereof," published by SK Hynix Inc.
• Publication/Filing Date: Publication: November 24, 2016. Filing: May 20, 2015.
• Brief Description: This application describes a semiconductor memory device and an operating method that aims to improve memory reliability, potentially by optimizing program/read operations and managing various types of disturb.
• Potential Anticipation: This is a very general description. Without specific details on the voltage application schemes and memory partitioning, it cannot be determined if it anticipates the unique features of claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent.

12. US20180190498A1

• Full Citation: US 2018/0190498 A1, "Memory device and method of operating the same," published by SK Hynix Inc.
• Publication/Filing Date: Publication: July 5, 2018. Filing: January 5, 2017.
• Brief Description: This application describes a memory device and its operating method, focusing on techniques to prevent various types of disturb or improve program/read performance.
• Potential Anticipation: Similar to the previous general descriptions, this abstract does not provide enough specific technical details to assess direct anticipation of the '941 patent's claims, particularly the multi-portion voltage scheme with decreasing voltages in lower portions (claims 1, 2, 5, 8, 9, 11, 12).

13. US20190006021A1

• Full Citation: US 2019/0006021 A1, "Leakage detection for inter-block sgd-wl shorts in storage devices," published by Sandisk Technologies Llc.
• Publication/Filing Date: Publication: January 3, 2019. Filing: June 29, 2017.
• Brief Description: This application concerns leakage detection, specifically for shorts between a string select gate drain (SGD) and a word line (WL) in storage devices. This is a diagnostic and reliability feature.
• Potential Anticipation: This reference focuses on detecting leakage due to shorts, which is a different technical problem from program disturbance mitigation through differentiated pass voltages as described in the '941 patent. It does not anticipate any of the key claims of the '941 patent.

14. US20190259456A1

• Full Citation: US 2019/0259456 A1, "Memory device," published by Samsung Electronics Co., Ltd.
• Publication/Filing Date: Publication: August 22, 2019. Filing: February 22, 2018.
• Brief Description: This application describes a memory device, potentially a 3D NAND flash, focusing on its architecture or operation to improve performance or reliability.
• Potential Anticipation: This is another general description. Without further details on the specific program disturb mitigation methods, it cannot be determined if it anticipates the multi-portion voltage application scheme with decreasing voltages in lower portions (claims 1, 2, 5, 8, 9, 11, 12) or the variable V1 scheme (claims 8, 9) of the '941 patent.

15. CN110689913A

• Full Citation: CN 110689913 A, "Nonvolatile memory device," published by Samsung Electronics Co., Ltd.
• Publication/Filing Date: Publication: January 14, 2020. Filing: July 5, 2018.
• Brief Description: This application describes a nonvolatile memory device, likely a 3D NAND, aiming to enhance its characteristics or operation.
• Potential Anticipation: Similar to the other general descriptions, there is insufficient detail to assess anticipation of the specific multi-portion voltage application scheme of the '941 patent (claims 1, 2, 5, 8, 9, 11, 12).

16. KR100297602B1

• Full Citation: KR 100297602 B1, "Method for programming a non-volatile memory device," published by Yoon Jong Yong.
• Publication/Filing Date: Publication: August 7, 2001. Filing: December 31, 1997.
• Brief Description: This Korean patent describes a method for programming a non-volatile memory device. Its title suggests a general programming method, which may include aspects of program disturb prevention.
• Potential Anticipation: As a general programming method, without specific details on multi-portion architectures and hierarchical voltage applications, it is unlikely to anticipate the specific claims of the '941 patent (claims 1, 2, 5, 8, 9, 11, 12).

17. CN101567213A

• Full Citation: CN 101567213 A, "Nand flash memory device and method of operating same," published by Samsung Electronics Co., Ltd.
• Publication/Filing Date: Publication: October 28, 2009. Filing: April 14, 2008.
• Brief Description: This Chinese patent application corresponds to US20090257280A1 (Dong-Yean Oh), which is also cited. Therefore, its description and potential anticipation are similar.
• Potential Anticipation: As a family member of US20090257280A1, it likely shares similar teachings regarding varying pass voltages but lacks the explicit multi-portion structure with specifically defined hierarchical voltage levels for portions below WLx, as found in claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent.

18. CN101740129A

• Full Citation: CN 101740129 A, "Nonvolatile memory device and read method thereof," published by Samsung Electronics Co., Ltd.
• Publication/Filing Date: Publication: June 16, 2010. Filing: November 14, 2008.
• Brief Description: This Chinese patent application corresponds to US20100124119A1 (Lee Changhyun), which is also cited. Therefore, its description and potential anticipation are similar.
• Potential Anticipation: As a family member of US20100124119A1, it primarily focuses on read operations and read disturb, not program operations and program disturb as claimed in the '941 patent.

19. US20120294087A1

• Full Citation: US 2012/0294087 A1, "Program method of nonvolatile memory device," published by Ji-Hyun Seo.
• Publication/Filing Date: Publication: November 22, 2012. Filing: May 20, 2011.
• Brief Description: This application describes a program method for nonvolatile memory, likely addressing program disturb by adjusting program conditions or voltages.
• Potential Anticipation: This general description does not provide enough specific detail to determine if it anticipates the multi-portion architecture and the specific hierarchical voltage application scheme for program disturb mitigation in the '941 patent (claims 1, 2, 5, 8, 9, 11, 12).

20. US20150262682A1

• Full Citation: US 2015/0262682 A1, "Semiconductor memory device," published by Kabushiki Kaisha Toshiba.
• Publication/Filing Date: Publication: September 17, 2015. Filing: March 14, 2014.
• Brief Description: This application describes a semiconductor memory device. The provided abstract is broad and indicates that it is related to memory.
• Potential Anticipation: This is a very general description. Without further specific information, it cannot be determined if it anticipates the specific claims of the '941 patent regarding multi-portion voltage application for program disturb (claims 1, 2, 5, 8, 9, 11, 12). This appears to be a family member of CN104916319A.

21. US10269570B2

• Full Citation: US 10,269,570 B2, "Memory device and method relating to different pass voltages for unselected pages," issued to SK Hynix Inc.
• Publication/Filing Date: Publication: April 23, 2019. Filing: January 5, 2017.
• Brief Description: This patent describes a memory device and a method for operating it that involves applying different pass voltages to unselected pages (which correspond to word lines) to manage program disturb. It may specify different pass voltages for different groups of unselected word lines.
• Potential Anticipation: This patent broadly discusses applying different pass voltages to unselected word lines/pages to manage program disturb. It is likely to be highly relevant as it addresses the core problem. However, the critical distinction for the '941 patent lies in the definition of "portions" and the specific hierarchical relationship of voltages (e.g., V6 < V5 < V4) for portions located below the programmed word line, especially when combined with the variable V1 based on the programmed word line's portion. Without explicitly detailing such a multi-portion structure and decreasing voltage hierarchy to portions below WLx, it might not fully anticipate claims 1, 2, 5, 8, 9, 11, 12.

22. US20190206690A1

• Full Citation: US 2019/0206690 A1, "Memory device and method of operating the same," published by SK Hynix Inc.
• Publication/Filing Date: Publication: July 4, 2019. Filing: January 5, 2017.
• Brief Description: This application describes a memory device and an operating method that aims to prevent various types of disturb or improve program/read performance.
• Potential Anticipation: This application is a family member of US20180190498A1 and US10269570B2. Therefore, its potential anticipation characteristics are similar to US10269570B2. It generally describes applying different pass voltages. However, it does not explicitly disclose the unique multi-portion voltage application scheme with decreasing voltages in lower portions (claims 1, 2, 5, 8, 9, 11, 12) or the variable V1 scheme (claims 8, 9) of the '941 patent.

23. CN108281166A

• Full Citation: CN 108281166 A, "Storage device and its operating method," published by SK Hynix Inc.
• Publication/Filing Date: Publication: July 13, 2018. Filing: January 5, 2017.
• Brief Description: This Chinese patent application is a family member of US20180190498A1 and US10269570B2. Therefore, its description and potential anticipation are similar.
• Potential Anticipation: As a family member of US10269570B2, it likely shares similar teachings regarding varying pass voltages but lacks the explicit multi-portion structure with specifically defined hierarchical voltage levels for portions below WLx, as found in claims 1, 2, 5, 8, 9, 11, 12 of the '941 patent.

24. CN110189784A

• Full Citation: CN 110189784 A, "Memory device," published by Samsung Electronics Co., Ltd.
• Publication/Filing Date: Publication: August 30, 2019. Filing: February 22, 2018.
• Brief Description: This Chinese patent application corresponds to US20190259456A1, which is also cited. Therefore, its description and potential anticipation are similar.
• Potential Anticipation: As a family member of US20190259456A1, it is a general description of a memory device without sufficient specific details to anticipate the multi-portion voltage application scheme of the '941 patent (claims 1, 2, 5, 8, 9, 11, 12).

Most Relevant Prior Art Summary:

The most relevant prior art documents appear to be those that specifically address the problem of program disturbance in non-volatile memory by applying different pass voltages to unselected word lines. These include:

• US20090257280A1 (Dong-Yean Oh): Discloses applying different pass voltages based on proximity to the selected word line.
• US20120163096A1 (Kabushiki Kaisha Toshiba): Suggests varying pass voltage based on distance from the selected word line or program loop count.
• US20130163326A1 (Samsung Electronics Co., Ltd.): Proposes varying pass voltages based on physical location or other criteria.
• US10269570B2 (SK Hynix Inc.): Discusses applying different pass voltages to unselected pages/word lines to manage program disturb.

These references collectively establish the general concept of applying differential pass voltages to mitigate program disturb. However, the '941 patent distinguishes itself by defining explicit "portions" of the memory and applying a specific hierarchical voltage relationship (e.g., V6 < V5 < V4) to these distinct portions, particularly those located below the programmed word line (WLx). Furthermore, the '941 patent introduces the concept of varying the first voltage (V1) based on which portion the WLx resides in (Claims 8 and 9), and explicitly mentions dummy word lines in a two-deck structure (Claims 4 and 10). These specific features, especially the graduated voltage levels to defined portions below the programmed word line, represent the potential inventive step over the cited general art.The analysis of US patent 11568941B2 (the '941 patent) and its cited prior art reveals several relevant documents concerning the reduction of program disturbance in non-volatile memory. The '941 patent focuses on a memory architecture divided into multiple portions and a method of applying distinct, often hierarchically related, voltages to these portions during a program operation to mitigate disturbance.

Here's an overview of the most relevant patent citations:

Prior Art Citations and Anticipation Analysis

1. US6061270A

• Full Citation: US6,061,270 A, "Method for programming a non-volatile memory device with program disturb control," issued to Samsung Electronics Co., Ltd.
• Publication/Filing Date: Publication: May 9, 2000. Filing: December 31, 1997.
• Brief Description: This patent introduces a method for controlling program disturbance in non-volatile memory by applying a pass voltage to unselected word lines during a program operation. The pass voltage is set to a level intended to prevent the programming of these unselected cells.
• Potential Anticipation: This reference broadly anticipates the concept of using pass voltages to prevent program disturbance. However, it lacks the specific multi-portion memory structure and the detailed hierarchical voltage application scheme (e.g., V6 < V5 < V4 for portions below WLx) to distinct portions as defined in claims 1, 2, 5, 8, 9, 11, and 12 of the '941 patent.

2. US20090257280A1

• Full Citation: US 2009/0257280 A1, "Nand flash memory device and method of operating same," published by Dong-Yean Oh.
• Publication/Filing Date: Publication: October 15, 2009. Filing: April 14, 2008.
• Brief Description: This application aims to reduce program disturbance in NAND flash memory by applying different pass voltages to unselected word lines. It suggests using a lower pass voltage for unselected word lines closer to the selected word line and a higher pass voltage for those further away, primarily to mitigate GIDL (Gate-Induced Drain Leakage) related disturb.
• Potential Anticipation: This patent anticipates the idea of varying pass voltages based on proximity to the selected word line during a program operation. However, it does not explicitly disclose the division of memory into distinct "portions" (e.g., first, second, third) with a progressively decreasing voltage hierarchy applied to these entire portions below the programmed word line (WLx), nor the condition-dependent variation of V1 based on WLx's location, which are central to claims 1, 2, 5, 8, 9, 11, and 12 of the '941 patent.

3. US20120163096A1

• Full Citation: US 2012/0163096 A1, "Nonvolatile semiconductor memory device and method for controlling the same," published by Kabushiki Kaisha Toshiba.
• Publication/Filing Date: Publication: June 28, 2012. Filing: December 28, 2010.
• Brief Description: This application describes a method to suppress unintentional programming of unselected memory cells by applying different pass voltages to unselected word lines, which can vary based on their distance from the selected word line or the program loop count.
• Potential Anticipation: Similar to US20090257280A1, this reference establishes the concept of varying pass voltages to unselected word lines for program disturb prevention. However, it does not clearly define a memory divided into distinct "portions" with a specific, decreasing voltage hierarchy (e.g., V6 < V5 < V4) applied to these entire portions located below the programmed word line, as claimed in claims 1, 2, 5, 8, 9, 11, and 12 of the '941 patent. Its focus is more on individual word line pass voltages.

4. US20130163326A1

• Full Citation: US 2013/0163326 A1, "Nonvolatile Memory Device and Program Method Thereof," published by Samsung Electronics Co., Ltd.
• Publication/Filing Date: Publication: June 27, 2013. Filing: December 26, 2011.
• Brief Description: This application describes a nonvolatile memory device and a programming method that mitigates program disturb by applying different pass voltages to unselected word lines, potentially based on their physical location or other criteria.
• Potential Anticipation: This reference broadly teaches applying differential pass voltages to unselected word lines for program disturb mitigation. Nevertheless, it does not explicitly articulate the multi-portion architecture with a distinct and specific hierarchical voltage relationship (e.g., V6 < V5 < V4) applied to entire portions below the programmed word line, nor the condition-dependent variation of V1 based on WLx location, as detailed in claims 1, 2, 5, 8, 9, 11, and 12 of the '941 patent.

5. US10269570B2

• Full Citation: US 10,269,570 B2, "Memory device and method relating to different pass voltages for unselected pages," issued to SK Hynix Inc.
• Publication/Filing Date: Publication: April 23, 2019. Filing: January 5, 2017.
• Brief Description: This patent describes a memory device and its operating method, involving the application of different pass voltages to unselected pages (word lines) to manage program disturbance. It may specify distinct pass voltages for various groups of unselected word lines.
• Potential Anticipation: This patent is highly relevant as it directly addresses applying different pass voltages to unselected word lines to control program disturb. However, the '941 patent distinguishes itself by explicitly defining "portions" of the memory and applying a specific, decreasing hierarchical voltage relationship (e.g., V6 < V5 < V4) to these distinct portions located below the programmed word line. The '941 patent also includes variable first voltage (V1) levels based on which portion the programmed word line resides in (claims 8 and 9), and the inclusion of dummy word lines in a two-deck structure (claims 4 and 10). Without these specific structural and voltage application details to defined portions, it likely does not fully anticipate claims 1, 2, 5, 8, 9, 11, and 12 of the '941 patent.

Other citations (US20100124119A1, CN102789814A, US20130272067A1, CN104916319A, US20160071595A1, US20160099060A1, US20160343414A1, US20180190498A1, US20190006021A1, US20190259456A1, CN110689913A, KR100297602B1, CN101567213A, CN101740129A, US20120294087A1, US20150262682A1, US20190206690A1, CN108281166A, CN110189784A) generally relate to non-volatile memory programming methods, read methods, or device structures and may cover broad aspects of memory operation or disturbance mitigation. However, based on their abstracts and general descriptions, they do not appear to disclose the specific combination of features related to memory partitioning and the detailed, hierarchical voltage application scheme for reducing program disturbance in different portions of a 3D memory, which is claimed in US11568941B2. In particular, none of these references explicitly describe the graduated voltage reduction (V6 < V5 < V4) for distinct physical/logical portions located below the word line being programmed.

US patent 11568941, titled "Memory including a plurality of portions and used for reducing program disturbance and program method thereof," addresses the issue of program disturbance and pass voltage disturbance in 3D non-volatile memory devices by dividing the memory into portions and applying different voltages to word lines based on their location relative to the word line being programmed. The patent aims to reduce programming failure rates as the number of memory layers increases.

I. Legal Basis for Obviousness (35 U.S.C. § 103)

Under 35 U.S.C. § 103, a patent claim is unpatentable if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains." To establish obviousness, one must demonstrate:

1. A motivation to combine prior art references.
2. A reasonable expectation of success in doing so.

II. Prior Art References

The following prior art references are considered for this analysis:

• US 6,061,270 A ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)): "Method for programming a non-volatile memory device with program disturb control." This patent generally describes methods for programming non-volatile memory devices with program disturb control.
• US 2009/0257280 A1 (Oh, Dong-Yean): "Nand flash memory device and method of operating same." This reference relates to NAND flash memory devices and their operation.
• US 2010/0124119 A1 (Lee, Changhyun): "Nonvolatile Memory Device and Read Methods Thereof." This document discusses nonvolatile memory devices and read methods.
• US 2012/0163096 A1 (Kabushiki Kaisha Toshiba): "Nonvolatile semiconductor memory device and method for controlling the same." This prior art concerns nonvolatile semiconductor memory devices and control methods.
• CN 102789814 A (Hynix Semiconductor Inc.): "Program method of nonvolatile memory device." This Chinese patent describes a program method for nonvolatile memory devices.
• US 2013/0163326 A1 (Samsung Electronics Co., Ltd.): "Nonvolatile Memory Device and Program Method Thereof." This reference details a nonvolatile memory device and its program method.
• US 2013/0272067 A1 (Aplus Flash Technology, Inc): "Non-boosting program inhibit scheme in nand design." This patent introduces a non-boosting program inhibit scheme for NAND flash memory, focusing on reducing error rates of threshold voltage levels.
• CN 104916319 A (Kabushiki Kaisha Toshiba): "Semiconductor storage device." This document relates to semiconductor storage devices.
• US 2016/0071595 A1 (Sandisk Technologies Inc.): "Controlling Pass Voltages To Minimize Program Disturb In Charge-Trapping Memory." This reference teaches controlling pass voltages to minimize program disturb.
• US 2016/0099060 A1 (SK Hynix Inc.): "Semiconductor memory device including a dummy memory cell and method of programming the same." This patent describes a semiconductor memory device with dummy memory cells.
• US 2016/0343414 A1 (SK Hynix Inc.): "Semiconductor memory device and operating method thereof." This document describes a semiconductor memory device and its operating method.
• US 2018/0190498 A1 (SK Hynix Inc.): "Memory device and method of operating the same." This patent concerns a memory device and its operating method.
• US 2019/0006021 A1 (Sandisk Technologies Llc): "Leakage detection for inter-block sgd-wl shorts in storage devices." This reference deals with leakage detection.
• US 2019/0259456 A1 (Samsung Electronics Co., Ltd.): "Memory device." This patent describes a memory device.
• CN 110689913 A (Samsung Electronics Co., Ltd.): "Nonvolatile memory device." This Chinese patent relates to a nonvolatile memory device.

III. Analysis of Obviousness for US 11568941 Claims

US 11568941 generally claims a memory and a program method designed to reduce program disturbance in multi-layered 3D non-volatile memory. The core inventive concept involves dividing the memory into multiple portions (e.g., first, second, and optionally third portions) and applying different voltages to word lines within these portions based on the location of the word line being programmed. Specifically, it describes varying voltages for word lines above and below the programmed word line, with lower voltages applied to portions located further away from the programmed word line to reduce disturbance.

A person having ordinary skill in the art (PHOSITA) in 3D NAND flash memory design would be aware of the challenges of program disturbance and pass voltage disturbance, especially as the number of layers increases. The prior art clearly demonstrates a motivation to reduce program disturbance. For instance, US 6,061,270 A explicitly aims to control program disturbance in non-volatile memory devices, and US 2016/0071595 A1 focuses on controlling pass voltages to minimize program disturb in charge-trapping memory. US 2007/0171718 A1 also discusses programming non-volatile storage elements to reduce program disturb by using modified pass voltages. These references establish a clear problem and a general motivation to mitigate program disturb.

A. Obviousness of Claim 1

Claim 1 describes a memory comprising a first portion and a second portion, with a controller configured to apply a first voltage to (x+2)th to nth word lines, a second voltage to an (x+1)th word line, a third voltage to an (x-1)th word line, a fourth voltage to (m+1)th to (x-2)th word lines, and a fifth voltage to (k+1)th to mth word lines when an xth word line is programmed. It specifies that the fifth voltage is lower than the fourth voltage.

Combination 1: US 2016/0071595 A1 in view of US 2012/0163096 A1 and US 2013/0272067 A1

• US 2016/0071595 A1 teaches controlling pass voltages to minimize program disturb in charge-trapping memory. This reference explicitly addresses the problem of program disturb and the use of pass voltages for its mitigation.
• US 2012/0163096 A1 discloses a nonvolatile semiconductor memory device and a method for controlling it, which would include the fundamental architecture of a multi-layered memory with word lines.
• US 2013/0272067 A1 describes a "non-boosting program inhibit scheme in NAND design" that aims to achieve a more reliable program inhibit operation in NAND flash memories. This patent discusses applying different voltages (e.g., a "decoupling voltage" lower than a "blocking voltage" and a "pass voltage") to word lines to inhibit programming of unselected cells and reduce program disturb. A PHOSITA would understand that different voltage levels applied to word lines at varying distances from the selected word line can effectively control program disturb.

Motivation to Combine: A PHOSITA, motivated to further reduce program disturbance in multi-layered non-volatile memories (as acknowledged in US 2016/0071595 A1), would seek to optimize the application of voltages to unselected word lines. US 2013/0272067 A1 teaches applying different voltage levels (e.g., Vblock, Vdcp, Vpass) to word lines based on their proximity and role in program inhibition, with Vdcp being lower than Vblock and Vpass. Applying this principle to a segmented memory structure as suggested by US 2012/0163096 A1, where word lines are conceptually grouped into "portions," would be a logical next step. The explicit disclosure in US 2013/0272067 A1 that a decoupling voltage (Vdcp) is lower than a blocking voltage (Vblock) and that Vdcp can be applied to word lines further away from the selected word line (e.g., "to at least one or more wordlines adjacent to a wordline to which the blocking voltage Vblock is applied, or applied to an upper wordline most adjacent to a selected wordline during a programming operation") provides a clear motivation for applying progressively lower voltages to word lines in portions further away from the programmed word line. This directly anticipates the concept of applying a fifth voltage lower than a fourth voltage to word lines in portions further from the selected word line, as claimed in claim 1 of US 11568941.

Reasonable Expectation of Success: The principles of applying varied pass voltages to reduce program disturb are well-established in the prior art. The combination merely applies these known principles within a segmented memory structure, which is a common way to organize memory cells in 3D NAND. The expectation of success would be high as it directly leverages established techniques for voltage application to mitigate program disturb.

B. Obviousness of Claim 5

Claim 5 describes a program method for a memory with first and second portions, comprising applying a first voltage to first to (x-2)th word lines, a second voltage to an (x-1)th word line, and a third voltage to an (x+1)th word line when an xth word line is used to perform a program operation.

Combination 2: US 6,061,270 A in view of US 2009/0257280 A1 and US 2016/0071595 A1

• US 6,061,270 A describes a "method for programming a non-volatile memory device with program disturb control," indicating a general awareness of the problem and the need for solutions.
• US 2009/0257280 A1 discloses a NAND flash memory device and methods of operating it, implying a multi-layered structure with numerous word lines.
• US 2016/0071595 A1 explicitly teaches "controlling pass voltages to minimize program disturb in charge-trapping memory." It further elaborates on applying modified pass voltages to reduce program disturb.

Motivation to Combine: A PHOSITA would recognize the pervasive problem of program disturbance in NAND flash memories, as highlighted by US 6,061,270 A. Given the teaching in US 2016/0071595 A1 regarding the use of "modified pass voltages" to reduce program disturb, a PHOSITA would be motivated to apply different voltage levels to word lines surrounding the selected word line during a program operation. The specific arrangement of applying different voltages to WL(x-2) and below, WL(x-1), and WL(x+1) represents a straightforward and logical segmentation of unselected word lines for differential voltage application to optimize program disturb reduction. This is a common strategy in memory design to precisely control electrical fields and minimize unwanted programming. The description of applying a "first voltage V1 to the first word line WL1 to an (x-2)th word line WL(x-2); a second voltage V2 to an (x-1)th word line WL(x-1); and a third voltage V3 is applied to an (x+1)th word line WL(x+1)" in US 11568941 is a specific implementation of applying modified pass voltages around the programmed word line.

Reasonable Expectation of Success: The concept of applying different voltages to adjacent and non-adjacent unselected word lines is a well-known technique in the field of non-volatile memory to manage electric fields and prevent disturb. The specific voltage levels and ranges would be a matter of routine optimization for a PHOSITA based on device characteristics.

C. Obviousness of Claim 11

Claim 11 describes a program method of a memory with a first portion and a second portion formed below the first portion, involving applying a first voltage to (x+2)th to nth word lines, a second voltage to an (x+1)th word line, a third voltage to an (x-1)th word line, a fourth voltage to (m+1)th to (x-2)th word lines, and a fifth voltage to (k+1)th to mth word lines, where the fifth voltage is lower than the fourth voltage. This claim introduces a memory structure where the portions are arranged such that the programmed word line can be in an upper portion, requiring voltages to be applied to word lines both above and below it, with a specific voltage gradient for lower portions.

Combination 3: US 2016/0071595 A1 in view of US 2012/0163096 A1 and US 2013/0272067 A1, further considering the general knowledge of multi-deck/multi-layer 3D NAND structures (e.g., as described in US 2009/0257280 A1 or US 11568941 itself, which explicitly mentions 3D stack NAND flash memory in its background).

• US 2016/0071595 A1 and US 2012/0163096 A1 and US 2013/0272067 A1 provide the basis for applying varying pass voltages and a voltage gradient (lower voltage for further portions) to mitigate program disturb, as discussed for Claim 1.
• The general knowledge of multi-deck/multi-layer 3D NAND structures is widely recognized in the field. The background of US 11568941 itself states that "a memory with a three-dimensional structure has been developed" to increase capacity, and "a three-dimensional stack NAND flash memory can be available presently." US 2009/0257280 A1 relates to NAND flash memory, which is commonly implemented in 3D structures. Other references, such as US 2023/0395495 A1, refer to "stack structure including gate lines stacked to be spaced apart from each other" in the context of memory devices, and US 2017/0148520 A1 describes a semiconductor memory device with a memory cell array including a plurality of non-volatile memory cells grouped in pages and blocks. The concept of dividing a 3D memory array into logical or physical portions is also shown in US 11488976B2, which discusses a semiconductor memory device with a "stack with a cell area and a connection area."

Motivation to Combine: A PHOSITA, faced with the need to manage program disturbance in advanced 3D NAND architectures that involve multiple stacked layers and distinct "portions" or "decks" (as discussed in the background of US 115689941), would be motivated to extend the voltage application schemes of US 2016/0071595 A1 and US 2013/0272067 A1 to such structures. The explicit mention in US 11568941 of different portions (e.g., "first portion," "second portion," "third portion") and the strategic application of voltages to these portions based on the location of the programmed word line (e.g., lower voltage for a lower portion, V76 < V75 < V74) directly builds upon the established principle of differentiated voltage application to reduce disturb. The PHOSITA would recognize that in a multi-layered memory, word lines can exist both above and below the currently programmed word line, and that adjusting voltages in these areas, particularly applying lower voltages to further-removed portions, would be a logical step to effectively mitigate program disturbance. This is explicitly stated in US 11568941 as a means to reduce "program disturbance and pass voltage disturbance".

Reasonable Expectation of Success: The expectation of success is high because the combination involves applying known principles of program disturb reduction (differentiated pass voltages) to a known memory architecture (3D multi-layered NAND with logical or physical portions). The specific voltage values and ranges would be empirically determined during the design and optimization phase, which falls within the routine skill of a PHOSITA.

IV. Conclusion

Based on the analysis of the prior art, the claims of US 11568941 appear to be obvious under 35 U.S.C. § 103. The various combinations of prior art references demonstrate that a person having ordinary skill in the art would have been motivated to combine the existing techniques for reducing program disturbance by applying different voltages to word lines in a multi-layered non-volatile memory, with a reasonable expectation of success. The specific arrangement of dividing the memory into "portions" and applying a voltage gradient to these portions represents an optimization of known principles rather than a novel inventive step.