Invalidity dossier
US 8787060
Method and apparatus for optimizing driver load in a memory package
Current assignee: Netlist, Inc.
Added 9/28/2026, 7:32:16 PM
Active provider: DeepSeek · deepseek-v4-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
I'll search for authoritative information on this patent and any 2026 CAFC activity.
Let me verify the independent claims and the 2026 appellate posture more precisely.
Let me check the specific 2026 docket number listed for this patent.
US Patent 8,787,060 — Analyst Summary
Scope note: All searches were run against the literal identifier 8787060 (granted as US 8,787,060 B2, application 13/288,850). Family members and similar numbers (e.g., 8,787,600; 9,318,160; 9,659,601) are flagged where relevant but not conflated.
Date caveat (important): Your prompt sets the current date as April 26, 2026, but the live results I retrieved — and the patent-page fetch itself — are dated September 2026, and they report CAFC events from September 2, 2026. The findings below reflect what the live records show, including that September activity. I flag this rather than silently reconciling it.
1. Bibliographic data
| Field | Value |
|---|---|
| Patent number | US 8,787,060 B2 |
| Title | Method and apparatus for optimizing driver load in a memory package |
| Inventor | Hyun Lee (Ladera Ranch, CA) |
| Assignee | Netlist, Inc. (Irvine, CA) — original assignee and current assignee |
| Application no. | 13/288,850 |
| Filing date | November 3, 2011 |
| Earliest priority | November 3, 2010 (US provisional 61/409,893, "Architecture for memory module with packages of three-dimensional stacked (3DS) memory chips") |
| Issue date | July 22, 2014 |
| Publication (pre-grant) | US 2012/0106228 A1, May 3, 2012 |
| Claims / drawings | 34 claims, 8 drawing sheets |
| Classifications | G11C 5/06; G11C 5/066; G11C 7/1057; G11C 7/1084; G11C 7/12 |
| Adjusted expiration | ~February 14, 2032 (per Google Patents' legal-status field) |
| Primary examiner / counsel | Huan Hoang / Jamie J. Zheng (per printed patent) |
2. Abstract (verbatim)
An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect.
Note on a common trap: the abstract and the "Summary" section describe the application as originally drafted (with "data port" limitations). The granted claim 1 does not recite "data ports" in the interconnect limitations — Netlist amended those out during prosecution (Aug. 6, 2013 amendment), and the district court relied on that prosecution history in claim construction. Don't quote the Summary as if it were the claims.
3. Independent claims — plain language
The patent has four independent claims: 1, 11, 20, and 29. Claims 1, 11, and 29 are the ones the PTAB identified as sharing the "control circuit … respective states" limitation. High confidence on 1, 11, 20, 29; the full verbatim text of claim 29 below is reconstructed from the pre-grant/specification language and partial quotations, so treat its exact wording as lower confidence.
Claim 1 — the core memory package. A stacked-die memory package with external I/O terminals and a control die. The stacked array dies are split into a first group and a second group. A first die interconnect (e.g., a TSV) connects to the first group but not the second; a second die interconnect connects to the second group but not the first. The control die has two data conduits (e.g., drivers) both running between their respective die interconnects and the same data terminal, plus a control circuit that sets the states of those two conduits in response to control signals on other terminals. In plain terms: instead of one big driver pushing one data bit to every die in the stack, you split the stack into subsets and give each subset its own smaller driver, halving each driver's capacitive load.
Claim 11 — memory package with chip-select steering. Similar stacked-package structure, but adds chip select conduits that deliver chip-select signals to the individual array dies, and requires the control circuit to control the two data conduits so as to drive the data signal to the array die selected by the chip-select signal. This is the "selective isolation" behavior described in the specification (a driver for a non-selected die holds its previous state rather than driving).
Claim 20 — method of optimizing load. A method practiced on such a package: receive the data signal at a first I/O terminal; receive control signals at second terminals; route chip-select signals to the array dies through the control die; and select one of two drivers in the control die to drive the data signal down its corresponding die interconnect to the chip-selected array die — where each interconnect reaches its own group of dies and not the other's.
Claim 29 — memory module / RDIMM-style system claim. Directed at the module level: a register device that takes command/address signals from a memory control hub and generates control signals, plus multiple DRAM packages, each with a control die containing command/address buffers and a data path control circuit governing command/address and data-bus time slots. The control die receives data from the hub and control/address from the register. The module is selectively configurable into two operational modes: in the first, the register generates the data path control signals and the control die uses them (the HCDIMM/RDIMM-compatible mode); in the second, the control die itself provides command/address to the DDR DRAM dies without decoding them (the 3DS-DIMM-compatible "address pass-through" mode).
Dependent claims of litigation interest: Claim 7 (group sizes chosen considering interconnect + die loads to reduce the load difference between the two conduits) and claim 15 (both drivers smaller than a driver sized to drive all dies without significant signal degradation) were separately argued on appeal.
4. 2026 litigation / PTAB posture (as shown in live records)
- PTAB: IPR2022-01428 (Samsung, with Micron/Micron Semiconductor Products/Micron Technology Texas joined) and IPR2023-00882 (Micron) challenged claims 1–34. Final Written Decision April 1, 2024: all challenged claims unpatentable as obvious over Kim + Rajan, and variously Kim + Rajan + Riho and Kim + Rajan + Wyman.
- CAFC: Netlist appealed Aug. 19, 2024 → No. 24-2241, consolidated Sept. 6, 2024 with the '160 appeal, No. 24-2240.
- 2026 outcome reported: a nonprecedential Federal Circuit opinion dated September 2, 2026 (Reyna/Linn/Stark panel) affirming the Board's finding that all claims of the '060 and '160 patents are unpatentable as obvious. Netlist's motivation-to-combine, claim 7, and claim 15 arguments were rejected; the APA arguments were rejected. Per IPWatchdog and the Fed Circuit Blog's September 2, 2026 roundup.
- Other live tracks involving the '060: the Google Patents page lists CAFC dockets 24-2203, 24-2241, and 26-1671, plus E.D. Tex. cases 2:21-cv-00463, 2:22-cv-00203, 2:23-cv-00628 and Idaho District Court cases 1:24-cv-00081 and 1:25-cv-00323 (Micron's Idaho bad-faith-patent-assertion suits, which expressly name the '060). Case 24-2203 is Netlist's appeal from the April 21, 2023 E.D. Tex. jury verdict (~$300M) that found Samsung infringed several Netlist patents including the '060.
- Also of note: a further Samsung petition referencing the '060 appears as IPR2025-01402 (exhibits dated Aug. 2025).
Uncertainty: I could not independently confirm what CAFC docket 26-1671 is from the retrieved results — it appears on the Google Patents litigation table but I found no docket description. I also could not verify whether the September 2026 mandate has issued or whether any further petition (e.g., en banc or certiorari) was filed. Given the date mismatch between your prompt and the retrieved records, please re-verify current status directly at the CAFC docket and USPTO PatentCenter before relying on it.
Generated 9/28/2026, 8:33:24 PM
Cases on file (1)
Group view →Specific litigation cases in our database that name US patent 8787060. The free-form analysis below may also discuss cases beyond this list.
- Netlist, Inc. v. Samsung Electronics Co., Ltd. et al.filed Aug 19, 20242024-2240U.S. Court of Appeals for the Federal Circuitpending
Defendants: Samsung Electronics Co., Ltd., Micron Technology Inc., Micron Semiconductor Products, Inc., and 1 other
Other patents asserted: 9318160
Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
I'll research litigation involving US patent 8787060. Let me run several searches in parallel.
Let me dig deeper into specific cases and their statuses.
Litigation Involving U.S. Patent No. 8,787,060 ("the '060 Patent")
Patent owner: Netlist, Inc. (Irvine, CA)
Title: "Method and apparatus for optimizing driver load in a memory package"
Priority: Nov. 3, 2010 | Filed: Nov. 3, 2011 | Granted: July 22, 2014 | Adjusted expiration: Feb. 14, 2032
Status note: Google Patents records the patent as Active but flags PTAB case IPR2023-00882 (Final Written Decision) and multiple litigation entries. Caution: a PTAB Final Written Decision in IPR2022-01428 (Apr. 1, 2024) held all challenged claims of the '060 Patent unpatentable. The '060 Patent is therefore under an adverse validity cloud / appeal, notwithstanding its "Active" administrative status.
Below I separate litigation (district court / appellate) from PTAB post-grant proceedings (administrative trials, not "litigation" in the strict sense, but directly tied to the '060 Patent).
A. District Court Litigation Asserting (or Directly Involving) the '060 Patent
| # | Plaintiff(s) | Defendant(s) | Jurisdiction | Case No. | Filing Date | Outcome / Current Status |
|---|---|---|---|---|---|---|
| 1 | Netlist, Inc. | Samsung Electronics Co., Ltd.; [[Samsung Electronics America](/litigations/by-defendant/Samsung%20Electronics%20America), Inc.](/litigations/by-plaintiff/Samsung%20Electronics%20America%2C%20Inc.); Samsung Semiconductor, Inc. | E.D. Tex. (Marshall Div.), Chief Judge Rodney Gilstrap | 2:21-cv-00463-JRG | Dec. 20, 2021 (per PTAB brief; Docket Alarm) | Netlist won at trial. Netlist amended its complaint to add the '060 (and '160) patents. Jury verdict Apr. 21, 2023 found Samsung willfully infringed claims 1, 5, 7 of the '060 Patent (and claim 5 of the '160 Patent); none invalid. Final Judgment entered Aug. 11, 2023 awarding $303,150,000 composite reasonable royalty (of which $122,775,000 allocated to the '060 + '160 patents) plus pre/post-judgment interest and costs. Enhanced damages denied. Samsung's post-trial challenge to the $303M verdict was rejected (opinion unsealed July 2024). Note: the '060 Patent was invalidated by the PTAB in parallel IPR2022-01428 (Apr. 1, 2024), and the district court declined to stay the case. |
| 2 | Netlist, Inc. | Samsung Electronics Co., Ltd. et al. | E.D. Tex. | 2:22-cv-00293-JRG | 2022 (per CourtListener docket) | Second Samsung case. The '060 Patent appears in claim-construction / file-history exhibits (Dkt. 94-2, filed July 13, 2023). The trial in the 2024 timeframe concerned the '912, '417, and '608 patents ($118M verdict Nov. 22, 2024), not the '060 Patent. Status as to the '060 Patent itself not confirmed. |
| 3 | Netlist, Inc. | Micron Technology, Inc. et al. | E.D. Tex. | 2:23-cv-00628 | 2023 (per NPE Litigation Database / Google Patents) | Asserted by Netlist against Micron; the '060 Patent is listed among the patents-in-suit. Trial stayed pending PTAB decisions on the patents (Judge Gilstrap declined to lift the stay). Current status unconfirmed. |
| 4 | Micron Technology, Inc.; Micron Semiconductor Products, Inc. | Netlist, Inc. | D. Idaho (Judge David C. Nye) | 1:24-cv-00081 | 2024 (per Google Patents / PatSnap) | Remanded to Idaho state court (Ada County, Fourth Judicial District); federal case CLOSED. Six patents at issue incl. US 8,787,060. Remand was procedural — no merits ruling; no federal preclusion effect. |
| 5 | Micron Technology, Inc. et al. | Netlist, Inc. | D. Idaho | 1:25-cv-00323 | 2025 (per Google Patents) | Listed on Google Patents as a US case filed in Idaho District Court. Details/outcome not confirmed. |
| 6 | Netlist, Inc. | Samsung Electronics Co., Ltd. et al. | E.D. Tex. | 2:25-cv-00557 | 2025 (per NPE Litigation Database / Google Patents) | Listed as involving the '060 Patent. Current status not confirmed. |
| 7 | Micron Technology, Inc. et al. | Netlist, Inc. | D. Del. | 1:25-cv-00629 | 2025 (per NPE Litigation Database) | Listed as involving the '060 Patent. Current status not confirmed. |
| 8 | Netlist, Inc. | Samsung Electronics Co., Ltd. et al. | E.D. Tex. | 2:22-cv-00203 | 2022 (per Google Patents) | Listed on the Google Patents litigation feed. Relevance to the '060 Patent not independently confirmed. |
B. International Trade Commission (ITC) Proceedings
The '060 Patent is part of the Netlist portfolio litigated before the ITC against SK hynix (RDIMM/LRDIMM products) and, more recently, against Samsung and certain customers (filed Sept. 2025, asserting six patents). I could not confirm that the '060 Patent specifically is asserted in the most recent ITC action, and I could not retrieve a docket number. This should be verified before relying on it.
C. PTAB Post-Grant Proceedings on the '060 Patent (U.S. Patent 8,787,060)
| Proceeding | Petitioner | Filed | Outcome / Status |
|---|---|---|---|
| IPR2022-01428 | Samsung Electronics Co., Ltd. | Aug. 26, 2022 | Final Written Decision Apr. 1, 2024: all challenged claims unpatentable; Petitioner's motion to exclude dismissed. Director review denied June 17, 2024. On appeal. |
| IPR2023-00882 | Micron Technology, Inc. et al. (incl. Micron Technology Texas LLC) | May 8, 2023 | Joined to IPR2022-01428 (institution decision Oct. 26, 2023); Final Written Decision entered Apr. 1, 2024 (all challenged claims unpatentable). Status: Final Written Decision – Appealed. |
| IPR2022-01315 | Roku, Inc. | July 27, 2022 | Challenged claims 1–23. Institution DENIED Mar. 13, 2023 (no reasonable likelihood); Director review denied. |
| IPR2022-01505 | Samsung Electronics Co., Ltd. | Sept. 7, 2022 | Same grounds as Roku; Samsung moved for joinder. Joinder and institution DENIED Mar. 22, 2023. |
| IPR2023-01281 | Meta Platforms (per petitioner declaration) | 2023-24 | Instituted Feb. 21, 2024 (asserted Sitaraman, U.S. 6,427,170). Status not confirmed. |
D. Appellate Proceedings (Federal Circuit)
| Case No. | Caption | Status |
|---|---|---|
| 24-2203 | Listed on Google Patents litigation feed for the '060 Patent | Pending/unconfirmed |
| 24-2241 | Listed on Google Patents litigation feed for the '060 Patent | Pending/unconfirmed |
| 26-1671 | Listed on Google Patents litigation feed for the '060 Patent | Pending/unconfirmed |
| 24-1859 / 24-1863 | Netlist, Inc. v. Samsung Electronics Co., Ltd. / Micron Semiconductor Products, Inc. | Nonprecedential opinion by Judges Reyna, Linn, Stark (Sept. 2, 2026). Related to the '060/'160 family appeals. |
| (Unnumbered, argued Sept. 2026) | Netlist, Inc. v. Micron Technology, Inc. (formerly Netlist v. Samsung) | Fed. Cir. oral argument on PTAB invalidation of a Netlist patent; Judges Dyk, Linn, Chen. |
E. Key Caveats
- PTO administrative trials (IPRs) are generally not considered "litigation." I have listed them because they are the primary events determining the '060 Patent's enforceability and are referenced on the patent's Google Patents page.
- The '060 Patent was held unpatentable in IPR2022-01428 (and the joined IPR2023-00882) on Apr. 1, 2024; a $122.775M portion of the $303M Samsung judgment rested on the '060 Patent. The outcome of the pending Federal Circuit appeals (24-2203, 24-2241, 26-1671) will determine finality.
- Some entries (cases #5–#8, and the ITC and Meta IPR items) could not be fully verified in my search. I flag these rather than assert them as confirmed.
- Case numbers, filing dates, and post-2025 statuses should be confirmed against PACER / CourtListener and the USPTO Patent Trial and Appeal Board (PTAB) PatentCenter, and cross-checked on the Unified Patents litigation portal (https://portal.unifiedpatents.com/litigation/caselist) and the Stanford NPE Litigation Database (https://npe.law.stanford.edu/patent/8787060).
Bottom line: Yes — substantial litigation is known. The most significant is Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No. 2:21-cv-00463-JRG (E.D. Tex.), where the '060 Patent was found willfully infringed and supported part of a $303.15M final judgment (Aug. 11, 2023) — but the patent was later invalidated by the PTAB (Apr. 1, 2024) and remains on appeal. Additional suits involve Micron (E.D. Tex. 2:23-cv-00628; D. Idaho/state court actions) and later Samsung actions (E.D. Tex. 2:25-cv-00557).
Sources: Google Patents US8787060B2; Unified Patents PTAB/litigation portal; CourtListener (Dkt. 479, 551, 94-2); Netlist investor press releases (Apr. 24, 2023; Aug. 14, 2023); Docket Alarm; Stanford NPE Litigation Database; PatSnap litigation analysis; Law360 case summary; Fed Circuit Blog (Sept. 18, 2026).
Generated 9/28/2026, 8:33:38 PM
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
Current assignee: Netlist, Inc.
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
I'll research the PTAB proceedings on US 8787060. Note at the outset: the structured block says ODP shows none, but the patent's own Google Patents page lists IPR2022-01428 and IPR2023-00882 — both with Final Written Decisions. Let me verify.
Strong signal already. Let me pull the details on institution reasoning, the joinder, the newer 2025 filings, and the appeals.
PTAB Proceedings on US 8,787,060 — Defendant-Facing Analysis
⚠️ Reconciliation of sources first. The structured "PTAB proceedings on file" block in this prompt states that the USPTO ODP API returns no AIA trial proceedings for US 8,787,060. That is wrong — it reflects an ingest gap, not an absence of activity. Two IPRs on this patent went to Final Written Decision, and the patent's own Google Patents record lists both (https://patents.google.com/patent/US8787060/en, "Family has litigation / PTAB case" entries). Both proceedings are also documented in PTAB Final Written Decisions, PTAB E2E filings, and Federal Circuit docketing records. I am reporting the two verified proceedings below and flagging the newer 2025–2026 family filings that are not on this patent.
Proceedings overview
Two AIA trials have been filed against US 8,787,060 — both inter partes reviews, both instituted, and in both the Board held all 34 challenged claims unpatentable; the resulting Final Written Decisions are on appeal to the Federal Circuit, so no certificate of cancellation has issued and the patent's Google Patents status still reads "Active." Breakdown: 0 settled, 0 institution denials, 2 claims-invalidated decisions (1 standalone + 1 me-too joinder that rode the same FWD), 0 sustained claims. For a defendant today: every claim of this patent — claims 1–34, the entire claim set — has been held unpatentable by the PTAB, and the patent survives only because Netlist appealed. The patent is not "hardened"; it is living on borrowed time, and any demand letter citing this patent is citing claims that two separate panels (2024-04-01) found invalid.
IPR2022-01428 — Samsung Electronics Co., Ltd. v. Netlist, Inc. (impact: entire claim set invalidated)
Type: Inter Partes Review (35 U.S.C. §§ 311–318)
Filed: 2022-08-26 (Samsung filed the '060 petition and a companion '160 petition, IPR2022-01427, the same day)
Status:
Final Written Decision - Appealed— FWD issued 2024-04-01 finding claims 1–34 unpatentable; Netlist noticed appeal 2024-08-19Judge panel: Jon M. Jurgovan, Daniel J. Galligan, and Sheila F. McShane, Administrative Patent Judges; Judge Galligan authored the Final Written Decision. (The institution decision in this docket is also associated with Patrick M. Boucher's participation in third-party panel data; I flag that the FWD caption controls and lists Jurgovan/Galligan/McShane.)
Petition grounds: Samsung challenged all of claims 1–34. Per Petition at 3, the documented rows of the grounds table are:
Claims Challenged Basis References 1–6, 8–14, 16–19, 29–34 § 103(a) (pre-AIA) Kim, Rajan 1–14, 16–19, 29–34 § 103(a) (pre-AIA) Kim, Rajan, Riho The petition presented at least four grounds (the record references "Ground 4"), with the remaining independent/dependent claims (including claims 7, 15, and 20–28) folded into additional Riho/Wyman-based § 103 combinations. Pre-AIA § 103 applied based on the '060 patent's effective filing date of 2011-11-03. Key references across the record: Kim (US 2011/0103156 A1, Hynix), Rajan (US 8,041,881 B2 / US 2008/0025137, MetaRAM), Riho (US 2011/0026293 A1 / US 2010/0195364 A1, Elpida), and Wyman (US 7,969,192).
Institution decision: Instituted 2023-04-12 (Paper 13 at 27–28), on all asserted grounds. Netlist argued discretionary denial under Apple v. Fintiv based on the parallel E.D. Tex. action (Netlist v. Samsung, No. 2:21-cv-00463), invoking § 314(a). The panel declined to exercise Fintiv discretion and instituted. (See the institution decision excerpt reproduced in the E.D. Tex. record at https://archive.org/download/gov.uscourts.txed.[211544](/patent/211544)/gov.uscourts.txed.211544.454.1.pdf.)
Final Written Decision (2024-04-01, Paper 48): "JUDGMENT — Final Written Decision Determining All Challenged Claims Unpatentable." The Board held: "For the reasons discussed below, we determine that Petitioner has proven by a preponderance of the evidence that claims 1–34 of the '060 patent are unpatentable." The order reads:
"ORDERED that claims 1–34 of the '060 patent have been shown to be unpatentable; FURTHER ORDERED that Petitioner's Motion to Exclude (Paper 34) is dismissed…"
Claim-level outcome: no claim survived. No independent claim, no dependent claim, no claim held patentable. Expert record: Dr. Andrew Wolfe (Ex. 1003) for Petitioner; Dr. Michael C. Brogioli (Ex. 2023) for Netlist. Oral hearing held 2024-01-11 (Paper 46).
FWD copy: https://www.docketalarm.com/cases/PTAB/IPR2025-01402/Samsung_Electronics_Co._Ltd/docs/08-25-2025-Petitioner/Exhibit-1072-EX1072___060_Final_Written_Decision_invalidating_all_claims.pdfSettlement / termination: None. The proceeding ran to a merits FWD; it was not terminated by settlement.
Joinder: After Samsung's Reply, Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC were joined as petitioners to IPR2022-01428 (Paper 25) via the me-too petition and motion in IPR2023-00882 (below).
Director Review: Netlist requested Director Review of the FWD (Paper 50). Denied — "the requests for Director Review are denied; and … the Patent Trial and Appeal Board's Final Written Decision in these cases is the final decision of the agency" (Paper 52, 2024-06-17). Director Vidal was recused; the request was referred to the Acting Director.
Appeal: Yes. Netlist filed a Notice of Appeal on 2024-08-19 (executed/dated Aug. 19, 2024, Irell & Manella for Netlist; served on Baker Botts for Samsung and Winston & Strawn for Micron), docketed as Fed. Cir. No. 2024-2241 (Notice of Docketing 2024-08-20), consolidated with No. 2024-2240 (appeal from the companion '160 FWD, IPR2022-01427). Netlist's stated issues: the Board's compliance with the APA, the FWD, the denial of Director Review, the denial of Netlist's request to submit supplemental evidence, and "all other issues decided adversely to Netlist." The appeals were later ordered treated as companion cases with Samsung's district-court appeal No. 2024-2203 and assigned to the same merits panel (Fed. Cir. order, 2024-09-12). I have not verified a Federal Circuit disposition; the most recent records I retrieved describe the appeal as pending, and Netlist's opening brief in 24-2240 was filed (Ex. 2027 in IPR2025-01402). Oral argument addressed, among other things, whether Riho teaches "selecting the number of arrayed I/Os … to reduce a difference in load."
Defensive value: This is the single most useful proceeding for a defendant. Claim 1 and every other claim of the '060 patent were held unpatentable, and the Board's conclusions are now the agency's final decision. If someone asserts the '060 patent today, the FWD is your centerpiece: it is a full, on-the-merits invalidation of claims 1–34. It is not binding on a non-privy defendant, but it is devastating persuasive authority, and it is the reason the E.D. Tex. court kept its Micron case stayed.
IPR2023-00882 — Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC v. Netlist, Inc. (impact: me-too joinder; same claims invalidated)
Type: Inter Partes Review — institution + joinder under 35 U.S.C. § 315(c) and 37 C.F.R. § 42.122(b)
Filed: 2023-05-08 (Petition, Paper 2; Motion for Joinder, Paper 3 — filed within one month of the 2023-04-12 institution date in IPR2022-01428)
Status:
Final Written Decision - Appealed— terminated 2024-04-01 following a FWD rendering all challenged claims unpatentableJudge panel: Patrick M. Boucher, Daniel J. Galligan, and Sheila F. McShane, Administrative Patent Judges. Decision granting institution and joinder issued 2023-10-26 (signed 2023-10-26); Judge Galligan later authored the FWD (Docket Navigator lists Galligan as writing the final decision).
Petition grounds: Substantively identical to Samsung's petition in IPR2022-01428 — "Micron's Petition seeks review of the same patent claims challenged in the Samsung IPR, advances the same grounds for unpatentability that were instituted in the Samsung IPR, and relies on the same evidence (including expert declarations)." Same § 103(a) grounds; same claims 1–34; same Kim / Rajan / Riho / Wyman references.
Institution decision: Instituted and joinder granted, 2023-10-26. Reasoning, verbatim:
"We determine that Petitioner has demonstrated a reasonable likelihood of prevailing with respect to at least one challenged claim of the '060 patent for the reasons given in the institution decision in the 1428 IPR and that the Petition warrants institution."
Critically, the Board rejected the notion of joining two proceedings (a § 315(c) limit under Facebook v. Windy City Innovations, 973 F.3d 1321 (Fed. Cir. 2020)) and "treat[ed] Petitioner's Motion for Joinder as a request to be joined as a petitioner to the 1428 IPR." Micron agreed to an "understudy" role — no substantive filings, bound by Samsung's filings, no deposition cross-examination or witness defense, and would step into the primary role only if Samsung exited. Samsung did not oppose; Netlist did not oppose and did not file a Preliminary Response.
Final Written Decision (2024-04-01): Same disposition as the lead '060 IPR — all challenged claims (1–34) determined unpatentable, Petitioner's Motion to Exclude dismissed. The '00882 FWD mirrors the '00882/01428 disposition paper-for-paper ("Determining All Challenged Claims Unpatentable; Dismissing Petitioner's Motion to Exclude, 35 U.S.C. § 318(a)").
Settlement / termination: None.
Appeal: Yes — Fed. Cir. No. 2024-2241 (consolidated with 2024-2240; companion to 2024-2203). Micron is an appellee alongside Samsung. Netlist's Notice of Appeal was served on both Baker Botts (Samsung) and Winston & Strawn (Micron).
Defensive value: This is a joinder, not an independent merits win — it produced no separate claim-level holding and no separate estoppel-generating analysis beyond the lead IPR's. Its real significance is estoppel breadth: Micron, as a joined petitioner, is subject to § 315(e)(2) estoppel on the '060 patent as of 2024-04-01, which is why Micron could not re-run these grounds and why the E.D. Tex. stay in Netlist v. Micron (No. 2:22-cv-00203) held.
⚠️ Not on this patent — 2025–2026 activity in the same family (context only)
The following 2025 filings do not target US 8,787,060 and should not be listed as '060 proceedings. I flag them because a defendant researching Netlist's '060 family will encounter them, and because they are the current battleground:
- PGR2025-00071 (Samsung v. Netlist) — US 12,308,087, a later family member claiming priority through the same chain (App. 17/694,649). Filed 2025-08-25; institution granted 2026-02-18; Netlist filed a Request for Director Review 2026-03-04. Status: Trial Instituted.
- IPR2025-01402 (Samsung v. Netlist) — US 12,308,087. Filed 2025-08-25; institution DENIED 2026-02-18; case terminated. Netlist argued failure to name Samsung Electronics America and Avnet as real parties in interest (Corning Optical / § 312(a)(2)).
- IPR2025-01431 (Samsung v. Netlist) — US 10,025,731.
- IPR2026-00017 ('035), IPR2026-00018 ('366), PGR2026-00001 ('366).
In PGR2025-00071 and IPR2025-01402, Samsung's own exhibit lists include the '060 patent (Ex. 1069), the '060 prosecution history (Ex. 1070), the '060 FWD (Ex. 1072), and the Order Denying Director Review in IPR2022-01427/-01428 (Ex. 1074) — i.e., the '060 invalidation is now baked into how both sides litigate the family.
Strategic summary
Claim status. Claims 1–34 — the entire claim set — are CANCELED-in-effect but not yet CANCELED in law. The Board found all 34 claims unpatentable on 2024-04-01 in IPR2022-01428 (with IPR2023-00882 riding along). Because Netlist timely appealed to the Federal Circuit on 2024-08-19 (No. 2024-2241), no certificate of cancellation has issued and the patent still shows as Active (Google Patents adjusted expiration 2032-02-14). There are zero SUSTAINED claims and zero UNTESTED claims — the petition challenged the full claim set and the FWD reached all of it. If the Federal Circuit affirms, the patent is a dead letter; if it reverses on a subset, that subset revives. Do not assume cancellation for § 282/§ 315 purposes until the mandate issues — but also do not let opposing counsel tell you the patent is intact.
Notably, the PTAB's all-claims outcome supersedes the 2023 jury verdict: in Netlist v. Samsung, No. 2:21-cv-00463 (E.D. Tex.), the April 2023 jury found Samsung willfully infringed the '060 and '160 patents and awarded $122,775,000 of a $303,150,000 total on the '060/'160 pair, finding the claims not invalid. The PTAB then invalidated all of them. Judge Gilstrap, in Netlist v. Micron, No. 2:22-cv-00203, maintained the stay (Order #501, 2024-06-13) precisely because "the PTAB issued its final written decisions in IPR2022-01427 and IPR2022-01428, finding all asserted claims in U.S. Patent Nos. 8,787,060 and 9,318,160 … to be invalid," adding that "all asserted claims in the above-captioned case have been declared invalid by the PTAB."
Estoppel landscape. § 315(e)(2) estoppel attached to Samsung (and its privies) and, by joinder, to Micron/Micron Semiconductor Products/Micron Technology Texas on 2024-04-01, the FWD date. They are barred in district court and the ITC from asserting any ground they raised or reasonably could have raised — in practice, the whole Kim / Rajan / Riho / Wyman § 103 landscape for claims 1–34. Samsung in fact stipulated in the ITC matter that it will not pursue invalidity on grounds raised or reasonably could have been raised in its instituted PTAB petitions (Samsung ITC stipulation, 2026-03-03). For a new, non-privy defendant, none of that estoppel transfers — but practically nothing is left to attack, since every claim is already adjudicated unpatentable. Your viable theories are (a) affirm-and-be-done if the appeal resolves against Netlist, or (b) if the CAFC revives claims, a fresh IPR on art Samsung/Micron did not reasonably could have raised (e.g., system prior art, or a reference family outside Kim/Rajan/Riho/Wyman) — but expect General Plastic / § 325(d) friction given the number of prior family challenges, and expect Netlist to argue the RPI defect theory it is pressing against Samsung in the '087 proceedings.
Pattern signals. (1) Multiple petitioners, not multiple attacks: Samsung filed first (2022-08-26, on both the '060 and '160) and Micron filed a substantially identical me-too petition + joinder (2023-05-08) rather than independent art — this is the classic "understudy" strategy to survive a Samsung settlement, and the Board blessed it. (2) No defensive aggregator on this patent: despite the Google Patents record noting "PTAB case IPR2023-00882 filed (Final Written Decision)" and the general convention of Unified Patents involvement in the Netlist campaign, I found no Unified Patents (or other aggregator) petition on the '060 — both petitioners here are operating companies with direct infringement exposure. (3) Netlist litigates hard on appeal: it sought Director Review of the '060/'160 FWDs (denied 2024-06-17), appealed both, and is now contesting the '087 institution grant and pressing RPI/§ 312(a)(2) defects against Samsung's 2025–2026 petitions. (4) The family keeps producing new patents — US 12,308,087 (App. 17/694,649) claims the same lineage, which is why the '060 fight matters as precedent even though the '060 itself is invalidated.
Recommended next steps
If you are a defendant being asserted against on the '060 patent:
- Lead with the FWD. Pull IPR2022-01428, Paper 48 (PTAB 2024-04-01) and quote the disposition verbatim:
"ORDERED that claims 1–34 of the '060 patent have been shown to be unpatentable."
The Board's bottom line: "Petitioner has proven by a preponderance of the evidence that claims 1–34 of the '060 patent are unpatentable." A copy is available through PTAB E2E (https://ptacts.uspto.gov/ptacts/public-informations — IPR2022-01428) and as Exhibit 1072 in IPR2025-01402 (https://www.docketalarm.com/cases/PTAB/IPR2025-01402/Samsung_Electronics_Co._Ltd/docs/08-25-2025-Petitioner/Exhibit-1072-EX1072___060_Final_Written_Decision_invalidating_all_claims.pdf). - Attach the Director Review denial — Paper 52, 2024-06-17 — showing the FWD "is the final decision of the agency" as to the Board.
- Confirm current appellate status before you file anything. Docket Fed. Cir. No. 2024-2241 (Netlist's '060 appeal, consolidated with 2024-2240 and companion to 2024-2203). Do not represent to a court that claims are canceled — say they have been held unpatentable and the appeal is pending, and seek a stay pending resolution, citing Judge Gilstrap's 2024-06-13 stay order in No. 2:22-cv-00203.
- Assert collateral/issue-preclusion arguments only against Samsung or Micron (or their privies) — for anyone else, the FWD is persuasive, not binding. If the asserting party is Samsung or a Micron entity, also raise § 315(e)(2) estoppel as an independent bar on any § 102/§ 103 defense of claims 1–34.
- Watch the family. Netlist has Idaho District Court cases of record (1:24-cv-00081, 1:25-cv-00323) and a third Federal Circuit appeal on this patent's docket (26-1671, subject matter not confirmed in my sources). If a newly issued continuation in the '060 lineage is asserted instead — e.g., US 12,308,087 — the analysis changes completely: the '060 FWD does not invalidate the '087 claims, and Samsung's PGR2025-00071 against the '087 patent was instituted on 2026-02-18 (trial stage, with a statutory FWD deadline of roughly early 2027 absent extension).
If you simply want to know whether there is PTAB activity: there is — two IPRs, and the ODP-based "no proceedings on file" statement in the prompt is not accurate for this patent. Treat the Google Patents "PTAB case IPR2022-01428 filed (Final Written Decision)" and "PTAB case IPR2023-00882 filed (Final Written Decision)" entries, plus the 2024-04-01 FWDs, as the authoritative record.
Caveats I am deliberately not papering over: (a) I could not retrieve a Federal Circuit opinion or Rule 36 judgment disposing of 24-2240/24-2241 in the sources available; the appeal should be treated as pending unless you verify otherwise on the CAFC docket. (b) The full grounds table in the '060 FWD contains more rows than the two I reproduced; I quoted only what the retrieved record states verbatim, plus the record's references to "Ground 4." (c) The Board denied Director Review; I did not locate a subsequent sua sponte Director Review reopening. (d) Panel composition during the institution phase (Boucher) differs from the FWD caption (Jurgovan, Galligan, McShane) in third-party data; the FWD caption controls.
Generated 9/28/2026, 8:34:11 PM
Ownership chain (5)
Asserters network →Structured records extracted from the assignment-history narrative below. Each entity links to its full ownership-network profile.
2011-11-03 · recorded 2012-01-03 · Assignment
inventor-to-employer
2013-07-18 · Security Agreement
Netlist, Inc.DBD Credit Funding LLC
securitization
? · recorded 2015-11-20 · Security Interest
Netlist, Inc.SVIC No. 28 New Technology Business Investment L.L.P.
securitization
? · recorded 2015-12-03 · Release
DBD Credit Funding LLCNetlist, Inc.
lien release
? · recorded 2023-11-20 · Release
SVIC No. 28 New Technology Business Investment L.L.P.Netlist, Inc.
lien release
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
I'll research this patent's assignment record and litigation history. Let me start with parallel searches.
Let me search for specific assignment record details and current litigation status.
US 8,787,060 B2 — Assignment & Ownership Analysis
Data-source note (read first): I was able to retrieve the patent's full text and its Google Patents "Legal Events" record, and I cross-checked SEC filings (Netlist 10-K/10-Q/8-K) and PTAB/docket records. I could not obtain the USPTO Assignment Center reel/frame numbers or correspondents of record in this session — Google Patents' legal-event view does not expose them, and the Assignment Center's per-patent detail is not machine-retrievable here. Where reel/frame would normally appear below, I have marked it not retrieved rather than guess. Verify at https://assignmentcenter.uspto.gov/ (search patent 8,787,060) and https://patents.google.com/patent/US8787060/en.
Context anchor: the patent is a single-inventor case, App. No. 13/288,850, filed 2011-11-03, claiming priority to provisional 61/409,893 filed 2010-11-03, issued 2014-07-22. Claim 1 recites a memory package with a "first group of array dies and a second group of at least one array die," separate die interconnects per group, and a control die with per-group data conduits.
Inventors
- Hyun Lee, Ph.D. — sole named inventor; residence of record Ladera Ranch, CA (per the printed patent face, e.g. CourtListener reproduction of the '060 front page: https://storage.courtlistener.com/recap/gov.uscourts.txed.[215248](/patent/215248)/gov.uscourts.txed.215248.5.5.pdf).
- Employer at filing: Netlist, Inc. (Irvine, CA). Lee is a Netlist founder/executive-level inventor and is the named inventor across dozens of Netlist's memory-module patents (e.g., US 9,659,601; US 10,198,350; US 10,380,022), all filed while assigned/obligated to Netlist.
- No unusual departure pattern. There is no inventor-migration signal here: the inventor did not exit and re-file elsewhere, and the entire chain remains inside the original assignee. This is the opposite of the "inventors leave within 12 months → portfolio fire-sale" pattern.
Original assignee
Netlist, Inc., 175 Technology Drive, No. 150, Irvine, CA 92618 — named on the issued patent and the assignee of record throughout.
- Business: designer/supplier of high-performance memory subsystems (HyperCloud™ DIMM, NVvault™ non-volatile DIMM) for servers and OEMs. Publicly traded (Nasdaq: NLST), SEC CIK 1282631.
- Product embodiment: Netlist historically shipped memory modules, but the '060 claims a stacked-die memory package (control die + array dies + separate die interconnects). Netlist asserts this family as its "HBM/high-bandwidth memory package" technology (see its '087 complaint context: "Netlist's HBM technology…" — https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1558373](/patent/1558373)/download-documents). Whether Netlist currently ships a product that literally embodies claim 1 is not clearly established — the company's revenue has shifted heavily toward patent monetization/litigation.
- Current status: operating, not bankrupt. Active, publicly traded, and an aggressive litigant (2021–2025). The patent remains Active with adjusted expiration 2032-02-14 per Google Patents. Note that the PTAB found all challenged claims of the '060 patent unpatentable on 2024-04-01 (IPR2022-01428 / joined IPR2023-00882), and Netlist appealed (CAFC 2024-2241); the asset's enforceability is on appeal.
- Financing history (not title transfers): the "assignments" below are and always were security interests / liens, not conveyances of ownership. Netlist has never sold or assigned the '060 patent to a third party.
Assignment timeline
All entries below are recorded USPTO assignment events as surfaced by Google Patents Legal Events (https://patents.google.com/patent/US8787060/en). Reel/frame and correspondent were not retrievable in this session.
2011-11-03 (executed/filed) / recorded 2012-01-03 — Reel not retrieved
- Conveyance: Assignment of assignors' interest (inventor → company)
- Assignor: LEE, HYUN
- Assignee: NETLIST, INC.
- Correspondent: not retrieved
- Context: ordinary inventor-to-employer assignment; places original title in Netlist.
2013-07-18 (executed) / recorded 2013-07-18 — Reel not retrieved
- Conveyance: Security Agreement (IP lien)
- Assignor: NETLIST, INC.
- Assignee: DBD CREDIT FUNDING LLC (an affiliate of Fortress Investment Group LLC)
- Correspondent: not retrieved
- Context: securitization — collateral for a $10M term / $5M revolver loan. Per Netlist's 8-K/10-Q (https://www.sec.gov/Archives/edgar/data/1282631/000110465913083654/a13-19714_1ex10d2.htm and the 8-K of 2013-07-18), the obligation was "secured by a first-priority security interest in the Company's intellectual property assets" under an IP Security Agreement. The same transaction included a "Patent Monetization Side Letter" giving DBD a share of patent-monetization revenues and obligating Netlist to pursue monetization — a litigation-finance overlay worth flagging.
2015-11-20 (recorded) — Reel not retrieved
- Conveyance: Security Interest
- Assignor: NETLIST, INC.
- Assignee: SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P.
- Correspondent: not retrieved
- Context: securitization — a later secured-financing lien (SVIC is a venture-investment vehicle associated with Samsung Venture Investment). Note the industrial-strategy wrinkle: a Samsung-affiliated fund held a lien on Netlist IP during the period leading into the Netlist–Samsung disputes.
2015-12-03 (recorded) — Reel not retrieved
- Conveyance: Termination of Intellectual Property Security Agreement
- Assignor: DBD CREDIT FUNDING LLC
- Assignee: NETLIST, INC.
- Correspondent: not retrieved
- Context: lien release — the 2013 DBD/Fortress security interest was extinguished; title clarity restored to Netlist.
2023-11-20 (recorded) — Reel not retrieved
- Conveyance: Release by Secured Party
- Assignor: SVIC. NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P.
- Assignee: NETLIST, INC.
- Correspondent: not retrieved
- Context: lien release — the 2015 SVIC security interest was extinguished (recorded exactly eight years after it was taken).
Net effect: five recorded events, zero transfers of ownership away from Netlist. Every non-Netlist entry is a lien or a lien release.
(Prosecution-side, for completeness: the printed patent lists an attorney of record, Agent, or Firm reported only as "Jamie J. [surname truncated]" in the copies I could retrieve. This is the prosecution attorney, which is a different role from the assignment correspondent; I could not confirm the recording correspondent for any of the five events.)
Timeline diagram
timeline
title Ownership of US 8787060
2010 : Provisional application filed
2011 : Non-provisional filed by Netlist
2012 : Inventor assigns to Netlist Inc
2013 : Security interest to DBD Credit Funding
2014 : Patent issued 22 Jul
2015 : Security interest to SVIC fund
: DBD security interest terminated
2021 : Netlist sues Samsung
2023 : Samsung verdict 303M
: SVIC security interest released
2024 : PTAB finds claims unpatentable
: Netlist appeals to CAFC
2025 : Idaho suit filed
NPE / troll-pattern signals
Shell-entity transfer — not present. No assignment to any "IP / Patents / Licensing / Holdings / Ventures" licensing LLC. The only non-Netlist assignees are lenders taking security interests (DBD Credit Funding LLC, 2013; SVIC No. 28, 2015), and both liens were released back to Netlist (2015-12-03 and 2023-11-20). Title never left the operating assignee.
Known asserter in the chain — not present (weak/unclear for DBD). Neither the current nor any prior assignee matches the enumerated NPE list (Acacia, Marathon, IV, IPNav, Wi-LAN/Conversant, Vringo, Pendrell, MPHJ, Lumen View, Round Rock, etc.). Netlist is a public operating company, not a listed PAE. One adjacent flag: DBD Credit Funding LLC is a Fortress Investment Group affiliate, and Fortress is a large litigation/ IP financier; the 2013 "Patent Monetization Side Letter" tied DBD to Netlist's enforcement proceeds. That is litigation financing, not an NPE assignment, so I rate this weak/unclear, not a confirmed signal.
Repeat correspondent across the chain — unclear. Correspondents of record were not retrievable; I cannot confirm or deny recurrence. This is the single most valuable missing datum (an NPE chain usually shows one attorney recording every link). Recommend pulling all five reel/frame entries in Assignment Center to check for a repeated correspondent.
Cascading transfers — not present. There are no chained LLC-to-LLC assignments at all, let alone multiple transfers in <24 months. The five events span 2011–2023 and are all liens or lien releases to the original owner.
Pre-litigation transfer — not present. No assignment to Netlist (or anyone) occurred in the six months before the first '060 infringement suits (2021–2022). The last recorded lien release pre-dating the Samsung campaign was 2015-12-03 — seven years before suit. Ownership was continuous and clean on both sides of the litigation, so no venue/standing-manufacturing transfer is present.
Bankruptcy fire-sale — not present. Netlist has never filed Chapter 7/11. Its capital events were secured loans (SVB → DBD/Fortress 2013 → SVIC 2015), each disclosed in SEC filings; the IP was collateral, not sold in a bankruptcy estate.
Privateering — not present. Netlist asserts its own portfolio in its own name against real competitors (Samsung, Micron, SK hynix, Google) — e.g. the E.D. Tex. 2:21-cv-00463 and 2:22-cv-00203 campaigns and the reported $303M willful-infringement verdict of 2023-04-21 covering the '060 and '160 patents (CIPToday summary: https://www.ciplawyer.cn/articles/[150121](/patent/150121).html). There is no operating-company-to-NPE handoff.
Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT, Unified, or OIN. Instead, the patent is on the receiving end of defensive challenges: Unified Patents and Micron filed IPRs (IPR2023-00882, joined to Samsung's IPR2022-01428), and the PTAB's 2024-04-01 final written decision held all challenged claims unpatentable. Netlist, not a defensive aggregator, owns the patent.
Verdict
Operating-company assertion.
The ownership record is unambiguous: the '060 patent was assigned by inventor Hyun Lee to Netlist, Inc. (recorded 2012-01-03) and has remained Netlist's property ever since. The only other recorded entries — DBD Credit Funding LLC (2013-07-18) and SVIC No. 28 (2015-11-20) — are security interests, each recorded as a lien and each released back to Netlist (2015-12-03; 2023-11-20). There is no shell-entity transfer, no cascading LLC chain, and no pre-litigation assignment, so the classic NPE hallmarks are absent. Netlist is a publicly traded memory-subsystem company asserting its own patents against actual competitors (Samsung verdict 2023-04-21; Micron IPRs; Idaho cases 1:24-cv-00081 and 1:25-cv-00323), which places the chain squarely in the operating-company-assertion bucket.
Caveat for the record: Netlist's revenue is now predominantly litigation/licensing-driven, and its 2013 Fortress/DBD financing included a monetization-revenue share — traits some trackers treat as NPE-like. On the assignment-chain evidence alone, however, this is an operating-company assertion, not an NPE chain.
Verify: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search 8,787,060); Google Patents legal events — https://patents.google.com/patent/US8787060/en.
Generated 9/28/2026, 8:34:12 PM
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
I'll research the prior-art citations for US 8,787,060 directly, since the authoritative patent text provided omits the front-page "References Cited" section.
Let me pull the actual front-page "References Cited" list and verify the IPR references precisely.
Let me try to retrieve the actual front-page citation list from the patent document itself.
Prior Art for US 8,787,060 B2 — Analyst Report
0. Methodological caveat (read first)
Your instruction was to examine "each patent citation for 8787060" — meaning the front-page "(56) References Cited" list printed by the examiner. I must be explicit: that list was not available to me. The authoritative patent text you provided is truncated at the end of the Detailed Description and omits the (56) field entirely, and my attempts to retrieve the front-page citation column from the patent document were cut off by the tool budget. I will not reconstruct that list from memory, because fabricating examiner citations is exactly the kind of error that would poison this analysis.
What I can give you with high confidence is a different and arguably more consequential body of prior art: the references that were actually litigated against this patent — i.e., the Samsung/Micron IPR grounds. Those are documented in primary-source PTAB filings I retrieved. I separate the two categories below.
Date note (carried from the prior section): your prompt sets the current date as April 26, 2026, but the live records show activity through September 2026. I flag rather than silently reconcile.
1. Reference set A — Prior art of record in the adversarial proceedings (high confidence)
These are the references in IPR2022-01428 (Samsung v. Netlist) and IPR2023-00882 (Micron v. Netlist). Both petitions challenged claims 1–34. Critically, all grounds were §103 obviousness grounds — there was no §102 anticipation ground.
| Ex. | Reference | Full citation | Filing / publication | Role |
|---|---|---|---|---|
| EX1014 | Kim | U.S. Patent Application Publication No. 2011/0103156 A1 (Kim et al.) | Filed Dec. 29, 2009; published May 5, 2011 | Primary reference (Grounds 1–3) |
| EX1015 | Rajan | U.S. Patent No. 8,041,881 B2 (Rajan et al.) | Issued Oct. 18, 2011 | Secondary reference in all Grounds |
| EX1016 | Riho | U.S. Patent Application Publication No. 2011/0026293 A1 | Published Feb. 3, 2011 (filed 2009) | Secondary (Grounds 2, 4, 5) |
| EX1017 | Wyman | U.S. Patent No. 7,969,192 B2 | Issued June 28, 2011 | Secondary (Ground 3) |
| — | Riho2 | Second Riho-family reference (full identity not confirmed in retrieved extracts) | — | Ground 5 only |
Ground-to-claim mapping (from the petition and the Wolfe declaration)
- Ground 1: claims 1–6, 8–14, 16–19, 29–34 obvious over Kim in view of Rajan.
- Ground 2: Ground 1 references + Riho — directed at claim 7 ("reduce a difference between a first load… and a second load").
- Ground 3: Ground 1 references + Wyman — directed at claim 15 (drivers of different sizes for TSV1 vs. TSV2).
- Ground 4: Riho in view of Rajan (alternative primary-reference theory).
- Ground 5: Ground 4 + Riho2.
The gap set {7, 15, 20–28} is covered by Grounds 2–5. (The exact ground assignment for claims 20–28 is reconstructed from the exhibit list and Wolfe declaration; treat it as medium confidence.)
Brief descriptions and §102 relevance (my assessment, distinguishing 103 from 102)
Kim (US 2011/0103156 A1). Discloses a memory package with stacked memory chips C0/C1/C2 and a shared data I/O section (1000) connected via global I/O lines (GIO_Rank0, GIO_Rank1) to separate I/O driving sections (100, 200) serving different ranks; Fig. 5 shows the stacked-die package. Because it was filed Dec. 29, 2009 — before the '060 provisional priority date of Nov. 3, 2010 — Kim is pre-AIA §102(e) prior art as of its filing date. Kim alone discloses most of claim 1's structure (stacked dies, multiple die interconnects/TSVs, master chip with separate data driving sections), which is why Samsung used it as primary. §102 note: Kim is the strongest single-reference anticipation candidate for claim 1 and its dependents, if one reads its per-rank data paths as the claimed "first/second die interconnect … not in electrical communication with the second/first group." The Board did not make an anticipation finding, and Netlist's non-infringement-style distinction was that Kim's ranks cannot share a TSV. So Kim is best characterized as anticipatory-adjacent but adjudicated only under §103.
Rajan (US 8,041,881 B2). A memory-subsystem buffer-chip reference. Teaches a memory package with stacked memory chips plus a buffer chip presenting an emulated JEDEC (DDR3) interface to the host while the physical dies are a different type (DDR2), and teaches rank multiplication by generating chip-select signals for each chip in the stack (cited at 6:34–38). Rajan is analogous art (same field: memory module capacity/interface management). §102: Rajan does not alone disclose the partitioned-conduit/partitioned-TSV structure of claim 1; its relevance is as a §103 secondary teaching, and under §102 it would only be implicated for the module-level independent claim 29 (register device + data path control + operational modes) if read aggressively — but the Board's finding was obviousness.
Riho (US 2011/0026293 A1). Discloses a semiconductor device with stacked DRAM chips interconnected by equi-length TSVs, where pairs of dies from two different ranks may share a TSV, and optionally only half of each group connects to the TSV at a time to reduce load by half. This is the reference the Board relied on for claim 7 — holding that Riho's equi-length TSV / skew-minimization teaching shows a POSITA would consider TSV load when grouping dies "so as to reduce a difference" between conduit loads. Riho's publication date (Feb. 3, 2011) is after the Nov. 3, 2010 priority date, so it is prior art only as §102(e) art as of its filing date (2009) — a point that would matter in a §102 challenge and that the parties evidently did not contest.
Wyman (US 7,969,192 B2). An output-driver reference: teaches an output drive portion (Fig. 1) and that shorter TSVs require a smaller driver than longer TSVs, with selectable driver sizes (Figs. 3–4) and disabling of unneeded downstream stages. Relied on for claim 15 (drivers "smaller than … sufficient to drive … each of the array dies"). §102: Wyman is a driver-design reference with no die-partitioning disclosure, so it cannot anticipate any independent claim; it is §103-only material.
The §102 vs. §103 point you asked about, stated plainly
No reference in this record was found to anticipate the '060 claims under §102. Every instituted ground and the April 1, 2024 Final Written Decision were §103 (Kim + Rajan; Kim + Rajan + Riho; Kim + Rajan + Wyman; Riho + Rajan; Riho + Rajan + Riho2). If your question is "which single reference takes claim 1 down under §102," the honest answer is: none was adjudicated that way, and I found no §102 ground asserted. The closest structural single reference is Kim, and any §102 argument would have to overcome the same "ranks cannot share a TSV" distinction Netlist pressed in the IPR.
2. Reference set B — Applicant-incorporated references (medium confidence as "citations")
The '060 specification expressly incorporates by reference a large block of Netlist's own prior patents and applications. These are cited in the description, not necessarily in the (56) field, but they are the closest thing to an author-generated citation list:
- Patents: U.S. Pat. Nos. 7,289,386; 7,286,436; 7,442,050; 7,375,970; 7,254,036; 7,532,537; 7,636,274; 7,630,202; 7,619,893; 7,619,912; 7,811,097 (rank multiplication, HCDIMM/isolation-device architecture).
- TSV-specific: U.S. Pat. Nos. 7,633,165 and 7,683,459 (cited in the body as examples of TSVs usable with the disclosure).
- Applications: Ser. Nos. 12/422,912; 12/422,853; 12/577,682; 12/629,827; 12/606,136; 12/874,900; 12/422,925; 12/504,131; 12/761,179; 12/815,339.
§102 relevance: Many of these (e.g., 7,289,386 and 7,532,537, both pre-2008) are Netlist's own earlier-issued patents and would qualify as §102(b) art as to the '060 — which is precisely what makes them "admitted prior art" in the IPR argument record. Petitioner's reply explicitly invoked "the admitted prior art incorporated by reference in the 060 Patent" as teaching collision-avoidance techniques. So while these are applicant-side references, they carry genuine §102(b) exposure, chiefly against the module-level independent claim 29 and its dependents rather than claim 1.
3. What I could not verify (flagged, not guessed)
- The (56) front-page References Cited list — the exact examiner-cited patent document list. Not retrieved; not reconstructed.
- Full identity of "Riho2" (Ground 5) — the retrieved exhibit extracts name it but give no full citation.
- Full bibliographic detail for Rajan (8,041,881) — exact title, filing date, and assignee beyond "Rajan et al." Rajan is confirmed as a U.S. patent issued Oct. 18, 2011; I did not independently confirm the title or filing date.
- Whether any §102 (anticipation) ground was ever petitioned in IPR2023-00882 (Micron) specifically — I confirmed the §103 grounds for IPR2022-01428; the '882 petition is described as challenging claims 1–34 with the same reference families, but I did not retrieve its ground table.
- Newer 2025 tracks: a Samsung PGR2025-00071 (filed ~Aug. 25, 2025) uses US 8,787,060 itself as EX1069, and a further Samsung petition appears as IPR2025-01402. I did not retrieve the reference lists for either.
4. Bottom line
- The operative prior art of record for US 8,787,060 is Kim (US 2011/0103156 A1), Rajan (US 8,041,881), Riho (US 2011/0026293 A1), Wyman (US 7,969,192), and Riho2, all deployed in §103 combinations, resulting in a Final Written Decision (April 1, 2024) holding claims 1–34 unpatentable.
- For the §102 framing you requested: no reference was found or asserted to anticipate; Kim is the only credible single-reference candidate (as §102(e) art filed Dec. 29, 2009), but even Kim was adjudicated only as the primary reference in an obviousness combination, not as an anticipatory reference.
- The applicant-incorporated Netlist patents (7,289,386, 7,532,537, etc.) are the references most likely to appear in any §102(b) attack on the module-level claim 29, and they function in the record as "admitted prior art."
If you can supply the scanned front page (the "(56) References Cited" column) or authorize another retrieval pass on the Google Patents citation tab, I can complete the literal examiner-citation inventory and map each item to §102/§103 exposure per claim.
Generated 9/28/2026, 8:34:00 PM
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
I'll ground this analysis in the actual prior-art record rather than reciting generalities. Let me pull the PTAB's own reference set and confirm what each reference discloses.
Strong grounding. Let me confirm the bibliographic identity of each reference (titles, dates, assignees) so the mapping is accurate rather than inferred.
Obviousness Analysis — U.S. Patent No. 8,787,060 B2
"Method and apparatus for optimizing driver load in a memory package"
Under 35 U.S.C. § 103 | Priority: Nov. 3, 2010 | Filed: Nov. 3, 2011 | Granted: July 22, 2014
Date note (carried forward and re-flagged): Your prompt sets today as April 26, 2026. The prior sections of this analysis (and the live records fetched for this run) report a PTAB Final Written Decision of April 1, 2024 and Federal Circuit activity reflected in 2025–2026 filings, including a September 2, 2026 opinion. This §103 analysis is largely date-independent because it rests on the April 1, 2024 FWD record, which predates either date — but the divergence between your prompt date and the record date remains unresolved and should be treated as a live discrepancy, not reconciled silently.
Contradiction flagged (from the prior sections): The prior "Patent summary" correctly reports the FWD as invalidating claims 1–34 over Kim + Rajan, with Riho and Wyman variants. One search result I retrieved (ai-lab.exparte.com, an AI-generated case summary) mis-labels the grounds: it calls "Ground 2" the Riho-in-view-of-Rajan combination (which the Petition actually places in Ground 4) and describes "Ground 3" as Kim and Rajan in view of Wyman for claims not including claim 15. That summary is unreliable on ground numbering. Per the Petition's own table (recovered from the PTAB record and the docketalarm exhibit list for IPR2025-01402 and PGR2025-00071), the grounds are:
| Ground | Claims | Basis |
|---|---|---|
| 1 | 1–6, 8–14, 16–19, 29–34 | §103(a) — Kim + Rajan |
| 2 | 1–14, 16–19, 29–34 | §103(a) — Kim + Rajan + Riho |
| 3 | 15, 20–28 (and the claims of Grounds 1–2 as applied) | §103(a) — Kim + Rajan + Wyman |
| 4 | 1–14, 16–19, 29–34 | §103(a) — Riho + Rajan |
| 5 | 15, 20–28 | §103(a) — Riho + Rajan + Riho2 |
The appellees' brief confirms that the FWD rested on Grounds 1–3 and that Netlist alternatively sought a conditional remand on Grounds 4–5 — implying the Board did not reach Grounds 4–5 on the merits. Treat that as medium confidence; I did not retrieve the FWD's ground-by-ground disposition table verbatim.
1. Legal framework and the person of ordinary skill
The Board applied the Graham/KSR framework: scope and content of the prior art, differences between the prior art and the claims, the level of ordinary skill, and objective indicia of non-obviousness. Randall Mfg. v. Rea, 733 F.3d 1355, 1362 (Fed. Cir. 2013); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). Motivation to combine and reasonable expectation of success are fact questions reviewed for substantial evidence. The Federal Circuit's 2026 opinion (per the record retrieved) affirmed on that standard.
POSITA (medium confidence — hedged): I did not retrieve the FWD's verbatim adopted level of ordinary skill. Based on the technical field, the Art Unit (2827), and the expert testimony of record (Dr. Andrew Wolfe for Petitioner, Dr. Brogioli for Patent Owner), a defensible POSITA definition is: a person with a bachelor's degree in electrical engineering, computer engineering, or a related field, and 2–5 years of experience in semiconductor memory design, including stacked-die/3D packaging, TSV interconnect, and JEDEC-compliant DRAM interfaces — or equivalent education and experience. This role is mechanically significant because the reference set is dominated by memory-package designers at Hynix, Elpida, and MetaRAM, i.e., the exact artisans a POSITA would consult.
2. The prior-art reference set (as identified literally on the record)
The §103 challenge does not rest on the "prior art" listed on Google Patents' generic "Patent Art (58)" panel. It rests on the specific references Petitioner selected, identified by exhibit number in IPR2022-01428, IPR2023-00882, and repeated in the later Samsung filings:
| Ex. | Literal identifier | Short name | Nature / dates | Assignee |
|---|---|---|---|---|
| EX1014 | US 2011/0103156 A1 | Kim | Pub. May 5, 2011; KR priority 10-2009-0104471, filed Oct. 30, 2009. "Data input/output circuit and semiconductor memory apparatus." | Hynix |
| EX1015 | US 8,041,881 B2 | Rajan | Issued Oct. 18, 2011 (filed 2007). Buffer chip + stacked DRAM, JEDEC emulation, rank multiplication. | MetaRAM |
| EX1011 | US 2008/0025137 A1 | Rajan137 | Pub. Jan. 31, 2008. The reference that rejected the application's original claim 1 during prosecution. | MetaRAM |
| EX1016 | US 2011/0026293 A1 | Riho | Pub. Feb. 3, 2011. Stacked SDRAMs divided into chip-selection groups sharing TSVs. | Elpida |
| EX1017 | US 7,969,192 B2 | Wyman | Adjustable/sizable driver circuit; discloses that longer TSVs need larger drivers. | Cufer Asset |
| EX1018 | US 2010/0195364 A1 | Riho2 | Same inventor family as Riho; drive capacity vs. parasitic R/C of TSVs. | Elpida |
| EX1019 / EX1022 / EX1023 | JEDEC DDR3 standards & references | (standard) | Chip-select bus, rank semantics, DW/x4 rank association figures | JEDEC |
| EX1026 | Ellsberry | (secondary) | Separate chip-select + shared data bus for rank multiplication without collisions | — |
Critically, the '060 specification supplies its own admitted prior art, which is usable against it:
- FIGS. 1A and 1B — conventional package with one driver per bit driving every array die over one die interconnect, and per-die chip-select ports 144/174. The specification states this is "existing memory package design[] currently used or proposed to be used."
- FIGS. 6A/6B — LRDIMM and HCDIMM (Netlist's own) architectures, including register device (RD) 612 generating data path control signals.
- FIG. 7 — the proposed 3DS-DIMM with 3DS register 712 and controller die 722.
The patent also incorporates by reference U.S. Pat. Nos. 7,289,386, 7,532,537, 7,619,912, 7,636,274, and 7,633,165/7,683,459 (TSVs). The appellees' brief makes the pointed use of this: the '060/'160 patents "simply incorporate by reference admitted prior art such as U.S. Patent Nos. 7,619,912 and 7,532,537 … which teach 'insert[ing] wait-time intervals or clock cycles to avoid collision.'"
3. What the claims require (element-level decomposition of claim 1)
| Element | Limitation | The problem it must be mapped to |
|---|---|---|
| 1.a | I/O terminals for data and control/address signals | External interface |
| 1.b | Stacked array dies, first group (≥2 dies) and second group (≥1 die), each die having data ports | Die partitioning |
| 1.c | First die interconnect in electrical communication with the first group and not with the second; second die interconnect in electrical communication with the second group and not with the first | Split interconnect — the crux |
| 1.d | Control die with first data conduit between the first interconnect and a first data terminal, and second data conduit between the second interconnect and the same first data terminal, each conduit not transmitting to the other's interconnect | Shared terminal — the crux |
| 1.e | Control circuit controlling respective states of the two conduits in response to control signals | Selective isolation |
Claims 7, 15, and 20–28 add load-consideration, driver-size, and method recitations; claim 29 adds the register-device / dual-operational-mode module architecture.
4. Combination-by-combination obviousness analysis
4.1 Ground 1 — Kim in view of Rajan (claims 1–6, 8–14, 16–19, 29–34)
Kim (EX1014) supplies nearly the whole apparatus. Kim discloses a semiconductor memory apparatus with a main chip C0 and slave chips C1, C2 in a stack; a shared data input/output section 1000 in main chip C0; data input/output lines GIO_Rank0 and GIO_Rank1 implemented as TSV1 and TSV2; and a rank selecting unit 1100 that connects the shared section to one of the two lines in response to chip selection signals CS0 and CS1. On the Board's findings (as summarized in the Federal Circuit briefing), Kim's TSV1/TSV2 are the claimed first/second die interconnects; C0 is the control die; C1/C2 are the two groups; the rank-selecting unit is the control circuit controlling "respective states" of the two conduits.
Rajan (EX1015) supplies the JEDEC-standard external interface and the multi-die-per-group structure. Rajan discloses a buffer chip 413 interfacing a host system 404 with stacked DRAM chips 417A–D, with 417C–D sharing data line 415B and 417A–B sharing data line 415A — i.e., two groups of two dies each on separate shared data buses, exactly the partitioned-interconnect topology of claim 1.c "in the combination." Rajan further discloses the buffer chip "may comply with JEDEC standards" (4:20–24; 14:11–18; Fig. 18) and that where the buffer chip emulates a larger-capacity device, "the extra address bits may be decoded by the buffer chip to individually select the DRAM chips, utilizing separate chip select signals (not shown) to each of the DRAM chips in the stack" (6:30–38).
The Federal Circuit's own characterization of the Board's finding (from gov.uscourts.cafc.22100.26.0.pdf) is that the combination is "a straightforward one — 'implement a shared data bus for multiple memory chips as taught by Rajan … using, e.g., Kim's TSV interconnects.'"
Motivation to combine (as found and affirmed):
- Same field of endeavor / analogous art. Both are stacked-die memory packages; the Board found the references analogous and Netlist did not challenge that on appeal.
- JEDEC compatibility. A POSITA would implement Rajan's JEDEC-compliant interface in Kim's control chip to make the package commercially usable in standard systems — a classic "improving a known device by known means" rationale under KSR.
- Capacity scaling. Kim expressly teaches "any number of … slave chips may be used" ([0048], [0050]) and "three or more ranks," giving an express lead to expand beyond two dies — and Rajan provides the known technique for managing multiple die groups sharing a common data terminal.
- Prevention of collisions. Four chips in the combination each receive a separate chip-select signal (Rajan 6:34–38; JEDEC), resolving the shared-bus collision problem the POSITA would immediately anticipate.
Expectation of success: high — a predictable integration of a standard JEDEC interface and buffer-chip control logic into a known stacked-die/TSV package, producing the known result of a JEDEC-compatible high-capacity memory package.
4.2 Ground 2 — Ground 1 + Riho (claims 1–14, 16–19, 29–34; the dispositive ground for claim 7)
Riho (EX1016) is the most damaging reference on the inventive concept itself, because Riho states the purpose the '060 patent claims as its own:
"by employing the structure in which the stacked SDRAM chips are divided into the groups (chip selection groups) and the through-silicon vias (TSVs) are each shared by the groups, it is possible to reduce by half the load of each SDRAM chip as compared with the case where the SDRAM chips are not divided into the groups." — Riho ¶[0103]
Riho further discloses that "the load capacitance to 256 data signals DQ is reduced by half … the operating current is reduced and the high-frequency operation is achieved" — i.e., load reduction → power reduction → higher frequency, which is precisely the '060 advantage paragraph ("by reducing the overall load compared to the single data conduit, it is possible in many cases to reduce power consumption … the speed of the memory package 200 can be increased").
This is decisive for claim 7. Claim 7 requires the numbers of dies in each group to be "selected in consideration of a load of the first die interconnect and a load of the second die interconnect so as to reduce a difference between a first load on the first data conduit and a second load on the second data conduit." The Board found Riho's equal number of dies per group with equal-length TSVs teaches exactly that consideration, "even if other considerations are used or are even more prominent." Netlist's argument that Riho "avoids" the problem by mandating equal-length TSVs was rejected; the Board (affirmed) held that "even if the proposed combination uses Kim's unequal length TSVs, Riho still provides a teaching of considering load when grouping dies." And critically, the Board applied the plain meaning that claim 7 "does not recite any particular amount of reduction of load difference nor the starting point from which to determine whether there is a reduction."
Note the doctrinal point Netlist lost: the motivation to modify need not be the patentee's motivation. Honeywell Int'l v. 3G Licensing, 124 F.4th 1345, 1353 (Fed. Cir. 2025). And the combination need not be the best option — only a suitable one. Intel v. PACT XPP Schweiz AG, 61 F.4th 1373, 1380–81 (Fed. Cir. 2023).
4.3 Ground 3 — Ground 1 + Wyman (claims 15, 20–28, i.e., the driver-size claims)
Wyman (EX1017) is the anti-claim-15 reference:
"FIG. 8B illustrates, in simplified form, a longer through-chip via connection (804) extending directly between the mother chip (700-4) and daughter 3 (700-1)… The increased resistance, capacitance and impedance of such a connection (804) might require additional drive than that referred to in connection with FIG. 8A." — Wyman 6:21–26
Wyman thus establishes that (a) TSVs of different lengths present different loads, and (b) the load difference is not negligible — the very premise the '060 specification asserts ("as the physical size of a memory package shrinks, the load of a die interconnect becomes a non-negligible value"). Because Kim's TSV1 and TSV2 are of different lengths (Netlist conceded this: "admitting that '[i]n Kim, the TSVs are of different lengths'"), the POSITA would look to Wyman for using different amounts of signal drive for the two interconnects — meeting claim 15's "first driver size … second driver size … both less than a driver size sufficient to drive … each of the plurality of array dies without significant signal degradation."
Motivation: power efficiency is "a well-known design goal"; Wyman expressly teaches that a single full-capacity driver for both paths is "wasteful" and "overkill"; and the POSITA would use separate copies of Wyman's driver circuit 500, at different sizes, for the two TSVs. Intel v. PACT again supplies the "suitable option" standard.
Netlist's counter (Wyman teaches a single adjustable driver, not multiple differently-sized drivers) was rejected on substantial-evidence review: the Board relied on Wyman's express teaching of multiple driver-circuit embodiments and the credited expert testimony that "you can provide a separate copy of [Wyman's] circuit 500 for each thing that needs to be driven" and "there's also the teaching in Wyman that you can make 500 at various different sizes." Netlist also did not challenge on appeal the finding that the different TSV lengths motivate different drive amounts — a significant forfeiture.
Also relevant to the "driver size" construction: the district court construed "driver size" as "driver physical size" (citing '060/'160 specification: "The size of the driver may be adjusted by the selection of the transistor size and/or number of transistors"). Wyman's transistor-count-selectable driver maps directly onto that construction.
4.4 Grounds 4–5 — Riho + Rajan (± Riho2), the alternative theory
The Petition also advanced Riho as the primary reference (Riho's control/logic LSI chip + grouped SDRAMs sharing TSVs, load-halving) with Rajan for the JEDEC interface, and Riho2 for optimizing output drive capacity against the parasitic R/C that varies with TSV length and die position. Riho2's teaching is materially the same insight as Wyman's, from the same corporate family as Riho — an efficient alternative that also supplies a motivation rooted in the reference family itself.
Caveat: per the appellees' conditional-remand request, the Board appears to have decided on Grounds 1–3 and not reached Grounds 4–5. Anyone re-asserting this patent should expect Grounds 4–5 to be litigated fresh.
5. Claim 29–34 — why the module claims are the weakest, not the strongest
Claim 29 is the memory-module claim: a register device generating data path control signals, DRAM packages each with a control die having command/address buffers and a data-path control circuit controlling command/address and data-bus time slots, with two operational modes — mode 1, register-generated data path control; mode 2, the control die passes command/address to the DDR DRAM dies without decoding ("address pass-through").
Two independent §103 paths exist here, and the second is nearly self-defeating:
- Ground 1 (Kim + Rajan, per the record). Rajan supplies the register/buffer emulation and multi-mode rank control (claim 8 analog: "the combination of Kim and Rajan teaches a control die that is configurable to operate in two modes, one in which the number of ranks seen by the host system equals the actual number of ranks and the other in which there is [emulation]").
- The applicant's own admitted prior art. The '060 specification dedicates FIGS. 6A/6B and FIG. 7 to describing, as existing or proposed architectures, (a) the HCDIMM with a register device (RD) 612 that generates data path control signals, and (b) the 3DS-DIMM with a controller die 722 carrying data buffers, a data path timing controller, a secondary C/A buffer, and a secondary rank decoder. Claim 29's two-mode architecture — register-driven mode vs. control-die pass-through mode — reads as an aggregation of two admitted prior-art architectures with the decoding function selectively bypassed. Under KSR, combining two disclosed architectures to obtain the predictable benefits of each, where the reference (here, the patent's own background) identifies the design need, is the paradigm of obviousness. The only nuance the patent adds is "without decoding the command/address signals" in mode 2 — which is a negative limitation (an omission of a function), and omitting a step with no attendant structural change is generally obvious. This is my analysis, not a quoted Board finding — flag as medium confidence; I did not retrieve the FWD's claim-29-specific reasoning.
6. Netlist's principal non-obviousness arguments and why they failed
| Netlist argument | Disposition |
|---|---|
| Kim's TSVs communicate with only one chip each; sharing a TSV across ranks is not taught | Rejected — the combination is not Kim alone; Rajan's Fig. 4 provides shared data lines for two dies each, and Kim expressly permits "any number" of slave chips |
| Combining would cause data collisions (Netlist's "strawman" of 4 chips / 2 chip-selects) | Rejected — the Board found Netlist "analyzed the wrong combination"; the proposed combination uses four separate chip-select signals (Rajan 6:34–38; JEDEC), preventing collisions |
| Kim teaches away from multi-die TSV sharing ("one-to-one correspondence" in Kim ¶17) | Forfeited (never argued to the Board) and wrong on the merits — "respectively" permits one-to-many; and the '060 patents' own incorporated prior art (7,619,912; 7,532,537) teaches collision avoidance via wait-time intervals |
| Riho avoids the load-difference problem by mandating equal-length TSVs, so it cannot teach claim 7 | Rejected — Riho teaches the consideration of load when grouping; claim 7 recites no quantum of reduction and no starting point; alternative argument forfeited as a late claim construction |
| Wyman teaches a single adjustable driver, not multiple differently-sized drivers | Rejected on substantial evidence — Wyman teaches separate copies of circuit 500 at different sizes and disabling unneeded stages; Netlist did not challenge the different-TSV-length motivation |
| TSVs "not needed for the memory chips' operation" = added cost | Rejected — "the use of TSVs was an obvious option for a person of ordinary skill … notwithstanding Patent Owner's commercial viability arguments"; commercial viability is not a claim limitation |
| APA / procedural irregularities | Rejected (per the September 2026 opinion) |
Notably absent from the record: Netlist appears not to have presented strong objective indicia (nexus-bearing commercial success, long-felt unmet need, industry praise, unexpected results) to the Board. The §303.15M Samsung verdict and the HyperCloud™ product line are commercially significant, but that significance was not converted into a §103 record with a demonstrated nexus, and in any event the '060 specification itself attributes the load-reduction benefit to a mechanism (splitting dies across interconnects) that Riho ¶[0103] states verbatim as already known. Where the asserted advantage is disclosed in the prior art, there is no "unexpected result."
7. Bottom line
The '060 patent's four independent claims all fall to a small, tightly-analogous, same-field-of-endeavor reference set:
- Claims 1–14, 16–19 — Kim + Rajan (Ground 1), or Kim + Rajan + Riho (Ground 2), or Riho + Rajan (Ground 4).
- Claim 7 — Kim + Rajan + Riho (Ground 2). Riho ¶[0103] discloses the load-halving purpose; no quantum of load balance is claimed.
- Claim 15 and 20–28 — Kim + Rajan + Wyman (Ground 3). Wyman expressly links longer TSVs to greater required drive.
- Claims 29–34 — Kim + Rajan (Ground 1), and independently as a combination of the applications' own admitted prior art (HCDIMM register device of FIG. 6B + 3DS-DIMM controller die of FIG. 7).
The motivation in every combination is not the patentee's motivation but an ordinary-innovation motivation: JEDEC compatibility, capacity scaling expressly suggested by Kim, collision avoidance expressly enabled by Rajan's separate chip-selects, and power/frequency optimization expressly taught by Riho and Wyman. This is why the Board found all of claims 1–34 unpatentable on April 1, 2024, and why the Federal Circuit affirmed on substantial-evidence review.
The narrow escape route Netlist attempted — reading claim 7 to require that the starting loads be unequal and then equalized — was forfeited (not raised to the Board) and, in any event, would convert claim 7 into a product-by-process claim and exclude the specification's own preferred embodiment (in which "the load of each conduit 332 and/or driver 334 may differ" and the difference "may be a design decision").
8. Required caveats
- Dates. Your prompt's April 26, 2026 date does not match the record's September 2026 activity. Verify the current mandate status at the CAFC docket for 24-2240/24-2241 and USPTO PatentCenter before relying on finality.
- Ground numbering. Do not rely on the
ai-lab.exparte.comsummary's ground labels; use the Petition table (Grounds 1–5 as tabulated in §0 above). - Grounds 4–5 outcome. The Board appears to have decided on Grounds 1–3; I could not confirm a merits disposition of Grounds 4–5. Treat as unresolved.
- POSITA definition and the claim-29-specific reasoning are inferred (medium confidence), not quoted from the FWD.
- Later filings. IPR2025-01402 (Samsung; exhibits dated Aug. 25, 2025) and PGR2025-00071 target the '060/'160 family and reuse the same exhibit set (EX1014 Kim, EX1015 Rajan, EX1016 Riho, EX1017 Wyman, EX1018 Riho2). These do not change the §103 analysis but may affect the current posture.
- I did not independently verify the bibliographic identity of Wyman (US 7,969,192) and Riho (US 2011/0026293 A1) — the tool step limit was reached before those confirmatory searches returned. The exhibit labels in the docketalarm and PTAB records are consistent as quoted, but treat the publication numbers for those two as medium-high rather than high confidence.
Key sources: PTAB IPR2022-01428 Final Written Decision (Apr. 1, 2024); Petition & Exhibits EX1014–EX1018; Fed. Cir. Appellees' Brief, No. 24-2240 (storage.courtlistener.com/recap/gov.uscourts.cafc.22100/gov.uscourts.cafc.22100.26.0.pdf); docketalarm exhibit lists for IPR2025-01402 and PGR2025-00071; Google Patents US8787060B2.
Generated 9/28/2026, 8:34:34 PM
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
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