US 6118776

US Patent 6,118,776 — Summary

Note on sourcing: The full patent text was provided in the brief and matches the USPTO/Google Patents record. I also verified bibliographic data and the complete claim set via EveryPatent.com, FreePatentsOnline.com, and Justia (patents.justia.com/patent/6118776). Searches for CAFC 2026 docket entries tied to this specific patent returned no results (details and caveats below).

Bibliographic Data (verified)

Assignee chain (current, per Google Patents legal events): Vixel Corp. → ARCXEL Technologies, Inc. → Vixel Corp. → Emulex Design & Manufacturing Corp. → Emulex Corp. → Avago Technologies General IP (Singapore) Pte. Ltd. → Avago Technologies International Sales Pte. Ltd. (current listed assignee). This is a standard assignment chain; the grant-time assignee was Vixel Corporation.

Data-quality caveat: A few third-party aggregator pages (e.g., UnifiedPatents/portal listings) show garbled metadata associating this title with "Zhong Sheng" and a 1997-02-17 priority date. Those records appear to be scraping errors (they correlate with unrelated patent numbers). The authoritative USPTO/Google Patents/Justia/EveryPatent records uniformly list Stuart B. Berman and filed Aug. 7, 1997, matching the full patent text provided.

Abstract (verbatim from the patent)

Methods and apparatus for Fiber Channel interconnection is provided between a plurality of private loop devices through a Fiber Channel private loop device interconnect system. In the preferred embodiments, the Fiber Channel private loop device interconnect system is a fabric or an intelligent bridging hub. In one aspect of this invention, a Fiber Channel private loop device is connected to two or more Arbitrated Loops containing, or adapted to contain, one or more private loop devices. Preferably, the interconnect system includes a routing filter to filter incoming Arbitrated Loop physical addresses (ALPAs) to determine which Fiber Channel frames must attempt to be routed through the fabric. Numerous topologies of interconnect systems may be achieved. In another aspect of this invention, a method is provided for implementing a logical loop of private loop devices by segmenting the logical loop into a plurality of sets, assigning each set to a physical Arbitrated Loop and connecting the Arbitrated Loops to a Fiber Channel private loop device interconnect system. Additional methods are provided for restricting attached devices to Arbitrated Loop physical addresses within certain ranges. Additionally, methods are provided for resetting hosts, the method generally comprising the steps of detecting the addition of a storage device to a first Arbitrated Loop, and thereafter, resetting the Arbitrated Loop or loops on which a host or hosts reside on second Arbitrated Loop. Methods for operation with use of SCSI initiators generate a link service reject when no address match is found, or when an address match is found, but where no device with the destination ALPA exists on the Arbitrated Loop corresponding to the destination.

Plain-Language Overview of the Independent Claims

The patent is the foundational "private loop switching" / "Stealth Mode" patent (announced by Vixel in Sept. 2000). It lets Fibre Channel private loop devices (devices that do not support full fabric attach) on different physical Arbitrated Loops communicate through a fabric/switch or intelligent hub, without modifying the devices or their drivers.

• Claim 1 (system — actual attached loops): An interconnect system (e.g., fabric) with a first port coupled to a first Arbitrated Loop holding private loop devices and a second port coupled to a second device (which could be on another loop or fabric-attached). Each port has a port control module containing an "active L_Port" that implements the Fibre Channel Arbitrated Loop protocol (generating ARBs, OPNs, and Closes), and the first port behaves like a point-to-point peer to the loop device. Route-determination circuitry selects a path and switching connectivity transfers frames between the ports — so a private loop device can exchange Fibre Channel frames with the second device.

• Claim 2 (system — adapted-to-attach version): The same system as claim 1, but drafted to cover loops and ports that are merely adapted to contain / be coupled to such devices (i.e., capability-based coverage even before a device is physically attached).

• Claim 18 (frame-routing/filtering method): A method for routing frames between a private loop device on a first loop and devices on another loop through the interconnect system: frames received on the first loop are filtered — (1) if the destination address is on the first loop, the frame is forwarded locally on that loop; (2) if the address is not on the first loop, the port control module generates an "open" response on the loop (so the loop protocol proceeds) and the frame can be handled off-loop.

• Claim 23 (ALPA-range restriction method): A method for configuring multiple loops of private loop devices (each device having zero domain/area and only an ALPA): divide the ALPA space into non-overlapping sets, assign each set to a separate physical loop, and during loop initialization force attached private loop devices to pick their ALPA only from the assigned set — simplifying fabric routing since each port's device addresses are predetermined.

• Claim 25 (host-reset-on-storage-add method): In a multi-loop system with private storage on one loop and non-storage devices (e.g., hosts) on another, when addition of a storage device to the first loop is detected, transmit a Loop Initialization Primitive (LIP) to reset only the ports whose loops contain non-storage devices — not the ports whose loops contain only storage — so hosts re-probe and discover the newly added storage.

• Claim 26 (PLOGI probe routing method): When Fibre Channel SCSI initiators send PLOGI (port login) I/O probes to discover targets, the interconnect system performs an address lookup and, when a match exists, routes the probes through the system to the actual private loop devices (which may be on a different port/loop).

• Claim 27 (LS_RJT spoofing method): For PLOGI probes, if the address lookup finds no match — or finds a match but no device with the destination ALPA actually exists on the corresponding loop — the probe is routed to the interconnect system's controller, which immediately returns a Link Service Reject (LS_RJT) to the initiator rather than letting it time out (speeding up the initiator's probe of the full 126-ALPA space).

• Claim 79 (loop isolation method): In a system with at least two loops of private loop devices that can communicate across loops, when a loop-initialization event occurs on a first loop, that first loop is re-initialized without affecting the other attached loops — i.e., device power-up/down/failure on one physical loop no longer resets the entire logical loop (one of the key advantages over passive hubs).

CAFC 2026 Docket Search — Result

• Web searches for CAFC 2026 docket entries referencing "6118776" / "6,118,776" returned no results.
• The patent is expired (anticipated expiration Feb. 18, 2017; Google Patents status "Expired – Lifetime"), and Google Patents flags the patent family as having litigation history (a Darts-IP litigation-family link is present), but I found no public indication of any 2026 CAFC appeal or case docketed against this specific patent number.
• Uncertainty statement: I could not access the USPTO PAIR/Patent Center docket or the CAFC's public docket directly in these searches, so I cannot rule out the existence of a 2026 CAFC filing with high confidence. If you need definitive docket confirmation, the authoritative sources are the USPTO Patent Center (assignment/maintenance records) and the CAFC docket system (PACER/CM-ECF), which I was unable to query directly here.

Primary sources: https://patents.google.com/patent/US6118776/en · http://www.everypatent.com/comp/pat6118776.html · https://FreePatentsOnline.com/6118776.html · https://patents.justia.com/patent/6118776

Based on the searches I could run (I hit the search-step limit before I could confirm docket numbers on PACER/Unified Patents), here is what is known about litigation involving US 6,118,776 ("Methods and apparatus for fibre channel interconnection of private loop devices"). I've separated confirmed facts from items I could not independently verify.

Litigation found

1. Vixel Corporation v. QLogic Corporation

• Plaintiff: Vixel Corporation
• Defendant: QLogic Corporation
• Jurisdiction: U.S. District Court for the District of Delaware
• Filing date: Contemporaneous reports conflict slightly — late February 2003 (Network Computing, May 28, 2003, says "on the last day of February") vs. a German industry report (silicon.de) saying the complaint was received by the court on March 3, 2003. Likely filed ~Feb 28 / docketed Mar 3, 2003.
• Patents asserted: US 6,118,776 (the Network Computing article describes this patent as "hotly contested" and states the QLogic suit was over "the very same patent"); some accounts place related Vixel patents in the same campaign.
• Case number: Not confirmed in my searches — I was unable to verify the docket number on PACER/Unified Patents before hitting the step limit.
• Outcome/status: Not confirmed. My search results did not produce a final judgment or settlement order. (Public history suggests the Fibre Channel switch patent wars of this era typically settled, and Brocade's later SEC filings reference a standstill-type resolution with Vixel — see below — but I cannot confirm a QLogic disposition with confidence.)

2. Vixel Corporation v. Brocade Communications Systems, Inc.

• Plaintiff: Vixel Corporation
• Defendant: Brocade Communications Systems, Inc.
• Jurisdiction: U.S. District Court for the Northern District of California
• Filing date: May 23, 2003 (suit "filed in the U.S. District Court for the Northern District of California last Friday" per a May 28, 2003 report; Brocade's SEC Form 10-Q likewise references a suit "captioned Vixel Corporation v. ..." dated May 23, 2003).
• Patents asserted: US 6,118,776, US 6,185,203 ("Fibre Channel Switching Fabric"), and US 6,470,007 ("Interconnection System for Fibre Channel Arbitrated Loop Including Private Loop Devices"). Brocade's accused products included SilkWorm features QuickLoop and Fabric Assist.
• Case number: Not confirmed in my searches.
• Outcome/status: Indicia of settlement. Brocade's SEC filings from 2004 (getfilings.com copy of a Brocade 10-Q) contain language about the parties preserving rights and agreeing to a three-year standstill during which neither party could initiate patent litigation against the other. That language appears in the Brocade filing in the context of the Vixel matter, which is consistent with a 2004 settlement of this case — but I could not retrieve the full filing to confirm the caption and disposition definitively.

Cases not found

• I found no evidence in these searches of post-2004 litigation (e.g., after the patents passed from Vixel to Emulex/Emulex Design & Manufacturing and later to Avago/Broadcom per the assignment record) specifically asserting US 6,118,776.
• Google Patents flags this patent family ("Family has litigation," linking to Darts-ip), but the flagged litigation is at the family level and I could not resolve which specific family members/cases are covered within my search limits.

Candid caveats

• I could not reach PACER, the Unified Patents litigation portal, or Darts-ip within the allowed steps, so case numbers, exact filing dates, and final outcomes for both suits above are unverified.
• The two cases above are well corroborated by contemporaneous press and SEC filings as involving US 6,118,776. If you need docket numbers and terminal dispositions, I'd recommend checking PACER (D. Del. and N.D. Cal. for 2003–2004) or the Unified Patents caselist, searching the parties' names rather than the patent number (older cases often aren't indexed by patent number).

Proceedings overview

Total AIA trial proceedings on file for US 6,118,776: zero. The USPTO Open Data Portal ingest shows no IPR/PGR/CBM proceedings, and web searches surfaced none (old or recent). The breakdown is therefore empty across every status bucket — active: 0; claims invalidated: 0; claims sustained: 0; settled: 0; institution denied: 0. The bottom-line defensive posture is driven not by PTAB history but by the patent's expiration: the patent is "Expired – Lifetime" (Google Patents lists anticipated expiration 2017-02-18, i.e., 20 years from the 1997-02-18 priority date), so no injunction is available and damages are limited to proven pre-expiration conduct — and there is no PTAB estoppel or claim-cancellation history to worry about either way.

No individual proceeding write-ups follow because there are no proceedings to report. The requested per-proceeding fields (judge panel, institution decision, FWD, settlement, appeal) are vacuous here; nothing has been fabricated to fill them.

What the record actually shows

No AIA trial activity

• The canonical structured data block in this prompt states: "The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest."
• Independent web searches for IPR/PGR/CBM activity on US 6,118,776 (including "IPR2015/2016/2017" style queries and PTAB/Unified Patents/RPX angles) returned no PTAB proceedings. RPX's patent page likewise reflects a plain "Expired due to Term" status with no PTAB history.
• Do not invent proceeding numbers — there are none to cite.

The patent's actual enforcement history was pre-AIA district-court litigation, not PTAB

The closest analogs to "attacks" on this patent were district court infringement suits filed by the original owner (Vixel Corp.), not validity challenges at the PTAB:

• Vixel Corporation v. Brocade Communications Systems, Inc., filed 2003-05-23 in the U.S. District Court for the Northern District of California, alleging infringement of U.S. Patent Nos. 6,118,776; 6,470,007; and 6,185,203 (Brocade 10-Q filing, getfilings.com, describing the complaint, case management conference scheduled for 2004-03-26).
• Contemporary press (NetworkComputing, 2003-05-28) also reports Vixel suing QLogic around the same period over the same Fibre Channel patent family.
• Ownership chain since: Vixel → Arcxel Technologies → Vixel (reassigned) → Emulex Design & Manufacturing Corp. → Emulex Corp. → Avago Technologies (now Avago/Broadcom entities), per the USPTO assignment records shown on Google Patents.

None of that is PTAB activity, and none of it resulted in PTAB claim cancellation.

Strategic summary

• CANCELED: None. No PTAB (or, per the available record, court) proceeding has canceled any claim of US 6,118,776. SUSTAINED: None — no claim has been tested at the PTAB, so there is no "survived IPR" badge. UNTESTED: All claims as issued remain in the patent document, but the entire patent is expired (term expired 2017-02-18) and therefore unenforceable against new conduct. Because the issued claim set of this patent is not reproduced in the source materials provided, I am deliberately not stating a specific claim count; the point is that the whole patent, not a subset, is expired and PTAB-untested.

• Estoppel landscape (§ 315(e)(2)): Vacuous. There is no petitioner, no IPR, and therefore no statutory estoppel binding anyone. For a defendant facing assertion today, the operative constraints are the district-court doctrines of laches/limitations and the absolute bar on relief for post-expiration conduct — not § 315(e) estoppel. Note also that any would-be IPR petitioner who was served with the old 2003–2004 Brocade/QLogic complaints (or is in privity with them) would face the § 315(b) one-year bar for those parties, but that is a historical footnote; the patent's expiration moots the practical value of IPR for most defendants.

• Pattern signals: No repeat petitioner, no Unified Patents or defensive-aggregator involvement, and no patent-owner PTAB appellate pattern — because the patent predates AIA review and expired before the IPR wave reached storage-networking patents. The only "pattern" is the old Vixel assertion campaign against SAN switch competitors (Brocade, QLogic) in 2003, which is pre-AIA and settled into the historical record. The absence of PTAB activity is exactly what you would expect for a 1997-filed, 2017-expired patent: the absence is not a sign of strength, it is a sign of age.

Recommended next steps

• Lead with expiration, not IPR. If a demand letter cites US 6,118,776 today, the first response is that the patent expired on 2017-02-18 (20 years from the 1997-02-18 priority date; Google Patents status: "Expired – Lifetime"). Any theory of liability must be limited to acts before that date, and must still clear the statute of limitations — which a plaintiff cannot do for conduct now roughly a decade old. There is no FWD or PTAB order to quote because none exists; do not let opposing counsel imply otherwise.

• Confirm the specific accused conduct and dates. Because the only viable exposure is pre-2017-02-18 conduct, your first discovery demand should pin down (a) when the accused products were first sold, (b) when the defendant first received notice, and (c) any license/settlement history in the 2003-era Vixel v. Brocade / Vixel v. QLogic litigations that might cover the accused products (covenants, releases, or exhaustion defenses). Those old case files (N.D. Cal., Vixel v. Brocade, filed 2003-05-23) are worth pulling for releases running to customers or downstream products.

• If the patent owner pivots to family members (e.g., 6,470,007, 7,012,914, 7,881,213, or later continuations in the same Berman chain), run a fresh PTAB/ODP check on each family member by number — some family members have different expiration dates and may have their own litigation/PTAB history. This report covers only US 6,118,776 itself.

• Do not file an IPR as a reflexive move. With the patent expired and no prospective relief available, an IPR petition would be poor leverage economics; your motion practice should be aimed at a 12(b)(6)/summary-judgment expiration-and-limitations dismissal. If the patent owner nonetheless asserts pre-expiration damages in court, validity challenges (including prior art from the Fibre Channel ANSI standards cited in the specification itself — FC-PH, FC-AL, FC-AL-2, PLDA) remain fully available to you in district court, since no § 315(e) estoppel attaches to anyone here.

Bottom line: There is no PTAB war to map because no PTAB war ever happened. The patent is dead by natural expiration, all claims are PTAB-untested but unenforceable prospectively, and a current defendant's strongest and cleanest defense is lapse of the patent term plus the statute of limitations — not IPR.

I'll research the assignment chain for US 6118776 by cross-referencing USPTO records, Google Patents legal events, and corporate history sources.

Let me search for the specific corporate history and the recorded assignments with reel/frame data.

Inventors

• Stuart B. Berman (sole named inventor). The application (Serial No. 08/907,385) was filed 1997-08-07 by Vixel Corporation, but the recorded inventor-assignment chain ran Berman → Arcxel Technologies, Inc. (recorded 1998-01-26) → Vixel Corporation (recorded 1998-07-24). That sequence suggests Berman's rights were held by or routed through Arcxel Technologies at the time of the invention — likely his employer or an affiliate — before consolidation into Vixel. I could not independently verify his employer at filing; that is an inference from the recorded chain, not a confirmed fact.

Unusual patterns: none. Single inventor; no mass-departure/fire-sale pattern. The same inventor/priority chain (priority claimed to 1997-02-18, parent US 08/801,471) produced a large continuation family (US 7012914, US 7881213, US 8121137, US 8204068, US 7522619, etc.) that moved together — a coherent operating portfolio, not a stripped single asset.

Original assignee

• Vixel Corporation is the assignee of record at grant (Google Patents lists it as original assignee of US 6118776A; the current-assignee field shows "Avago Technologies International Sales Pte Ltd," which Google flags as potentially inaccurate).
• Line of business: Fibre Channel storage-networking hardware — hubs and switches, including the AGS/8 eight-port fabric switch referenced in the specification (FIG. 1 and routing tables). Vixel shipped products embodying the claimed "Stealth Mode" Fibre Channel private-loop interconnect (the patent describes its own product implementation, including port ALPA filtering tables).
• Current status: acquired/absorbed. Vixel Corporation was renamed Emulex Design & Manufacturing Corporation (recorded 2004-05-19) after Emulex's acquisition; Emulex Corporation was acquired by Avago Technologies (announced Feb 2015); the patent portfolio now sits in Avago's Singapore IP-holding subsidiaries, ultimately within Broadcom Inc. The patent itself shows Expired – Lifetime, anticipated expiration 2017-02-18.

Assignment timeline

Verification caveat: I could not retrieve reel/frame numbers or correspondent-of-record names from the USPTO Assignment Center in this session (the database requires interactive query and was not accessible through the tools available to me). The entries below are the recorded-assignment events as reflected in Google Patents legal events (https://patents.google.com/patent/US6118776/en), which are derived from USPTO assignment records but do not carry reel/frame or correspondent fields. Execution dates are likewise not separately shown. No reel/frame numbers are stated below because none were verifiable — do not treat these entries as reel/frame-verified.

• 1998-01-26 (recorded) — Reel not verified

  • Conveyance: Assignment of Assignor's Interest (inventor → company)
  • Assignor: Stuart B. Berman
  • Assignee: Arcxel Technologies, Inc.
  • Correspondent: not retrievable in this session
  • Context: Pre-issuance vesting of inventor rights in Arcxel Technologies; the application itself had been filed by Vixel Corp five months earlier (1997-08-07), so this documents the formal inventor chain rather than an asset sale.

• 1998-07-24 (recorded) — Reel not verified

  • Conveyance: Assignment
  • Assignor: Arcxel Technologies, Inc.
  • Assignee: Vixel Corporation
  • Correspondent: not retrievable
  • Context: Consolidation of the application into Vixel Corporation, the entity that filed and prosecuted it (consistent with a corporate reorganization or name alignment between Arcxel and Vixel).

• 2004-05-19 (recorded) — Reel not verified

  • Conveyance: Change of Name
  • Assignor: Vixel Corporation
  • Assignee: Emulex Design & Manufacturing Corporation
  • Correspondent: not retrievable
  • Context: Post-acquisition renaming of the Vixel entity after Emulex Corporation acquired Vixel's Fibre Channel switch business; internal corporate action only.

• 2014-01-17 (recorded) — Reel not verified

  • Conveyance: Assignment
  • Assignor: Emulex Design and Manufacturing Corporation
  • Assignee: Emulex Corporation
  • Correspondent: not retrievable
  • Context: Upstream transfer of the patent from the former-Vixel subsidiary to the Emulex parent — an internal consolidation.

• 2015-10-23 (recorded) — Reel not verified

  • Conveyance: Assignment
  • Assignor: Emulex Corporation
  • Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
  • Correspondent: not retrievable
  • Context: Patent transferred to Avago's Singapore IP subsidiary following Avago's acquisition of Emulex (closing 2015); a standard acquisition-chain transfer to an operating company's IP-holding entity.

• 2016-02-11 (recorded) — Reel not verified

  • Conveyance: Patent Security Agreement
  • Assignor: Avago Technologies General IP (Singapore) Pte. Ltd.
  • Assignee: Bank of America, N.A., as Collateral Agent
  • Correspondent: not retrievable
  • Context: Avago pledged its patent portfolio as collateral in debt financing (contemporaneous with Avago's Broadcom acquisition financing); a security interest, not an ownership transfer.

• 2017-02-03 (recorded) — Reel not verified

  • Conveyance: Termination and Release of Security Interest
  • Assignor: Bank of America, N.A., as Collateral Agent
  • Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
  • Correspondent: not retrievable
  • Context: Release of the 2016 security interest, restoring full ownership to the Avago subsidiary.

• 2017-02-18 — Anticipated expiration (no assignment): patent expired by term (20 years from the Feb 18, 1997 priority date). Status: Expired – Lifetime.

Bottom line on records: the chain is long but every link is a corporate acquisition, internal reorg, or name change among operating companies. There is no recorded transfer to any LLC, licensing entity, or NPE. Google Patents flags the family with a Darts-IP litigation marker ("Family has litigation"), but I found no evidence that this specific patent was asserted by an NPE; I could not verify the family-litigation particulars in this session.

Timeline diagram

timeline
    title Ownership of US 6118776
    1997 : Filed by Vixel Corp
    1998 : Berman assigns to Arcxel Tech
         : Arcxel assigns to Vixel Corp
    2000 : Patent issued
    2004 : Vixel renamed Emulex Design
    2014 : Assigned to Emulex Corp
    2015 : Avago acquires Emulex
         : Assigned to Avago Singapore
    2016 : BofA security interest filed
    2017 : Security interest released
         : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. Every assignee is a named operating company or its wholly owned IP subsidiary (Vixel Corp → Emulex Design & Manufacturing Corp → Emulex Corp → Avago Technologies General IP (Singapore) Pte. Ltd.). Avago's Singapore IP entities are standard multinational tax/legal structure, not single-purpose licensing shells, and the transfer dates track the 2004 Emulex and 2015 Avago acquisitions.
2. Known asserter in the chain — Not present (per sources reviewed). No chain member appears on the Acacia/Marathon/IPNav/Wi-LAN/Conversant/Vringo/Pendrell/MPHJ-type lists. I could not query RPX/Unified Patents directories in this session, so "not present" is limited to the materials I could verify.
3. Repeat correspondent across the chain — Unclear. Correspondent-of-record names were not retrievable from my sources; no recurrence can be assessed. This is the one signal I could not test, and it should be checked directly in the USPTO Assignment Center before finalizing any diligence memo.
4. Cascading transfers — Not present. Transfers span 1998–2015 and track real acquisitions/reorganizations (Vixel→Emulex 2004; Emulex→Avago 2015), not chained LLC conveyances within months.
5. Pre-litigation transfer — Not present (no evidence). No transfer is timed within six months of an NPE suit on this patent; the 2015–2017 events track the Avago acquisition and its debt collateral, and the patent expired 2017-02-18.
6. Bankruptcy fire-sale — Not present. Vixel was acquired by Emulex and Emulex by Avago in going-concern M&A; no Chapter 7/11 patent sale appears in the record.
7. Privateering — Not present. No SEC filings or press evidence surfaced showing Avago/Emulex handing the patent to an NPE to assert against competitors.
8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX/AST/LOT/Unified/OIN; it terminates at Avago (Broadcom), an operating company.

Verdict

Operating-company assertion — with the caveat that the "suing actual competitors" element of the rubric is not applicable because the patent expired 2017-02-18 (Expired – Lifetime) and no assertion by or against this patent was identified.

Justification: Every recorded assignment (Google Patents legal events: 1998-01-26, 1998-07-24, 2004-05-19, 2014-01-17, 2015-10-23, plus the 2016-02-11 security agreement and 2017-02-03 release) moves the patent among operating companies — Vixel (Fibre Channel switch maker that shipped the AGS/8 product described in the patent), Emulex, and Avago/Broadcom — with no shell LLC, no known asserter, and no bankruptcy or privateering pattern. Reel/frame numbers and correspondent names remain unverified in this session, so the assignment record should be confirmed at the USPTO Assignment Center (https://assignmentcenter.uspto.gov/ — search patent 6118776) before this chain is relied on for standing purposes, but the evident NPE signals are uniformly absent.

I'll research US Patent 6,118,776 and its cited prior art references.

I found the patent's "References Cited" listing. Now let me verify details of the most relevant cited references, including filing/priority dates and technical content.

Let me verify the two foreign patent documents cited (EP 0 709 987 A2 and EP 0 876 075 A2) and a few remaining U.S. references.

Prior Art Analysis — U.S. Patent 6,118,776

1. Patent confirmed

US 6,118,776 — "Methods and apparatus for fiber channel interconnection of private loop devices"

• Inventor: Stuart B. Berman (Newport Beach, CA)
• Assignee (at issue): Vixel Corporation (Bothell, WA); later chain to Avago/Emulex
• Application No. 08/907,385, filed Aug. 7, 1997
• CIP of Application 08/801,471, filed Feb. 18, 1997 ("Fibre Channel Switching Fabric", later US 6,185,203)
• Granted Sept. 12, 2000; 81 claims
• Sources verifying the grant and the reference list: uspto.report/patent/grant/6118776; FreePatentsOnline.com/6118776.html; everypatent.com/comp/pat6118776.html; patents.google.com/patent/US6118776/en

Important §102 timing caveat. Because the patent is a continuation-in-part, claim limitations supported by the Feb. 18, 1997 parent can rely on that earlier effective filing date, while new matter added Aug. 7, 1997 cannot. Under pre-AIA 35 U.S.C. § 102, each cited U.S. patent is prior art as of its earliest effective U.S. filing date (§ 102(e)) if that date precedes the invention; references "patented" or published more than one year before Aug. 7, 1997 are § 102(b) statutory bars. "Anticipates" below is a screening-level conclusion — a full § 102 anticipation finding requires that a single reference disclose every element of the claim, arranged as in the claim.

Independent claim map used for the analysis

• Claims 1 & 2 (system): two ports with port control modules, each containing an FC Arbitrated Loop Port State Machine with an active L_Port generating ARBs/OPNs/Closes; route-determination apparatus; connectivity/switch apparatus; first loop holds private loop devices; second "device."
• Claim 18 (method): frame routing with (1) forward on local loop if local address, (2) "open" response at port control module if address is not on the first loop (plus dependent claims 19–22: routing attempt, buffering, table compare, ALPA mask filtering).
• Claim 23 (method): dividing ALPAs into non-overlapping sets assigned to separate loops; restricting devices during loop init (claim 24: fabric interconnection).
• Claims 25 & 29–31: LIP reset of host/non-storage ports upon storage addition (no LIP to storage-only loops).
• Claims 26–28: PLOGI probe address lookup / routing and LS_RJT return for nonexistent destinations.
• Claims 79–81: loop-initialization isolation per port.
• Dependent system claims 3–17, 32–78: storage types (JBOD/RAID/tape), hosts, bridges, routers, redundant paths, fabric/intelligent-bridging-hub implementations, ALPA filtering/restriction, PLOGI spoofing, 8B/10B Endec, R_RDY flow control, D_ID extractor, etc.

2. U.S. Patent references cited on the face of 6,118,776

Highest relevance (Fibre Channel loop/hub/switch art)

US 5,751,715 — Chan et al., "Accelerator fiber channel hub and protocol"

• Issued May 12, 1998; filed Aug. 8, 1996 (verified via Google Patents citation data); assignee Gadzoox Microsystems
• Discloses a Fibre Channel Arbitrated Loop hub that divides one logical loop into multiple physical subloops, each attached to a hub port containing switching logic/state machines; simultaneous local arbitration on subloops, broadcast OPNs, and switching that directly connects only the source and destination subloops while bypassing non-participating subloops; handles ARBs, OPNs, CLS, RRDY; supports multiple pairs of devices communicating concurrently.
• Potentially anticipates: system claims 1, 2 (interconnect between physically separate FC loops with per-port state machines/route determination/switching; private-loop devices on loops); method claim 18 and dependents 19–22 (loop-to-loop frame routing with local forwarding vs. off-loop handling); 79–81 (per-loop isolation); dependent loop/hub/switch claims such as 16, 57, 66, 67, 71, 76. This is the closest cited reference to the "segment one logical loop into multiple physical loops" concept (the patent's "Stealth Mode" core). It does not appear to disclose the ALPA-range forcing (claim 23), storage-add LIP reset (claim 25), or PLOGI/LS_RJT spoofing (claims 26–28) features.

US 5,638,518 — Malladi, "Node loop core for implementing transmission protocol in fibre channel"

• Issued Jun. 10, 1997; filed Oct. 24, 1994 (verified); assignee LSI Logic
• Discloses a node loop core whose loop state machine performs loop initialization, arbitration, and fairness per FC-AL, recognizes FC primitive signals/sequences, and includes encode/decode, CRC, and buffering.
• Potentially anticipates: the "port control module containing a Fibre Channel Arbitrated Loop Port State Machine … active L_Port … generation of ARBs, OPNs and Closes" limitation present in claims 1, 2, 18, 26 and dependent details in claims 33–38 (Endec, frame buffers, R_Rdy flow control, D_ID handling). As a node core rather than a multi-port interconnect, it alone likely does not satisfy the route-determination/connectivity limitations of claims 1–2.

US 5,598,541 — Malladi, "Node loop port communication interface super core for fibre channel"

• Issued Jan. 28, 1997; filed Oct. 24, 1994 (verified via related-application reference in 5,638,518); assignee LSI Logic
• Companion NL_Port "super core" implementing the Fibre Channel NL_Port functions for Arbitrated Loop, including arbitration and primitive handling.
• Potentially anticipates: same claim elements as 5,638,518 — portions of claims 1, 2, 18, 26 and dependents 33–38.

US 5,894,481 — Book, "Fiber channel switch employing distributed queuing"

• Issued Apr. 13, 1999; filed Sep. 11, 1996 (verified via Google Patents citation data); assignee McData
• Fibre Channel switch with distributed queuing and frame switching between ports.
• Potentially anticipates: system claim elements of 1, 2 (route determination + connectivity apparatus between FC ports) and dependent fabric claims 57–65, 76–78. Issued after the '776 filing date, so only available as § 102(e)/§ 103 prior art based on its Sep. 11, 1996 filing date; not a § 102(b) bar.

US 5,490,007 — Bennett et al., "Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch"

• Issued Feb. 6, 1996; filed Oct. 31, 1994 (verified via EP0709987 family data); assignee Ancor
• Fiber optic (Fibre Channel-class) switch with bypass switching and messaging to support intermix data transfer (Class 1/2/3 intermix).
• Potentially anticipates: fabric-switch system elements of claims 1, 2 and dependent fabric claims (e.g., 57, 61, 76); intermix/class-of-service features support dependent subject matter in the specification but no dedicated claim.

US 5,519,695 — Purohit et al., "Switch element for fiber channel networks"

• Issued May 21, 1996 (assignee Ancor family)
• A switch element for Fibre Channel networks (frame routing between ports).
• Potentially anticipates: portions of claims 1, 2 (connectivity/route elements) and 57–61.

US 5,502,719 — Grant et al., "Path allocation system … for a high performance fiber optic switch"

• Issued Mar. 26, 1996 (Ancor family)
• Potentially anticipates: route-determination/path-allocation elements of claims 1, 2, 59.

US 5,528,584 — Grant et al., "High performance path allocation system … fairness insurance mechanism for a fiber optic switch"

• Issued Jun. 18, 1996 (Ancor family)
• Potentially anticipates: path-allocation/arbitration elements of claims 1, 2, 59; fairness features relate to loop arbitration background.

US 5,535,035 — DeFoster et al., "Optical fiber ring communications system and communications method"

• Issued Jul. 9, 1996; filed Sep. 15, 1994 (verified via Google Patents citation data); assignee IBM
• Optical fiber ring network with nodes and hub/bypass control for removing failed nodes.
• Potentially anticipates: loop/hub/bypass background elements; possibly claim 16 (loop comprising a hub) and claim 66-type hub concepts, though it is not a Fibre Channel-specific switch.

US 5,768,530 — Sandorfi, "High speed integrated circuit interface for fibre channel communications"

• Issued Jun. 16, 1998
• Fibre Channel physical-layer interface (GLM-type) circuitry.
• Potentially anticipates: dependent port-implementation claims 33–38 (Endec, buffers, flow control, D_ID extractor) as part of a combination; not the core routing/loop claims. Prior art only via earlier filing date (§ 102(e)) since it issued after Aug. 7, 1997.

Moderate relevance (Ethernet/LAN bridging — "intelligent bridging hub" background)

US 5,432,907 — Picazo, Jr. et al., "Network hub with integrated bridge"

• Issued Jul. 11, 1995
• LAN hub with an integrated bridge allowing selective frame forwarding between hub segments — conceptually close to the "intelligent bridging hub" of claim 66, but for Ethernet-type LANs, not FC-AL private loops.
• Potentially anticipates: generic hub/bridge elements only; would not alone read on FC-AL L_Port/ARB/OPN/CLS claim limitations of claims 1–2 or 18.

US 5,841,990 — Picazo, Jr. et al., "Network connector operable in bridge mode and bypass mode"

• Issued Nov. 24, 1998 (continuation-family of 5,432,907)
• Hub/connector operable in bridge mode (forwarding between segments) or bypass mode — same LAN-oriented concept.
• Potentially anticipates: analogous bridging-hub concept (claim 66 and 67 route-filtering concepts) but lacks Fibre Channel/private-loop specifics; § 102(e)-only candidate given post-Aug. 1997 issue.

Lower relevance (general switching/routing art)

US 4,821,034 — Anderson et al., "Digital exchange switch element and network" (Apr. 11, 1989) — general digital switch fabric; background for "connectivity apparatus"; no FC-AL disclosure.

US 4,958,341 — Hemmady et al., "Integrated packetized voice and data switching system" (Sep. 18, 1990) — general packet switch; background only.

US 5,412,653 — Hoppe et al., "Dynamic switch cascading system" (May 2, 1995) — cascading switch modules; background for multi-fabric topologies (specification FIGS. 1–12) but not loop protocol.

US 5,418,780 — Henrion, "Routing logic means for a communication switching element" (May 23, 1995) — routing logic in a switching element; background for the route-determination module (claims 1–2, 59).

US 5,619,497 — Gallagher et al., "Method and apparatus for reordering frames" (Apr. 8, 1997) — frame reordering in a high-speed switch; background for frame buffering/order aspects of claim 20-type operations.

These five general references would not, standing alone, anticipate any full claim of 6,118,776 because none discloses Fibre Channel Arbitrated Loop private-device interconnection with active L_Port state machines and per-loop filtering.

3. Foreign patent documents cited

EP 0 709 987 A2 — "Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch"

• Published May 1, 1996 (EP application 95113039 filed Aug. 18, 1995, claiming priority from US 08/332,185 filed Oct. 31, 1994) — verified via Google Patents (patents.google.com/patent/EP0709987A3)
• This is the European family counterpart of US 5,490,007 (Bennett et al./Ancor). Same disclosure and same anticipation analysis as US 5,490,007; as a foreign printed publication published before Aug. 7, 1996 it is available under § 102(a)/(b).

EP 0 876 075 A2 — "Fibre channel switching system and method"

• Published Nov. 4, 1998
• Based on available data, this appears to be in the Berman/Vixel "Fibre Channel switching fabric" family — i.e., the same family as the '776 patent's own parent application (US 08/801,471 → US 6,185,203). Because it published after the '776 CIP's Aug. 7, 1997 filing date, it is not § 102 prior art against 6,118,776 (a foreign publication is not § 102(e) prior art), and it cannot anticipate claims of the patent it descends from. It was evidently listed as a related/family document on the face of the patent.
• Note: the earlier WO 99/48252 (PCT/US1998/015554) publication is the PCT counterpart of the '776 itself, not prior art.

4. Non-patent literature cited (secondary; § 102(a)/(b) printed publications)

The "Other References" on the face of the patent include: Malavalli, "Distributed Computing With Fibre Channel Fabric," IEEE Compcon (Feb. 1992); Malavalli, "High Speed Fibre Channel Switching Fabric Services," Proc. SPIE vol. 1577 (Sep. 4, 1991); C.R. Martin, "Fabric Interconnection of Fibre Channel Standard Nodes," Proc. SPIE vol. 1784 (Sep. 8, 1992); G.R. Stephens et al., "Fibre Channel — The Basics" (Ancot, Jun. 1995); W. Richard, Wescon (Sep. 27, 1994); H. Chin, Computer Technology Review (Dec. 21, 1995); A. Varma et al., "Using Camp-On…Fibre Channel Switch," IEEE LCN (1993); Ravindran et al., IEICE Trans. (Aug. 1996); Platt et al., "Traffic Management in Frame Relay Networks" (Jan. 1992); Fibre Channel Association "Executive Overview"; Meggyesi "Fibre Channel Overview"; FC-FLA Rev 2.7 (NCITS draft, Aug. 12, 1997); and the PCT International Search Report (Jul. 20, 1998). The FC-FLA (Fibre Channel Fabric Loop Attachment) technical report is the most substantive: it addresses exactly the public/private loop-to-fabric attachment problem space, and is potentially relevant to claims 1–2, 18–22 and 23–24 (ALPA assignment), though as a draft standard it is best treated as § 103-type evidence of the state of the art rather than a single anticipatory § 102 disclosure. The 1991–1995 publications (Malavalli, Martin, Stephens, etc.) predate Aug. 7, 1996 and could be § 102(b) printed publications if they sufficiently describe the claimed interconnect features.

5. Bottom line — most relevant § 102 candidates

1. US 5,751,715 (Chan/Gadzoox) — the strongest single-reference anticipation candidate for the "multiple physical loops interconnected with switching that bypasses non-participating segments" core of claims 1, 2, 18–22, 79–81 and hub-related dependents. § 102(e) as of Aug. 8, 1996.
2. US 5,638,518 and US 5,598,541 (Malladi/LSI) — strongest for the FC-AL "active L_Port / port state machine / ARBs, OPNs, Closes" claim limitations of claims 1, 2, 18, 26 and dependents 33–38; § 102(e) as of Oct. 24, 1994 (5,598,541 also a § 102(b) bar as issued Jan. 28, 1997, less than one year before filing — actually not a 102(b) bar; it qualifies under 102(e)).
3. US 5,490,007 / EP 0 709 987 (Bennett/Ancor) — § 102(b)/102(e) fiber-optic switch with bypass/intermix, relevant to fabric-switch claim elements.
4. US 5,894,481 (Book/McData), US 5,519,695, US 5,502,719, US 5,528,584 (Ancor/McData switches) — fabric-switch route-determination/connectivity elements; § 102(e) (5,894,481 filed Sep. 11, 1996).
5. US 5,432,907 / US 5,841,990 (Picazo) — "intelligent bridging hub" concept (claim 66), LAN-flavored.

No single cited reference appears, from the face-of-patent disclosure alone, to teach the combination of ALPA-range restriction via LIFA (claim 23), host-port LIP reset upon storage addition without resetting storage-only loops (claim 25), or PLOGI probe LS_RJT spoofing (claims 26–28) — those appear to be the features that distinguish the '776 claims from the cited loop/hub art.

Caveat on sources: The reference list above is taken from the USPTO face-of-patent data reproduced by uspto.report/patent/grant/6118776, FreePatentsOnline.com/6118776.html and everypatent.com, which agree with one another. Filing dates were verified only where noted via Google Patents/USPTO citation data; where I could not verify a filing date (e.g., US 5,768,530, US 5,841,990, US 5,619,497, US 5,412,653, US 5,418,780), I flagged the § 102 subsection as conditional. For authoritative confirmation of each reference's earliest effective filing date you should pull the individual records from the USPTO Patent Center/PAIR.

§ 103 Obviousness Analysis — US 6,118,776

Preliminary note on the record used

The prompt directs me to "use the results from the Prior Art section of this page," but no Prior Art section was included in the materials provided (only the Patent Summary and Litigation Summary sections were attached). I therefore reconstructed the prior-art record from the "References Cited" on the face of the patent (retrieved from FreePatentsOnline.com/6118776 and EveryPatent.com/pat6118776, which mirror the USPTO record) and verified the content of the most important references via web searches (Google Patents entries for US 5,638,518 and US 5,894,481; an EPO opposition document quoting the Malavalli SPIE paper). Where I could not verify a reference's content, I say so and do not attribute specific teachings to it.

I have not assumed any particular litigation invalidity theory; no party's § 103 contentions for this patent are in the record, and the Vixel v. Brocade / Vixel v. QLogic matters (see Litigation Summary) appear to have settled without a merits holding on validity.

1. The claimed invention in one paragraph (for § 103 purposes)

The patent's contribution is a mode of operating a Fibre Channel fabric switch or intelligent hub ("Fibre Channel Private Loop Device Interconnect System") so that private loop devices — devices that under the FC-AL/FC-PH standards cannot do fabric login (FLOGI) and only understand 8-bit Arbitrated Loop Physical Addresses (ALPAs) with zero domain/area — on different physical loops can exchange frames through the switch without modifying the devices or their drivers (the "Stealth Mode"). Each switch port terminates its own physical loop with an active L_Port that speaks FC-AL as a peer (generates ARBs, OPNs, Closes), filters frames by ALPA (local vs. remote), and routes off-loop frames through the switch fabric. Supporting methods: partitioning the ALPA space across ports and enforcing the partition during loop initialization via LIFA manipulation (claim 23); selectively transmitting LIP only to host-carrying ports when storage is hot-added (claim 25); routing SCSI initiator PLOGI probes to real targets and answering probes to nonexistent ALPAs with an immediate LS_RJT (claims 26–27); and isolating loop re-initialization to the single physical loop on which the event occurred (claim 79).

Independent claims: 1, 2, 18, 23, 25, 26, 27, 79 (system claims 1/2; method claims 18/23/25/26/27/79).

2. Person of ordinary skill in the art (PHOSITA)

Circa February–August 1997: a designer of Fibre Channel physical/signaling layer (FC-PH, FC-AL) controllers and of FC fabric switches — familiar with the ANSI FC-PH/FC-AL/FC-AL-2 working drafts and the FC-FLA fabric-loop-attachment technical report; with 8B/10B ENDEC and loop port state machines; with arbitrated-loop primitives (ARB, OPN, CLS, LIP, LIFA, LISM) and loop initialization; with switch core / route-determination architectures; and with SCSI-3 FCP initiator discovery behavior (PLOGI probing after loop reset).

3. The available prior-art record

A. Standards and technical literature (foundation knowledge)

• ANSI FC-PH / FC-PH-2 / FC-PH-3 and FC-AL / FC-AL-2 (the patent's own "Other Documents" list; earlier revisions cited inside US 5,638,518, e.g., FC-PH Rev. 4.1 (Aug. 12, 1993) and FC-AL Rev. 4.2 (Mar. 11, 1994)). These define: the loop topology; NL_Port loop state machines; primitives ARB/OPN/CLS/LIP; loop initialization (LISM→LIFA→LIRP/LILP); the ALPA table and its non-contiguous valid values; the 126-address limit; the FL_Port concept (one fabric port per loop); and the private vs. public device distinction.
• Fibre Channel Fabric Loop Attachment (FC-FLA) Rev. 2.7, NCITS working draft (the version on the face is dated Aug. 12, 1997 — five days after the '776 filing; a challenger would need an earlier revision to use it as § 102(a)/(b) art, but the draft series was circulating before the filing date and it evidences the PHOSITA's working knowledge).
• Malavalli, "High Speed Fibre Channel Switching Fabric Services," Proc. SPIE vol. 1577 (Sep. 4, 1991) 216–225 and Malavalli, "Distributed Computing with Fibre Channel Fabric," IEEE COMPCON (Feb. 1992) — teach a switching fabric that routes frames between N_Ports using the D_ID, with fabric services, name service, and multiple attached ports.
• Martin, "Fabric Interconnection of Fibre Channel Standard Nodes," Proc. SPIE vol. 1784 (Sep. 8, 1992) 65–71 — fabric interconnection of standard FC nodes.
• Varma et al., "Using Camp-On to Improve the Performance of a Fibre Channel Switch" (1993) and the various FC overview papers (Stephens, Richard, Chin) — general switch/loop performance art.

B. Verified hardware/switch implementations

• US 5,638,518 (Malladi, LSI Logic; filed Oct. 24, 1994; issued Jun. 10, 1997) — "Node Loop Core for Implementing Transmission Protocol in Fibre Channel." Verified: a hardware NL_Port/arbitrated-loop core with a loop state machine performing loop initialization protocol, arbitration and loop fairness per FC-AL, recognizing/generating primitive signals and sequences (ARBs, OPNs, Closes, LIP), plus ENDEC, CRC, and R_RDY flow control. This is squarely the "active L_Port implementing the Fibre Channel Arbitrated Loop protocol, including the generation of ARBs, OPNs and Closes" recited in claims 1/2/18/26.
• US 5,894,481 (Book, McData; filed Sep. 11, 1996; issued Apr. 13, 1999) — "Fiber Channel Switch Employing Distributed Queuing." Verified: an FC fabric switch with a plurality of port controllers (F_Ports), route determination/address validation and translation from frame headers, and a shared-memory switch fabric transferring frames between ports — i.e., the "route determination apparatus" + "connectivity apparatus" of claims 1/2. Because it was filed before the '776's earliest priority date and issued before examination completed, it is § 102(e) prior art for all claims.
• US 6,185,203 (Berman/Vixel) — the '776's own parent (filed Feb. 18, 1997; the "Fibre Channel Switching Fabric"). Not prior art (same applicant, unpublished at the '776 filing date), but its disclosure shows the switch architecture (port control modules, router, switch core) that claims 1/2 presuppose was conventional in the inventor's own earlier work.
• EP 0 876 075 A2 (Nov. 4, 1998), "Fibre channel switching system and method" (counterpart of US 6,160,813, Brocade, filed Mar. 21, 1997). The EP publication post-dates the '776 filing, so it is not § 102(a)/(b) art; the US counterpart, if it issued (it did, Dec. 12, 2000), is § 102(e) art only against '776 claims whose effective filing date is Aug. 7, 1997 (CIP new matter), not against claims fully supported in the Feb. 18, 1997 parent. I could not verify the content of 6,160,813 in this analysis and do not rely on it affirmatively.

C. Face-of-patent references whose content I could not verify in this analysis

US 4,821,034 (Anderson), 4,958,341 (Hemmady), 5,412,653 (Hoppe), 5,418,780 (Henrion), 5,432,907 and 5,841,990 (Picazo), 5,490,007 (Bennett), 5,502,719 and 5,528,584 (Grant), 5,519,695 (Purohit), 5,535,035 (DeFoster), 5,598,541 (Malladi), 5,619,497 (Gallagher), 5,751,715 (Chan), 5,768,530 (Sandorfi), EP 0 709 987 A2. These are primarily general switching/hub patents; I treat them only as background and do not build primary grounds on them.

4. Claim-by-claim obviousness analysis

4.1 System claims 1 and 2 — FC switch whose ports each terminate a private loop with an active L_Port

Elements: first AL with private loop device(s); second device; interconnect system with first and second port control modules, each containing an FC-AL Loop Port State Machine with an active L_Port (ARB/OPN/CLS generation); first state machine providing a point-to-point-like connection with the attached private device; route determination apparatus; connectivity apparatus (switch core).

Proposed combination (primary ground):

1. Book '481 (or Malavalli/Martin) — FC fabric switch with multi-port control modules, route determination by D_ID, and switch connectivity;
2. Malladi '518 — hardware FC-AL loop port state machine / active L_Port that generates ARBs, OPNs, Closes and executes loop initialization;
3. FC-AL / FC-PH standards — loop topology, NL_Port/FL_Port behavior, ALPA addressing, the fact that a loop may contain private devices, and the known FL_Port concept for attaching a loop to a fabric port.

Why a PHOSITA would combine: The record (including the patent's own Background) documents the known deficiencies of single Arbitrated Loops — blocking topology, additive per-device buffering delay, additive distance delay, jitter, and whole-loop reset when any device powers down or is hot-added. The standard remedy trajectory in 1994–1997 was (a) hubs with port bypass to preserve loop integrity, and (b) fabrics for direct-attach devices. The obvious bridging step — putting a Malladi-type FC-AL port engine on each port of a Book-type switch so that each port attaches to its own small loop instead of a single large loop — gives the textbook benefits (bandwidth multiplication, fault isolation, reduced delay) that the fabric paradigm already promised for direct-attach devices. The FC-AL standard's own FL_Port concept already contemplates a fabric port participating in loop protocol at the physical/loop level, and Malladi supplies the state machine to do it. Claim 2's "adapted to contain" language is purely capability-based and is even easier to meet on the art (no device need be present).

Where the ground is vulnerable (why this may be the "real" invention): Prior-art FL_Port operation presupposes a public loop: devices perform FLOGI, and the fabric port occupies ALPA 0 with domain/area fields above the loop. Private devices by definition never FLOGI and cannot address anything with nonzero domain/area, so a stock FL_Port cannot carry their frames off-loop. The '776 terminates each private loop with an active L_Port that impersonates a loop peer/target (transparently, "without the private loop device's knowledge") and filters by ALPA. Whether that transparency trick — as opposed to merely attaching a loop to an FL_Port — was "obvious" is the crux. A challenger would argue the only difference is design choice (terminate the loop at the port and bridge frames, exactly as a switch does for any shared segment); a patentee would argue the prior art taught away by requiring public-loop behavior and that the active-L_Port-per-port + ALPA filtering + off-loop routing combination is not suggested by any single reference. Malladi is a node core (an NL_Port for a device), not a switch port; nothing in Malladi or Book suggests making a fabric port masquerade as a full ALPA-space device. This is a genuine § 103 battleground.

4.2 Claim 18 — receive-and-filter frames; forward locally if the D_ID is on the local loop; generate an "open" response at the port control module if the address is off-loop

Proposed combination: Book '481 + Malladi '518 + FC-AL (OPN semantics), optionally with Varma "camp-on" (switch accepts frames for later delivery).

Motivation: Any switch port must distinguish frames it should forward (local destination) from frames it should absorb and route (remote destination) — the mask-and-compare ALPA filter of dependent claim 22 is a trivial address-filter implementation. The interesting step is "generating an 'open' response": on an arbitrated loop, if the fabric port did not respond to the initiator's OPN directed at an off-loop ALPA, the OPN would circulate and return to the initiator, which would abort the exchange. A PHOSITA who has decided to route private-loop frames off-loop (per 4.1) must make the port respond to the open — Malladi's loop state machine does exactly that as part of the FC-AL protocol. Once the system of claim 1 is obvious, claim 18 is largely the protocol-necessary consequence. The main non-obvious hook is the "if not on the first loop → open response" filtering decision being made in the port control module before the loop protocol completes; a challenger would say this is inherent in any loop-attached switch port and was already implicit in the camp-on art.

4.3 Claim 23 — partitioning ALPAs into non-overlapping sets, assigning sets to physical loops, enforcing the assignment during loop initialization (restricting devices to choose from the assigned set)

Proposed combination: FC-AL loop-initialization procedure (LISM/LIFA — the temporary loop master controls the LIFA ALPA bitmap and can reserve ALPAs) + Book '481/Malavalli switch architecture (which already needs per-port address tables) + Malladi '518 (loop initialization state machine in the port).

Motivation: A fabric routes by address; the PHOSITA designing a multi-loop private-device switch needs predictable, collision-free ALPA assignments per port to build the routing table. The standard already gives the loop master the LIFA bitmap as the mechanism to grant/withhold ALPAs, and the standard's ALPA table (non-contiguous valid values in 1x–Ex ranges) is published. Subnetting/address-space partitioning to simplify routing tables is one of the most pedestrian techniques in networking. Enforcing the partition by having the port (as temporary loop master, e.g., by claiming the lowest WWN of zero in LISM) set the LIFA bitmap to reserve all but the assigned range is a direct application of the standard's own master-selection and LIFA tools. On this record, claim 23 is the most vulnerable of the independent claims: the elements are (i) a known address space, (ii) a known partitioning concept, and (iii) a known standard mechanism (LIFA) that happens to be controlled by the port when it wins LISM. Dependent claim 24 adds only "interconnecting at least certain of the Arbitrated Loops through a Fibre Channel [switch]," which is the 4.1 combination.

4.4 Claim 25 — on detecting storage added to a first loop, transmit LIP only on ports whose loops contain non-storage (host) devices, not on storage-only loops

Proposed combination: FC-AL (LIP is the standard "configuration change → re-initialize" primitive; host SCSI initiators discover targets only by re-probing after loop reset/LIP) + the multi-loop switch of 4.1 + routine hot-plug/event-detection logic.

Motivation: In a single-loop environment, inserting a device automatically causes LIP and therefore re-probing of the whole loop. When loops are segmented (4.1), the host's loop never sees the new storage's initialization — so hosts would never discover the new device unless the switch initiates LIP on the host ports. The idea that a configuration manager triggers a reset of affected (host) segments while leaving unaffected (storage-only) segments running is a straightforward application of the segmentation rationale itself (isolate disruptions to the segment that needs them). The selective aspect — LIP only non-storage ports — follows from the stated goal of not disrupting storage traffic; a PHOSITA optimizing the 4.1 system would arrive at it naturally. The genuine question is whether the specific trigger (storage hot-add on a different physical loop through the switch) would have occurred to the PHOSITA; the patent's own Background concedes the underlying "hosts can't see new devices" problem is caused by loop segmentation, so the fix (host reset) is a predictable response to a problem the designer created — which cuts in favor of obviousness under the KSR "obvious to try / predictable variation" rubric, but a patentee would counter that the claimed selection (host ports only) is a deliberate optimization not suggested by the hub art, where a hot-add resets everyone.

4.5 Claims 26 and 27 — PLOGI probe routing to real targets; LS_RJT response to probes for nonexistent ALPAs

Elements (27): receive PLOGI I/O probes; perform address lookup; route the probe to the controller and return LS_RJT if (i) no match, or (ii) match but no device with that destination ALPA exists on the corresponding loop. Dependent claim 28 detects "no device" by sending a frame on the loop and simultaneously receiving the same frame back — the standard FC-AL self-receive behavior.

Proposed combination: FC-AL/FCPH (PLOGI and LS_RJT are standard Extended Link Services; the initiator's serial probing of all 126 ALPAs after each loop reset is standard behavior) + FC fabric art (Book '481; Malavalli — a fabric routes frames and its control processor can generate link-service responses) + 4.1 multi-loop system.

Motivation: This is the clearest "problem–solution" pairing in the patent. Once a switch terminates the loop and silently discards undeliverable Class 3 frames (as FC-PH requires), a SCSI initiator probing a nonexistent ALPA receives no response and must wait out a timeout that the patent itself quantifies as up to ten seconds per ALPA × 126 ALPAs — an initialization time no system designer would accept. The protocol-correct, immediate answer to a PLOGI for a nonexistent port is an LS_RJT, a standard FC ELS response defined in FC-PH Rev. 4.3 (as the patent itself acknowledges in its Definitions). The only "deviation" from the standard is returning LS_RJT for Class 3 frames that a pure fabric would discard — and doing so is the obvious way to avoid the timeout. A PHOSITA combining 4.1's system with knowledge of PLOGI probing and LS_RJT semantics would naturally program the fabric controller to answer nonexistent ALPAs. Claim 26 (route to real devices when a match exists) is even more clearly obvious: that is the ordinary function of any fabric — route a frame addressed to an attached device. This group is likely the weakest against a § 103 challenge, though dependent claim 28's loop-back detection is standard FC-AL behavior and would add little resistance.

4.6 Claim 79 — a loop-initialization event on one physical loop is contained to that loop; other attached loops are unaffected

Proposed combination: Same 4.1 combination. Loop isolation is an inherent physical property of terminating each loop at its own active L_Port: LIP and other loop primitives circulate only within a loop and cannot cross a switch port that does not retransmit them onto other ports (contrast a passive hub, whose internal loop is continuous and propagates LIP to every attached device). Once the 4.1 system (separate physical loop per port) is in place, claim 79's behavior follows as a matter of course; the only additional step is not propagating the LIP. The patent's own Background identifies whole-loop reset on device power-up/down/failure as a known problem, and the passive-hub art's solution (port bypass) shows the industry's motivation to contain failures. Claim 79 is highly vulnerable: if the system of claim 1 is held obvious, this method claim adds little beyond what the system inherently does.

5. Cross-cutting motivation to combine

The patent's own Background supplies the acknowledged engineering problems (blocking topology; additive 225 ns/device buffering delay; additive distance delay; jitter from bypassed nodes; loop-wide resets on hot-add/removal/power events; a single loop's bandwidth ceiling; unacceptable PLOGI timeouts). Each independent claim maps onto one of those acknowledged problems: 1/2/79 → segmentation/bandwidth/fault isolation; 18 → routing between segments; 23 → making segmentation administrable; 25/26/27 → preserving SCSI initiator discovery semantics across segments. Under KSR, where the art's known problems point to the solution and the combination is of known elements (FC-AL loop engine + FC switch) each performing its known function, a challenger has a coherent prima facie case for claims 18, 23, 25, 26, 27, and 79 once the system of claims 1/2 is in place or assumed obvious.

6. Counterweights — arguments for non-obviousness (and litigation realities)

1. No single reference or simple combination teaches "Stealth Mode." The prior art splits into two camps: FC-AL node/hub art (loops of private devices, no off-loop routing) and fabric art (off-loop routing, but for public/direct-attach N_Ports requiring FLOGI and full 24-bit addresses). Nothing in Malladi, Book, Malavalli, Martin, or the FC-AL/FC-PH drafts on this record tells the PHOSITA to make a fabric port masquerade as a large-ALPA private-loop peer so that unmodified private devices can be switched across loops. An FL_Port per the standard expects public behavior; the '776's transparency for private devices is the type of design insight § 103 is meant to protect if the art taught away from it.
2. The LS_RJT "deviation" (claims 26–27) is presented by the patent as a deliberate departure from the ANSI requirement that undeliverable Class 3 frames be silently discarded — a challenger must show the PHOSITA would have been motivated to violate the standard's discard rule; the counter is that the standard itself defines LS_RJT for rejected link-service requests, making the response the obvious, standards-compliant way to say "no such port."
3. Secondary considerations (from the Litigation Summary): the patent was asserted against QLogic and Brocade; the Brocade matter settled with a multi-year standstill, and the technology was commercially adopted — consistent with the claims having value, though settlements are not validity holdings. Brocade's own, roughly contemporaneous switch work (US 6,160,813, filed Mar. 1997 — a few weeks after Vixel's Feb. 1997 priority date but before the CIP filing) cuts both ways: simultaneous independent development can suggest the solution was obvious, but Brocade's QuickLoop/Fabric-Assist approach was marketed as a different mechanism, which a patentee would use to argue no single obvious path existed.
4. File-wrapper unknowns: I do not have the prosecution history, so I cannot identify which references the examiner applied to which claims, whether new-matter rejections shaped the independent claims, or whether terminal-disclaimer/priority issues (cf. the '647,000 continuation) constrain the effective filing dates of particular claims. Those facts materially affect any real § 103 ground, especially the use of Brocade's Mar. 1997 filing against CIP-only limitations.

7. Bottom line

• Strongest § 103 cases (likely obvious if challenged with a developed record): claim 23 (ALPA partitioning via the standard's own LIFA master mechanism); claims 26/27 (routing PLOGI probes and answering nonexistent ALPAs with the standard LS_RJT to avoid the acknowledged multi-second timeouts); and claim 79 (loop isolation as the inherent result of per-port loop termination). These read largely as predictable applications of standard FC-AL mechanisms to the multi-loop switch environment.
• Intermediate: claim 18 (filtering + open response) and claim 25 (selective LIP on host ports) — strong motivation exists, but the specific claimed responses depend on first adopting the 4.1 architecture.
• Weakest § 103 case (best chance of surviving): claims 1 and 2 — the "Stealth Mode" system itself, where the record lacks a reference that attaches a private loop to a switch port through an active L_Port acting transparently as a loop peer. The outcome would turn on whether the FL_Port concept in FC-AL/FC-FLA plus Malladi's loop core plus Book's switch is held to render that design choice obvious, and on secondary considerations.
• Recommended next steps if this were a real challenge: obtain the USPTO file wrapper (to see the applied art and any priority/new-matter positions), verify the content and effective dates of Brocade US 6,160,813/EP 0 876 075 and earlier FC-FLA revisions, obtain expert testimony on whether the FL_Port standard taught away from private-loop transparency, and pin down the precise effective filing date of each independent claim (Feb. 18, 1997 parent support vs. Aug. 7, 1997 CIP new matter), since that date controls which references (e.g., Brocade's Mar. 1997 filing) qualify at all.

Confidence caveat: Everything above is analytical inference from the face-of-patent references and verified reference content; I did not review the prosecution history, the full text of most cited patents, or the FC-FLA draft, and no court or PTAB has made a merits finding on the validity of these claims in any searchable record available to me.