US 6266324

I'll search for information on US Patent 6266324 in the USPTO database and check for any CAFC docket activity.

The first search confirmed the patent's bibliographic data. Let me do additional targeted checks for CAFC docket activity and USPTO status.

I've gathered what's available. Note: the searches returned no CAFC 2026 docket or PTAB/litigation results for this patent number, and I could not access the USPTO's official PAIR/PatentCenter interface directly. The bibliographic data below is taken from the authoritative Google Patents full-text record (fetched 2026-09-09) and is consistent across third-party mirrors (FreePatentsOnline, Justia, EveryPatent).

Summary — US Patent 6266324 B1

Abstract

"In an ATM device comprising a switch core 11, a port shaping unit 25 is arranged within the switch core 11 to carry out a port shaping operation. The port shaping unit 25 controls reading timing of each cell stored in a shared buffer 10. Therefore, a delay to absorb the CDV is decided by the reading timing and the port shaping operation is achieved within the ATM device without attaching any additional memories to the ATM device."

Field / technical problem

The invention relates to an ATM (asynchronous transfer mode) device used in networks providing Constant Bit Rate (CBR) service. CBR traffic (e.g., voice) requires synchronization between transmitter and receiver, which is disturbed by cell delay variation (CDV). The prior-art solution (Japanese Unexamined Patent Publication No. 8-163150) placed dedicated shaping units with shaping FIFOs after each output port — hardware-heavy. The invention instead performs "port shaping" by controlling read timing out of the ATM device's existing shared buffer, eliminating per-port shaping FIFOs. A second embodiment adds shaping-error correction to prevent throughput loss when (a) no cell is present at a scheduled output time or (b) output timings of multiple output ports mapped to one physical trunk collide.

Independent claims — plain-language overview

Claim 1 (apparatus) — An ATM device having input ports, output ports, a shared buffer that stores incoming cells for transmission as output cells, and a switch core that controllably switches the shared buffer. The switch core contains:

• a judging section that checks, per output port, whether a cell is actually stored in the shared buffer; and
• a shaping control section that holds a shaping rate for each output port and generates an output-indication signal at the timing when a stored cell should be output.

If the judging section finds a stored cell present, the switch core reads that cell from the shared buffer and outputs it through the particular output port for which the shaping control section produced the indication signal. (Note: the printed claim uses the word "compromises," which appears to be a typographical error for "comprises" — quoted literally, not auto-corrected.)

Claim 6 (method) — A port shaping method for use in the same type of ATM device (input ports, output ports, shared buffer, switch core). The switch core is provided with the same judging section and shaping control section, and operates the same way: when the judging section confirms a stored cell exists, that cell is read from the shared buffer and output through the particular output port associated with the produced output-indication signal. Effectively the method counterpart of claim 1.

Dependent claims (all depend from claim 1)

• Claim 2 — The switch core additionally has a queue controller (queue control for writing/reading cells to/from the shared buffer) and an output port selecting section that, upon the indication signal plus a finding that a cell is present, tells the queue controller which output port to use.
• Claim 3 — The shaping control section shifts the cell output timing when no stored cell is present in the shared buffer at the scheduled output time.
• Claim 4 — The shaping control section shifts one of the cell output timings when the output timings for at least two output ports coincide (i.e., collision resolution where multiple ports share a physical trunk).
• Claim 5 — The shaping control section comprises shaping-error correcting means (receives a stored-cell-absence signal and a permission signal for a specific port, and produces a timing-error signal) plus a shaping controller that responds to the timing-error signal to produce the output-indication signal with corrected timing. (Implemented in the specification as subtracter 53, counters Ct 57 and Cs 58, inverter 54, AND gate 55, OR gate 59, SPR register 56.)

Uncertainty / notes

• CAFC 2026 dockets: No results were found linking patent 6266324 to any Federal Circuit appeal or 2026 docket entry in my searches. Given the patent's 20-year term (from the April 22, 1998 filing date) and its "Expired – Lifetime" status as of April 2018, active post-expiry litigation is inherently limited (at most to pre-expiry damages claims), so the absence of docket hits is unsurprising.
• I did not directly query the USPTO Patent Center/PAIR or the CAFC docket database in this session; the bibliographic and status data rest on the Google Patents authoritative record plus consistent secondary sources. If you need official confirmation of current ownership or any proceeding history, the USPTO Assignment Database and Patent Center would be the authoritative next check.

Based on my searches of publicly available sources (including general web searches and patent-litigation oriented queries), I found no litigation involving U.S. Patent No. 6,266,324 (titled "ATM device and shaping method").

Findings

Known litigation involving US 6,266,324: None found.

The searches I ran specifically for this patent number (queried as "6266324," "6,266,324," and "6266324B1," including combined with terms like "litigation," "lawsuit," "civil action," and "defendant") returned no case results tied to this patent. The results that did appear were unrelated (e.g., other patent numbers, other technologies, or general patent-litigation news), and none involved the '324 patent.

Context that may explain the absence of litigation

• Patent status: US 6,266,324 B1 expired (per Google Patents: "Expired - Lifetime," with anticipated expiration on 2018-04-22, i.e., at the end of its full term). An expired patent generally cannot support new infringement suits for post-expiration conduct.
• Assignee history: The patent originated with NEC Corporation (filed 1998-04-22, priority date 1997-04-23; JP priority application JP9-106009), was assigned to NEC Electronics Corporation (2003), and then to Renesas Electronics Corporation (2010). I found no records of these entities asserting the '324 patent in district court or at the ITC.
• Technology vintage: The patent concerns ATM (Asynchronous Transfer Mode) port shaping using a shared buffer — an older networking technology that peaked in the late 1990s/early 2000s, further reducing the likelihood of modern enforcement.

Caveat

My searches were limited to general web sources; I could not directly query PACER, the USPTO Assignment/Patent Center records, or the Unified Patents litigation portal (the requested portal did not return searchable results in my queries). It is therefore possible that an older, pre-2000s district court case naming this patent exists in paper records or databases not indexed on the open web. If you need absolute certainty, I recommend a docket-database search (e.g., PACER, Docket Navigator, RPX, or LexisNexis/ Westlaw) using the patent number 6,266,324.

Bottom line: On the available evidence, no litigation is known involving US patent 6266324, and I will not speculate or fabricate case details.

Proceedings overview

There is zero AIA trial activity on file for US Patent 6,266,324. The USPTO Open Data Portal (ODP) returns no IPR, PGR, or CBM proceedings for this patent as of the most recent ingest, and targeted web searches (including PTAB-specific and docket-oriented queries on the patent number in multiple formats) surfaced no older or recently-filed petitions, no Final Written Decisions, and no Federal Circuit appeals. For a defendant, this is a neutral-to-favorable posture in a narrow sense — there is no PTAB estoppel baggage and no prior petition record to work around — but it also means the patent has never been stress-tested at the Board, so an IPR-based defense would be starting from scratch on a now-expired, 2001-era ATM patent whose claim scope has never been PTAB-construed.

Proceedings detail

None on file

• Type: N/A — no Inter Partes Review, Post-Grant Review, or Covered Business Method proceeding has ever been filed against US 6,266,324.
• Filed: N/A
• Status: No PTAB proceedings (canonical structured data from USPTO ODP: no AIA trial proceedings returned; web search corroborates — no petition numbers, no institution decisions, no FWDs exist to cite).
• Judge panel: N/A
• Petition grounds: N/A
• Institution decision: N/A
• Final Written Decision: None issued.
• Settlement / termination: N/A
• Appeal: N/A
• Defensive value: No claim of 6,266,324 has ever been canceled or even challenged at the PTAB. The patent is expired (USPTO status: "Expired – Lifetime," anticipated expiration 2018-04-22, with maintenance fees paid through the 12th year), which caps any recovery to pre-expiration conduct regardless of PTAB outcome — but there is no Board ruling you can wave at a plaintiff today.

Strategic summary

Claims CANCELED vs. SUSTAINED vs. UNTESTED. All six claims (claims 1–6: independent claims 1 and 6 — the device and port-shaping method claims — plus dependents 2–5) remain exactly as granted on 2001-07-24. None has been canceled, none has been sustained by a PTAB merits decision, and all are effectively UNTESTED in any AIA trial forum. The only post-grant scrutiny on the record was the original foreign prosecution and the Japanese Office Action noted on the file wrapper — not a U.S. PTAB trial.

Estoppel landscape (§ 315(e)(2)). Because there have been no IPR/PGR/CBM petitions, there are no petitioners and no estoppel running against anyone. Every prior-art ground that could have been raised remains fully available to any defendant in district court or in a future IPR petition — subject to the § 315(b) one-year bar measured from service of a complaint, and subject to the practical reality that the patent expired in April 2018. For a defendant facing assertion today, that means: (1) any § 102/§ 103 defense based on the substantial body of mid-1990s ATM shaping and scheduling art (e.g., the JP '150 CDV reference discussed in the patent's own Background, Hitachi's traffic-shaping work, Fujitsu's buffer-control art, NEC's own traffic-shaping devices) can be raised in litigation without any PTAB estoppel concern; and (2) the more relevant threshold question is likely laches / damages limitation, not validity — this is a pre-AIA, expired ATM switch patent whose commercial relevance peaked in the late 1990s.

Pattern signals. No repeat petitioner, no defensive-aggregator chain (no Unified Patents or similar entity appears anywhere in the record), and no evidence of the patent owner (NEC → NEC Electronics → Renesas Electronics) litigating or defending this patent at the PTAB. The absence of IPRs is itself informative: this is precisely the profile of a patent that was never commercially asserted with enough force to provoke a petition — the assignee is a large semiconductor company, the art is obsolete ATM hardware, and the patent expired nearly a decade ago with maintenance fees paid to term. Well-asserted patents attract IPRs; this one never did, which strongly suggests it has not been the subject of meaningful recent assertion activity.

Recommended next steps

• There is no FWD to link or quote — do not let anyone tell you otherwise. If opposing counsel cites a PTAB decision against this patent, the representation is false; the ODP and independent searches show no AIA proceeding ever existed.
• No active proceedings — there are no institution-decision deadlines, oral-hearing dates, or FWD due dates to calendar.
• If you are a defendant facing assertion of 6,266,324 today, the PTAB record is a blank slate. The highest-value moves are: (a) confirm the patent's expired status (2018-04-22) and cap any exposure to pre-expiration conduct — in most post-expiration scenarios that means no prospective injunctive relief and damages only for past infringement within the limitations period; (b) evaluate a district-court validity defense using the pre-AIA prior art catalogued in the patent's own file history and cited references (including JPH08-163150, EP0471344, EP0753981, US6005868, US5940375) — none of these grounds is estopped; and (c) only if a district-court case is actually filed against you and the one-year § 315(b) clock has not run, consider a fresh IPR petition on expired-patent grounds — but weigh the cost against the reality that an expired ATM patent from 2001 with no assertion history is unlikely to be the linchpin of a serious damages case. The absence of PTAB history is a signal, not a shield — it means the patent is unweakened by prior Board litigation, and if you fight, you will be the first to test it.

Note: I could not locate any PTAB proceeding, FWD, or CAFC appeal for this patent through the structured USPTO data or web searches as of 2026-09-09. If a proceeding number is not on the ODP record and cannot be verified by public search, per the operating rules I will not invent one. If you have a specific proceeding number from a demand letter or litigation notice, I can verify it against PTAB E2E and pull the full record.

Inventors

• Kiyoshi Kirino — NEC Corporation (Japan). Confirmed as assignor to NEC Corp on the original assignment (reel 009229/0550, effective 1998-04-21).
• Nobuyuki Mizukoshi — NEC Corporation (Japan). Same assignor entry.
• Hideo Ishida — NEC Corporation (Japan). Same assignor entry.

All three inventors were employed by the original assignee NEC Corporation at filing (the JP priority application JP 106009/1997 was assigned to NEC, and the US assignment names NEC as the sole assignee). No public data in the retrieved record indicates any of them left NEC within 12 months of filing; nothing unusual is evident from the assignment record itself.

Original assignee

NEC Corporation is the entity named on the issued patent (also the current assignee at grant per Google Patents legal events). NEC was (and is) a large operating Japanese electronics/telecommunications company whose product lines included ATM switching systems and ATM-layer semiconductor devices, so it is highly likely that products embodying these claims were shipped by NEC or its semiconductor affiliate — though the retrieved record does not identify a specific product SKU.

The patent's current status: expired (anticipated expiration 2018-04-22, i.e., full 20-year term from the 1998-04-22 US filing), with maintenance fees paid through the 12th year (payments recorded 2004-12-29, 2008-12-24, 2012-12-27). The assignee kept the patent alive to natural expiration — not an abandonment pattern. NEC Corporation still operates. The semiconductor arm, NEC Electronics Corporation, was merged into Renesas Electronics Corporation in 2010, which remains an operating semiconductor company.

Assignment timeline

Note: Correspondent names (attorney/agent of record per USPTO cover sheets) are not surfaced in the Google Patents legal-event feed used as the source for this reconstruction, and the USPTO Assignment Center could not be queried directly within this session. The conveyances, dates, and reel/frame numbers below are taken from the recorded legal events; the correspondent field for each link should be confirmed by opening the PDF at the Assignment Center (search patent 6266324).

• 1998-04-21 (executed) / recorded 1998-06-02 — Reel 009229/0550

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Kiyoshi Kirino, Nobuyuki Mizukoshi, Hideo Ishida
  • Assignee: NEC Corporation
  • Correspondent: not available in retrieved record
  • Context: Standard inventor-to-employer assignment at filing (US application 09/064,038 claiming JP priority 1997-04-23).

• 2002-11-01 (effective) / recorded 2003-02-25 — Reel 013774/0295

  • Conveyance: Assignment
  • Assignor: NEC Corporation
  • Assignee: NEC Electronics Corporation
  • Correspondent: not available in retrieved record
  • Context: Internal corporate reorganization — transfer of NEC's semiconductor-related assets to its semiconductor subsidiary (spin-off of the NEC Electronics business).

• 2010-04-01 (effective) / recorded 2010-10-22 — Reel 025183/0611

  • Conveyance: Change of Name
  • Assignor: NEC Electronics Corporation
  • Assignee: Renesas Electronics Corporation
  • Correspondent: not available in retrieved record
  • Context: Change of name recorded following the 2010 merger creating Renesas Electronics from NEC Electronics + Renesas Technology — an internal reorg, not a sale.

• 2015-08-06 (effective) / recorded 2017-11-29 — Reel 044928/0001

  • Conveyance: Change of Address
  • Assignor/Assignee: Renesas Electronics Corporation (same entity)
  • Correspondent: not available in retrieved record
  • Context: Address update only — not an ownership conveyance.

No other conveyances (no security agreements, licenses, releases, or NPE transfers) appear in the recorded legal-event history. There are no recorded post-issuance transfers outside the NEC → NEC Electronics → Renesas corporate family.

Timeline diagram

timeline
    title Ownership of US 6266324
    1997 : JP priority filed by NEC
    1998 : US application filed
         : Inventors assign to NEC
    2001 : US patent issued
    2003 : Assigned to NEC Electronics
    2010 : Renesas change of name
    2017 : Renesas change of address
    2018 : Patent expired

NPE / troll-pattern signals

1. Shell-entity transfer — not present. Every assignee is a large operating corporation (NEC Corp, NEC Electronics Corp, Renesas Electronics Corp). No "IP / Licensing / Holdings / Ventures" LLC, no registered-agent address, no single-purpose entity appears at any reel/frame (009229/0550, 013774/0295, 025183/0611).
2. Known asserter in the chain — not present. No Acacia, Marathon, Intellectual Ventures, Wi-LAN, Conversant, or any Unified Patents / RPX-listed entity appears as assignor or assignee in any recorded event.
3. Repeat correspondent across the chain — unclear. Correspondent names are not published in the Google Patents legal-event records retrieved, so recurrence could not be verified. However, all conveyances are intra-corporate reorg filings; there is no affirmative evidence of any NPE-associated correspondent.
4. Cascading transfers — not present. Only three ownership conveyances over 12 years (1998, 2003, 2010), each a standard corporate event separated by years — the opposite of chained-LLC cascading.
5. Pre-litigation transfer — not present. No infringement litigation involving this patent was identified; the last ownership event (2010) predates expiration by eight years and no assertion followed.
6. Bankruptcy fire-sale — not present. NEC and Renesas never sold this patent in bankruptcy; it expired in the Renesas family after maintenance fees were paid through year 12.
7. Privateering — not present. No operating-company-to-NPE transfer exists in the record.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN; it remains with operating company Renesas Electronics.

Verdict

Operating-company assertion — with the clarification that no assertion was ever identified and the patent expired in 2018. Every recorded conveyance (reels 009229/0550, 013774/0295, 025183/0611) is an internal corporate reorganization inside the NEC → NEC Electronics → Renesas family of operating companies; no shell LLC, known asserter, cascading transfer, or pre-litigation transfer appears anywhere in the chain. This is a legacy operating-company patent that was maintained to natural expiration — there is no NPE pattern of any kind. Verification: search patent number 6266324 at https://assignmentcenter.uspto.gov/.

I'll research US Patent 6,266,324 and its cited references. Let me start by locating the patent record and gathering details on each citation.

The patent record is confirmed. Now let me research each cited reference. I'll batch searches for the U.S. patent citations first.

I have reached the research step limit, so I'll now provide the analysis based on the USPTO/Google Patents record for 6,266,324 (fetched full text), the live search results I gathered, and citation metadata. Where a full-text of a given reference was not retrievable within the search budget, I say so explicitly and label the claim-mapping as provisional.

US 6,266,324 B1 — Patent Record Confirmed

• Title: ATM device and shaping method
• Inventors: Kiyoshi Kirino, Nobuyuki Mizukoshi, Hideo Ishida
• Assignee: NEC Corporation (later NEC Electronics, then Renesas Electronics)
• Priority application: JP 9-106009, filed 1997-04-23
• U.S. application: Ser. No. 09/064,038, filed 1998-04-22
• Grant date: 2001-07-24; status: Expired–Lifetime (expired 2018-04-22)
• Family: EP 0878937 A1/B1, JP 2965070 B2 (JPH10303906A), DE 69833587 T2

Independent claims (pre-AIA, filed pre-2013-03-16, so § 102 in its pre-AIA form applies):

• Claim 1 — ATM device: input ports, output ports, a shared buffer, and a switch core that includes (i) a judging section judging presence of a stored cell in the shared buffer for each output port and (ii) a shaping control section having a shaping rate per output port that produces an output indication signal at a cell-output timing; if the judging section finds a cell present, the cell is read from the shared buffer and output on the port whose indication signal was produced.
• Claim 2 — adds a queue controller (write/read queue control of the shared buffer) and an output-port selecting section that informs the queue controller of the chosen port.
• Claim 3 — shaping control section shifts the cell output timing when no stored cell is present at the scheduled timing.
• Claim 4 — shaping control section shifts one of the timings when two output ports' timings coincide (plural ports on one physical trunk).
• Claim 5 — specific structure: shaping-error correcting means (receiving a stored-cell-absence signal and a permission signal, producing a timing-error signal) plus a shaping controller producing the timing-controlled indication signal.
• Claim 6 — method claim mirroring claim 1.

The inventive core (per the specification): CDV absorption/port shaping is performed inside the switch core by controlling the readout timing from the existing shared buffer, thereby eliminating per-output-port shaping FIFOs placed downstream of output ports (the technique in the patent's own Background art, JP-A 8-163150).

Cited References and § 102 Analysis

Below are the twelve patent documents appearing in the "Patent Citations" list of the 6,266,324 record. For § 102 purposes, the relevant dates are: invention/priority date 1997-04-23 and U.S. filing date 1998-04-22 (one-year § 102(b) critical date: 1997-04-22). Claim mapping reflects which limitations each reference plausibly discloses on its face; I flag where I could not verify full text.

A. References that are clearly prior art (published before 1997-04-23)

1. EP 0471344 A1 — Hitachi, Ltd., "Traffic shaping method and circuit"

• Dates: priority (JP 2-215705) 1990-08-17; published 1992-02-19.
• Description (verified in substance via its U.S. counterpart, US 5,280,475): A shared-buffer ATM switch in which cells are chained in list structures per output and per VP/VC identifier; a counter periodically designates output lines, a bandwidth table assigns connection identifiers to output time slots at a frequency matching the connection bandwidth, and cells are read out of the shared buffer in accordance with the time-slot assignment — i.e., per-output shaping by controlling shared-buffer read timing (the same general mechanism claimed in 6,266,324).
• § 102 status: Prior art under § 102(a)/(b) (published 1992, well before both the 1997-04-23 invention date and the 1997-04-22 bar date).
• Potentially anticipates: Claim 1 (shared buffer; per-output, rate-based shaping by readout timing; judging presence via the list-structure check) and Claim 6 (method). Its dependent-claim 2 discloses examining another slot "if no packet exists" in the assigned list structure — arguably touching Claim 3's "shift timing when no cell present." Claims 4 and 5 (dual-port conflict correction; shaping-error correcting counter) are not clearly disclosed.

2. US 5,280,475 A — Hitachi, Ltd., "Traffic shaping method and circuit" (Yanagi, Takase, Kozaki, Gohara)

• Dates: U.S. filed 1991-08-14 (Appl. 07/745,466); JP priority 1990-08-17; granted 1994-01-18.
• Description: Same disclosure as EP 0471344 (above); shared-buffer switching system with traffic shaping per output/connection, using bandwidth tables, counters, and address chains in the shared buffer; if no cell exists for the assigned connection identifier, another identifier/time-slot is examined.
• § 102 status: Prior art under § 102(a)/(b) (issued 1994-01-18). This is the strongest single U.S. patent reference for the "shape by controlling shared-buffer read timing" concept.
• Potentially anticipates: Claims 1, 3, and 6; arguably Claim 2 (queue/address-chain controller is present). Claims 4–5 less likely on their specific error-correction/counter structure.

3. JPH0498938A — Hitachi, Ltd., "Band control method and circuit"

• Dates: filed 1990-08-17; published 1992-03-31.
• Description: Japanese companion to the Hitachi traffic-shaping work (band/bandwidth control circuit for cell output timing). Full text not retrieved in this search; description inferred from title/family.
• § 102 status: Prior art under § 102(a)/(b) (published 1992).
• Potentially anticipates: Most plausibly Claim 1/6 in combination with the family member above; as a stand-alone § 102 reference I cannot confirm full element coverage without the text — flagged as provisional.

4. JPH02121549A — Fujitsu Ltd., "Packet transmission device"

• Dates: filed 1988-10-31; published 1990-05-09.
• Description: Early packet/cell transmission device (this document is also cited inside the Hitachi ATM switch family, e.g., in US 5,799,014's file history, as a Japanese reference on cell buffer control). Full text not retrieved here.
• § 102 status: Prior art under § 102(a)/(b).
• Potentially anticipates: Unclear from metadata alone; plausibly relevant only to the most generic buffer/read-control limitations of Claims 1/6. Provisional.

5. JPH08125668A — Hitachi, Ltd., "ATM interface and shaping method"

• Dates: filed 1994-09-02; published 1996-05-17.
• Description: ATM interface with shaping; full text not retrieved. Likely discloses shaping at the ATM-layer interface (per-connection cell spacing).
• § 102 status: Prior art under § 102(a)/(b).
• Potentially anticipates: Candidate for Claims 1/6's generic shaping-timing/read-control limitations if it shows shared-buffer read-timing shaping; unverified — provisional.

6. JPH08163150A — NEC Corp., "CDV control method and device for CBR traffic"

• Dates: filed 1994-12-12; published 1996-06-21.
• Description: This is the reference the 6,266,324 specification itself identifies as the conventional approach: a shaping FIFO + monitor circuit + control circuit placed in each stage posterior to the output ports, delaying each cell by a computed amount to absorb CDV for CBR traffic.
• § 102 status: Prior art under § 102(a)/(b). Note that the 6,266,324 patent expressly argues its improvement is to eliminate such post-output shaping FIFOs by shaping through shared-buffer read timing — which cuts against a finding that this reference fully anticipates Claim 1 (which requires reading from the shared buffer under switch-core timing control).
• Potentially anticipates: The monitor circuit arguably maps to the "judging section" and the timing/delay control to the "shaping control section" at a high level, so it is a legitimate § 102 candidate for Claims 1 and 6 if the shared-buffer-read limitation is read broadly; weaker for Claims 2–5 (no queue-controller/port-selector combination, no missing-cell or coincident-timing shifting within a shared-buffer read scheduler as claimed).

7. EP 0753981 A2 — Fujitsu Limited, "Buffer control system"

• Dates: filed 1995-07-14; published 1997-01-15 (i.e., before the 6,266,324 priority date of 1997-04-23).
• Description: Buffer control system in a cell-exchange context; full text not retrieved in this search. Title suggests shared/queued buffer read/write scheduling rather than downstream FIFO shaping.
• § 102 status: Prior art under § 102(a)/(b).
• Potentially anticipates: Candidate for Claims 1/2/6 (buffer queue control with read scheduling); detailed element mapping unverified — provisional.

B. U.S. patent references whose U.S. filing dates precede 1997-04-23 (§ 102(e)/(g) candidates) or which otherwise post-date publication

8. US 5,799,014 A — Hitachi, Ltd., "ATM cell switching system" (Kozaki, Yanagi, Aiki, Ito, Aoki, Gohara)

• Dates: Continuation application filed 1994-09-16 (08/306,978) in a chain back to US 07/218,217 filed 1988-07-13 (JP priority 1987-07-15); granted 1998-08-25.
• Description (verified from retrieved text): Shared-buffer-type ATM switch with per-output-line FIFO address queues; the buffer-memory control circuit reads cells out at predetermined time intervals per output line using a control table that designates, in circulation, which output-line queue chain to read — i.e., output scheduling at line rates by controlling shared-buffer read timing. Accommodates output links of differing rates.
• § 102 status: Although granted 1998-08-25 (after 6,266,324's priority date), it qualifies as prior art under § 102(e) (and potentially § 102(g)) because the U.S. chain was filed in 1988–1994, long before the 1997-04-23 invention date. Not § 102(b) (issued within one year of 6,266,324's filing? — no, more than one year before filing it is not; it issued after; the § 102(b) analysis is irrelevant given § 102(e) applies).
• Potentially anticipates: Claim 1 (shared buffer; per-output read timing control in the switch core; queue-presence judgment per output) and Claims 2 and 6 (queue controller + FIFO address queues per output port). Claims 3–5 (shift-on-empty, shift-on-conflict, error-correcting counter) are not clearly disclosed; note the family's later members do discuss QoS/class presence checking.

9. US 5,940,375 A — Fujitsu Limited, "Feedback control apparatus and cell scheduling apparatus for use with cell exchange"

• Dates: priority/filing 1996-10-31; published 1999-08-17.
• Description: Cell scheduling/feedback control for a cell exchange; full text not retrieved here. Filing precedes 6,266,324's priority date.
• § 102 status: Prior art under § 102(e)/(g) via its 1996-10-31 U.S. filing (before 1997-04-23); not § 102(b) (published after the bar date).
• Potentially anticipates: Likely relevant to the scheduling/timing-control elements of Claims 1/6; element-level mapping unverified — provisional.

10. US 6,028,843 A — IBM, "Earliest deadline first communications cell scheduler and scheduling method for transmitting earliest deadline cells first"

• Dates: filed 1997-03-25 (before the 1997-04-23 priority date); published 2000-02-22.
• Description: Cell scheduler transmitting cells in earliest-deadline-first order — a scheduling approach for cell output, though not "port shaping" in the CDV-absorption sense of 6,266,324.
• § 102 status: Prior art under § 102(e)/(g) (US filing 1997-03-25 precedes invention date); not § 102(b).
• Potentially anticipates: Only the generic timing/scheduling aspects of Claims 1/6; dependent claims 2–5 unlikely. Provisional.

11. US 6,005,868 A — NEC Corporation, "Traffic shaping device" (inventor Atsuo Ito)

• Dates: JP priority 1996-09-26/27; U.S. Appl. 08/937,707 filed 1997-09-24; granted 1999-12-20/21.
• Description (verified from retrieved text): Traffic shaper with per-VC cell buffers and per-traffic shaping counters, a common output-time notice counter, per-traffic cell-output-enabling-time registers, and a cell-sending permit circuit that enables a buffer whose enabling time has arrived and, on conflict, selects by priority/rotation. Uses "not-empty" presence signals from cell buffers.
• § 102 status: Nuanced. Its U.S. filing (1997-09-24) is after the 6,266,324 JP priority date (1997-04-23) but before the U.S. filing (1998-04-22). If 6,266,324 is entitled to the 1997-04-23 priority date, US 6,005,868 is not § 102(e) prior art (its U.S. filing is later than the invention date), and its 1999 grant/publication is after both 6,266,324 dates, so § 102(a)/(b) would require showing the JP priority document or equivalent was publicly available before 1997-04-23 — generally not the case for a 1996 JP filing (laid open ~1998). If the 6,266,324 priority claim fails, US 6,005,868 would be § 102(e) prior art as of 1997-09-24.
• Potentially anticipates: If it qualifies, it is a strong candidate for Claims 1/6 (presence judging + rate-based output permitting) and possibly Claim 5's error/shaping correction concept (it has priority-raising/lowering arbitration, though not a shaping-error correcting counter per se). Its use of per-VC buffers rather than switch-core-controlled shared-buffer read timing is the main distinction from Claim 1.

12. US 5,791,865 A — "Bag palletizer" (Bublitz, Rod W.) — flagged anomaly

• Dates: priority 1996-09-13; published 1998-08-11.
• Description: As listed by Google Patents, this citation's title is "Bag palletizer" — subject matter wholly unrelated to ATM cell switching or traffic shaping. This is almost certainly a data-extraction artifact (a corrupted or mis-associated number) in the citation list rather than a genuine prior-art reference. Interpreting the number literally as instructed: even taken at face value it would be a § 102(e) candidate by its 1996-09-13 U.S. filing, but it discloses nothing about ATM shaping and therefore cannot anticipate any claim. I recommend verifying this entry against the USPTO Image File Wrapper of 09/064,038 to identify the true cited document.

Other references on the face of the patent (for completeness)

The record also lists non-patent literature that the examiner considered:

• Wallmeier et al., "Traffic control in ATM switches with large buffers," Munich, pp. 45–60 (Nov. 7, 1995) — § 102(b) printed-publication candidate against Claims 1/6 (large shared buffers with traffic control); not a patent citation, so no formal claim map is required here.
• Black, ATM Foundation for Broadband Networks, pp. 206, 224–233 (1995) and Sackett et al., ATM and Multiprotocol Networking, p. 203 (1996) — general ATM textbooks.
• Japanese Office Action dated Dec. 2, 1998 — prosecution history, not prior art.

Summary of strongest § 102 positions

Caveats: (1) A formal § 102 anticipation finding requires every claim limitation to be present in a single reference; the mappings above are best-effort assessments from titles, abstracts, and retrieved excerpts. (2) For the Japanese documents JPH02121549A, JPH0498938A, JPH08125668A, and EP 0753981 A2, I could not retrieve full texts within this search budget, and their claim coverage is therefore provisional. (3) The "Bag palletizer" entry should be re-verified against the USPTO file wrapper of application 09/064,038.

§ 103 Obviousness Analysis — U.S. Patent 6,266,324 ("ATM Device and Shaping Method")

I. Scope of Analysis and Legal Framework

This analysis assesses whether the claims of US6266324B1 would have been obvious to a person having ordinary skill in the art (PHOSITA) as of the invention date (Japanese priority application JP9-106009, filed 1997-04-23), under 35 U.S.C. § 103 as informed by Graham v. John Deere Co., 383 U.S. 1 (1966) and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). Under KSR, a combination of familiar elements is obvious when it yields a predictable result, and the motivation to combine may be found in the nature of the problem to be solved, common knowledge, or the explicit teaching of a reference.

I have based this analysis on the prior-art record compiled on the Google Patents page for US6266324 (https://patents.google.com/patent/US6266324/en) — the references the Examiner cited during prosecution — supplemented by verified content from the underlying documents where available via live search.

II. The Invention and Claimed Subject Matter

The '324 patent is directed to port shaping (CDV absorption and rate smoothing) for CBR traffic in an ATM device. The patent's own Background concedes that the conventional approach (exemplified by JPH08163150A, NEC, 1994) placed a dedicated shaping unit — a shaping FIFO plus monitor and control circuits — after every output port, making hardware "bulky." The stated object of the invention (col. 6) is an ATM device that "does not need to prepare additional hardware or buffers for a shaping operation to each output port."

The claimed solution: integrate port shaping into the switch core of a shared-buffer ATM switch by controlling when cells are read out of the shared buffer, so that the shared buffer itself provides the delay that absorbs CDV, and no per-output shaping FIFOs are needed.

Claim 1 (independent) requires, in relevant part:

• (1A–1C) an ATM device with input ports, output ports, a shared buffer storing input cells, and a switch core controlling the shared buffer;
• (1D) a judging section in the switch core that judges the presence of a stored cell in the shared buffer for each output port;
• (1E) a shaping control section having a shaping rate for each output port, producing an output indication signal at a cell output timing; and
• (1F) operation such that if a stored cell is present, the cell is read from the shared buffer and output through the particular output port for which the indication signal was produced.

Claims 2–5 add: (2) a queue controller plus output-port-selecting section; (3) shifting the cell output timing when no cell is present at the scheduled timing; (4) shifting one timing when two ports' output timings coincide; (5) a specific "shaping error correcting means" (absence signal + permission signal → timing error signal) and a shaping controller. Claim 6 is a method claim tracking claim 1.

III. Prior Art of Record (from the Patent's Citation Pages)

Note: all U.S. and EP references above are marked "* Cited by examiner" in the record. (US5791865A, a bag palletizer, is irrelevant.)

IV. Element-by-Element Mapping

The claim elements of claims 1–2 map almost completely onto the pre-1997 art:

• Shared-buffer ATM switch with switch-core-controlled read (1A–1C, 2A): Standard shared-buffer ATM switches with queue controllers (idle-address FIFO + per-output address queues) and read control were well known. US5799014A is a canonical example: a buffer memory control circuit with FIFOs per output line controls reads "at predetermined time intervals" and "in timing with the cell output," including for output links of different transmission rates. EP0471344A1/US5280475A likewise discloses a shared-buffer switch forming per-output (and per-VP/VC) list structures controlled through write/read chain-address tables.
• Judging presence of a stored cell per output (1D): Per-output queue non-empty/presence detection was routine. US6005868A (cols. describing both the admitted prior-art device of its Fig. 3 and its own embodiment) uses per-buffer "not-empty signals" gating output permission. In EP0471344A1, a cell is read only from the head of the list structure corresponding to the identifier designated for the current output time slot — i.e., read occurs only if a cell exists for that output.
• Shaping rate per output + output indication signal (1E): EP0471344A1 assigns a bandwidth table, periodically referenced by a fixed-period counter, designating which VP/VC (and hence which queue/output) is read in each output time slot — a shaping rate mechanism at per-output granularity, with dependent claims even allowing the counter period to differ per output line. US5799014A schedules per-output-line reads at rates matched to each line's transmission rate. JPH08163150A provides per-port CDV-absorbing delay scheduling. US6005868A provides per-buffer "shaping counters" issuing output request signals "at a rate assigned to the corresponding... buffer."
• Read-and-output only when a cell is present at the indicated timing (1F): This is precisely the gating taught in US6005868A: a cell output permit is issued only where an output request from a shaping counter coincides with a non-empty cell buffer, with a selector choosing among competing buffers. It is also inherent in US5799014A (read address pulled from the per-output FIFO only when the corresponding output is serviced in its scheduled interval).

V. Proposed Obviousness Combinations

Combination A — EP0471344A1 / US5280475A in view of US6005868A → claims 1, 2, 6

EP0471344A1 (family member JPH0498938A; U.S. counterpart US5280475A) is the closest art. Its stated objects are, remarkably, the same as the '324 patent's:

"It is an object of the present invention to reduce a memory capacity necessary for the traffic shaping. It is another object... to realize the traffic shaping without increased amount of buffers of an apparatus by using a large amount of buffers included originally in a switch as a memory necessary for the traffic shaping." (EP0471344A1, as retrieved from http://data.epo.org/publication-server/rest/v1.2/patents/EP0471344NWA1/document.pdf)

EP0471344A1 thus already discloses the '324's core insight — perform shaping inside a shared-buffer switch using the buffer that already exists, rather than adding per-output shaping FIFOs — and it does so by: (i) forming per-output/per-VC list structures in the shared buffer; (ii) using a fixed-period counter and bandwidth-assignment table to designate, for each output time slot, which connection's cells are read (a per-output shaping rate); and (iii) reading the cell from the top of the corresponding list structure — i.e., only when a cell for that output exists.

What claim 1 adds in express terms is the explicit "judging presence / indication signal / read-if-present" gating structure. That gating is the entire operation of the traffic shaper disclosed in US6005868A, whose admitted prior-art Figure 3 combines (a) shaping counters generating output-request (permission) signals at assigned intervals, (b) cell buffers generating not-empty (cell-presence) signals, and (c) an output cell buffer selector that issues a cell-output-permit signal only when a request and a stored cell coincide — and, where several buffers request simultaneously, resolves the conflict by fixed priority or round robin.

Why a PHOSITA would combine: The shared problem in both references and in the '324 is the same — preserving a guaranteed cell spacing/rate without multiplying hardware per port/connection. EP0471344A1 supplies the shared-buffer/shaping-rate framework; US6005868A supplies the standard request/not-empty arbitration logic for deciding exactly when a cell actually leaves the buffer. Substituting US6005868's counter-and-presence arbitration for EP0471344's bandwidth-table read selection, to obtain a shaping controller that outputs an indication signal only for ports whose queues are non-empty, is the substitution of one known, predictable scheduler element for another — the paradigm KSR obviousness case. Claims 2 (queue controller + output-port selector informing the queue controller) adds only the ubiquitous shared-buffer queue-controller hardware (US5799014A's buffer memory control circuit; EP0471344's chain-address tables) and a standard selector (US6005868's output cell buffer selector; US5799014A's demultiplexer distributing scheduled reads to output lines). Claim 6 falls with claim 1.

Combination B — US5799014A with JPH08163150A (optionally JPH08125668A) → claims 1, 2, 6

US5799014A (Hitachi, effective U.S. filing lineage from 1987) discloses a shared-buffer ATM switching system explicitly designed to accommodate input/output links of different transmission rates. Its buffer-memory control circuit reads cells from each output line's FIFO "at predetermined time intervals" and "in timing with the cell output," generating read/write processes "at a frequency corresponding to the data transmission rate of each line" by cycling a counter through a control memory — i.e., per-output-port read-rate scheduling from a shared buffer, exactly the '324's architecture (see https://patents.google.com/patent/US5799014A/en).

JPH08163150A is the patent's own admitted conventional art: per-output-port shaping FIFOs that absorb CDV by delaying each CBR cell to a predetermined delay. JPH08125668A (Hitachi) likewise addresses shaping in an ATM interface.

Why a PHOSITA would combine: A designer wanting CBR/CDV port shaping in the Hitachi shared-buffer switch would recognize that the delay-and-reorder function JPH08163150A performs in dedicated output FIFOs can be performed by the shared buffer itself, because US5799014A already controls each output line's read timing from the shared buffer and already services each output queue at its own line rate. Moving the JPH08163150A delay function "upstream" into the existing read scheduler of US5799014A — and deleting the per-port FIFOs — is (a) expressly motivated by EP0471344A1's stated object of eliminating added shaping buffers, (b) a design choice yielding a predictable hardware saving, and (c) the very cost-reduction trajectory the record shows: US6005868A (NEC) likewise states its object is to control "a cell sending rate by means of a common circuit portion... regardless of the number of cell buffers," and US6026666A's family shows NEC's continuing work to remove per-port shaping counters. The claimed judging-section/indication-signal/read-if-present combination is the well-known request/not-empty/permit logic of US6005868A's shaper applied to US5799014A's per-output read scheduler.

Combination C — Adding timing-shift / conflict / error-correction references → claims 3, 4, 5

Claims 3–5 address the situation where a scheduled output slot is wasted because (i) no cell for that port is queued at the assigned timing (claim 3), or (ii) two ports' scheduled timings collide where multiple output ports share a physical trunk (claim 4), with claim 5 claiming the counter/register implementation that defers the grant and compensates the interval to preserve the long-run average rate.

• Claim 4 is the easiest of the three. Simultaneous requests from multiple queues/buffers, resolved by permitting one and deferring the others, is disclosed in US6005868A: "in a case where, in a certain cell period, there are output requests from a plurality of the shaping counters and there are cells stored in a plurality of cell buffers... a cell output permit signal is sent to one of the cell buffers having the highest priority... or... according to a simple rotation." Deferring one colliding output's grant to the next available non-colliding slot (the '324's Fig. 7C process) is the same arbitration expressed in timing terms. US6028843A (IBM EDF scheduler) and US5940375A (Fujitsu, whose per-connection "dynamic shaper" reads cells "at cell read intervals corresponding to" a computed rate and recalculates next send times) both teach scheduling where conflicts/order are managed by comparing computed times and re-computing the next grant time. A PHOSITA designing a shared output trunk under the UTOPIA Level 2 multi-PHY arrangement (the '324's own Fig. 2 environment) would know collisions among polled ports must be resolved by deferral — this is standard arbitration.
• Claim 3 (shift timing when the queue is empty at the scheduled instant) addresses a known defect of strictly periodic shapers — the "cell flicker"/throughput loss the '324 illustrates in its Fig. 7A. The record shows this was a recognized problem in large-buffer ATM traffic control (Wallmeier et al., Traffic control in ATM switches with large buffers, Nov. 7, 1995, pp. 45–60), and the standard remedy — defer the grant to the next slot in which the connection's queue is non-empty while shortening the following interval to hold the average rate — is a conventional "slip-and-compensate" credit technique. US5940375A's dynamic shaper teaches exactly the re-computation paradigm (next output time = current time + interval, recomputed on actual output); US6005868A's time-register shaper teaches re-arming each buffer's next enabling time from an interval register upon output. Implementing the same behavior with a down-counter (Ct), an error counter (Cs), and a subtracter — the '324's Fig. 8 — is a standard digital-logic choice, not an invention. The prior-art shaping devices already used per-buffer shaping counters counting down over intervals (US6005868A's Figs. 1/3 prior-art discussion; US5799014A's counter-cycled control memory).
• Claim 5 adds means-plus-function language (absence signal + permission signal → timing error signal; a shaping controller responding to it). The claimed circuit is a straightforward logic realization of "if no cell is present when the permission fires, suppress the grant and count the slip so the next interval is reduced by the slip." The functional equivalent appears in US6005868A (permission gated by not-empty; enabling times re-registered from interval registers) and US5940375A (send time recomputation). Combining an ordinary OR/AND/inverter gate network with countdown and error counters, to carry out a known defer-and-compensate algorithm, would have been obvious to a PHOSITA (a logic/ASIC designer in ATM switching) and is the kind of "predictable variation" KSR treats as obvious.

VI. Motivation Summary

A PHOSITA (an ATM switch/ASIC designer familiar with shared-buffer switch fabrics, ATM Forum traffic-management specifications — see Black, ATM Foundation for Broadband Networks (1995) pp. 206, 224–233, and Sackett (1996) p. 203 — and CBR/CDV requirements) would have had concrete, articulable reasons to combine the references:

1. Cost/hardware reduction was the dominant, explicitly-articulated motivation in the field. EP0471344A1 states verbatim its object of performing shaping using the buffers "included originally in a switch" with no added buffer; US6005868A states its object of controlling send rate with a "common circuit portion regardless of the number of cell buffers"; the '324 patent itself frames the same problem. A designer following this well-documented trajectory would naturally move the shaping function into the shared-buffer read controller.
2. The component functions were all known and compatible: per-output queues and read scheduling in shared-buffer switches (US5799014A; EP0471344A1); per-port/connection rate registers and counters (EP0471344A1; US6005868A; JPH08163150A); presence/not-empty gating (US6005868A); and arbitration/deferral among competing grants (US6005868A; US6028843A; US5940375A).
3. The combination yields only predictable results — scheduled, CDV-smoothed cell egress at a programmed per-port rate, with no new technical obstacles. There is no showing in the record of unexpected results, a long-felt unmet need, industry skepticism, or commercial success tied to the claimed features. (The patent expired in 2018 after full maintenance-fee payments — unremarkable for a large-entity NEC/Renesas portfolio patent.)

VII. Candid Limitations of This Analysis

• I have verified detailed content for EP0471344A1/US5280475A, US5799014A, US6005868A, and US5940375A from live sources. I have not independently verified the full internal disclosure of EP0753981A2, US6028843A, JPH08125668A, JPH02121549A, or the Wallmeier paper beyond their titles/abstracts in the record; I therefore rely on them only for the propositions stated (scheduler/deadline-based cell ordering; buffer control; interface shaping; large-buffer traffic control) and flag that a validity brief should confirm those details before relying on them.
• Whether EP0471344A1 anticipates claim 1 (rather than merely rendering it obvious) is a close question worth pursuing: it appears to disclose every structural element (shared buffer, per-output list structures, counter/bandwidth-table shaping rate, read-only-if-queued). If anticipation fails only on the explicit "judging section ... for each output port" wording, Combination A's obviousness case fills that gap.
• Claims 3–5 present the patent's strongest (though, in my view, rebuttable) validity arguments, because no single reference appears to disclose the specific defer-and-compensate error-correction counter in the shared-buffer shaping context. The obviousness case for those claims depends on the routine-nature of slip/compensation scheduling and on the general scheduler art (US6005868A, US5940375A, US6028843A, Wallmeier), which is the appropriate KSR framework but is inherently more contestable than claims 1–2.

VIII. Bottom Line

On the record assembled by the Examiner, claims 1, 2, and 6 of US6266324 are highly vulnerable under § 103: EP0471344A1/US5280475A (alone or combined with US6005868A), or alternatively US5799014A combined with JPH08163150A, supplies every claimed element, and the motivation to combine — eliminating per-port shaping FIFOs by reusing the shared buffer's existing read scheduler — is stated verbatim in the prior art itself. Claims 3–5 are more defensible but still likely obvious as routine defer-and-compensate scheduling implemented with conventional counters and gates, in view of US6005868A, US5940375A, US6028843A, and Wallmeier.