Invalidity dossier
US 5638518
Node loop core for implementing transmission protocol in fibre channel
Current assignee: Avago Technologies International Sales Pte Ltd
Added 9/23/2026, 5:11:59 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview: US5638518A
Title: Node loop core for implementing transmission protocol in fibre channel
Patent Number: US5638518A
Application Number: US08/327,748
Inventor: Srinivasa R. Malladi
Original Assignee: LSI Logic Corp (current assignee listed as Avago Technologies International Sales Pte Ltd)
Priority/Filing Date: 1994-10-24
Publication (Grant) Date: 1997-06-10
Legal Status: Expired – Lifetime (anticipated expiration 2014-10-24)
Classifications: H04L1/0057 (block codes), H04L12/433 (loop networks with decentralised control, asynchronous transmission), H04L2012/445 (star/tree networks with switching in a hub)
Purpose (from the source text): The invention relates generally to data communication and processing, and more particularly to a "Node Loop Core" for implementing the transmission protocol in a Fibre Channel Node Port. It is described as flexible in structure and operation when used with a "Node Loop Port Super Core" implementing the Fibre Channel Standard (FCS) as adopted by ANSI.
Plain-language scope: The patent describes a Node Loop Core used with a modular "super core" structure containing an imbedded processor. This structure is said to support full-featured Fibre Channel operation at 80 Mbytes/second sustained throughput. The Node Loop Core and Super Core together implement the FC-1 (transmission/signalling) and FC-2 (framing) protocols of the Fibre Channel standard. FIG. 2 of the source is described as a functional block diagram of the NL Core 10 and Super Core 12.
Background context (from the source): Fibre Channel provides a low-cost, high-speed interconnect for workstations, mass storage, printers, and displays; transfer rates exceed 100 Mbytes/second per direction and can scale to 50, 25, and 12.5 Mbytes/second. The Node Loop Port (NL_Port) provides functions for Arbitrated Loop operation (closed and open loop topologies illustrated in FIGS. 1C–1D). The source notes such protocols were previously implemented with application specific integrated circuits (ASICs) with a host computer.
Source: https://patents.google.com/patent/[US5638518](/patent/US5638518)/en (excerpted).
What the excerpt does not establish: It does not provide the full claims, detailed embodiments, or the complete list of cited prior-art references. It does not verify inventorship, ownership, or legal status beyond the stated Google Patents listings, and no independent validity or litigation analysis is included here.
Generated 10/1/2026, 9:43:45 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
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