Invalidity dossier
US 6160813
Fibre channel switching system and method
Current assignee: Brocade Communications Systems LLC
Added 9/23/2026, 4:59:53 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 6,160,813 A
Title: Fibre channel switching system and method
Patent number: US 6,160,813 A
Application number: US 08/823,025
Inventors: David C. Banks; Steven L. Farnworth; Bent Stoevhase; Paul Ramsay
Assignee (per source): Brocade Communications Systems LLC (listed assignees may be inaccurate)
Priority/filing date: 1997-03-21
Publication/grant date: 2000-12-12
Status (per source): Expired – Lifetime; anticipated expiration 2017-03-21
Purpose. The patent relates generally to network switching devices and more particularly to Fibre Channel switching devices. It addresses the Fibre Channel fabric topology, in which a switching fabric built from one or more Fibre Channel switches provides a bidirectional connection from one node to another, with each node managing only a simple point-to-point connection to the fabric.
Plain-language scope. According to the excerpt, the switching system has a data switching path and a message switching path. The data switching path includes a shared central memory and memory control circuitry to transfer data frames from a receiving port to a transmitting port with high bandwidth and low latency. The shared memory includes memory modules configured for time-sliced access by each port, with each port assigned its own time slot for each memory module, permitting simultaneous access. Data frames are striped across the memory modules by dividing a frame into sub-portions, storing each sub-portion in a memory module, with the start of the frame stored in a first module and remaining portions stored in modules accessed sequentially per the time-slot protocol. Each frame is stored in a plurality of contiguous buffer lines, where a buffer line is a single memory location across all memory modules, and a frame buffer comprises 32 buffer lines.
Source: https://patents.google.com/patent/US6160813/en
What the excerpt does not establish: It does not provide claim text for independent or dependent claims, a complete written description, drawing details, prior-art references, the message switching path's operation, or any information about litigation, ownership transfers, validity, or enforceability.
Generated 10/1/2026, 9:43:57 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.