Invalidity dossier

US 5768530

High speed integrated circuit interface for fibre channel communications

Current assignee: EMC Corp

Added 9/23/2026, 3:14:09 PM

At a glanceNo PTAB challengesNo litigation on file

Active provider: DeepSeek · deepseek-flash

Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview: US 5,768,530

Title: High speed integrated circuit interface for fibre channel communications

Patent number: US 5,768,530 A
Application number: US08/580,508
Inventor: Miklos A. Sandorfi
Assignee: EMC Corporation
Priority/filing date: 1995-12-28
Publication (grant) date: 1998-06-16
Legal status (as listed): Expired – Lifetime; anticipated expiration 2015-12-28

Purpose: The invention relates to interfaces interposed between data channels having diverse characteristics, particularly an interface adapted for construction as a single integrated circuit. One stated aim is an application specific integrated circuit (ASIC) architecture capable of interconnecting a fibre channel to a standard data processing system bus with flexibility across diverse systems and high-speed channels.

Plain-language scope: The ASIC (10) includes a first connection circuit to a high-speed data channel (fibre channel interface 13), a second connection circuit to a data processing system input/output bus (data system interface 14), and a third connection circuit to a buffer memory system (memory system interface 17). A frame processing circuit (18) receives and transmits information via the high-speed channel and divides and combines header and data portions. A sequence managing circuit between the frame processing circuit and the second and third connection circuits manages internal information transfer, with a first transfer control circuit controlling transfers between the frame processor and buffer memory, and a second transfer control circuit controlling transfers between the data system bus and buffer memory. The description notes the ASIC typically works with an external local memory and may interconnect a PCI bus with fibre channel, SCSI, or Ethernet.

Source: https://patents.google.com/patent/US5768530/en

What the excerpt does not establish: It does not supply the full claims, complete description, or drawing contents (figures are referenced but not reproduced). It gives no independent verification of assignee, legal status, or dates beyond the listed bibliographic data; it does not establish validity, enforceability, litigation history, or ownership transfers. Prior-art discussion in the excerpt is expressly not analyzed here per scope limits.

Generated 10/1/2026, 9:51:43 PM

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Litigation summary

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Proceedings on file (0)

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AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

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Assignment history

Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.

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Prior art

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Obviousness

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Extensions

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Derivative works

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