US 11232054

I'll research US 11232054 across the USPTO and CAFC sources.

Let me get the Federal Circuit decision details and the patent's claim structure.

Let me pin down the full independent claim set of the '054 patent.

US Patent 11,232,054 — Analyst Summary

Scope note on dates/IDs: You asked me to treat identifiers literally and prefer live-search results over prior assumptions. Two things need flagging up front. First, the current-date you supplied (April 26, 2026) is inconsistent with the source data I retrieved — the Google Patents page for US11232054 was fetched 2026-09-28, and the litigation records below include events dated September 2026. I am following your instruction to prioritize the search results, so this summary includes post-April-2026 developments. Second, the Google Patents record labels the '054 patent "Active," which is misleading as to claim scope (see Litigation Status below).

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1. Bibliographic Data

Source: https://patents.google.com/patent/US11232054/en ; E.D. Tex. complaint copy at https://storage.courtlistener.com/recap/gov.uscourts.txed.[215248](/patent/215248)/gov.uscourts.txed.215248.5.4.pdf ; RPX: https://insight.rpxcorp.com/patent/[US11232054B2](/patent/US11232054B2)

Note on inventorship records: a 2023-08-25 USPTO assignment record for NETLIST, INC. lists assignors BHAKTA, CHEN, LEE (Hyun), MILTON and SOLOMON. "Hyun Lee" does not appear as a named inventor on the face of the patent; I cannot explain that discrepancy from the available record.

2. Abstract (verbatim)

"In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage."

Remark up front: the title ("Flash-DRAM hybrid memory module") does not match the abstract or the claims. The '054 claims are directed to on-DIMM voltage regulation and voltage monitoring, not to the Flash/DRAM hybrid data-management architecture described in the specification's Figures 5–11. The hybrid-memory disclosure is largely inherited from the priority family.

3. Plain-Language Overview of the Independent Claims

The specification describes a memory module (DIMM) with volatile DRAM, non-volatile Flash, an on-module controller, a data manager, an isolation switch, and a multi-rail power module (Fig. 16: sub-block 1122 = buck converter; 1124 = dual buck converter; 1126 = buck-boost). The issued claims, however, were drafted to the power/regulation embodiment.

Claim 1 — memory module with at least three buck converters

• A PCB with an edge-connector interface fitting a host slot, carrying power, data, address and control signals.
• A voltage conversion circuit on the PCB providing at least three regulated voltages, including at least three buck converters, each producing one of those regulated voltages.
• Multiple components on the PCB, each powered by at least one of those regulated voltages; the components include SDRAM devices plus a first circuit coupled to the SDRAM devices and to a first set of edge connections.
• The first circuit is coupled to first and second of the regulated voltages; the SDRAM devices are coupled to the first regulated voltage.

Claim 16 — memory module with voltage monitor and two operable states

• Same PCB/interface preamble.
• A voltage conversion circuit providing multiple regulated voltages via three buck converters.
• Components including SDRAM devices coupled to a first regulated voltage.
• A controller on the PCB including a voltage monitor circuit monitoring the host input voltage at the interface; on detecting an amplitude change in that input voltage, the module transitions from a first operable state to a second operable state (i.e., the power-loss backup trigger).

Claim 24 — memory module (voltage conversion circuit variant)

• Identified by Petitioner's expert as one of the three independent claims ("[e]ach of independent claims 1, 16, and 24 include a limitation requiring 'a voltage conversion circuit'"). Claim 25 (and claim 26 depending from it) appear to sit below it.
• Uncertainty: I did not retrieve the verbatim text of claim 24. The sources I found give full verbatim text for claims 1 and 16 only, and there is ambiguity in the record as to whether claim 25 is also independent.

Caveat on claim-1 text: one PTAB exhibit OCR renders a claim body beginning "a first buck converter… a second buck converter… a third buck converter… a converter circuit configured to provide a fourth regulated voltage…" with the limitation "a first one of the second and fourth voltage amplitudes is less than a second one…". That language (first/second/third/fourth regulated voltages with relative amplitudes) matches the '918 patent's claim set as described in the E.D. Tex. claim-construction order, not the '054 claim 1 I quote above. The two patents share a specification and overlap heavily, so I would not rely on OCR'd claim text from those combined exhibits without checking the printed patent.

Claim construction context (E.D. Tex., 2:21-cv-00463 and 2:22-cv-00203): the court construed "dual buck converter" as "a buck converter with two regulated voltage outputs," held the preambles of claims 1, 4, 6, 11, 16 and 25 limiting, and construed "memory module" to require structure connecting to the host's memory controller, but not limited to main memory modules. "Pre-regulated input voltage" was given its plain and ordinary meaning (i.e., a modulated input voltage).

4. Litigation / PTAB Status — the Material Point

Google Patents shows "Active," but the claims were invalidated. The controlling events:

Sources: https://fedcircuitblog.com/2026/09/02/opinions-orders-september-2-2026/ ; https://ipwatchdog.com/2026/09/02/federal-circuit-upholds-ptab-obviousness-finding-against-memory-module-patent/ ; https://www.govinfo.gov/app/details/USCOURTS-ca13-24-02241 ; https://portal.unifiedpatents.com/patents/patent/11232054 ; https://www.courtlistener.com/docket/63378313/324/3/netlist-inc-v-micron-technology-inc/

Practical bottom line: as of the September 2, 2026 Federal Circuit affirmance, all claims of US 11,232,054 stand cancelled. The "Active" status shown by Google Patents reflects administrative status, not claim survival. Any freedom-to-operate or valuation analysis premised on the '054 claims being live would be wrong.

5. Statements I Am Not Confident About

• The verbatim text of independent claim 24 (and whether claim 25 is independent).
• The precise priority chain between 2007-06-01, US 12/240,916 (2008-09-29), and the 2021 filing — and whether the June 1, 2007 date corresponds to a provisional application. Petitioner's expert Dr. Wolfe argued the effective filing date is "no earlier than June 2," disputing Netlist's priority claim.
• Why "Hyun Lee" appears in the 2023 assignment record but not as a named inventor.
• Whether any petition for rehearing or en banc petition followed the September 2, 2026 decision — I did not find one in the retrieved results.

I'll research the litigation history for US patent 11232054. Let me start with searches on patent litigation databases.

Let me dig deeper into specific cases and their outcomes.

Litigation Involving U.S. Patent No. 11,232,054 ("the '054 patent")

Patent identity (taken literally from the record): U.S. Pat. No. 11,232,054 B2, "Flash-dram hybrid memory module," Netlist Inc., application no. 17/328,019, filed 2021-05-24, granted 2022-01-25, earliest priority 2007-06-01 (provisional 60/941,586).

Below is the litigation I was able to identify. Note that "the '054 patent" is a continuation of the same family as the '918 patent (11,016,918), and the two share a common specification, so they are usually asserted together. I have flagged where a case involves the '054 patent directly versus where it involves the same litigation family.

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1. Netlist, Inc. v. Samsung Electronics Co., Ltd., et al.

2. Netlist, Inc. v. Micron Technology, Inc., et al.

3. PTAB — Samsung Electronics Co., Ltd. v. Netlist, Inc.

4. PTAB — Micron Technology, Inc. v. Netlist, Inc.

5. Federal Circuit appeals

6. Micron Technology, Inc. v. Netlist, Inc. (Idaho)

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Other entries on the patent's litigation family (for completeness)

The Google Patents litigation panel for this family also lists:

• E.D. Tex. 2:23-cv-00628 (Netlist–Samsung declaratory-judgment/related action)
• D. Idaho 1:25-cv-00323

I could not independently confirm from a primary source that the '054 patent itself is asserted in 2:23-cv-00628 or 1:25-cv-00323; those appear to involve other patents in the same Netlist portfolio/family.

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Summary of the '054 patent's litigation footprint

• Asserted in two district-court patent cases: Netlist v. Samsung (2:21-cv-00463-JRG) and Netlist v. Micron (2:22-cv-00203-JRG-RSP). It formed part of the $303.15M Samsung verdict (April 21, 2023).
• Challenged twice at the PTAB: IPR2022-00999 (Samsung, with Micron joining) and IPR2023-00405 (Micron) — both resulted in Final Written Decisions on Dec. 5, 2023 holding all challenged claims (1–30) unpatentable.
• On appeal at the Federal Circuit (24-1863 / 24-2203 / 24-2281); the related '918 appeal was affirmed in a nonprecedential decision (Sept. 2, 2026).
• Subject of Micron's Idaho action (D. Idaho 1:24-cv-00081), which was remanded to Idaho state court and closed.
• Settled globally in the August 2026 Netlist–Samsung agreement resolving the ED Tex and ITC disputes between those parties.

Caveats: PTAB/court case status is subject to change, and some outcomes (e.g., the precise disposition of the '054-specific Federal Circuit appeal as opposed to the related '918 appeal, and the exact filing date/number of the Micron Idaho state-court action) could not be confirmed from a single primary source. Where the record was ambiguous I have said so rather than assume. All patent numbers and case numbers are reproduced literally as found.

I'll research the PTAB proceedings surfaced in the patent record before finalizing.

Proceedings overview

Two AIA trials on file against US 11,232,054 — both true IPRs, both fully decided, and both ended with every claim of the patent held unpatentable: IPR2022-00999 (Samsung, filed 2022-05-17) and IPR2023-00405 (Micron, filed 2023-01-06, joined into the Samsung trial); the FWDs issued 2023-12-05, Director Review was denied 2024-03-18, and the Federal Circuit affirmed on 2026-09-02. Netlist has zero claims sustained in any AIA proceeding on this patent.

⚠️ Structured-data discrepancy (flagged per your instruction): the "PTAB proceedings on file" block states the USPTO ODP API returns no AIA trial proceedings for this patent. The public record contradicts that — the Google Patents page for this very patent lists both proceedings and links to Unified Patents' PTAB portal (portal.unifiedpatents.com/ptab/case/IPR2022-00999, .../IPR2023-00405), and the POPR/joinder papers are in PTAB E2E. Treat the ODP "no proceedings" result as a false negative for this patent; do not rely on it.

Bottom-line defensive posture: the trolling posture is inverted — all 30 claims of US 11,232,054 have been held unpatentable in two separate IPRs and those judgments were affirmed on appeal. If a demand letter cites claims 16 or 17 (the claims Netlist actually asserted in district court), those claims are dead. A new IPR is unnecessary; the FWDs plus the Federal Circuit affirmance are the defense.

Breakdown by status: claims invalidated: 2 proceedings / 30 of 30 claims · active: 0 · claims sustained: 0 · settled: 0 · institution denied: 0.

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IPR2022-00999 — Samsung Electronics Co., Ltd. (+ Micron entities, joined) v. Netlist, Inc.

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2022-05-17
• Status: Final Written Decision — appealed (FWD 2023-12-05, Paper 51, 80 pages); Director Review denied 2024-03-18
• Judge panel: Not confirmed in the sources I retrieved for the original -00999 panel. Note that after joinder the proceeding ran under the caption listing both Samsung and Micron entities as petitioners, so the post-joinder panel/record is shared with IPR2023-00405 (Jurgovan, Galligan, Boucher — see below).
• Petition grounds: All 30 claims (1–30) challenged. Primary art is Harris (Ex. 1023) in view of the FBDIMM Standards documents (Ex. 1027, Ex. 1028), asserted under § 103; the public grounds table reflects Harris + FBDIMM under § 103 against the challenged claims. The dispute turned on (a) "a plurality of edge connections configured to couple power, data, address and control signals between the memory module and the host system," and (b) the "three buck converters… and a converter circuit" / "first circuit" architecture of '054 claim 1.
• Institution decision: Instituted as to all challenged claims and grounds. "[W]e determine that Petitioner has established a reasonable likelihood that it would prevail with respect to at least one challenged claim, and we institute an inter partes review as to all the challenged claims and grounds raised in the Petition." (POPR filed 2022-09-08, Paper 7; institution entered late 2022 — I could not confirm the exact calendar date from retrieved sources.) Real parties in interest: Samsung Electronics Co., Ltd. and Samsung Semiconductor, Inc.
• Final Written Decision (2023-12-05, Paper 51): Claims 1–30 unpatentable — every claim of the patent. As Netlist's own notice of appeal frames it, the appeal is from "the Board's determination that Claims 1 through 30 of the '054 Patent have been shown by a preponderance of the evidence to be unpatentable." No claim was held patentable. Substantial evidence found that Harris, in view of the FBDIMM standards, teaches the module receiving power/data/address/control through the edge connections, and that a POSITA implementing Harris's on-module regulation in an FBDIMM architecture would have used separate converters to generate the required rails ("a straightforward implementation"). Petitioner's Motion to Exclude was dismissed.
• Settlement / termination: No settlement — litigated to FWD. (Any settlement discussions, if any, are not on the public record.)
• Appeal: Yes. Netlist's Notice of Appeal filed 2024-05-20 → CAFC No. 2024-1863 (consolidated/companion with No. 2024-1859, which covers IPR2022-00996, IPR2022-00999, IPR2023-00405 and IPR2023-00406; the Federal Circuit's 2024-09-12 order treated 2024-1707, 2024-1859, 2024-1863 and 2024-2203 as companion cases before one merits panel). Issues on appeal: claim construction; substantial-evidence challenges to the obviousness findings (motivation to combine, reasonable expectation of success); the Board's procedural rulings (preservation, denial of post–sur-reply supplemental evidence); APA/procedural-regularity arguments; and the denial of Director Review (Paper 56). Disposition: AFFIRMED (nonprecedential), 2026-09-02. The Federal Circuit blog's 2026-09-02 opinions/orders post cites the Board's "'054 Decision," and the accompanying nonprecedential disposition (accessible copy captioned to the '918 companion) applies "substantial evidence" review and affirms on the Harris + FBDIMM combination. Verify the '054-specific disposition text on the 2024-1863 CourtListener docket before quoting it.
• Defensive value: This is the kill shot. All 30 claims are unpatentable, and the judgment survived Director Review and Federal Circuit review — any assertion of the '054 patent today rests on claims already adjudicated invalid. Accused parties should treat a demand-letter citation to claims 16 or 17 (the claims Netlist pressed in E.D. Tex.) as a citation to canceled subject matter.

IPR2023-00405 — Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC v. Netlist, Inc.

• Type: Inter Partes Review, filed with a Motion for Joinder into IPR2022-00999
• Filed: 2023-01-06
• Status: Final Written Decision — appealed; docket reflects "Terminated 2023-12-05," status "Final Written Decision – Appealed"
• Judge panel: Jon M. Jurgovan (author of the Final Written Decision), Daniel J. Galligan, Patrick M. Boucher
• Petition grounds: Claims 1–30 challenged. Micron's petition was expressly "substantively identical to the Samsung Petition," used the same grounds and the same expert declaration (Dr. Andrew Wolfe). Micron's district-court briefing characterizes its '054 challenge as resting on Harris, the FBDIMM Standards, Amidi, Hajeck, and Spiers under § 103. Micron sought joinder to "take an 'understudy' role," agreeing to make no substantive filings and to be bound by Samsung's filings absent Samsung's exit — i.e., one record, two petitioners.
• Institution decision: Instituted / joined — docket and Patexia both record an institution date of 2023-06-23; the Netlist district-court exhibit index lists a 7-page paper in IPR2023-00405 entered 2023-06-23 (the joinder/institution decision).
• Final Written Decision: 2023-12-05 — issued on the Samsung trial schedule (a consequence of joinder), finding all challenged claims (1–30) unpatentable. Netlist's SEC disclosure is explicit: "On December 5, 2023, the PTAB issued a final written decision in the two IPRs finding all challenged claims unpatentable." No claim survived. (The -00999 FWD was Paper 51, 80 pages; the FWD in the -00996/-00999 pair, Papers 53 & 56, includes the 2024-03-18 Director Review denials.)
• Settlement / termination: None — no settlement or adverse-judgment termination; the case terminated with the FWD.
• Appeal: Yes — Netlist's 2024-05-20 notice of appeal covered it. The Federal Circuit's 2024-09-12 companion-case order places IPR2023-00405 within CAFC Nos. 2024-1859 and 2024-1863. AFFIRMED 2026-09-02 (same disposition group as above).
• Defensive value: Because Micron joined rather than litigating independently, Micron is bound by and estopped by the same record as Samsung. For anyone else facing the patent, this second FWD is cumulative confirmation: there is no claim left to attack and nothing left to defend.

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Strategic summary

Claim status. US 11,232,054 issued with 30 claims, and the Board in IPR2022-00999 (Paper 51, 2023-12-05) and IPR2023-00405 found claims 1–30 unpatentable — the entire patent. There are no sustained claims and no untested claims. Because the Federal Circuit affirmed on 2026-09-02, the § 318(b) certificates canceling claims 1–30 should issue on the termination of the appeals (barring a timely rehearing/en banc petition). Independent claims 1, 15/16 and 24-era claims — including the "three buck converters plus converter circuit" and "first/second operable state" families, and dependent claims 16 and 17 that Netlist actually asserted in district court — are all within the invalidated set. For practical purposes, this patent is unassertable.

Estoppel landscape. Under 35 U.S.C. § 315(e)(2), Samsung Electronics/Samsung Semiconductor and the Micron entities (and their privies) are estopped in the district court litigations from asserting any ground they raised or reasonably could have raised in these IPRs — that is the full § 102/§ 103 universe based on patents and printed publications available to them as of the petitions. That estoppel is largely academic now that the claims are canceled, but it matters for the related-patent campaigns (the '918 patent family, IPR2022-00996/-00405/-00406, and the DDR5/HBM patents). For a new defendant who is not a Samsung/Micron privy, § 315(e)(2) does not bind you, but any new IPR on the '054 would face near-certain § 325(d) discretionary denial as presenting art/arguments the Board has already adjudicated — and there is no reason to file one. Your prior-art window remains open only in the sense that the patent is already dead; invalidity grounds that Samsung/Micron could not have raised (e.g., system prior art under § 102(a)(1), public use/on-sale) are untested, but are superfluous.

Pattern signals. No defensive aggregator filed here: both petitions came from competitors (Samsung first, Micron joining as an "understudy" with a substantively identical petition and the same expert — an efficient, low-cost piggyback rather than a second independent challenge). The patent owner fought hard and lost at every level: Preliminary Response (2022-09-08), Patent Owner Response, real Samsung I parallel litigation argument, a request for Director Review (denied 2024-03-18, Papers 53/56), a Federal Circuit appeal on both substantive and APA/procedural grounds (2024-1863), and a companion appeal campaign spanning the '918/'054 and HBM/DDR5 patent clusters. Netlist's pattern is to appeal every adverse FWD; here every appeal failed.

One item to verify (not counted above): an IPWatchdog-hosted paper for PGR2025-00071 cites the '918/'054 FWDs in its exhibit list. I could not confirm that PGR is against US 11,232,054 (it appears to target a later continuation in the same family). Do not treat it as a third proceeding on the '054 patent without checking PTAB E2E.

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Recommended next steps

1. Get the dispositive documents before responding to any assertion. Pull the IPR2022-00999 Final Written Decision (Paper 51, 2023-12-05) and the IPR2023-00405 FWD (2023-12-05) from USPTO PTAB E2E (links via https://portal.unifiedpatents.com/ptab/case/IPR2022-00999 and https://portal.unifiedpatents.com/ptab/case/IPR2023-00405). Quote the ORDER paragraph verbatim (the Form-style order "claims 1–30 of the '054 patent have been shown to be unpatentable") rather than paraphrasing.
2. Cite the affirmance, not just the FWD. Netlist's own Notice of Appeal (filed 2024-05-20, served on Baker Botts and Winston & Strawn) recites the Board's finding that Claims 1 through 30 were unpatentable, and the notification of appeal covers both the FWD (Paper 51) and the Director Review denial (Paper 56). Confirm the 2026-09-02 nonprecedential affirmance text on the CAFC docket 2024-1863 / CourtListener before quoting it: https://www.courtlistener.com/docket/69849093/24/netlist-inc-v-samsung-electronics-co-ltd/ (companion dockets 2024-1859 and 2024-1707, consolidated by the 2024-09-12 order).
3. If you are a defendant in a case that also asserts sibling patents: the same Samsung/Micron IPR record invalidated the '918 patent (IPR2022-00996 / IPR2023-00406) on the same Harris + FBDIMM theory and the same 2023-12-05/06 timing. Where the FWDs went unappealed or were affirmed, they are equally usable under § 282 / collateral estoppel as to those parties.
4. No trial-stage milestones to track on this patent — no active AIA proceeding remains. The only residual calendar items are (a) any rehearing petition on the 2026-09-02 affirmance and (b) issuance of the § 318(b) cancellation certificates for claims 1–30. Neither changes the defensive calculus.
5. On the ODP signal: re-run the ODP query with a direct patentNumber/applicationNumber lookup (17/328,019) because the "no proceedings" result here is demonstrably wrong per the Google Patents record for this exact publication.

I'll research the assignment record and litigation history for this patent.

Ownership & Assignment Analysis — US 11,232,054 B2

Scope note / evidence limitation (read first). I was able to verify the patent's bibliographic data, its legal-events record, and its litigation footprint. I was not able to retrieve the USPTO Assignment Center's reel/frame numbers or the correspondent-of-record for this patent's recorded assignment(s) in this session, and I will not invent them. Every reel/frame field below is marked unverified where I could not confirm it; the entries that follow are drawn from the Google Patents legal-events record for this patent (which mirrors USPTO assignment notices into its "Reassignment" log) and from court/PTAB records. Verify at the Assignment Center before relying on any of it: https://assignmentcenter.uspto.gov/ (search by patent number 11232054) — cross-check: https://patents.google.com/patent/US11232054/en (Legal Events › Reassignment).

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Inventors

Source: Google Patents front page for US 11,232,054 lists inventors Chen, Solomon, Milton, Bhakta. The PTAB/court record confirms these four as inventors of the '918 sibling (captured in the Samsung DJ briefing: "The '366 Patent is titled 'Memory With On-Module Power Management' and names Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, and Jayesh Bhakta as inventors").

Unusual pattern — flag for verification. The recorded reassignment event of 2023-08-25 lists Hyun Lee among the assignors, alongside Bhakta, Chen, Milton, and Solomon (Google Patents Legal Events, "Assigned to NETLIST, INC."). Hyun Lee is not a named inventor on the '054 patent. Hyun Lee is Netlist's former CTO (he appears as a witness in the EDTX bench trial — "Doctor Lee is a former CTO of Netlist"). The most plausible reading is that Netlist recorded a batch of confirmatory inventor→company assignments in August 2023 covering multiple properties in the family, and the Google Events rendering aggregated the assignor names. This is a procedural/chain-of-title cleanup during litigation, not a fire-sale signal — but it should be confirmed against the individual reel/frame entries.

Departure pattern: No evidence that the named inventors left Netlist within 12 months of filing. Note that "filing" is ambiguous here: the '054 issued from Application 17/328,019 filed 2021-05-24, but the family traces to a 2007-06-01 priority date with an external priority claim from US 12/240,916 filed 2008-09-29. Inventorship is therefore tied to a 2008-era Netlist team; the 2021 filing was a continuation exercise (see the assertion-pattern note under NPE signals).

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Original assignee

Netlist, Inc. (Irvine, California; publicly traded, NASDAQ: NLST).

• Line of business: Historically a manufacturer/supplier of specialty memory modules (e.g., NVvault NVDIMM, HyperCloud) and an early developer of hybrid DRAM/Flash module architectures (the "HybriDIMM" concept that this family describes). Its current revenue is dominated by IP licensing and litigation recovery, not module sales — a transition that any ownership analysis must weight.
• Product embodying the claims: Partially confirmed, treat with care. Netlist publicly traced DDR5 on-module power management (the '918/'054 family) to designs it says it "first deployed... over a decade ago in some of our early custom designs for high-performance memory modules." Whether a commercial Netlist module shipped with the '054 claim scope as issued (claims 16/17, "first operable state → second operable state" on voltage change) is not established in the record I reviewed. Do not assert a shipping product without pulling Netlist's 10-K product descriptions and the HybriDIMM/NVvault datasheets.
• Current status: Operating, publicly listed, and litigating. Not dissolved, not in bankruptcy. It has licensed its portfolio (SK hynix in 2021) and is a repeat plaintiff.

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Assignment timeline

Only one post-issuance assignment event is indexed for this patent. No chain of LLC transfers exists. Reel/frame numbers were not retrievable — I am not supplying placeholders.

• Executed date: not recorded in the indexed data / recorded 2023-08-25 — Reel NNNNNN/NNNN (unverified — must be pulled from Assignment Center)
  • Conveyance: Assignment (inventor-to-company / confirmatory; Google renders it as "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: Jayesh Bhakta; Chi-She Chen; Hyun Lee; Scott H. Milton; Jeffrey C. Solomon
  • Assignee: Netlist, Inc.
  • Correspondent: Not retrievable in this session — unverified. (Related record for context: Jamie Zheng, Esq. is identified in the D. Del. DJ action as "the prosecuting attorney for all but two of the eight patents (the '918 and '054 patents)", and Morgan, Lewis & Bockius LLP appears in the Samsung witness/disclosure list in connection with prosecution of the '054. That is prosecution counsel, not confirmed as the assignment-recording correspondent. Do not conflate the two.)
  • Context: Internal chain-of-title confirmation running from the named inventors to the original assignee — recorded ~20 months after issue and ~21 months after Netlist sued Samsung, i.e., mid-litigation housekeeping to shore up standing. This is not an acquisition, fire-sale, securitization, or transfer-to-asserter.

No records found of: an assignment from Netlist to any IP-holding LLC, a security agreement encumbering the patent, a merger/change-of-name, a license recorded against the patent, or a release. For a patent this heavily litigated, the absence of any third-party recorded interest is itself meaningful: Netlist has held title continuously since the 2008 priority application.

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Timeline diagram

timeline
    title Ownership of US 11232054
    2007 : Earliest priority date claimed
    2008 : Parent application filed by Netlist
    2021 : Continuation filed by Netlist
    2021 : Netlist sues Samsung in EDTX
    2022 : Patent issues to Netlist
    2023 : Inventor assignments recorded to Netlist
    2023 : PTAB finds the claims unpatentable
    2024 : Director Review denied
    2025 : New suits filed against Micron and Samsung

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NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT.
The only recorded assignment moves title from named individuals to Netlist, Inc., the operating company that is also the original assignee. There is no "IP / Holdings / Licensing / Ventures" entity anywhere in the chain, no registered-agent service address, no single-member LLC. (Contrast the classic pattern: an operating entity → Delaware LLC at a registered-agent address, recorded on a distinct reel/frame.) Nothing of the sort appears here.

2. Known asserter in the chain — NOT PRESENT (with a caveat).
No assignee matches the public NPE lists (Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Spangenberg entities). The current and only assignee is Netlist, Inc.
Caveat worth stating precisely: Netlist is a high-frequency plaintiff tracked in the Unified Patents and RPX ecosystems, and it is a serial continuation-filer and serial litigant — it has asserted the same family against Google, Samsung, Micron, SK hynix and others for over a decade. It is challenged as a patent-monetization actor, but it does so in its own name as the record owner, not through an NPE vehicle. That distinction matters for your taxonomy. Petitioners against the '054 were Samsung (IPR2022-00999, filed 2022-05-17, RPIs identified as Samsung Electronics Co., Ltd. and Samsung Semiconductor, Inc.) and Micron (IPR2023-00405, filed 2023-01-06) — i.e., accused competitors, which is the inverse of the NPE pattern.

3. Repeat correspondent across the chain — UNCLEAR (no data).
There is only one indexed assignment, so "recurrence across the chain" cannot be tested. The correspondent of record for that recording was not retrievable here. The names that are documented — Jamie Zheng, Esq. (prosecution, per the D. Del. record) and Morgan, Lewis & Bockius LLP (prosecution, '054) — belong to prosecution, not assignment recording, and a single appearance is not a finding under your own rule. Action item: pull the correspondent field from the 2023-08-25 reel/frame and from the parallel recordings on '918/'366 to see whether one attorney/firm recorded the whole family in one sitting.

4. Cascading transfers — NOT PRESENT.
Zero chained transfers. One assignment in ~15 years of prosecution, and it terminates at the original assignee.

5. Pre-litigation transfer — NOT PRESENT (inverted).
The only recorded assignment is dated after the first suit naming this patent. Netlist filed against Samsung in EDTX on 2021-12-20; Samsung filed its D. Del. DJ action on 2021-10-15 seeking a declaration on the '054 the day it issued; the assignment was recorded 2023-08-25. The transfer postdates the litigation rather than preceding it — the opposite of venue-shopping chain arrangement.

6. Bankruptcy fire-sale — NOT PRESENT.
No Chapter 7/11 event for Netlist is reflected in the record; no trustee/estate assignment appears; the patent was never a liquidated asset in a bankruptcy sale.

7. Privateering — NOT PRESENT.
Netlist has not spun the family out to a proxy NPE to assert on its behalf. It asserts directly and openly (it is the plaintiff of record in EDTX, D. Del., the ITC, and the Federal Circuit appeals 24-1859 / 24-1863 / 24-2203 / 24-2281). Its SK hynix relationship (2021 portfolio license) is direct licensing, not privateering.

8. Defensive aggregator — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. The patent is live, asserted, and owned by the plaintiff. Inverse signal not met — this patent has not been neutralized, although its asserted claims were held unpatentable by the PTAB and the decision was upheld on Director Review denial:

• 2022-05-17 — Samsung petitions (IPR2022-00999); instituted 2022-12-06.
• 2023-01-06 — Micron petitions (IPR2023-00405); instituted 2023-06-23.
• 2023-12-05 — Final Written Decisions in both, holding claims unpatentable (Papers 51 / 53).
• 2024-03-18 — Director Review denied (Paper 56); appeals to the Federal Circuit followed.
• Parallel EDTX outcomes: asserted claims 16/17 of the '054 went to verdict in 2:21-cv-00463 (April 2023) and were the subject of Samsung's JMOL on written description; Netlist pursued new continuations in the same family ('087, '731, '366) and filed fresh suits in 2025 (including in the Idaho District Court, Micron's home venue).

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Verdict

Operating-company assertion.

The chain contains exactly one recorded transfer — named inventors → Netlist, Inc., recorded 2023-08-25 — with no shell LLC, no security interest, no NPE assignee, and no defensive-aggregator termination anywhere in the record, meaning Netlist has held title continuously since the 2008 parent filing and asserts the patent in its own name against identified competitors (Samsung and Micron as IPR petitioners; the same parties as district-court defendants and Federal Circuit appellees). The only complicating fact is that Netlist's present revenue is predominantly licensing/litigation-driven rather than product-driven, and its 2021 continuation filings (the '918/'054 claims were drafted to reach non-hybrid DDR5 DIMMs, per Samsung's successful written-description JMOL) exhibit classic monetization behavior — so if your taxonomy requires the current assignee to be shipping a product practicing the claims today, downgrade this to operating-company assertion with a monetization overlay, not an NPE finding.

Verification links:

• Assignment Center (search patent 11232054): https://assignmentcenter.uspto.gov/
• Google Patents legal events for the '054: https://patents.google.com/patent/US11232054/en
• PTAB IPR2022-00999: https://portal.unifiedpatents.com/ptab/case/IPR2022-00999
• PTAB IPR2023-00405: https://portal.unifiedpatents.com/ptab/case/IPR2023-00405
• EDTX 2:21-cv-00463 (first suit naming the '054): https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A22-cv-00203
• Fed. Cir. appeal 24-1863: https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/24-1863

Two open items you should close before this memo goes out: (1) the reel/frame and correspondent of record for the 2023-08-25 recording, and whether the same correspondent appears on the '918 and '366 recordings; (2) why Hyun Lee appears as an assignor on a patent on which he is not a named inventor — either benign batch-recording aggregation or a defect in the recorded record worth documenting.

I'll research US patent 11232054 and its prior-art citations.

Let me retrieve the front-page "References Cited" list from the patent document itself.

Let me verify bibliographic details for the key references and locate the full front-page citation list.

Prior-Art Analysis — US 11,232,054 B2

A. The patent as identified (literal reading)

Critical analytical point: although the title and much of the specification concern a Flash-DRAM hybrid DIMM (FDHDIMM), the granted claims of the '054 patent are drawn to on-module voltage regulation/power management. Claim 1 recites a PCB with edge connections; a voltage conversion circuit providing at least three regulated voltages via at least three buck converters; components each coupled to one of those regulated voltages; SDRAM devices; and a first circuit coupled to the SDRAMs and a first set of edge connections, with the SDRAMs on the first regulated voltage. The dependent claims add a controller including a voltage monitor circuit, a trigger signal, transitions between first/second operable states, pre-regulated voltages, diodes, and backup-power elements. Consequently the Flash/DRAM-hybrid art (EcoRAM, NVDIMM, etc.) is far less probative against the issued claims than the power/voltage-distribution art.

Litigation/web grounding: https://patents.google.com/patent/US11232054/en · https://portal.unifiedpatents.com/patents/patent/11232054

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B. Important honesty caveat about the face-of-patent "(56) References Cited"

The printed front page of the '054 patent carries an unusually large cumulative list of U.S. Patent Documents (in the 100+ range) that appears to have been carried forward wholesale from the IDSs of the 2007–2008 priority applications. Most entries predate 2006 (the earliest is reportedly a 1936 patent) and are only marginally relevant to the granted voltage claims.

I attempted to retrieve this list directly. The only machine-readable reproductions I could locate (Docket Alarm and CourtListener renderings) are OCR-degraded to the point that patent numbers, dates and inventor names are misaligned and out of sequence — e.g., a rendering that lists "4,420,821 A – 12/1983 – Hoffman" before "4,409,305 A – 8/1984 – Hoffman," and a Num=5,458,839 entry dated 10/1996 sitting between 5,519,xxx entries. Because the OCR cannot be trusted, I will not attribute specific numbers/dates/names beyond those corroborated by an independent source. The one face-of-patent entry I saw reproduced consistently and in-context is:

• US 6,944,042 B2 — Miks et al. — June 2005 (face-of-patent U.S. Patent Document)

I was unable to retrieve the "Foreign Patent Documents" column of the front page, and I could not verify the full face list claim-by-claim. Anyone relying on this should pull the printed front page (e.g., from USPTO PatentCenter or the CourtListener copy of the issued patent: https://storage.courtlistener.com/recap/gov.uscourts.txed.[215248](/patent/215248)/gov.uscourts.txed.215248.5.4.pdf).

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C. The substantively relevant prior art (references actually applied against the '054 claims)

The examiner's face citations are not where the action is. The prior art that actually matters for the '054 claims was assembled by the Petitioner in IPR2022-00999 (Samsung Electronics / Micron v. Netlist) and IPR2023-00405 (Micron), and is documented in the Wolfe declaration (Ex. 1003). Every ground was pled as obviousness under 35 U.S.C. § 103 — not as § 102 anticipation. I note this because the question asks about § 102; I address that tension in Part E.

1. Harris — US 2006/0174140 A1 (Ex. 1023)

• Full citation: U.S. Patent Application Publication No. 2006/0174140 A1, "Voltage Distribution System and Method for a Memory Assembly," Harris, Shaun L.; Williams, Gary; Peterson, Eric C.; Oberski, Jeffrey A.; Appl. No. 11/047,304.
• Filed / published: filed 2005-01-31; published 2006-08-03. Petitioner asserts § 102(a). The same disclosure appears to have issued as US 7,360,104 B2 ("Redundant voltage distribution system and method for a memory module having multiple external voltages") — the identical reference numerals (100A, 102 VRM, 104 external supply, 106 Vcc, 108 Vdd, 110-1…N, 112 buffer, 114, 116) and Fig. 1A/1B appear in both, though I flag this correspondence as an inference rather than something I verified from the grant's front page.
• Description: a memory module (DIMM; unbuffered, registered or fully buffered) with an on-board voltage regulator module 102 converting an externally supplied voltage 104 into local rails Vcc 106 (buffer) and Vdd 108 (DRAMs), 0.5–3.5 V; buffer/logic component 112 (the AMB in the FBDIMM implementation); daisy-chain interface 116; a redundant VRM and voltage-selection mechanism (claim 11).
• Claims it potentially reaches (§ 102/§ 103): the claim 1 preamble (PCB/interface, plurality of components, SDRAM devices, first circuit/buffer coupled to the SDRAMs and edge connections) and claim 15/16-type "voltage conversion circuit providing regulated voltages." Standing alone, Harris discloses only two rails (Vdd, Vcc) — it does not by itself show "at least three regulated voltages" or "at least three buck converters," which is why the Petitioner paired it with the JEDEC FBDIMM standards.
• Ground coverage: Ground 1 = Harris + FBDIMM Standards (claims 1–3, 16, 19, 23 ** rendered obvious**); Grounds 2–3 = Harris + FBDIMM Standards + Amidi (claims 1–30).

2. Amidi — US 7,724,604 B2 (Ex. 1024)

• Full citation: U.S. Patent No. 7,724,604 B2 (Amidi). (I did not independently confirm the title of record in this session — treating the number as authoritative and the subject matter as described in the record.)
• Dates: the record cites Amidi's figures/columns (e.g., 4:44–52; 5:25–62; 7:52–59; 8:23–62; 9:8–22; Figs. 3, 4, 6–8, 13–15). I could not confirm the issue date from a primary source in this session; a closely related Amidi publication, US 2006/0117152 A1 (June 1, 2006), is used in the parallel Netlist reexamination record, so do not conflate the two.
• Description (as relied on): a memory module with power-management/backup-battery circuitry — power supervisory module 480, voltage supervisory blocks 665 and 800; buck converters (e.g., 640) for backup power; a power-switch multiplexer (Fig. 7, 4:56–5:09); system supply 520/605/825 and memory supply 540; reference voltage 675/820 set 5–10 % below nominal 12 V; trigger signal 670/858/868; entry into a self-refresh state on power fault (Fig. 14, steps 1435–1460); DDR/DDR2 SDRAMs (Figs. 3, 13; 7:52–59; 10:17–20).
• Claims it potentially reaches: claim 4 and its dependents (5, 6, 7, 8, 17, 23, 24) — "controller including a voltage monitor circuit" monitoring the input voltage from the edge connections; "predetermined threshold voltage"; "trigger signal"; and (with Harris's S3 mode) the "controller … configured to perform … a write operation to transfer data to non-volatile memory." Amidi also supplies the second regulated/second pre-regulated voltage mappings for the state-transition claims (18, 19, 20, 21).
• Ground coverage: Ground 2/3 (with Harris + FBDIMM Standards); Grounds 4–5 (with Spiers).

3. Spiers — US 2006/0080515 A1 (Ex. 1025)

• Full citation: U.S. Patent Application Publication No. 2006/0080515 A1 (Spiers et al.). (Title not independently confirmed in this session; described in the record as directed to data backup in memory modules on power failure.)
• Published: ~April 2006 (2006/0080515 series).
• Description (as relied on): a memory module with backup energy for preserving data; NAND flash memories 194; SDRAMs 190 that may be implemented as DDR2 or DDR3 devices; switching the power supply from system power to backup power (Abstract; Fig. 14); an alternative implementation relying on capacitors rather than a battery.
• Claims it potentially reaches: the claim 1 architecture in combination (SDRAM devices, regulation, module form factor) and the state-transition/backup claims (claims 18–21, 25–28 class), plus the "trigger condition → transfer data to non-volatile memory" concept in the specification.
• Ground coverage: Ground 4 = Spiers + Amidi; Ground 5 = Spiers + Amidi + Hajeck (claims 1–30).

4. Hajeck — US 6,856,556 (Ex. 1038)

• Full citation: U.S. Patent No. 6,856,556 (Hajeck). (Title not independently confirmed in this session; cited and quoted by column/line and by code (57).)
• Description (as relied on): a memory-system controller 40 powered by a charge pump 46 producing a near-constant V_REG; a voltage detection circuit 48 generating a "busy" signal 38 to host 32 upon undervoltage or overvoltage; and battery backup used in response to loss of host power to complete outstanding operations while the charge pump protects the controller from surges/spikes (Ex. 1038, code (57), 1:10–18, 1:28–31, 1:62–2:7, 3:6–10, 3:13–16, 3:30–43, 3:66–4:3, 4:62–65, Fig. 1).
• Claims it potentially reaches: the overvoltage-detection dependent claims — 7, 9–12, 17, 29, 30 (and the trigger-signal claims 6, 9, 17, 29) — supplying the over-voltage half of the voltage-anomaly detection that Amidi (undervoltage) lacks.
• Ground coverage: Ground 3 and Ground 5 only (i.e., never alone).

5. JEDEC FBDIMM Standards (Exs. 1027–28) — printed publications

• Full citation: JEDEC Standard JESD82-20 (March 2007) for Fully Buffered DIMM / Advanced Memory Buffer, together with the FB-DIMM Architecture and Protocol Specification. Petitioner collectively labels these the "FBDIMM Standards."
• Dates: JESD82-20 published March 2007 (after the 2007-06-01 provisional; before the 2008-06-02 effective date relied on by Petitioner) → prior art under § 102(a) on Petitioner's theory, and § 102(b) on Netlist's earlier-date theory.
• Description (as relied on): DIMM supply rails VDD/VDDQ 1.8 V, VCC/VCCFBD 1.5 V, VTT ≈ 0.5×VDD, VDDSPD 3.3 V; 240-pin connector; S3 power mode (Section 4.1.3; pp. 21, 39) in which VCC is switched off while DRAMs stay powered in self-refresh; requirement that control/status registers be stored in non-volatile memory before entering S3 and restored before normal DRAM transactions (Section 3.7.3, p. 25; Tables 11.7–11.8, pp. 95–96, 141).
• Claims it potentially reaches: supplies the "at least three regulated voltages" and "selectively switched off … while one or more components … are powered on" limitations that Harris alone lacks — i.e., claims 1, 2, 3, 16, 19, 23.
• Status: a printed publication — § 102(a)/(b) art, but of course not a "patent citation."

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D. Prosecution-history "citation" that was legally decisive

During prosecution of the '019 application, the examiner's 2021-09-27 Office Action rejected claims 2–15, 20, 22–23, 26–31, objected to claims 24–25, and allowed 16–19 and 21. The rejection included nonstatutory double patenting over claims 1–30 of U.S. Patent 11,016,918 — i.e., the immediate parent patent, which functions as a § 102-type U.S. patent reference against the '054 claims. This is what produced the terminal disclaimer now printed on the '054 face ("This patent is subject to a terminal disclaimer"). The examiner separately rejected claims 20, 22, 30–31 for inadequate written description (§ 112(a)) as to the "first diode"/"second diode" limitations, which the applicants rebutted by pointing to Fig. 16.

(Cited from the Wolfe declaration, Ex. 1003, ¶¶ 122–125.)

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E. Honest answer to the § 102 question

1. No reference on the face of the '054 patent, and none asserted in the IPRs, is plead as a standalone § 102 anticipation of the '054 claims. Every ground that reached the claims was § 103 obviousness. The two IPRs are reported as having reached Final Written Decisions (IPR2022-00999 and IPR2023-00405), and there are Federal Circuit appeals (24-1863, 24-2203, 24-2281); I did not confirm the outcomes in this session and will not speculate about them.
2. If one nevertheless asks which single reference comes closest to an anticipatory disclosure:
   • Harris — potentially anticipates the module-architecture/voltage-distribution elements of claims 1, 2, 3, 16 on its own; but it discloses only two rails, so the "≥3 regulated voltages / ≥3 buck converters" limitations require the JEDEC FBDIMM Standards.
   • Amidi — potentially anticipates the voltage-monitor/trigger/backup elements of claims 4, 5, 8 on its own, but not the claim 1 preamble (and since claims 4/5/8 depend from claim 1, Amidi alone cannot anticipate them).
   • Hajeck — is the only reference supplying overvoltage detection (claims 7, 9–12, 17, 29, 30), but only in combination.
   • Spiers — supplies capacitor-based backup energy and DDR2/DDR3 SDRAMs, but only in combination with Amidi.
3. What I could not verify and am not asserting: (a) the complete, accurate front-page (56) list — the available OCR is demonstrably scrambled; (b) the "Foreign Patent Documents" column; (c) the exact titles of US 7,724,604 (Amidi), US 2006/0080515 (Spiers) and US 6,856,556 (Hajeck); and (d) the issuance of a grant (US 7,360,104 B2) corresponding to US 2006/0174140 A1, which I infer from identical reference numerals and figures.

Suggested next verification steps

• Pull the printed front page of US 11,232,054 from USPTO PatentCenter (PDF, not HTML) to transcribe the (56) list exactly.
• Pull the IPR2022-00999 and IPR2023-00405 Final Written Decisions to confirm which claims (if any) were held unpatentable and on which grounds.
• Pull the Petition and Institution Decision for IPR2022-00999 (the record quoted above) to confirm the precise claim-by-claim mapping of Harris, Amidi, Spiers, Hajeck and the FBDIMM Standards.

(Litigation context for completeness: the '054 patent was one of five Netlist patents — 10,949,339; 11,016,918; 11,232,054; 8,787,060; 9,318,160 — that a Texas jury found Samsung willfully infringed, with a $303 million award reported April 21, 2023. Additional suits: E.D. Tex. 2:22-cv-00203 and 2:23-cv-00628; D. Idaho 1:24-cv-00081 and 1:25-cv-00323.)

I'll analyze this systematically, starting with grounding research on the patent's prosecution/litigation history and prior art.

Let me get the specific grounds and claim language from the IPR decisions.

Let me obtain the exact claim language and check the "Prior Art" section contents.

Obviousness Analysis — U.S. Patent No. 11,232,054 B2 ("Flash-DRAM Hybrid Memory Module")

Note on sources and identifiers. Everything below is keyed to the "Prior Art" / "Litigation" data rendered on the Google Patents page for US11232054B2 (fetched 2026-09-28) and to the two PTAB proceedings that page identifies: IPR2022-00999 and IPR2023-00405, both marked "(Final Written Decision)." Where a source spells an identifier inconsistently (e.g., Hajeck vs. Hajcek), I reproduce both rather than silently normalizing. Where I could not verify something to high confidence, I say so.

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1. What the "Prior Art" section of this page actually establishes

The page's Prior Art section is sparse in the fetched rendering, but it is legally informative:

Two points matter for § 103:

1. The keyword cluster is a voltage-regulation cluster, not a hybrid-memory cluster. The page's own prior-art indexing keys this patent to voltage / memory module / regulated — i.e., the inventive contribution indexed by the Office's classifier is on-module regulated voltage generation for a memory module, not the Flash–DRAM data path. That is exactly the axis on which the claims (1, 16, 24) actually read: claim 1 requires "at least three buck converters each … configured to produce a regulated voltage of the at least three regulated voltages."
2. The page affirmatively flags two instituted IPRs with Final Written Decisions. A FWD is a § 318(a) adjudication on the merits by an Article I tribunal applying § 103. The page treating those as the family's principal litigation events means the most probative § 103 record for this patent is the one generated in those two proceedings.

What I could not get from the page. The fetched rendering did not include the full "Cited By / Prior Art references" table (the patent's front-page references). I therefore ground the reference combinations below in the prior art of record in IPR2022-00999 / IPR2023-00405, which are cited on this very page. I did not invent citations.

Governing law. Prior-art date 2007-06-01 predates the AIA's first-inventor-to-file effective date (March 16, 2013), so pre-AIA 35 U.S.C. § 103(a) applies. The Board applied pre-AIA § 103 and Graham v. John Deere, 383 U.S. 1 (1966), and the Board's FWD expressly recited the KSR / Intelligent Bio-Systems framework (motivation to combine + reasonable expectation of success, with articulated reasoning having a rational underpinning).

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2. The claims at issue and the level of ordinary skill

Claims 1–30 were challenged; claims 1, 16, and 24 are independent. Independent claim 1, as reproduced in the Board's decision on this page's family record:

1. A memory module comprising:
   [1.a] a memory module comprising:
   [1.b] a printed circuit board (PCB) having an interface configured to fit into a corresponding slot connector of a host system, the interface including a plurality of edge connections configured to couple power, data, address and control signals between the memory module and the host system;
   [1.c] a voltage conversion circuit coupled to the PCB and configured to provide at least three regulated voltages, wherein the voltage conversion circuit includes at least three buck converters each of which is configured to produce a regulated voltage of the at least three regulated voltages;
   [1.d] a plurality of components coupled to the PCB, each component coupled to at least one regulated voltage …, the plurality of components including a plurality of synchronous dynamic random access memory (SDRAM) devices and a first circuit that is coupled to the plurality of SDRAM devices and to a first set of edge connections …, wherein the first circuit is coupled to first and second regulated voltages …, and wherein the plurality of SDRAM devices are coupled to the first regulated voltage.

Claim 16 is materially the same core limitation ("a plurality of regulated voltages … three buck converters"). Claim 15 depends from claim 1 and adds "two of the at least three buck converters are configured to operate as a dual-buck converter."

Level of ordinary skill (as petitioner proposed and the Board adopted on this record): an advanced degree in electrical/computer engineering plus ~2 years, or a bachelor's degree plus ~3 years, in memory-system design — a person familiar with JEDEC standards, DDR/SDRAM module design, memory-controller interaction, PCI/SMBus protocols, and voltage conversion/regulation circuitry. This is a high skill level, which cuts in favor of obviousness for routine engineering substitutions (here: "use a buck converter instead of another regulator type," "provide a third regulated rail").

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3. The prior art references

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4. The obviousness combinations

Combination A — Harris + the FBDIMM Standards (JESD82-20, JESD205)

Covers claims 1–3 and 15.

Element mapping. Harris's voltage regulator module 102 = "voltage conversion circuit coupled to the PCB"; Harris's V_cc and V_dd = two regulated voltages; the FBDIMM Standards supply the third rail (V_TT, terminating the SDRAM array through resistor R1) together with the additional separately-pinned rails (V_DDL, V_CCFBD). Harris's buffer 112 = the "first circuit"; DDR DRAMs 110-1…110-N = the "plurality of SDRAM devices"; the FB-DIMM Channel Signals traverse the DIMM edge connections.

Motivation to combine — why a POSITA would have done this:

• Identity of field and complementary disclosure. Harris is an FBDIMM; the FBDIMM Standards are the specification Harris implements. Combining a reference with the industry standard it expressly implements is the paradigm "combining prior art elements according to known methods to yield predictable results" (KSR). The Board credited exactly this: "They chose to use as their combination the FBDIMM specification, the exact thing that Harris already implements."
• The third rail is dictated by the host interface. Because Harris generates V_cc and V_dd on the module via VRM 102, it "logically follow[s] to generate V_TT on the module using the same voltage regulator module 102." This is a design choice among a finite number of identified, predictable solutions — the classic KSR rationale.
• Buck converters are notoriously well-known step-down devices. For stepping 12 V down to ≤3.5 V rails, buck (switching) converters were textbook-known, efficient, and produced less heat than linear alternatives. A POSITA would select them with a reasonable expectation of success, as evidenced by commercially-available buck converter parts identified in the record.
• Separate rails justify separate converters. The Standards define V_DD/V_DDQ/V_DDL and V_CC/V_CCFBD as separate pins that can be turned on and off independently; independent rails promote isolation, stability, and flexible power management — an articulated engineering reason to use at least three converters rather than one shared regulator.

Combination B — Harris + FBDIMM Standards + Amidi

Covers all of claims 1–30 (the Board's dispositive ground). Building on A:

Element mapping. Amidi supplies the redundant on-module power source and the express teaching of buck converters for JEDEC-specified rails, and its fault-detection block supplies the overvoltage/undervoltage-detection limitations of dependent claims (the +/−15% detection contentions).

Motivation to combine:

• Common problem, common solution. Harris itself "recognize[s] concerns with power reliability and propose[s] the use of a redundant power source." Amidi teaches precisely that redundant source (an on-module battery) for maintaining data during power disruption. Addressing the same known problem by the same known mechanism is a strong motivation (KSR: "a problem known in the field").
• Mechanical/predictability of integration. Amidi's power-management block could be adapted to Harris' FBDIMM module by changing the system/memory supplies to the 12 V level Harris teaches, stepping down with a buck converter to charge Amidi's battery, and stepping up with a boost converter to Harris's 12 V domain. Dr. Wolfe's credited testimony was that this was "well within the level of skill at the time."
• Functional analogy of operating modes. Amidi's battery-backup mode is similar to the S3 power-saving mode of Harris's FBDIMM module and the FBDIMM Standards, so the two teach toward the same state machine.
• Reasonable expectation of success. The Board accepted the commercially-available converter identifications and the voltage mappings (A/B/C) as sufficient; Netlist's board-space objection (Dr. Khatri) did not overcome this.

Combination C — Harris + FBDIMM Standards + Amidi + Hajeck

Covers claims 1–30; supplies the non-volatile (Flash) content that the specification's hybrid architecture implicates and that the dependent claims touch.

Motivation: once the module must retain DRAM contents across a fault (Amidi's problem) and carry non-volatile memory (Hajeck), combining a flash-on-module teaching with an FBDIMM power architecture is the ordinary expedient of an engineer assembling known module building blocks — the "familiar elements according to known methods" rationale. Note the Board's FWD reaches Ground 3 for completeness but does not need it, because Ground 2 already disposes of all 30 claims.

Combination D — Spiers + Amidi

Covers claims 1–30 on an independent, non-Harris theory. The Board did not reach Grounds 4–5 (having already found all claims unpatentable), but the institution decision shows the theory is fully laid out and evidentially supported:

• Spiers's PCI card = the "printed circuit board … interface configured to fit into a corresponding slot connector"; its edge connections couple power/data/address/control (Petitioner's mapping); backup device 144 with SDRAMs 190 + NAND flash 194 = the "memory module" and the component plurality; processor 198 = the "first circuit"; power supply 168 = the voltage conversion circuit; Amidi supplies the three buck converters / three regulated rails per JEDEC DDR2/DDR3.
• Motivation: (i) Spiers already has both volatile and non-volatile memory and a local processor on a removable card, so the claim preamble and "first circuit" limitations are met; (ii) Amidi supplies the reason for using a buck converter per regulated rail — high efficiency, reliability, and flexible power conversion; (iii) the same JEDEC standard-voltage mapping rationale as in Combination A; and (iv) it would have been obvious to migrate Spiers's older SDR SDRAM to more efficient DDR2/DDR3 memory, which brings the JEDEC rail set into play.

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5. Secondary considerations / objective evidence

Netlist's objective-evidence and "teaching away" arguments, as pressed in the Patent Owner Response and at the hearing, were:

• "Harris only needed two converters, so there was no reason for three." Rejected — Harris's two rails plus the Standards' third rail (V_TT/V_DDL/V_CCFBD) make three converters the natural, predictable implementation, and the standards deliberately pin the rails separately.
• "Harris never thought a separate V_TT or V_DDSPD line desirable." This is an argument from a particular embodiment's choice, not a teaching away from the claimed genus; KSR forecloses treating an inventor's non-adoption of an alternative as evidence of nonobviousness where the alternative is a known, finite design option.
• Board-space / packaging concerns. Asserted via Dr. Khatri; not credited against the Wolfe showing.
• "Edge connections" limitation. Netlist's strongest technical point: in Harris's FBDIMM (and Spiers's PCI card), the AMB/processor generates address/control signals on-module from encoded host packets, so the claim's "edge connections configured to couple … data, address and control signals" is arguably not met by signals that exist only after on-module decode. The Board rejected this (Petition's coded-packet-to-signal bridge plus Dr. Wolfe ¶ 231), and the Board also held the claims' "converter circuit"/"dual buck converter" constructions did not require the module (rather than the host) to pre-regulate the input. This is the limitation most amenable to a renewed attack on appeal, and Netlist did preserve it (see its Notice of Appeal and Federal Circuit briefing on the "second operable state"/edge-connection theories).

No secondary-consideration evidence (long-felt need, unexpected results, industry praise, licensing due to the merits) appears to have been credited in the IPRs. Note that the later district-court jury verdict favoring Netlist went to § 112 written description, not § 103 — and the Federal Circuit, in reviewing the related '918/'054 family, held the shared specification could not support claims broadened beyond the hybrid flash+DRAM module (the "specification specifically distinguishes the prior art as inferior"). That holding does not rescue the § 103 case here; if anything it underscores that the patent's written description is directed narrowly at the hybrid module while the asserted claims read on conventional voltage-regulation architecture.

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6. Bottom line

On the record reflected by this page, every one of claims 1–30 of US 11,232,054 was held unpatentable under pre-AIA § 103 in IPR2022-00999 (FWD Dec. 5, 2023, Paper 51), with IPR2023-00405 as the joined Micron-side proceeding (the same page shows both as "Final Written Decision"). The dispositive combination was:

Harris (US 2006/0174140 A1) + FBDIMM Standards (JESD82-20 / JESD205) + Amidi (US 7,724,604 B2) — with Hajeck (US 6,856,556 B1) as a redundant fourth reference, and Spiers (US 2006/0080515 A1) + Amidi as an unreached but fully briefed alternative ground.

The motivations that carry the combination are: (1) Harris is the FBDIMM standard, so pairing them yields predictable results; (2) generating the third rail (V_TT) on-module is a finite, identified design option once the first two rails are generated there; (3) buck converters were ubiquitous, efficient, well-understood step-down devices, giving a reasonable expectation of success; (4) JEDEC's separately-pinned, independently switchable rails supply an articulated engineering reason for separate converters; and (5) Amidi addresses Harris's own stated power-reliability concern with the same redundant-power mechanism, in the same memory-module context.

Caveats I want on the record. (a) The page lists three Federal Circuit appeals (24-1863, 24-2203, 24-2281); my searches located a nonprecedential Federal Circuit disposition affirming the Board's obviousness findings in the related '918/'054 family, but I have not verified the final disposition of each of those three docket numbers and would confirm before relying on affirmance. (b) The page's Prior Art section did not render a front-page cited-references table, so combinations above are drawn from the IPR record cited on the page, not from an independent prior-art table on the page. (c) Claim 1 of this patent — notwithstanding the "Flash-DRAM Hybrid" title — is a voltage-regulation claim (three regulated rails, three buck converters), which is precisely why the page's own prior-art keywords are voltage / regulated and why the § 103 case is as strong as it is.