US 10949339

I'll search for authoritative information on this patent, including litigation/docket data.

Let me pull the exact text of the other independent claims (11, 19, 27) and confirm the docket posture.

US Patent 10,949,339 B2 — Analyst Summary

⚠️ Date discrepancy flag (material to your request)

Your prompt states the current date is April 26, 2026, but my system date is September 28, 2026, and the search results below include an en banc/precedential CAFC opinion dated September 2, 2026. I am reporting those results as the current ground truth per your instructions, but you should confirm which date is operative — if the true date is April 2026, a September 2026 decision could not yet exist, and the '339 patent's legal status would then be appeal pending rather than affirmed invalid.

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1. Bibliographic data (confirmed against the patent front page and USPTO records)

The terminal disclaimer matters: it links the '339 patent's enforceable term to an earlier Netlist patent in the chain (familiarly the '907 patent), which was itself litigated at the PTAB.

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2. Abstract (verbatim)

"A memory module is configured to communicate with a memory controller. The memory module comprises DDR DRAM devices arranged in multiple ranks each of the same width as the memory module, and a module controller configured to receive and register input control signals for a read or write operation from the memory controller and to output registered address and control signals. The registered address and control signals selects one of the multiple ranks to perform the read or write operation. The module controller further outputs a set of module control signals in response to the input address and control signals. The memory module further comprises a plurality of byte-wise buffers controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal associated with the read or write operation between the memory controller and the selected rank."

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3. Plain-language overview of the four independent claims

Claim 1 — the write-path "byte-wise buffer" claim (the representative claim).
An N-bit-wide memory module (e.g., a 72-bit DIMM) that plugs into a socket and has: (a) a PCB with an edge connector; (b) DDR DRAM devices wired in multiple N-bit-wide ranks; (c) a module controller that registers incoming address/control signals and issues registered address/control signals to make one rank perform a write, and separately emits module control signals; and (d) a set of byte-wise buffers, each with a first side to a byte-wide data line set from the controller, a second side to at least one DRAM in each rank, a byte-wise data path between them, and placed on the PCB at a location matching its data line set. Logic in each buffer controls that data path in response to the module control signals: the path is enabled for a first time period in accordance with a latency parameter to actively drive a byte of write data from controller side to DRAM side, and the path contains first tristate buffers that are enabled to drive that data onto the module data lines during that period.
Note: limitation wording [1e]/[1f] containing "tristate buffers" and "latency parameter" reflects amendments made during prosecution (per petitioner briefing), and the granted text sits at 19:9–67.

Claim 11 — "data transmission circuit" variant with paired 4-bit DRAMs.
Essentially claim 1's architecture but drafted around a "data transmission circuit" (the specification's other name for the same component) rather than a "byte-wise buffer," and requiring the DRAM devices be 4-bit-wide devices used in pairs (i.e., two 4-bit devices serving one byte section), with the circuit configurable to enable its data paths for a first time period to drive write data.

Claim 19 — successive-operations claim (read-data, second-side-to-first-side).
A memory module with a module controller that registers signals for first and then second memory operations, plus multiple buffers with data paths and logic. The logic enables the data paths for a first time period to drive a respective section of the first N-bit-wide data from the second side to the first side (i.e., out of the DRAMs toward the controller), and enables them again for a second, subsequent time period for the second operation — and critically the data paths are disabled between the first and second periods. Claim 21 adds that timing of both periods is set using a latency parameter.

Claim 27 — write/read bidirectional buffer claim with two tristate sets.
Requires "a plurality of n-bit-wise data buffers" (note: "n-bit-wise," not "byte-wise"). Covers a write operation and a read operation, with first tristate buffers enabled for the write period to drive write data, second tristate buffers enabled for the read period to drive read data, and mutual exclusion — first set disabled during the second period and second set disabled during the first period. Dependent claim 28 adds that both sets are disabled whenever the module is not targeted by the controller; claims 34/35 add the latency-parameter limitation to each set.

Uncertainty note: I have high confidence in the verbatim claim 1 text (reproduced in the CAFC opinion and Netlist's appellate brief) and in the gist of claims 11, 19 and 27 (from PTAB final written decision excerpts and district-court briefing). I have not retrieved the complete verbatim text of claims 11, 19 and 27 in one source; paragraph-level citations for those three are approximate (e.g., claim 27 spans ~25:29–26:31; claim 19 ~23:29–24:29).

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4. Claim-construction note relevant to scope

In the E.D. Tex. litigation, the court adopted a "fork-in-the-road" construction of "drive"/"actively drive": "enabling only one of the data paths while the other possible paths are disabled." This reading (a) requires the buffer to have multiple possible paths with only one enabled, and (b) underpinned the parties' infringement disputes over JEDEC JESD82-32A-compliant DDR4 module circuits.

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5. PTAB and CAFC status — the decisive development

Challenges at the PTAB

• IPR2022-00639 — Samsung Electronics Co., Ltd. v. Netlist, Inc.
• IPR2023-00204 — Micron Technology, Inc. v. Netlist, Inc. (Samsung joined)
• Ground: claims 1–35 obvious under 35 U.S.C. § 103 over Ellsberry (US 2006/0277355 A1) alone or in combination with Halbert (US 7,024,518).
• Outcome: PTAB found all challenged claims unpatentable as obvious; claim 1 treated as representative. Key findings: Ellsberry's switch-ASIC Ports A/B are within the buffer and their enablement constitutes enabling a data path; Ellsberry's Posted CAS (AL) latency bits satisfy "in accordance with a latency parameter"; Halbert's tristate buffers supply the tristate limitation with motivation to combine (bus conflicts, load reduction, power savings).

Federal Circuit appeal — No. 2024-1707

• Caption: Netlist, Inc. v. Micron Technology, Inc. (Samsung settled and withdrew; Micron sole appellee). Precedential.
• Decision: affirmed (opinion dated September 2, 2026), holding substantial evidence supported the Board's obviousness findings and rejecting Netlist's APA arguments.
• Practical effect as reported: all challenged claims of the '339 patent held unpatentable, i.e., the patent's asserted claims are invalid. Netlist's stock reportedly fell ~21% on the news.
• Primary source: https://www.cafc.uscourts.gov/opinions-orders/24-1707.OPINION.9-2-2026_2749527.pdf

Other dockets touching this patent (as listed on the Google Patents family/litigation page — several unverified as to subject matter)

• CAFC 24-1707 (the appeal above) and CAFC 24-2203; a further CAFC entry numbered 26-1671 is listed but I could not verify its subject matter from search results.
• E.D. Tex.: 2:21-cv-00463, 2:22-cv-00203, 2:22-cv-00293 (Netlist v. Samsung), 2:23-cv-00628
• D. Del.: 1:21-cv-01453 (Samsung v. Netlist, DJ of non-infringement)
• N.D. Cal.: 3:09-cv-05718 (Netlist v. Google)
• D. Idaho: 1:24-cv-00081, 1:25-cv-00323 (Micron unfair-competition/bad-faith-assertion action naming the '339 patent among others; remanded to Idaho state court March 25, 2026)
• Family litigation record: https://patents.darts-ip.com/?family=42610062

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6. Bottom line

US 10,949,339 is a Netlist continuation patent (2009 priority, filed 2017, issued 2021) claiming DIMMs with a centralized registering module controller plus distributed byte-wide buffers that store the "fork-in-the-road" data paths, selectively enabling tristate drivers under CAS-latency control to reduce controller load. Its four independent claims (1, 11, 19, 27) cover write-path buffering, a "data transmission circuit" variant with paired 4-bit DRAMs, successive read-path operations with a disabled interval between them, and dual-tristate write/read buffering respectively. The patent is subject to a terminal disclaimer and, per the most recent search results, all challenged claims 1–35 were found obvious over Ellsberry in view of Halbert, affirmed by the Federal Circuit on September 2, 2026 — subject to the date discrepancy flagged at the top.

Sources: Google Patents https://patents.google.com/patent/US10949339/en; CAFC opinion 24-1707 (Sept. 2, 2026); CourtListener CAFC brief in No. 24-1707; PTAB IPR2022-00639 and IPR2023-00204 records; Docket Alarm IPR exhibits; CourtListener district-court filings (D. Del. 1:21-cv-01453; E.D. Tex. 2:22-cv-00293, 2:21-cv-00463).

I'll research litigation involving US patent 10949339. Let me start with searches covering patent litigation databases.

Let me dig deeper into specific cases and outcomes.

Litigation involving U.S. Patent No. 10,949,339

Important framing note: U.S. 10,949,339 (the "’339 patent," Netlist, Inc., "Memory module with controlled byte-wise buffers") is one patent in a large, multi-front Netlist v. Samsung / Netlist v. Micron campaign. I've separated true district-court litigation from the PTAB and Federal Circuit proceedings, since the ’339 patent's current status is largely defined by the IPR/A appeal rather than by any single infringement verdict.

A date caveat: your prompt states the current date is April 26, 2026, but several authoritative sources I found (the Federal Circuit opinion and the Samsung settlement) are dated later in 2026. I flag that rather than silently reconcile it. Per your instructions, I'm treating the search results as ground truth and reporting what they show, with dates attached.

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1. Netlist, Inc. v. Samsung Electronics Co., Ltd.; Samsung Semiconductor, Inc.; [Samsung Electronics America, Inc.](/litigations/by-plaintiff/Samsung%20Electronics%20America%2C%20Inc.)

• Court / Jurisdiction: U.S. District Court for the Eastern District of Texas (Marshall Division)
• Case No.: 2:21-cv-00463-JRG (Chief Judge Rodney Gilstrap)
• Filed: December 20, 2021
• ’339 involvement: Asserted (Netlist amended its complaint to add the ’339). The ’339 was one of five patents tried; asserted claims were claims 1, 8, and 9 of the ’339 patent.
• Outcome: Jury verdict April 21, 2023 — Samsung willfully infringed all five patents (’339, ’918, ’054, ’060, ’160); none invalid; composite reasonable royalty of $303,150,000. Final judgment entered August 11, 2023, also rejecting Samsung's equitable defenses (prosecution laches, estoppel, unclean hands).
• Current status: Samsung appealed to the Federal Circuit (see No. 2024-2203 below); its motion to stay that appeal was denied Feb. 18, 2025. The parties later settled all pending litigation in 2026 as part of a strategic alliance/portfolio license (Irell & Manella announcement, Aug. 2026), and Samsung withdrew from the IPR appeal.
• Sources: Netlist press releases (Apr. 24, 2023; Aug. 14, 2023); SEC Form 8-K (Aug. 14, 2023); E.D. Tex. Dkt. 479 (verdict), Dkt. 551 (final judgment); CourtListener

2. Netlist, Inc. v. Micron Technology, Inc.; Micron Semiconductor Products, Inc.; Micron Technology Texas LLC ("Micron I")

• Court / Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case No.: 2:22-cv-00203-JRG-RSP
• Filed: June 10, 2022
• ’339 involvement: Asserted (one of six patents originally pleaded: ’506, ’339, ’918, ’054, ’060, ’160).
• Outcome: After the PTAB's Oct. 18, 2023 final written decision in IPR2023-00204 invalidated the ’339, Netlist informed the court on Oct. 23, 2023 that it would no longer pursue the ’339 (dropped along with the ’506). The case was stayed; on June 13, 2024 the court ordered the case maintained notwithstanding that all asserted claims had been invalidated at the PTAB.
• Current status: The ’339 is no longer asserted here; the case remained pending/affected by the appeal of the IPRs.
• Sources: E.D. Tex. Dkt. 286, 345, 421, 426, 501; CourtListener

3. Netlist, Inc. v. Micron Technology, Inc. et al

• Court / Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case No.: 2:23-cv-00628-JRG
• Filed: December 22, 2023
• Character: Declaratory judgment action (tied to the Micron/Netlist Idaho bad-faith dispute) rather than a straightforward infringement case.
• ’339 involvement — LOW CONFIDENCE: The Google Patents litigation record lists this case for the ’339 family, and a third-party complaint analysis of this docket shows ’339 infringement allegations against Micron DDR4 LRDIMMs. However, the docket is captioned as a declaratory judgment action, so I cannot confirm with high confidence that the ’339 patent was itself asserted as a claim in this case. Treat as unverified.
• Source: NPE Litigation Database; Ex Parte docket

4. Idaho District Court actions — 1:24-cv-00081 and 1:25-cv-00323 (D. Idaho)

• Listed in the Google Patents family-litigation data for this patent. Based on the record, these appear to be the Micron-initiated Idaho bad-faith/state-law litigation and later Netlist filings arising from the same dispute, not ’339 infringement suits. I do not have confirmed party/case details tying the ’339 patent to these dockets, so I'm flagging them as possible rather than confirmed.

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PTAB proceedings (administrative — not Article III litigation, but decisive for the ’339 patent)

5. Samsung Electronics Co., Ltd. v. Netlist, Inc. — IPR2022-00639

• Filed: March 2, 2022 (Petitioner Samsung; Micron joined)
• Patent: 10,949,339
• Outcome: Final Written Decision (Oct. 2023) holding all challenged claims (claims 1–35) unpatentable as obvious over Ellsberry (US 2006/0277355) in view of Halbert (US 7,024,518). Request for rehearing denied Feb. 9, 2024.
• Sources: Docket Alarm; Unified Patents portal

6. Micron Technology, Inc. v. Netlist, Inc. — IPR2023-00204

• Filed: November 18, 2022 (Petitioner Micron)
• Patent: 10,949,339
• Outcome: Final Written Decision Oct. 18, 2023 — all challenged claims unpatentable (same Ellsberry + Halbert ground); petitioner's motion to exclude dismissed. This is the FWD that caused Netlist to drop the ’339 from Micron I and that was appealed.
• Sources: E.D. Tex. Dkt. 349; Unified Patents portal

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Federal Circuit appeals

7. Netlist, Inc. v. Micron Technology, Inc., No. 2024-1707 (Fed. Cir.)

• Filed/argued: Appeal of the IPR2022-00639 / IPR2023-00204 FWDs on the ’339 patent.
• Parties: Originally Netlist v. Samsung and Micron; Samsung settled and withdrew, leaving Micron as sole appellee.
• Outcome / Status: Precedential opinion issued September 2, 2026 — AFFIRMED. The Federal Circuit upheld the Board's obviousness determination that all challenged claims of the ’339 patent are unpatentable. The court rejected Netlist's arguments on (a) the "latency parameter" limitation (finding substantial evidence in Ellsberry's "Posted CAS_n" disclosure), (b) "enabling a data path" (finding Ellsberry's Ports A/B are within the switch ASIC), and (c) APA violations. Any error in the Board's reliance on Netlist's own U.S. 7,532,537 was held harmless.
• Sources: CourtListener opinion; IPWatchdog; Fed Circuit Blog

8. Netlist, Inc. v. Samsung Electronics Co., Ltd., et al., No. 2024-2203 (Fed. Cir.)

• Filed: August 9, 2024 (Samsung's notice of appeal of the E.D. Tex. final judgment in 2:21-cv-00463, the $303M case that included the ’339).
• Status: Samsung's motion to stay the appeal pending the California CDCA license case was denied without prejudice on Feb. 18, 2025. Later encompassed by the 2026 Samsung–Netlist settlement.

9. No. 26-1671 (Fed. Cir.)

• Listed in the Google Patents litigation data for this family. I do not have confirmed party/issue details for this docket and won't speculate.

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Net effect on the ’339 patent

The ’339 patent's claims were invalidated by the PTAB (all challenged claims 1–35 unpatentable) in IPR2022-00639 and IPR2023-00204, and that invalidation was affirmed by the Federal Circuit on September 2, 2026 in Netlist v. Micron, No. 2024-1707. That is consistent with the patent's Google Patents page showing PTAB cases IPR2022-00639 and IPR2023-00204 under litigation.

Where I am not confident / cannot verify: (a) whether the ’339 was actually asserted in the 2:23-cv-00628 declaratory judgment action; (b) the precise role of the ’339 in the two Idaho dockets; and (c) the subject matter of CAFC No. 26-1671. I also could not confirm a standalone ITC action specifically asserting the ’339 patent. So the confirmed ’339 litigation is best summarized as: the Samsung E.D. Tex. case (2:21-cv-00463) and the Micron E.D. Tex. case (2:22-cv-00203), plus the two IPRs and the Federal Circuit appeal that invalidated the claims.

If you want, I can try to pull the actual docket sheets via PACER/CourtListener for 2:23-cv-00628 and the Idaho cases to close those gaps.

I'll start by verifying what's actually on file, since the structured block says "no PTAB activity" but the patent's own Google Patents page lists two PTAB case numbers (IPR2022-00639, IPR2023-00204).

The structured block is wrong — the patent's own record shows two IPRs, and search has surfaced a possible new PGR. Let me dig into each and check for others.

Important: PGR2026-00001 and IPR2026-00018 are on patent 12,373,366, not the '339 patent — those must be excluded. Let me confirm the institution dates, Director Review activity, and the CAFC docket mapping.

⚠️ Source-integrity flag before anything else

The structured "PTAB proceedings on file" block says the ODP API returns no AIA trial proceedings for US 10,949,339. That is wrong / incomplete. The patent's own Google Patents record lists two PTAB cases with Final Written Decisions, and public docket sources confirm both. I am using the docket-derived proceedings rather than the empty ODP block, and I'm flagging the discrepancy rather than defaulting to "no PTAB activity."

Also flagging two look-alikes that are not about this patent and must be excluded:

• PGR2026-00001 / IPR2026-00018 (Samsung v. Netlist) — these are on U.S. Patent 12,373,366 B2, a different member of the same Netlist family. Denied institution 2026-03-23 under the Director's Fintiv-style discretionary-denial analysis. Not a '339 proceeding.
• IPR2023-00454 / IPR2023-00455 — on U.S. Patents 11,093,417 and 9,858,215. Not the '339.

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Proceedings overview

Two AIA trial proceedings on US 10,949,339: both instituted, both tried to a Final Written Decision, and both resulted in every challenged claim being held unpatentable — 0 claims sustained, 0 settled pre-FWD, 0 institutions denied. The patent has been completely invalidated: claims 1–35 were cancelled by the Board on 2023-10-18, rehearing was denied on 2024-02-09, and the Federal Circuit affirmed on 2026-09-02 in a precedential opinion. The bottom line for a defendant: there is nothing left of this patent to assert. Any demand letter citing US 10,949,339 is asserting cancelled claims, and Netlist itself told the E.D. Tex. court on 2023-10-23 that it was no longer pursuing infringement of any claim of the '339 patent.

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IPR2022-00639 — Samsung Electronics Co., Ltd. v. Netlist, Inc. (Micron joined as petitioner)

• Type: Inter Partes Review
• Filed: 2022-03-02 (docket listed; the printed Google Patents record says "filed" without date)
• Status: Final Written Decision issued — all challenged claims unpatentable; rehearing denied; affirmed by the Federal Circuit (precedential). (The ODP block gave no status because it had no record of the case; this status is docket-derived.)
• Judge panel: Administrative Patent Judges Jon M. Jurgovan (writing), Daniel J. Galligan, and Kara L. Szpondowski
• Petition grounds: § 103 obviousness over U.S. Patent Application Publication No. 2006/0277355 ("Ellsberry"), alone and/or in combination with U.S. Patent No. 7,024,518 ("Halbert"), against claims 1–35 (all claims). No § 102 or § 112 ground carried the decision.
• Institution decision: Instituted under 35 U.S.C. § 314(a) (Paper 15). The Board agreed Samsung had shown a reasonable likelihood that Ellsberry, viewed alone or with Halbert and with the general knowledge of a POSITA, teaches "enabling and disabling data paths through the data buffer." The exact institution date is not confirmed in the sources I retrieved; the 2023-10-18 FWD is consistent with an October 2022 institution under the § 316(a)(11) one-year clock.
• Final Written Decision: Paper 45, entered 2023-10-18 — "Determining All Challenged Claims Unpatentable." Claims 1–35 all unpatentable; independent claim 1 treated as representative. Every challenged claim was cancelled; no claim was held patentable. Key reasoning (quoted from the opinion/J.A.):
  • "Ellsberry alone or in combination with Halbert, when viewed with the general knowledge of a person of ordinary skill in the art, teaches enabling and disabling data paths through the data buffer."
  • Petitioner "established that Ellsberry's switch ASICs use Posted CAS latency (AL) bits to control timing of the enablement of the data path across its switch ASICs."
  • The Board dismissed Netlist's argument that Ellsberry's Ports A/B sat outside the switch ASIC as "manifestly incorrect."
  • The Board also dismissed Petitioner's Motion to Exclude.
  • Oral hearing: 2023-07-19.
• Rehearing / Director Review: Netlist filed a Request for Rehearing (Paper 47). Denied 2024-02-09 (Paper 48) — the panel found Netlist's assertions "do not show that the Board misapprehended or overlooked any matters." Netlist raised four points (Ellsberry disables devices not data paths; Halbert + JEDEC don't cure the gap; no latency-parameter teaching; no motivation) — all rejected. (Link: IPR2022-00639 Paper 48, denial of rehearing.)
• Settlement / termination: Samsung later settled with Netlist and withdrew from the appeal; Micron continued as the sole appellee. The settlement terms are not public — treat as confidential.
• Appeal: Yes. Netlist appealed; appellees included Samsung and Micron. Appeal No. 24-1707 (Fed. Cir.), treated as a companion case with Nos. 24-1859, 24-2203, and 24-2240 by order dated 2024-09-12. Netlist's opening brief was filed 2024-10-15 (Irell & Manella / Mololamken). Disposition: AFFIRMED — precedential opinion issued 2026-09-02, Netlist, Inc. v. Micron Technology, Inc. (CAFC opinion PDF; CourtListener). The court held (a) substantial evidence supported the "in accordance with a latency parameter" finding (Ellsberry stores "Posted CAS_n" in the bank switch; JEDEC standards corroborate); (b) substantial evidence supported the "enabl[ing] a data path" finding (Ports A/B are components within the switch ASIC), with an alternative Ellsberry+Halbert finding; (c) any Board reliance on Netlist's own U.S. Patent 7,532,537 was harmless error; and (d) the APA arguments failed.
• Defensive value: Total. Claim 1 is dead, claims 2–35 are dead. Any infringement theory built on any claim of the '339 is non-viable, and Netlist is judicially estopped from walking it back in the E.D. Tex. case where it already gave up the patent.

IPR2023-00204 — Micron Technology, Inc., Micron Semiconductor Products, Inc., Micron Technology Texas LLC v. Netlist, Inc.

• Type: Inter Partes Review (joinder to IPR2022-00639 under § 315(c))
• Filed: 2022-11-18 (petition and motion for joinder filed concurrently; petition defects cured with the motion per § 42.122(b))
• Status: Final Written Decision issued — all challenged claims unpatentable; on appeal with the '639 case; affirmed.
• Judge panel: Same panel — Jurgovan, Galligan, Szpondowski
• Petition grounds: § 103 obviousness on the same Ellsberry / Halbert art and the same claims as the '639 IPR. This was a deliberate follow-on/joinder, not an independent art attack.
• Institution decision: Instituted and joinder granted, 2023-06-07 (Paper 7). Reasoning in one line: an IPR had already been instituted in the '639 IPR on Samsung's petition; Micron timely filed a petition and joinder motion; Samsung did not oppose joinder; Netlist filed no preliminary response and no opposition to joinder. The Board therefore joined Micron and instituted. (Confirmed as Exhibit B to E.D. Tex. Dkt. 101-2.)
• Final Written Decision: Paper 8, entered 2023-10-18 — "Determining All Challenged Claims Unpatentable." Because '204 was a joined, streamlined case, its FWD issued the same day and to the same effect as the '639 FWD. Netlist's post-FWD rehearing was sought in the '639 case; the Board in the rehearing decision refers to Samsung and Micron collectively as "Petitioner."
• Settlement / termination: No settlement by Micron. Micron litigated the appeal and was the sole remaining appellee by the time of the 2026-09-02 decision.
• Appeal: Yes — consolidated into the same companion-case group (Nos. 24-1707, 24-1859, 24-2203, 24-2240); the Federal Circuit's order recites "Appeal from ... PTAB in Nos. IPR2022-00639 and IPR2023-00204." Disposition: AFFIRMED, 2026-09-02.
• Defensive value: This is the case that gave Micron its own § 315(e)(2) estoppel and its own judgment of invalidity, which Micron then used to win a stay motion in E.D. Tex. and to support its bad-faith-assertion counterclaim in Idaho. If you are a defendant, this is the FWD you cite for the proposition that the invalidation is adversarially tested, not a one-petitioner fluke.

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Strategic summary

Claim status: CANCELED — everything. The '339 patent issued with claims 1–35. Samsung challenged all 35; the Board found all 35 unpatentable on 2023-10-18, denied rehearing on 2024-02-09, and the Federal Circuit affirmed on 2026-09-02. No claims of the '339 are SUSTAINED, and none are UNTESTED — the entire claim set was on the table. (The Board treated claim 1 as representative; Netlist's appellate brief separately argued claims 7, 16, and 21 carried parallel "module control signal … latency parameter" limitations, which suggests those are also independent claims — I flag that as an inference from the briefing, not something I can confirm from the FWD text I retrieved. It does not change the outcome: all 35 claims fell.) The remaining question is only whether the mandate has issued and whether any rehearing en banc/cert petition is pending; the 21-day Federal Circuit rehearing window from 2026-09-02 runs out around 2026-09-23, and I have not verified whether Netlist filed one — do not assume finality without checking the 24-1707 docket.

Estoppel landscape. Because both proceedings ran to FWD (no adverse judgment, no settlement as to Micron), 35 U.S.C. § 315(e)(2) estoppel has attached against Samsung and Micron and their privies as to any ground raised or that reasonably could have been raised. That estoppel is largely academic now — the claims are cancelled, so there is nothing to invalidate again. The practical point runs the other way: with the patent dead, there is no live prior-art question left for a defendant to fight about. If you are nonetheless served with a '339 assertion, the correct first move is not an IPR (you cannot IPR cancelled claims) — it is a motion to dismiss / Rule 11 or § 285 letter pointing at the FWD and at Netlist's 2023-10-23 representation to the E.D. Tex. court.

Pattern signals worth knowing. (1) Same-petitioner stacking: Samsung filed the lead IPR and Micron joined via a concurrently-filed petition + motion for joinder — a coordinated two-front attack that the Board allowed straight through (Netlist filed no preliminary response in '204). (2) Netlist litigates hard but loses this family: Netlist appealed, retained Irell & Manella and Mololamken, raised both substantive and APA/SAS-based arguments, and still lost on a precedential opinion. (3) No defensive aggregator here — this was not a Unified Patents or RPX challenge; it was Micron/Samsung self-help. (4) The family fights on: Netlist keeps obtaining new claims (U.S. Pat. 12,373,366; 11,994,982; and publication 2024/0394177), and the newest Samsung challenges (PGR2026-00001 / IPR2026-00018 on the '366 patent) were denied institution on discretionary grounds on 2026-03-23 — so a defendant's exposure, if any, has migrated to the newer family members, not to the '339.

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Recommended next steps

1. If you hold or have received a '339 demand: it cites cancelled claims. Quote the FWD disposition verbatim — "Determining All Challenged Claims Unpatentable" (IPR2022-00639 Paper 45, 2023-10-18) — and the affirmance (24-1707, 2026-09-02). Pair it with Netlist's own 2023-10-23 statement to the E.D. Tex. court that it was "no longer pursuing infringement of any claim in the '339 patent" (Dkt. 349).
2. Check the 24-1707 docket for finality (CourtListener 24-1707). Confirm (a) whether a petition for rehearing/en banc was filed after 2026-09-02, and (b) whether the mandate has issued. Until the mandate issues, use the phrase "affirmed on appeal; mandate pending" rather than "final judgment."
3. Do not file an IPR on the '339 — cancelled claims are not IPR-eligible, and a filing would be a waste of the post-institution fee and a credibility hit.
4. Re-scope your freedom-to-operate to the live family. The assertion risk has moved to US 12,373,366, US 11,994,982, and US 2024/0394177 A1. Note that Samsung's '366 petitions were denied institution on 2026-03-23 on discretionary grounds (untimely Sotera-type stipulation; stipulation failed to bind co-respondents Google and Super Micro) — that denial is not a merits win and gives you no estoppel benefit against the '366 claims.
5. If you are a Micron/Samsung-adjacent defendant, note that § 315(e)(2) estoppel already binds those petitioners as to the '339; if you are a different defendant, you are not bound, but you also have nothing to gain — the claims are gone.

Caveats / what I could not verify: the exact institution date and paper number for IPR2022-00639 (Paper 15 is confirmed as the institution document; the date is not); whether a Federal Circuit rehearing or cert petition has been filed post-2026-09-02; the exact independent/dependent claim topology of the '339; and the confidential terms of the Samsung–Netlist settlement. Everything else above is grounded in the cited FWD, rehearing decision, CAFC opinion, and district-court filings.

I'll start by pulling what I can verify about the assignment record and litigation context.

Good — I have one recorded assignment (64686/603). Let me pin down the correspondent and check for other recordings.

Assignment & Ownership Reconstruction — US 10,949,339 B2

Patent: US 10,949,339 B2 — "Memory module with controlled byte-wise buffers"
App. No. 15/470,856 (filed 2017-03-27) · Issued 2021-03-16 · Current assignee (per Google Patents legal events): Netlist Inc
Priority: 2009-07-16 via US 12/504,131 (→ US 8,417,870) → 12/761,179 (→ US 8,516,185) → 13/970,606 (→ US 9,606,907) → 15/470,856
Anticipated expiration: 2029-07-16

Sourcing note / limitation. I could not complete a live authenticated query against assignmentcenter.uspto.gov in this session (the search interface requires an interactive session and my direct lookups returned no record-level data). The assignment record below is reconstructed from the USPTO assignment data as mirrored in the Google Patents legal-events feed on this patent's page and in PlainSite's mirror of the USPTO assignment database. Reel/frame, execution and recording dates are reproduced as recorded. The correspondent of record entry could not be retrieved and is flagged as unverified rather than guessed. Verify at USPTO Assignment Center using the "Search by patent number" tab (patent 10949339) before relying on this for anything dispositive.

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Inventors

Unusual-pattern check — NEGATIVE. Both inventors are Netlist insiders and the assignee never changed hands. There is no evidence of the inventors departing the original assignee within 12 months of filing, and no evidence of an inventor-originated portfolio fire-sale. This is the inverse of the classic pre-fire-sale tell. The only inventor-side anomaly is procedural, not commercial: the inventors' assignment paperwork was executed in 2010 but sat unrecorded for ~13 years (see timeline), and was recorded in 2023 while Netlist was mid-litigation — a standing/perfection housekeeping step rather than an ownership change.

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Original assignee

Netlist, Inc., Irvine, CA (address on the 2023 assignment: 3 Goddard, Irvine, CA 92618; the EPO/INPI family record shows later 175 Technology Drive, Irvine). Assignee on the face of the issued patent ("Applicant: Netlist, Inc., Irvine, CA (US)").

• Primary line of business: Historically a designer/manufacturer of specialty server memory modules — Netlist's HyperCloud load-reduced DIMM line is the product family directly relevant to this specification (Netlist's own trial testimony references the HyperCloud datasheet listing the grandparent/parent patents, PX-16 in Netlist v. Micron, E.D. Tex. 2:22-cv-00203). Netlist is a publicly traded company (NASDAQ: NLST) and a JEDEC participant; it submitted Letters of Assurance committing to RAND licensing of DDR4-essential claims for the '185 and '870 parents, which per Samsung's pleadings extend to the '339 "to the extent they are essential to the DDR4 Standards."
• Current status: Operating/gong-concern public company, not in bankruptcy, not dissolved, not acquired. No bankruptcy filing, Chapter 7/11 sale, or assignment out of Netlist appears in the record.
• Product-embodiment status (important nuance): Netlist's historical HyperCloud-generation modules implemented the load-reduced/byte-buffered architecture claimed here. Netlist's revenue mix, however, is now dominated by patent licensing and enforcement rather than module sales — it is a genuine operating company that has become litigation-revenue dependent, which is why the verdict below requires care.

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Assignment timeline

Searched sources disclose exactly one recorded assignment touching US 15/470,856 / US 10,949,339. There is no recorded transfer of the '339 patent away from Netlist.

• 2010-08-30 (executed) / recorded 2023-08-23 — Reel 64686 / Frame 0603
  • Conveyance: Assignment Of Assignors Interest (confirmatory / nunc pro tunc inventor-to-company assignment)
  • Assignor: Lee, Hyun; Bhakta, Jayesh R. (individually)
  • Assignee: Netlist, Inc., 3 Goddard, Irvine, CA 92618
  • Correspondent: ⚠️ Not retrieved. PlainSite's mirror of USPTO assignment record 64686/603 renders a "Correspondent" column but exposes no name in the returned text, and I could not pull the underlying Assignment Center record. I will not name a firm here. Flag for follow-up: the prosecution correspondence of record for at least one sibling Netlist application in this family (13/412,243, filed 2012-03-05) was The Law Office of Jamie Zheng, Ph.D., Esq. (Customer No. 20995; filer "Jamie Jie Zheng"), filed under attorney docket NETL.045C1 — that is prosecution correspondence, not assignment correspondent, and is offered only as a lead, not as a finding on this reel/frame.
  • Context: Internal perfection / standing-record cleanup. The instrument was executed 2010-08-30 — years before this patent existed — and recorded 2023-08-23, while the patent was in suit (Netlist v. Samsung, E.D. Tex. 2:21-cv-00463, filed 2021-12-20) and in IPR2022-00639. It transfers rights from the inventors to the same company that already owned the patent; no third party receives anything.

No other recordings located. In particular, I found no security-agreement, license, release, merger, or change-of-name recording for the '339 in the sources searched. The absence of a security-interest recording is notable given the value at stake, but I cannot certify a negative without a live Assignment Center query.

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Timeline diagram

timeline
    title Ownership of US 10949339
    2009 : Priority application filed by Lee and Bhakta
    2010 : Inventors execute assignment to Netlist
    2017 : Continuation application filed
    2021 : Patent issued to Netlist
         : Netlist sues Samsung in EDTX
    2023 : Inventor assignment recorded after 13 years
         : PTAB invalidates all challenged claims
    2026 : Federal Circuit affirms invalidity

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NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. The only recorded assignment (Reel 64686/0603) runs to the original operating assignee, Netlist, Inc. There is no transfer to any "IP / Holdings / Licensing / Ventures" entity, no registered-agent address, and no single-purpose LLC anywhere in the chain. The patent has never left Netlist.

2. Known asserter in the chain — NOT PRESENT (for the listed lists). No assignee in the chain matches Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, or a Spangenberg vehicle. Important precision point: the Google Patents page annotates IPR2022-00639 and IPR2023-00204 as sourced from "Unified Patents PTAB Data" — that is a database attribution, not petitioner attribution. The actual petitioner in IPR2022-00639 was Samsung Electronics Co., Ltd. (filed 2022-03-02), with Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC joined. I found no Unified Patents or RPX ownership interest. Netlist itself is a frequent plaintiff, so it may appear on plaintiff-frequency databases, but it is a public operating company, not an anonymous assertion vehicle.

3. Repeat correspondent across the chain — UNCLEAR. With only one recorded link, "recurrence" is structurally impossible to demonstrate, and the correspondent name on that single link was not retrievable. A single appearance would not be a finding in any event. This signal cannot be scored.

4. Cascading transfers — NOT PRESENT. One assignment in 14 years, between two parties who were already in an employer/employee relationship. No chained LLCs, no common-principal clustering, no sub-24-month cascade.

5. Pre-litigation transfer — NOT PRESENT (and the facts run the other way). The instrument was executed 2010-08-30 — roughly 11 years before the first '339 suit (Netlist v. Samsung, 2:21-cv-00463, filed 2021-12-20) — and recorded 2023-08-23, i.e. ~20 months after suit commenced and about two months before the 2023-10-18 final written decision in IPR2022-00639. This is a post-filing confirmatory record to tidy the chain of title for standing, not a pre-suit transfer arranged to set venue or manufacture a clean plaintiff.

6. Bankruptcy fire-sale — NOT PRESENT. No Chapter 7/11 proceeding, no §363 sale, no stalking-horse or credit-bid assignment involving Netlist or the '339. Netlist is an ongoing, publicly listed concern.

7. Privateering — NOT PRESENT. The patent is asserted by its owner, in the owner's own name, against direct competitors in the owner's market (Samsung, Micron, and — in the parallel ITC actions and consolidated EDTX cases — SK hynix and, in Inv. No. 337-TA-2025 filing, Google and Super Micro). Patent Owner identified itself as the sole real party in interest in IPR2022-00639. There is no proxy NPE asserting on Netlist's behalf and no evidence of a behind-the-scenes funder.

8. Defensive aggregator (anti-NPE) — NOT PRESENT. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at Netlist.

Adverse development worth recording: on 2023-10-18 the PTAB found all challenged claims 1–35 unpatentable as obvious over Ellsberry in view of Halbert (IPR2022-00639, Paper 45); rehearing was denied 2024-02-09 (Paper 48); and the Federal Circuit affirmed on 2026-09-02 in Netlist, Inc. v. Micron Technology, Inc., No. 2024-1707 (precedential). A companion IPR2023-00204 is also listed on this patent's page. Whatever the ownership posture, the asserted claims of the '339 have been invalidated — the asset is effectively spent.

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Verdict

Operating-company assertion.

The chain is a single confirmatory instrument — Reel 64686/0603, executed 2010-08-30, recorded 2023-08-23 — running from inventors Lee and Bhakta to Netlist, Inc., the company that already owned the patent and that appears as assignee on the face of US 10,949,339. There is no transfer to a licensing entity, no anonymous LLC, no bankruptcy sale, and no defensive aggregator; Netlist has asserted the patent in its own name against genuine competitors (Samsung in E.D. Tex. 2:21-cv-00463, filed 2021-12-20; Micron in 2:22-cv-00203) and, as Patent Owner, identified itself as the sole real party in interest in IPR2022-00639. Two caveats keep this from being a clean bill of health: Netlist is now litigation-revenue dependent with a shrinking product business, and the patent it is asserting was held unpatentable (PTAB 2023-10-18; Fed. Cir. affirmed 2026-09-02), so the patent is no longer a live assertion asset.

Verify at: USPTO Assignment Center — search patent 10949339 (also indexed at assignment.uspto.gov)

Errors and omissions to correct if you have Assignment Center access: (a) the correspondent of record on Reel 64686/0603; (b) confirmation that no security-agreement or license recording exists for this patent; (c) the exact reel/frame string formatting (64686/603 vs. 64686/0603) as USPTO renders it.

I'll research US patent 10949339 and its cited prior art. Let me search for authoritative information.

Let me get the specific cited references from the patent's front page and the related IPR proceedings.

Let me get the patent's own front-page cited references and the specific IPR ground details.

Prior Art Analysis — US 10,949,339 B2

0. Important methodological note (read first)

I must be transparent about two things before the analysis:

1. I could not directly query the USPTO PatentCenter / Patent Full-Text (PatFT) or the USPTO's own citation database in this session. The reference list below is reconstructed from (a) the patent's own Google Patents record and front-page "(56) References Cited" OCR, (b) the exhibit list of IPR2022-00639 and the Final Written Decision, and (c) the related litigation records. Where a citation comes from OCR of a scanned front page, I flag it.

2. The user's framing asks which claims each reference "potentially anticipates under 35 U.S.C. § 102." In the actual Office practice, no reference was applied as a § 102 anticipation rejection. The prior art was applied under § 103 (obviousness), and the PTAB's final decision (affirmed by the Federal Circuit on Sept. 2, 2026, Netlist v. Micron, No. 2024-1707) held all challenged claims unpatentable as obvious. I will therefore state, for each reference, whether it was the primary reference (i.e., closest to a § 102-type single-reference showing) or a secondary reference, and note the actual statutory ground. I will not fabricate a § 102 rejection that does not exist in the record.

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1. Patent identification (verified literally, no auto-correction)

Source: https://patents.google.com/patent/US10949339/en

The patent claims a memory module with DDR DRAM devices in multiple N-bit-wide ranks, a module controller that registers address/control signals and emits module control signals, and a plurality of byte-wise buffers having byte-wise data paths (with tristate buffers) that are enabled "in accordance with a latency parameter" for a "first time period" to actively drive write data. See claim 1 limitations [1pre], [1a]–[1f].

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2. The most relevant prior art (the IPR2022-00639 references)

These are by far the most relevant cited references, because they were the only references on which claims 1–35 were actually adjudicated unpatentable.

2.1 — PRIMARY REFERENCE — Ellsberry

• Full citation: U.S. Patent Application Publication No. 2006/0277355 A1, "Capacity-Expanding Memory Device," Ellsberry et al. (Ex. 1005 in IPR2022-00639).
• Publication date: December 7, 2006 (published ~2006).
• Filing/priority: 2005 application (pre-dates the July 16, 2009 priority date by ~3 years).
• Brief description: A memory module that expands addressable memory banks using "memory bank switch" ASICs interposed between the system memory bus and multiple physical banks of DRAM. The switch ASIC receives address/command via a control bus, contains Port A / Port B outputs with bidirectional signal drivers (402/404), and stores Posted-CAS (AL) latency bits in the switch during initialization to control timing of data-path enablement. Data buses 230/232 are byte wide.
• § 102 / § 103 status: Applied as the primary reference, and the Petitioner's Ground 1 was that Ellsberry alone discloses every limitation of claims 1–35 (i.e., the closest thing in the record to a single-reference § 102 anticipation). The Board found "Ellsberry alone or in combination with Halbert … teaches enabling and disabling data paths through the data buffer." The Federal Circuit affirmed (latency parameter satisfied by Ellsberry's Posted-CAS bits; Ports A/B held to be within the switch ASIC).
• Claims it bears on: claim 1 (all limitations [1pre]–[1f]), and dependents 2–35 (the Board walked claim-by-claim through 4–10 etc.). This is the single most relevant reference.

2.2 — SECONDARY REFERENCE — Halbert

• Full citation: U.S. Patent No. 7,024,518 B2, Halbert et al. (Ex. 1006) — memory-module architecture with a module controller and data interface circuit (the "dual-port buffer-to-memory interface" family).
• Issue date: April 4, 2006 (filed in the 1998/2000 priority chain; well before the 2009 priority date).
• Brief description: Memory module 100 with module controller 110 and data interface circuit 120. Data interface circuit 120 provides m-bit-wide data transfers between the module and the system memory data bus, and R×m-bit-wide data transfers between the interface circuit and the memory device array. Includes bidirectional buffer 122, MUX/DeMUX 124, data registers 126/128 for ranks 140/142, and tristate buffers 122, 126, 128 that enable/disable data paths between the system bus and the memory bus (4:49–5:14, Fig. 4).
• § 102 / § 103 status: Used as the secondary/"teaching" reference supplying the tristate buffer limitation [1f] (and supporting [1e]) that was the point of novelty Netlist argued. The Board and CAFC relied on Ellsberry+Halbert as an alternative basis for enabling/disabling data paths.
• Claims it bears on: claim 1 [1e], [1f], and dependent claims generally, in combination with Ellsberry.

2.3 — Amidi

• Full citation: U.S. Patent Application Publication No. 2006/0117152 A1, Amidi et al. (Ex. 1007).
• Publication date: June 1, 2006.
• Brief description: Memory module 400 with four ranks of DRAM 404 and a CPLD 410 that emulates a two-rank module by combining chip-select signals CS0/CS1 with a high-order address bit Add(n) to select one of four ranks during read/write. Relevant to rank-select / rank-multiplication and the "only one rank selected" limitation.
• § 102 / § 103 status: Secondary reference on the rank-count/rank-select aspects (used in the parallel IPR2018-00364/00365 on the sibling '907 patent). Bears on claim 1 [1pre]/[1a] and claims reciting multiple ranks / rank-select signals (e.g., claim 8).

2.4 — Solomon

• Full citation: U.S. Patent Application Publication No. 2006/0262586 A1, Solomon et al. (Ex. 1008). Also issued as US 7,532,537 B2 (Ex. 1014) and US 7,289,386 B2 (Ex. 1013) — both assigned to Netlist and expressly incorporated by reference in the '339 specification.
• Publication date (pub.): November 23, 2006; US 7,532,537 issued May 12, 2009; US 7,289,386 issued October 30, 2007.
• Brief description: "Memory module with a circuit providing load isolation and memory domain translation" — the foundational Netlist load-reduction/decoder work on which the '339 specification itself relies (see the '339 patent's incorporation of US 7,289,386 and US 7,532,537). Relevant to the load-isolation concept and the module controller / registered control architecture.
• § 102 / § 103 status: These are Netlist's own earlier patents; the '339 specification cites them as background, and in the IPR the '537 patent was invoked by the Petitioner in Reply (Netlist objected that this was improper "AAPA" sandbagging; the CAFC found any error harmless because the Board had an independent Ellsberry-only finding).
• Claims it bears on: The module controller / load-isolation limitations of claim 1 broadly; recited as prior art, not as an anticipation rejection.

2.5 — Rajan

• Full citation: U.S. Patent No. 8,130,560 B2, Rajan et al. (Ex. 1019).
• Issue date: March 6, 2012.
• Brief description: Memory buffer/hub device and data-path architecture for buffered DIMMs. Relevant to buffering and rank selection.
• § 102 / § 103 status: Secondary reference; no standalone anticipation.

2.6 — Leung

• Full citation: U.S. Patent No. 5,784,705, Leung (Ex. 1020).
• Issue date: July 21, 1998.
• Brief description: Memory-module control/address circuitry.
• § 102 / § 103 status: Secondary reference; supports the general module-control/registration concepts.

2.7 — Wu

• Full citation: U.S. Patent Application Publication No. 2009/0248969 A1, Wu et al. (Ex. 1021).
• Publication date: October 1, 2009.
• Brief description: Memory module / buffer arrangement.
• § 102 / § 103 status: Secondary reference. (Note: its October 2009 publication is after the July 16, 2009 § 102(b) date; it could only be relied on under § 102(a)/(e) as of an earlier effective filing—flag for date-sensitivity.)

2.8 — JEDEC standards (printed publications)

• JESD79 — DDR SDRAM Specification (June 2000) (Ex. 1009)
• JESD21-C — DDR SDRAM Registered DIMM Design Specification (Jan. 2002) (Ex. 1010)
• JESD79-2B — DDR2 SDRAM Specification (Jan. 2005) (Ex. 1011)
• § 102 / § 103 status: Used to establish the "latency parameter" / Posted-CAS concept as known art (supports the [1e] "in accordance with a latency parameter" limitation). Secondary/evidentiary.

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3. Front-page U.S. patent citations (patent's own "(56) References Cited")

The '339 patent's front page lists a long block of U.S. patent documents. These are front-page citations only; none was the basis of the § 103 holding. The earliest-listed entries (OCR-provisional) include:

US 4,249,253 (Gentili, 2/1981); US 4,571,676 (Mantellina, 2/1986); US 4,592,011 (Mantellina, 5/1986); US 4,739,473 (Ng, 4/1988); US 5,060,188 (Zulian, 10/1991); US 5,313,624 (Harriman, 5/1994); US 5,345,412 (Shiratsuchi, 9/1994); US 5,513,135 (Dell, 4/1996); US 5,532,954 (Bechtolsheim, 7/1996); US 5,537,584 (Miyai, 7/1996); US 5,541,448 (Carpenter, 8/1996); US 5,572,691 (Koudmani, 11/1996); US 5,617,559 (Le, 4/1997); US 5,630,096 (Zurawler, 5/1997); US 5,649,159 (Le, 7/1997); US 5,655,113 (Leung, 8/1997); US 5,717,851 (Yishay, 2/1998); US 5,724,064 (Moyer, 3/1998); US 5,729,716 (Lee, 5/1998); US 5,784,705 (Leung, 7/1998); US 5,802,541 (Reed, 9/1998); US 5,905,401 (Sher, 5/1999); RE39,629 (Cady, 6/1999); US 5,953,280 (Matsui, 9/1999); US 5,973,392 (Senba, 10/1999); US 6,011,710 (Wiegers, 1/2000); US 6,061,754 (Cepulis, 5/2000); US 6,070,217 (Connolly, 5/2000); US 6,141,245 (Bertin, 10/2000); US 6,173,357 (Ju, 1/2001); US 6,188,641 (Uchida, 2/2001); US 6,205,516 (Usami, 3/2001); US 6,223,629 (Stuck, 3/2001) — and continuing through the 2000s.

Also cited among the U.S. patent-document references are US 2006/0117152 A1 (Amidi, 6/2006), US 2006/0262586 A1 (Solomon, 11/2006), and US 2006/0277355 A1 (Ellsberry, 12/2006).

Caveat: the numbers/dates immediately above are from OCR of a scanned front page and exhibit copies; I did not verify each against the USPTO database. Treat individual entries as provisional unless corroborated.

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4. Which reference anticipates which claims — honest assessment

Bottom line: The single most relevant reference is Ellsberry (US 2006/0277355 A1) — it was the primary reference on which every one of claims 1–35 was ultimately held unpatentable, with Halbert (US 7,024,518 B2) supplying the tristate-buffer limitation. No claim was invalidated by these references under § 102; the operative statutory basis was § 103 obviousness, affirmed by the Federal Circuit on September 2, 2026.

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5. Litigation / validity context (relevant to "most relevant prior art")

• IPR2022-00639 (Samsung / Micron v. Netlist) — FWD held claims 1–35 unpatentable (obvious over Ellsberry and/or Halbert); rehearing denied Feb. 9, 2024.
• IPR2023-00204 — separate Micron petition (single ground: Ellsberry + Halbert).
• Fed. Cir. No. 2024-1707 — Netlist, Inc. v. Micron Technology, Inc., precedential opinion Sept. 2, 2026: affirmed the Board. https://www.cafc.uscourts.gov/opinions-orders/24-1707.OPINION.9-2-2026_2749527.pdf
• Related sibling-patent IPRs: IPR2018-00362/-00363 (Ellsberry-based) and IPR2018-00364/-00365 (Halbert+Amidi-based) against US 9,606,907 — the same Ellsberry reference that the Board previously held disclosed the '907 limitations.

Primary URLs used:

• Patent: https://patents.google.com/patent/US10949339/en
• Petition/exhibits (IPR2022-00639): https://www.docketalarm.com/cases/PTAB/IPR2022-00639/Samsung_Electronics_Co._Ltd/docs/03-02-2022-Petitioner/Petition-1-Petition_for_IPR_of_USP_10,949,339.pdf
• FWD / rehearing denial exhibit: https://www.docketalarm.com/cases/PTAB/IPR2023-00455/Samsung_Electronics_Co._Ltd._v._Netlist_Inc/docs/03-09-2024-Petitioner/Exhibit-1108-IPR2022_00639_denial_of_rehearing_339_patent.pdf
• CAFC opinion: https://www.cafc.uscourts.gov/opinions-orders/24-1707.OPINION.9-2-2026_2749527.pdf

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Confidence and gaps

• High confidence: patent identification, claim set, priority chain, the Ellsberry/Halbert IPR grounds, and the § 103 (not § 102) basis and CAFC affirmance.
• Medium confidence: exact publication dates for the front-page U.S. patents (OCR-derived).
• Acknowledged gap: I could not run a live USPTO PatentCenter/PatFT "References Cited" query in this session, so the front-page list should be re-verified against the USPTO record before being treated as exhaustive. I have not fabricated any citation to fill that gap.

I'll ground the obviousness analysis in the actual prior-art references from the record before drafting.

Obviousness Analysis — U.S. Patent No. 10,949,339 B2 under 35 U.S.C. § 103

Building on the claim map, claim-construction note, and PTAB/CAFC posture established in the two prior sections. This section does not restate them; where I disagree with or must qualify them, I flag it inline.

Carry-forward date caveat (one line only): the prompt's operative date is April 26, 2026, but the record I retrieved includes, and this analysis relies on, the Federal Circuit's September 2, 2026 opinion in No. 2024-1707. If April 2026 is truly operative, then the analysis below describes the predicted/argued posture as it stood at the PTAB rather than the affirmed posture. Either way, the substantive § 103 grounds do not change — only their procedural finality does.

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1. Governing framework

Because the '339 patent claims priority to July 16, 2009 — before March 16, 2013 — pre-AIA 35 U.S.C. § 103(a) governs. The inquiry follows Graham v. John Deere, 383 U.S. 1 (1966), as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007):

1. Determine the scope and content of the prior art;
2. Ascertain the differences between the prior art and the claims;
3. Resolve the level of ordinary skill in the art; and
4. Evaluate secondary considerations (objective indicia) if timely proffered with nexus.

Two KSR principles drive the outcome here:

• Predictable substitution of known elements. "When a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable result." KSR, 550 U.S. at 416. A tristate buffer with an enable pin is the paradigm of such a known element.
• Motivation may come from the problem to be solved. The reference need not disclose the claimed combination; it need only supply "a reason . . . to modify" drawn from "the background knowledge, the laws of nature, or the ordinary creativity of a skilled artisan." Here the "reason" is documented in the references themselves — bus conflict avoidance, load reduction, and power saving.

The § 103 analysis and the § 112/claim-construction analysis are separate but interact: the E.D. Tex. "fork-in-the-road" construction of drive/actively drive ("enabling only one of the data paths while the other possible paths are disabled") narrows the claim. Narrowing helps the challenger, because Ellsberry's express "one-port-disabled" embodiment maps onto it directly (see § 5(a) below).

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2. Level of ordinary skill in the art (POSITA)

The record is consistent across the PTAB petitions: a POSITA would hold a bachelor's degree in electrical engineering, computer engineering, or computer science (or equivalent), with roughly 3–5 years of experience in computer memory system or memory module design, including DDR SDRAM signaling, JEDEC module standards, and PCB-level signal integrity — or a master's degree with fewer years.

Two consequences:

• JEDEC JESD79-x (DDR/DDR2) and JESD21-C (module form factors), and the concept of Posted CAS / additive latency (AL) and CAS latency (CL) as mode-register-programmable timings, are background knowledge chargeable to the POSITA. That is precisely how the Board treated the "latency parameter" limitation.
• Replacing a pair of ordinary (non-tristating) bidirectional drivers in an ASIC with tristate bidirectional drivers is, at this skill level, a routine design choice, not an inventive leap.

Note on the record's use of Netlist's own U.S. Pat. No. 7,532,537 as evidence of POSITA knowledge: this is a legitimate use of a patent-as-publication (it is § 102(b) prior art in its own right and also evidence of what skilled artisans knew), and the Board used it only to corroborate what a POSITA would have understood about Accounting for buffer propagation delay via a latency parameter. The Federal Circuit held any error in that specific reliance harmless, because Ellsberry's own Figure 9 / ¶ [0044] disclosure ("if cl_mode = subtract; cl = cl − 1") independently evidences the practice.

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3. Scope and content of the prior art

3.1 Ellsberry — U.S. Pub. No. 2006/0277355 A1 ("Capacity-Expanding Memory Device")

https://patents.google.com/patent/US20060277355A1/en (published Dec. 7, 2006; filed June 1, 2005) — § 102(b) prior art.

Relevant disclosures, pinned to paragraphs/figures:

3.2 Halbert — U.S. Pat. No. 7,024,518 B2 ("Memory buffer with programmable computer bus connection" / buffered module)

https://patents.google.com/patent/US7024518B2/en (issued Apr. 4, 2006) — § 102(b) prior art. IPC G06F 13/1689, class 711/101.

3.3 Secondary/backup references appearing in the same family of IPRs

These are not the primary § 103 ground for the '339 patent, but they are on the record and usable for dependent claims or as alternative grounds: Perego (buffered module with rank multiplication), Amidi (rank multiplication via CPLD/address decoding, CPLD 410 determines which rank… to activate based upon the address and command signals), Ruckerbauer, and Netlist's own U.S. 7,289,386 and U.S. 7,532,537 (the latter, https://patents.google.com/patent/US7532537B2/en).

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4. The differences: what the '339 claims add over Ellsberry alone

Ellsberry alone supplies: module-mounted controller, capacity expansion, ports A/B, byte-wide module data lines, bidirectional drivers, and a latency parameter. The genuine additions in the granted claims are:

1. DDR DRAM devices arranged in multiple N-bit-wide ranks substantially identical to Ellsberry's DDR A / DDR B bank groups, but framed at rank granularity.
2. "First tristate buffers" in the byte-wise data path, enabled for a first time period to drive the byte-wise write data (claims 1/11/27).
3. Read-direction tristate/input buffers with mutual exclusion between write and read periods (claims 19, 27, 28).
4. "Disabled between" the first and second operations (claim 19).
5. Timing "in accordance with a latency parameter" (claims 1, 19/21, 27/34–35).
6. In claim 11, 4-bit-wide DRAMs used in pairs, with first/second subsets of the tristate buffers driving first and second nibbles.

Every one of items 1–5 is either disclosed by Ellsberry or supplied by Halbert's tristate buffers, or is a predictable design alternative within the POSITA's ordinary skill.

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5. Primary ground: Ellsberry in view of Halbert

5(a) Claim 1 (representative of claims 1 and 8–10)

Critical point on [1e]: the "latency parameter" limitation is the one Netlist most strenuously contested. It fails because Ellsberry stores "Posted CAS_n" in the bank switch and Figure 8B's note "if cl_mode = subtract; cl = cl − 1" expressly shows the module adjusting the latency presented to the DRAMs to compensate for a one-clock buffer delay. That is met either as disclosure or as an obvious implementation given JEDEC MRS/EMRS practice.

5(b) Claim 11 — "data transmission circuit" variant with paired 4-bit DRAMs and nibble splitting

• "Data transmission circuit" is the specification's own synonym for the same buffer (each data transmission circuit 416 comprises or functions as a byte-wise buffer, and FIGS. 4A/4B describe an 8-bit circuit feeding two 4-bit devices). Claim 11 is therefore the same subject matter, re-labelled — and Ellsberry's Fig. 2 explicitly shows a byte (Byte 0) split across DQ(7:0) with two nibble-level sub-buses, previewing the "first nibble / second nibble" split.
• The 8-bit-buffer-to-two-4-bit-DRAM relationship is exactly the arrangement the '339 specification itself presents as a design choice (FIG. 4B), and the record's JEDEC/DRAM density evidence (Perego/Amidi) confirms that pairing narrower devices to emulate a wider one was conventional.
• Conclusion: obvious over Ellsberry + Halbert, and further supported by Perego/Amidi if narrower devices are treated as a claim-11 requirement.

5(c) Claim 19 (and claim 21) — successive operations, read data driven second side → first side, with the path disabled between the two periods

• Ellsberry's drivers 402/404 are bidirectional by name and by the "read/write logic unit 406" (¶ [0045]); the read direction is inherent. Halbert supplies the read-side gating (RDQS/REG_SEL, FIG. 5) and, importantly, the disable interval: FIG. 6 shows the internal busses actively driven only for the duration of the burst.
• The "disabled between the first and second time periods" limitation is met by the natural consequence of tristate/one-port-disabled operation: a tristate driver is in high-Z between enables. The PTAB credited the petitioner's argument that "a POSITA would have understood from Ellsberry and Halbert that data bursts… are actively driven on the data path only during the duration of the burst, and the tristate drivers… are disabled (put into a high impedance state) between two such bursts."
• Claim 21's "latency parameter" adds nothing beyond § 5(a).
• Conclusion: obvious.

5(d) Claim 27 (and claims 28, 34, 35) — dual tristate sets, write and read

• Halbert's FIG. 4 is the cleanest mapping: one set of (write-direction) tristate buffers gates data toward the ranks; a second set (read-direction buffer 122 / registers 126, 128) gates data back toward the controller. Because they are tristate, mutual exclusion is inherent to correct bus operation — enabling both would create the very bus conflict § 6(a) says the POSITA wanted to avoid.
• Claim 28 ("both sets disabled when the module is not targeted") maps to Halbert's "otherwise, the modules remain in a standby mode" (col. 7:54–61) and to high-Z default state.
• Note the claim-27 drafting quirk "n-bit-wise" data buffers (not "byte-wise"). That broadening does not help patentability — if anything it widens the claim into still more squarely-read-upon prior art.
• Conclusion: obvious.

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6. Why the POSITA would have been motivated to combine (the KSR articulation)

Each motivation below is grounded in the references themselves, not in hindsight:

1. Eliminating bus conflicts on bidirectional data lines. Halbert's tristate/high-Z operation isolates loads so that only the selected device drives. Ellsberry's bidirectional buses 230/234/236 are exactly the environment where this matters. The Board found "sufficient evidence that bidirectional tristate buffers would be effective in eliminating bus conflicts if driven appropriately by a controller" (see the E.D. Tex. exhibit at https://archive.org/download/gov.uscourts.txed.211544/gov.uscourts.txed.211544.454.1.pdf).
2. Presenting a single load to the system memory controller. Ellsberry's own stated object is that the switch presents "a single load to the bus, not the load of the individual memory devices" (¶ [0011]); adding Halbert's bidirectional buffer at the module/system interface and implementing drivers 402/404 as tristate devices extends that benefit to the system data bus 230. This is the same problem the '339 patent addresses — the answer is not novel, only the drafting is.
3. Power savings. High-Z states draw no drive current; the record establishes that buffers left enabled needlessly dissipate significant energy. This is a recognized, articulable motivation and was accepted by the Board and the Federal Circuit.
4. Signal regeneration / signal integrity. Halbert's buffers regenerate and reshape read and write data; Ellsberry's drivers amplify/reshape read data and reduce RC loading (¶ [0031]). Combining them improves waveform fidelity at DDR/DDR2 rates.
5. JEDEC timing compatibility via the latency parameter. Both references operate in the JEDEC DDR world; Ellsberry's Posted-CAS/EMRS handling and Halbert's matching of the controller's CAS latency show that the POSITA would use the existing latency parameter (CL/AL) — and the burst length — to time the buffer's enablement, rather than invent a new one. The '339 claims' "latency parameter" recites an existing, standardized parameter; using it to gate a buffer is the predictable design.
6. Integration/feasibility. Ellsberry already teaches putting control system 300 and switch ASIC 400 on the same die (¶ [0045]) — so the POSITA would expect implementation to be straightforward.
7. Yield/capacity economics. Ellsberry exists to raise module density with smaller devices; adding rank-selective tristate buffering furthers that objective. (See Perego/Amidi for the family-wide version of this rationale.)

Reasonable expectation of success: every added element — tristate buffer, enable logic, latency counter, rank decode — was known, commercially available, and used in memory modules of the day. KSR: "combining familiar elements according to known methods to yield predictable results." The Board expressly so held, and the Federal Circuit affirmed on substantial-evidence review.

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7. Netlist's counter-arguments, and why they fail

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8. Secondary considerations (objective indicia)

No objective indicia with the required nexus appear to have been established on this record:

• No unexpected results: the benefits claimed (lower load, fewer bus conflicts, power savings, signal regeneration) are precisely the expected consequences of tristate buffering and were articulated as motivations. Under KSR/MPEP 716.02, a result that is the natural and expected product of the combination cannot rebut obviousness.
• No long-felt need with nexus to the claimed combination rather than to Netlist's broader LRDIMM product line; the commercial-success evidence, to the extent any exists, is not tied to the specific ordered combination of Ellsberry + Halbert beyond what those references already teach.
• No teaching away, for the reasons in § 7.
• Copying/licensing: the Samsung settlement and the Micron license are as consistent with litigation-risk economics and portfolio-wide settlement as with deference to the '339 claims specifically; absent a nexus showing, this is not probative.

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9. Dependent claims

The dependent claims do not save the independent claims, because each adds only conventional structure or timing:

• Claim 2 (nibble splitting across a pair of DRAMs) — Ellsberry Fig. 2's DQ(7:0) / Byte 0 split with DQS A0/B0; conventional DRAM organization.
• Claim 3 (write buffer before the tristate buffers) — Ellsberry's drivers + Halbert's bidirectional buffer 122 in the write direction.
• Claim 4 and the buffer-loading dependents — the specification itself concedes these buffers are "comparable to an input/output buffer on one of the memory devices," i.e., the prior art's own loading model.
• Claim 21 (latency timing of both periods) — § 5(c).
• Claims 25–26 (first input buffer + second buffer for each bit) — mapping shown in the petitioner's claim chart: read tristate buffer in drivers 402/404 + additional read buffer interfacing system bus 230.
• Claim 28 (both sets disabled when not targeted) — Halbert's standby mode (col. 7:54–61).
• Claims 34–35 (latency parameter for each set) — § 5(a).

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10. Alternative and fallback grounds (for completeness / robustness)

1. Ellsberry alone — the FWD found claim 1 unpatentable "over Ellsberry alone or in combination with Halbert," meaning the Board considered Ellsberry self-sufficient for at least some limitations (particularly [1e]). If Ellsberry's ASIC-integrated switching is read broadly, several claims are obvious over Ellsberry alone.
2. Ellsberry + Halbert + Perego/Amidi — if narrower DRAMs or rank multiplication are treated as required (relevant to claims 11 and any 4-bit-device-dependent claims), Perego and Amidi supply lower-capacity/rank-multiplied architectures with express cost/upgrade-flexibility motivations.
3. Ellsberry + Halbert + JEDEC JESD79-x/JESD21-C — the latency, burst-length, and chip-select conventions recited by the claims are standardized, i.e., printed publications evidencing ordinary skill.
4. Ellsberry + Halbert + Netlist's own U.S. 7,289,386 / 7,532,537 — usable as prior art publications and as admissions of what the field knew about latency-tuned buffered modules.

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11. Conclusion

Under Graham/KSR:

• Scope/content: Ellsberry discloses near-verbatim the '339's module architecture (module-mounted registering controller, rank/bank-dependent module control signals, byte-wide bidirectional module data lines, latency-parameter timing, single-load objective). Halbert discloses the missing hardware element — tristate bidirectional buffers with enable logic gating the data paths for the burst duration.
• Differences: narrow and mechanical; the tristate limitation and the "latency parameter" limitation (both added during prosecution) are each anticipated or obvious.
• Motivation: documented in the references themselves (bus-conflict elimination, single-load reduction, power saving, signal regeneration) with a reasonable expectation of success.
• Indicia: none with nexus.

Result: Claims 1–35 of U.S. 10,949,339 B2 are obvious under pre-AIA § 103(a) over Ellsberry (US 2006/0277355 A1) in view of Halbert (US 7,024,518 B2). This is the ground the PTAB adopted in IPR2022-00639 and IPR2023-00204, and — subject to the date caveat carried forward from the prior sections — the ground the Federal Circuit affirmed on September 2, 2026 in Netlist, Inc. v. Micron Technology, Inc., No. 2024-1707 (https://www.cafc.uscourts.gov/opinions-orders/24-1707.OPINION.9-2-2026_2749527.pdf).

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12. Residual uncertainty (stated explicitly)

• I have not independently retrieved the full verbatim text of claims 11, 19, and 27 in a single source; the element mappings for those claims are reconstructed from PTAB petition excerpts and the FWD, and paragraph citations (~23:29–24:29; ~25:29–26:31) are approximate, consistent with the caveat in the prior "Patent summary" section.
• The Federal Circuit opinion text I relied on is from the petitioner/Board excerpts returned by search and the secondary summaries cited; I did not open the full 24-1707 PDF. The holdings summarized (latency parameter, "enabling a data path," APA/harmless error) are corroborated across two independent sources.
• Whether claim 11's "n-bit-wide" / 4-bit paired-DRAM limitations are expressly disclosed versus obvious is the weakest link in the ground; if a fact-finder required literal disclosure of paired 4-bit devices, the Perego/Amidi fallback (§ 10(2)) becomes load-bearing.
• The date discrepancy flagged in both prior sections remains unresolved and is material only to the finality of the invalidation, not to the merits of the § 103 ground.