US 10431282

I'll search for information on this specific patent number.

No CAFC or litigation hits yet. Let me confirm with targeted searches for claims and any litigation.

Let me pin down the independent claims precisely.

US Patent 10,431,282 — Analyst Summary

Bottom line: I found no CAFC 2026 docket entry, no district-court docket, and no PTAB (IPR/PGR) proceeding naming US 10,431,282. My searches were web-level (Google Patents, Justia, PTAB/CAFC listings, litigation news); they are not a substitute for a PACER/PTAB docket query, so treat "no litigation found" as absence of evidence rather than proof. Nothing in the results contradicted the bibliographic data below.

Bibliographic data (from the patent text you supplied, plus corroborating Google Patents)

Do not conflate: US 10,431,281 B1, "Inverting array data bits" (filed 2018-08-17, granted 2019-10-01, Micron) is a different, similarly numbered patent that appears in the same search results. The result listing "Patents Assigned to Microns Technology, Inc." is a different (misspelled) assignee entity and is not this patent.

Abstract

The patent text you supplied does not include the verbatim abstract, and I do not want to reproduce one from memory. Paraphrase (flagged as non-verbatim): the disclosure relates to maintaining performance of ferroelectric memory cells that store a logic value for extended periods, by periodically re-writing a cell with the inverted logic state while still reading back the intended logic state, using two sets of transistors ("true" and "inverting") around the sense component so the sense amplifier itself need not invert its output, and using a counter to track which addresses hold inverted data. Uncertainty noted — treat the wording above as a summary, not a quotation.

Plain-language overview of the independent claims

The claim set is a set of method claims (no apparatus/system claim is visible in the retrieved claim text). From the claim text retrieved, the independent claims are, in substance:

Independent claim 1 — read/write-through-different-transistor-sets method. A method that includes reading a first logic state stored in a memory cell through a first set of transistors that couples the cell to a sense component, and then writing a second, different logic state into the same cell through a second (different) set of transistors that also couples the sense component to the cell. Plainly: you read via one wiring path and write back the opposite value via the other wiring path, so the bit physically flips. (I could not retrieve claim 1's exact wording with confidence — see uncertainty note below.)

Independent claim 2 (as published) — sense-then-apply-inverted-output method. "Sensing, by a sense component through a first set of transistors, a first logic value stored at a memory cell; and applying an output of the sense component to the memory cell through a second set of transistors different than the first set of transistors, the output corresponding to the first logic value, wherein a second logic value different than the first logic value is stored at the memory cell based at least in part on the applying." Plainly: the sense amp's output is routed to the cell through the opposite input/output path, so applying the sensed value actually stores the complement.

Independent claim (determining original vs. inverted state). "Determining whether a memory cell is in an original state or an inverted state; selecting either a first set of transistors or a second set of transistors based at least in part on the determining; and accessing the memory cell through the selected set." Plainly: decide whether the cell currently holds the true or flipped bit, then pick the matching transistor path for the access.

Independent claim (counter/comparison-based accessing). A method of comparing a counter value with a value associated with a first address of a set of memory cells (the counter value being associated with a second address), and reading the logic states using either the first set or the second set of transistors based on that comparison — i.e., the counter acts as the "flip boundary" marker so the controller knows which pages/addresses have already been inverted.

Dependent claims add, e.g.: activating the first set before sensing; transferring cell charge to the digit line; virtual-ground/word-line/plate-line biasing sequence; isolating the sense component before sensing; the specific cross-wiring of the first/second transistor sets between the two sense-amp inputs and the digit line/reference line; comparing the two sense-amp input voltages; flipping/write-back operations and reading the intended value back; setting a per-cell indicator after a flipping operation; and incrementing/updating a counter after a flipping operation.

Uncertainty and method caveats

1. Claim 1 exact wording is not confirmed. My retrieved claim listings appear internally offset by one (a Justia rendering began at claim 2; a Google Patents rendering of what should be claim 4 displayed claim-5 language). I therefore describe the independent claims by subject matter and flag claim 1's precise language as unverified. For a filing or litigation purpose, pull the claims from the USPTO PatentCenter / official granted-claim text, not from a secondary aggregator.
2. Abstract is a paraphrase, not the authoritative text.
3. Priority date 2016-06-21 is listed by Google Patents as an assumption; the application itself was filed 2018-07-13. Verify any pre-2018 priority document before relying on it.
4. No CAFC 2026 docket, district-court case, or PTAB proceeding tying to 10,431,282 appeared in these searches. The Micron litigation results that did surface concern other patents (Netlist's '087, '366, '912, '417, YMTC's '254/'322, etc.) and should not be attributed to this patent.
5. Earlier-generated sections of this patent analysis should be treated as controlling where they conflict with anything above.

I'll research litigation involving US patent 10431282. Let me run several searches.

Let me search more specifically for litigation asserting this patent.

Let me try more targeted searches on litigation databases.

Summary — Litigation Involving U.S. Patent No. 10,431,282

No litigation specifically asserting U.S. Patent No. 10,431,282 was found in the sources I searched.

I want to be direct about this: I could not identify a single district court complaint, ITC action, CAFC appeal, or PTAB proceeding that names U.S. Patent No. 10,431,282 ("Array data bit inversion," Micron Technology, Inc., filed 2018-07-13, granted 2019-10-01, priority 2016-06-21) as a patent-in-suit. Accordingly, there are no plaintiff/defendant/jurisdiction/case-number/filing-date/status entries to report.

What I searched and what I found

The Micron-related litigation my searches surfaced (e.g., Netlist v. Micron matters in W.D. Tex./E.D. Tex. involving U.S. Patents 8,301,833; 9,824,035; 10,268,608; 10,489,314; 7,619,912; and the YMTC v. Micron matters) asserts different patent numbers and family members. I am expressly not importing those results here, because your instruction was to avoid results for similar-but-different numbers, and none of those patents is U.S. 10,431,282.

Important context and caveats

1. The patent is owned by Micron Technology, Inc. (original and current assignee). It is part of a ferroelectric-memory (FeRAM) family whose later continuations include U.S. 10,748,596; U.S. 11,062,753; and U.S. 11,636,890 (all appearing in the Google Patents "Other versions / Priority to" data). If any family member has been litigated, that would be a lead — but that is a separate patent number and does not, by itself, establish litigation on '282.

2. Absence of evidence is not proof of absence. My search coverage was partial. I could not fully query PACER (paywalled), Docket Navigator, Lex Machina, or the full Unified Patents litigation caselist, and one RPX search was cut off. A definitive "no litigation" conclusion would require checking:

   • PACER / CourtListener RECAP for complaints citing "10,431,282"
   • Docket Navigator or Lex Machina patent case databases
   • USPTO Patent Trial and Appeal Board (PTAB) API for IPR/PGR petitions against the '282 patent
   • The USPTO Patent Assignment / litigation records and Unified Patents litigation portal

3. No PTAB challenge identified either. I did not find any IPR, PGR, or other post-grant proceeding against U.S. 10,431,282.

Bottom line

Based on the searches performed, no known litigation is identified involving U.S. Patent No. 10,431,282. If you need a conclusive negative, I recommend running the exact string "10,431,282" against Docket Navigator, Lex Machina, and the PTAB API, and pulling the patent's "Litigation" tab on the Unified Patents portal — those are the authoritative sources that would reveal any case my web searches may have missed. I should not represent the absence as confirmed without those direct database checks.

I'll verify the structured-data finding with targeted web searches before finalizing.

Confirming no proceedings against the '282 patent or its family members before I finalize.

Proceedings overview

Zero AIA trial proceedings are on file for U.S. Patent No. 10,431,282. The canonical structured source for this exercise — the "PTAB proceedings on file" block sourced from the USPTO Open Data Portal — returns no IPR, no PGR, and no CBM naming this patent, and that null result is corroborated by web searches of PTAB E2E/PTAB Decisions content and Federal Circuit/CourtListener material (searches run 2026-09-29). Breakdown by status is therefore: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0.

Bottom-line defensive posture: this is an untested patent. The '282 patent has never been through an AIA trial, so there is no FWD narrowing or killing any claim, no § 315(e) estoppel against anyone, and no Board claim-construction ruling to borrow for a district court defense. Equally, there is no PTAB win to hide behind — a defendant considering an IPR is the first mover, with a clean slate and no General Plastic/§ 325(d) baggage inherited from a prior petitioner. The whole 20-claim set (see claim text at patents.google.com/patent/US10431282B2) is UNTESTED, not sustained.

No proceedings to report

There is no {PROCEEDING_NUMBER} to populate. I will not manufacture one. For completeness, here is what was checked and what was affirmatively ruled out.

Explicitly excluded as different patents. My searches surfaced a large volume of Micron-side AIA activity — e.g., Netlist v. Micron IPRs on U.S. 9,824,035 (IPR2022-00236), 10,268,608 (IPR2022-00237, IPR2023-00847, IPR2024-00370), 10,489,314 (IPR2022-00744/-00745), 10,860,506 (IPR2023-00205), 10,949,339 (IPR2023-00204), 11,232,054 (IPR2023-00999), 11,016,918 (IPR2023-00996), 8,787,060 (IPR2023-00882), 9,318,160 (IPR2023-00883), 9,858,215/11,093,417 (IPR2023-01141/-01142); and the Micron v. YMTC campaign (e.g., IPR2024-00788 through -00795, -00909, -00911, IPR2025-00034, -00098/-00099, and others). None of these patents is U.S. 10,431,282, and none is in the '282 family. I am not importing any of them.

Statutory posture (why the numbers matter)

• PGR — foreclosed by timing. The '282 patent issued 2019-10-01. The § 321(c) nine-month PGR window closed on 2019-07-01, so no PGR is available to anyone today.
• CBM — unavailable. The claims are directed to ferroelectric memory array circuitry (CPC G11C 11/221, 11/2273, 11/2275), not a "financial product or service," and the transitional CBM program has in any event sunset.
• IPR — fully available to a new petitioner. The '282 patent issued from an application filed 2018-07-13 (continuation of 15/641,020, filed 2017-07-03), with earliest priority 2016-06-21. It is therefore an AIA (first-inventor-to-file) patent, and an IPR petition on § 102/§ 103 grounds over patents and printed publications may be filed at any time — subject only to the § 315(b) one-year bar once a petitioner is served with a complaint alleging infringement.
• No estoppel of any kind attaches. With no FWD, § 315(e)(1) and § 315(e)(2) are inoperative. A defendant is free to raise in district court any prior-art ground, including art it also puts in a petition — and any art it does not.

Consistency check against the earlier sections

No contradiction. The previously generated litigation summary concluded that no litigation asserting the '282 patent was identified; the PTAB null result is consistent with that. Note the logical direction though: the absence of PTAB activity is explained by the absence of assertion. Well-asserted patents in crowded semiconductor fields (as the Netlist and YMTC campaigns show) reliably attract IPRs. A clean PTAB docket here is a signal that the '282 patent has not been materially asserted, not that it has been tested and survived.

Strategic summary

Claim status: 20 claims, 0 canceled, 0 sustained, 20 UNTESTED. The '282 patent carries claims 1–20. Independent claims in this family claim the core "true-transistor / inverting-transistor around a sense component" architecture and the counter-based tracking of inverted addresses (see, e.g., claim 16 at patents.google.com/patent/US10431282B2). Because no tribunal has construed or adjudicated any of them, there is no narrowing, no disclaimer-by-amendment, and no prosecution-history estoppel beyond what the family's own file wrappers create. A defendant gets no free invalidity win and no free claim-construction ruling from the PTAB record — it has to build both from scratch.

Estoppel landscape. Empty. The § 315(e)(2) bar applies only to a petitioner, its RPI, and privies after an FWD. There is no petitioner and no FWD, so there is no class of entities currently barred from raising § 102/§ 103 grounds on this patent. Conversely, a defendant who does file first takes on that risk prospectively: anything it raises or reasonably could have raised in an instituted IPR becomes unavailable in the litigation if the trial reaches an FWD. The tactical consequence of the clean docket is that the first petitioner sets the invalidity narrative — there is no earlier institution decision, no POPR, and no FWD to piggyback on or to be collaterally estopped by.

Pattern signals. No repeat petitioner (none exists). No PTAB appeal pattern — the patent owner has never had occasion to appeal an adverse FWD on '282, so there is no read on how aggressively Micron defends this family at the Board. No defensive aggregator (Unified Patents or similar) appears anywhere in the chain on this patent. The only relevant pattern is family discipline: Micron has kept this line alive through a chain of continuations — 9,715,919 → 10,043,566 → 10,431,282 → 10,748,596 → 11,062,753 → 11,636,890 — and has parallel foreign filings (KR102067365, CN109416921, JP6802401, TW I636457). That is a portfolio-management signal: expect Micron to assert the strongest sibling, not necessarily the '282, and to leverage the family's continuation breadth.

Recommended next steps

If you are a defendant and were hoping for a free kill: there isn't one.

• Do not represent to a court or to your client that any claim of the '282 patent has been invalidated. No claim has been canceled or held unpatentable — there is no FWD to link to, because there is no proceeding.
• Run your own confirmatory negative check before relying on this: PTAB E2E search (ptacts.uspto.gov/ptabweb), the PTAB Decisions page, and CourtListener for "10,431,282" (courtlistener.com/?q=%2210%2C431%2C282%22). Public sources can lag the Office; the ODP null result is the baseline, not necessarily the last word.
• Treat the absence of PTAB history as a first-mover opportunity, not a shield. If you intend to file an IPR, note the § 315(b) clock (one year from service of any complaint alleging infringement of the '282 patent) and the current institution regime — under the October 16, 2025 Squires memorandum, institution decisions are made by the Director, and the October 15, 2025 proposed rules would, if finalized, bar IPRs against patents that already survived a validity challenge or that face an earlier-decided parallel proceeding. Neither bar is triggered here, because the '282 patent has no such history.

If you are the patent owner (Micron) — the '282 patent's exposure is unknown. Its term runs to the anticipated expiration of 2036-06-21, roughly 9.7 years of runway, and the family's continuation chain gives several additional assertion candidates with the same 2016-06-21 priority.

If you are monitoring — the fact pattern to watch is an IPR petition against 10,431,282 (or a sibling such as 10,043,566 / 10,748,596) appearing in PTAB E2E. That filing would be the first concrete evidence that this patent is being asserted, and it would immediately create the claim-level record — institution reasoning, claim constructions, and eventually an FWD — that today simply does not exist.

Caveats on scope: I could not query Docket Navigator or Lex Machina (paywalled) or the full PTAB E2E docket directly; the ODP structured result plus the searches above are the basis for the "no proceedings" finding. AIA trials are public and are indexed promptly, so a long-concealed proceeding is unlikely — but I am not treating the negative as independently confirmed beyond these sources.

I'll research the assignment history for this patent before writing up. Let me run several targeted searches.

Let me dig into the specific assignment records and the Micron security-agreement chain.

Let me try to pin down the exact reel/frame entries and confirm there are no post-issuance ownership transfers.

Assignment / Ownership Reconstruction — U.S. Patent No. 10,431,282

Method note (read first). I could not open Assignment Center directly in this session (tool step limit), so the record below is reconstructed from (a) the Google Patents legal events block for US10431282, and (b) cross-referenced USPTO assignment reels surfaced via Espacenet INPADOC and public copies of Micron's 2016 secured-financing recordings. Two caveats apply throughout: Google's legal-events block does not print reel/frame numbers, and the reel/frame numbers I cite for the blanket Micron security/release records come from sibling Micron patents that share the same recording — I have flagged every such inference rather than presenting it as a direct read of '282's own reel. Nothing below is fabricated; where I could not verify, I say so.

Inventors

Employer basis: The patent issued to Micron as assignee, both inventors reside in Micron's Boise/Meridian, Idaho headquarters area, and their entire visible patent output is Micron-assigned. That is strong circumstantial evidence of Micron employment at filing, but I did not review employment agreements — treat "Micron employee" as a high-confidence inference, not a document-verified fact.

Unusual-pattern check — clean. The classic fire-sale precursor (all inventors departing the original assignee within ~12 months of filing) is not present. Both inventors continued to invent for Micron for years afterward and are co-named on later continuations in this very same family (e.g., US 11,636,890, "Array data bit inversion," naming both). There is no inventor-exodus signal. Likewise there is no sign of the family being "prepped for sale" — it was kept as a live internal continuation chain (US 9,715,919 → 10,431,282 → 10,748,596 → 11,062,753 → 11,636,890) by the operating company.

Original assignee

• Entity: Micron Technology, Inc., Boise, Idaho (Delaware corporation).
• Status: Operating, public (NASDAQ: MU), never acquired, never dissolved, not in bankruptcy. Micron is one of the world's three large DRAM manufacturers and a major NAND producer, with its own fabs (Boise/Manassas/etc.) and multi-billion-dollar annual revenue.
• Does it ship a product embodying the claims? Partially / with a caveat. The claims are directed to array and sense-amplifier circuitry for inverting data bits stored in memory cells — including ferroelectric (FeRAM) cells. Micron is the original assignee and continues to develop FeRAM-adjacent sensing technology, but Micron's shipping revenue products are DRAM/NAND/NOR; a discrete, high-volume FeRAM product line matching this disclosure is not established. So "ships products embodying the claims" is unclear for the FeRAM-specific subject matter.
• Portfolio context: The '282 is a continuation of application 15/188,890 (filed 2016-06-21), which issued as US 9,715,919. The '282 itself issued 2019-10-01 and spawned further continuations (US 10,748,596; 11,062,753; 11,636,890) plus foreign family (JP 6705117 / JP 6802401; TWI675370B). All family members remain Micron-owned.

Assignment timeline

Bottom line up front: there is no ownership assignment of this patent to any third party. The only recorded conveyances are (1) a collateral security interest in favor of a bank acting as collateral agent, and (2) the release of that lien back to Micron. Micron Technology, Inc. is the owner throughout and today.

1. 2018-07-13 — application filed (16/035,135, the continuation that became '282). Not an assignment; shown for chronology. Priority date 2016-06-21 via parent 15/188,890.

2. Executed 2018 / recorded 2018-08-09 — Reel not exposed by Google Patents legal events (this is the '282-specific supplement to the 2016 Patent Security Agreement; the reel/frame could not be independently verified in this session — do not treat any number as confirmed for this entry)

   • Conveyance: Security Agreement — "Supplement No. 9 to Patent Security Agreement"
   • Assignor: Micron Technology, Inc.
   • Assignee: Morgan Stanley Senior Funding, Inc., as Collateral Agent (Baltimore, Maryland — address 1300 Thames Street, 4th Floor, Baltimore, MD 21231 per the parallel Micron/Morgan Stanley recording)
   • Correspondent: not printed in Google's legal events. On the parallel Micron/Morgan Stanley 2016 security recordings (USPTO reel 5805/0271, covering Micron's trademarks), the correspondent of record was Genevieve Dorment, Esq., Simpson Thacher & Bartlett LLP, 425 Lexington Avenue, New York, NY 10017. I flag this as a related correspondent from the same financing, not a confirmed read of the '282 reel. Recurrence flag: Simpson Thacher recurs across Micron's 2016 lender-side records — expected lender counsel, not an NPE filing pattern.
   • Context: Securitization — collateral pledge under Micron's April 26, 2016 credit facility (Morgan Stanley Senior Funding as collateral agent / "Authorized Representative" under the 2016 Note Indenture), adding the then-pending '282 application to the lenders' lien. This is an encumbrance, not a transfer of ownership.

3. Executed 2019-07-31 / recorded 2019-10-11 (Google Patents) — Reel 050937/0001 (blanket release reel covering the Micron portfolio; the reel/frame is taken from the INPADOC record of a sibling Micron patent subject to the same release, so treat it as highly likely but not '282-verified)

   • Conveyance: Release / Release of Security Interest
   • Assignor: Morgan Stanley Senior Funding, Inc., as Collateral Agent
   • Assignee: Micron Technology, Inc.
   • Correspondent: not printed. Micron-side recordings in this chain have carried WSGR (Wilson Sonsini Goodrich & Rosati), c/o Qui Lu, Senior Paralegal, 650 Page Mill Road, Palo Alto, CA 94304 (USPTO reel 5792/0001 on the parallel 2016 record). Recurrence flag: WSGR appears as Micron's recording correspondent on multiple Micron records — ordinary outside IP counsel, not an NPE tell.
   • Context: Collateral release — lien lifted after repayment/refinancing; ownership of '282 becomes unencumbered. Note a date discrepancy: Google Patents shows the event as 2019-10-11, while Espacenet INPADOC shows the same blanket release recorded 2019-10-09, executed 2019-07-31. I report both rather than reconciling them.

Surrounding portfolio-level recordings (context; these cover the broader Micron portfolio, and the '282's parent application 15/188,890 would have been swept into the 2016 records — the continuation '282 entered the lien via the 2018 supplement):

• 2016-04-26 / recorded 2016-05-12 — Reel 038669/0001 — Security Interest; Assignor Micron Technology, Inc.; Assignee U.S. Bank National Association, as Collateral Agent (633 W. Fifth St., 24th Fl., Los Angeles, CA 90071); Correspondent WSGR, c/o Qui Lu, Senior Paralegal, 650 Page Mill Rd., Palo Alto, CA. Context: securitization (collateral for Micron's $1.25B 7.500% senior secured notes due 2023).
• 2016-04-26 / recorded 2016-06-02 — Reel 038954/0001 — Patent Security Agreement; Assignor Micron Technology, Inc.; Assignee Morgan Stanley Senior Funding, Inc., as Collateral Agent; Correspondent Genevieve Dorment, Esq., Simpson Thacher & Bartlett LLP, New York. Context: securitization (new credit facility).
• 2017-06-08 — Reel 043079/0001 — Corrective Assignment (correcting an erroneously filed patent number in the 2016 record). Context: administrative correction only.
• 2018-06-29 / recorded 2018-07-13 — Reel 047243/0001 — Release by Secured Party; U.S. Bank National Association, as Collateral Agent → Micron. Context: collateral release.
• 2018-07-03 / recorded 2018-08-23 — Reel 047540/0001 — JPMorgan Chase Bank, N.A., as Collateral Agent; Assignors Micron Technology, Inc. and Micron Semiconductor Products, Inc. Context: securitization (new 2018 credit agreement replacing the Morgan Stanley facility).

Finding: every recorded event touching this patent is either a blanket portfolio collateral pledge or its release. There is no assignment to any LLC, no NPE, no fire-sale, no defensive aggregator. Ownership never left Micron.

Timeline diagram

timeline
    title Ownership and encumbrance of US 10431282
    2016 : Parent application filed by Micron
         : Pledged under Micron security agreements
    2018 : Continuation application filed
         : Security agreement supplement recorded
         : Lien to Morgan Stanley Senior Funding
    2019 : Continuation granted as US 10431282
         : Release of security interest
         : Ownership back at Micron unencumbered
    2020 : Continuation family added US 10748596
    2021 : Continuation family added US 11062753
    2023 : Continuation family added US 11636890

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. No assignee in the chain is a licensing vehicle. The only non-Micron assignees are Morgan Stanley Senior Funding, Inc., as Collateral Agent (2018-08-09 security supplement) and, at the portfolio level, U.S. Bank National Association and JPMorgan Chase Bank, N.A. — all banks taking collateral, none an IP-holding LLC, none with "IP / Patents / Licensing / Holdings / Ventures" naming.

2. Known asserter in the chain — NOT PRESENT. No assignee matches Acacia, Marathon Patent Group, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Round Rock, or any Spangenberg entity. The chain terminates at Micron.

3. Repeat correspondent across the chain — PRESENT (but benign; expressly NOT an NPE signal). Recording counsel recurs: Simpson Thacher & Bartlett LLP (Genevieve Dorment, Esq.) on the lender-side recordings and WSGR (Qui Lu) on the Micron-side recordings. Both firms are recurring Micron secured-financing/IP counsel of record — the recurrence is explained by a single corporate client running a single financing, not by one lawyer churning a string of shell LLCs. I record it for completeness and mark it not probative of NPE activity.

4. Cascading transfers — NOT PRESENT. Only two recorded events touch '282 (2018-08-09 and 2019-10-11), ~14 months apart, and neither is an ownership change. No chained LLCs, no shared-registered-agent pattern, no common principals.

5. Pre-litigation transfer — NOT PRESENT. No infringement suit naming US 10,431,282 is documented (consistent with the litigation section generated earlier — no contradiction), and no assignment sits within 6 months of any suit.

6. Bankruptcy fire-sale — NOT PRESENT. Micron was solvent and publicly traded (NASDAQ: MU) throughout 2016–2019. The 2019 lien release (Reel 050937/0001, exec. 2019-07-31) followed refinancing/repayment, not a Chapter 7/11 sale; there is no Kodak/Nortel-style sale of this patent out of proceedings.

7. Privateering — NOT PRESENT. No transfer of '282 to an NPE asserting on Micron's behalf. No SEC disclosure or RPX/Unified/Patent Progress reporting ties this patent to an NPE assertion program.

8. Defensive aggregator — NOT PRESENT. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at the original operating company.

Verdict

Operating-company assertion (with one explicit caveat: the "assertion" prong is not evidenced for this patent — I use the label because the chain ends at an operating company and shows zero NPE signals; the operative characterization is a clean, operating-company-owned, currently-unasserted patent. If the taxonomy demands an actual filed suit, the strict fallback is "non-NPE / not asserted," because no category fits a fully documented operating-company ownership record perfectly.)

Justification: The complete record is Micron Technology, Inc. → Morgan Stanley Senior Funding, Inc., as Collateral Agent (security supplement, recorded 2018-08-09) → back to Micron Technology, Inc. (release of security interest, executed 2019-07-31, recorded 2019-10-11, Reel 050937/0001 for the blanket release). Those are the only two events, both of them encumbrances rather than ownership transfers, leaving the patent with its original operating-company assignee, an entity with fabs and public reporting. All eight NPE signals resolve to not present, and the litigation section generated earlier independently found no assertion of this patent — the two sections are consistent, and neither supports an NPE characterization.

Verify at: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (or the legacy index at https://assignment.uspto.gov/patent/index.html), searching US 10,431,282; and the legal-events tab at https://patents.google.com/patent/US10431282/en#legalEvents.

Residual uncertainty to close out: I did not directly read the '282-specific reel/frame for the 2018-08-09 security supplement or the '282-specific correspondent of record. Pull those two fields from Assignment Center to convert the two flagged inferences (supplement reel; correspondent) into verified facts; I expect them to confirm Micron-side WSGR and lender-side Simpson Thacher, but I am not asserting it.

I'll research the prior-art citations for U.S. Patent No. 10,431,282 using the USPTO and related sources.

Let me pull the cited references and family/PCT data for this patent.

Let me look for the patent's front-page "References Cited" list from alternative patent databases.

Prior-Art Analysis — U.S. Patent No. 10,431,282

1. USPTO record confirmation for 10,431,282

Based on the authoritative full text supplied and the searches performed, the record for this number is confirmed as:

Caveat on the "search the USPTO database" instruction: I was able to reach the patent record only through Google Patents (which mirrors the USPTO bibliographic data) and general web results — not a direct USPTO Patent Public Search / PatentCenter "References Cited" view. The authoritative full text you supplied (the Google Patents HTML) does not include the front-matter "References Cited" list (the U.S. Patent Documents / Foreign Patent Documents / Other Publications block that normally appears on page 1). My searches returned the description text but never the front-page citation list. I therefore cannot enumerate the examiner-cited references verbatim, and per my operating rules I will not fabricate them.

2. Explicit limitation: I could not retrieve the cited-reference list

This is the single most important finding for your task: the deliverable you asked for — "look at each patent citation for 10431282" — cannot be completed from the sources I could reach. Everything below is (a) family/related documents and (b) topically relevant prior art that the searches surfaced. It is not the patent's official citation list, and I am labeling it as such so you do not mistake candidates for confirmed citations.

If you need the exact list, it must be pulled from: USPTO PatentCenter → Application 16/035,135 → "References Cited"; or the Google Patents "Citations / Cited By" panels (Patent citations / Non-patent citations); or the printed front page of the grant PDF (US10431282.pdf, page 1, field (56)).

3. Related documents surfaced (family — NOT prior art)

These surfaced repeatedly and are same-family or sibling documents; they cannot be § 102 prior art to '282 because they share the 2016-06-21 priority or post-date it:

• US 2018/0350420 A1 — the '282 pre-grant publication itself.
• US 10,748,596 B2, US 11,062,753 B2, US 11,636,890 B2 — later Micron continuations claiming priority to the '282 family (per the "Priority to" data on the record).
• US 10,431,281 B1 ("Inverting array data bits," Micron, filed 2018-08-17, granted 2019-10-01) — a sibling patent, filed after '282's 2016-06-21 priority date. Not prior art to '282.
• Foreign family members: TW I636457 B, JP 2019-525374 A, KR 20190019196 A, KR 102067365 B1, CN 109416921 A / B.

Flagging these explicitly per your rule: none of these is a "similar-number" substitute for '282, and none is prior art to it.

4. Topically relevant prior art the searches surfaced (candidate references only)

I catalog these because they are the kind of art an examiner or litigant would cite against a "bit inversion in a memory array" patent — but I have not confirmed any of them appears in the '282 citation list.

(Note: The search also returned patent-office documents from an unrelated Inter Partes Review discussion of "DBI" and "data arrangement alteration" and a patent about on-chip test-pattern inversion — these are different patents and are not imported here as citations of '282.)

5. § 102 anticipation assessment — with an explicit scope warning

A proper anticipation analysis under 35 U.S.C. § 102 requires the actual claim text. The authoritative excerpt you provided does not contain the granted claims of '282 — it ends inside the description of a later claim ("…write a second logic state … to the memory cell using the second set of t…"), and the search snippets only hint at claim language (e.g., a "flipping operation" in which, after writing a first logic value, a second, different logic value is written). I therefore cannot map a reference to "claim 1," "claim 16," etc. reliably.

What I can say with confidence, from the specification:

• Claim concepts that appear (from the disclosure): reading a first logic state through a first/true set of transistors; writing a second, different logic state through a second/inverting set of transistors; activating the transistors based on a counter compared against the cell's address; periodic flipping; and reading the intended state despite the cell storing the inverted state.
• For any reference to "anticipate" (§ 102), it must disclose every element as arranged in the claim. Based on the disclosures:
  • US 5,488,583 — anticipates only if a claim is drafted broadly to "inverting data written to memory cells." It does not disclose a *sense component with true/inverting transistor pairs or the counter-vs-address activation. So it is not an anticipatory reference for the principal claims.
  • US 8,766,828 / US 10,297,294 (DBI) — disclose inverting data bits, but for bus noise/power (or intra-module DBI), not for ferroelectric imprint mitigation, and without the ferroelectric cell + sense-component reconfiguration. Not § 102 art for the ferroelectric-specific claims.
• Bottom line: none of the candidate references I could surface reads on the full combination recited in the '282 disclosure, so I cannot identify a § 102 anticipatory reference with confidence from the material available.

6. What I recommend to finish this task

To produce the citation-by-citation § 102 table you want, retrieve these and re-run:

1. USPTO PatentCenter → Appl. 16/035,135 → Documents → "References Cited" (gives examiner-cited U.S./foreign/ NPL references).
2. Grant PDF front page (US10431282.pdf, field 56) for the same list plus the examiner's field-of-search.
3. PTAB API / Google Patents "Cited By" for post-grant art and any IPR that cites '282 (none was found in my searches, consistent with the earlier "no litigation found" summary).
4. The granted claim set (not in the supplied excerpt) — required before any § 102 mapping can be stated as anything other than provisional.

I want to be direct: the specific output requested (full citation, date, description, and § 102 claim mapping for each cited reference) is not deliverable from the sources reached in this session, because the front-page citation list for '282 was not obtained. I have not substituted similar-number patents for it, and I have flagged every candidate above as unconfirmed. If you can supply the field-(56) list (or let me query PatentCenter directly), I can complete the reference-by-reference § 102 analysis with claim numbers and element mapping.

Obviousness Analysis — U.S. Patent No. 10,431,282 ("Array Data Bit Inversion")

0. Scope note and a data-integrity caveat (read first)

I was not able to retrieve the actual "Prior Art" / "Patent Citations" table from the patent page. The web fetch of https://patents.google.com/patent/US10431282B2/en that produced the "full patent text" in this workflow captured the "Prior art keywords" block (memory cell; voltage; sense component; transistors; logic value) but did not capture the front-page reference list (U.S. Patents cited, foreign documents cited, or non-patent literature cited). Searches to reconstruct that specific citation table were cut off by a step limit.

Accordingly, this analysis uses (a) the "Prior art keywords" that were captured, (b) references that surfaced in related searches (titles/dates verified, but the precise disclosure paragraphs not verified line-by-line), and (c) the well-documented state of the art. Every reference-level assertion below should be verified against the actual file wrapper (USPTO PatentCenter/"References Cited") before being used in a real invalidity contention. Where I am not confident, I say so explicitly.

I also flag one probable contradiction with the earlier "Litigation summary" section: that section concluded no litigation on '282. In my searches, the small table on the '282 page that appeared to mix "Patent Citations" and "Cited By" listed several Micron documents (e.g., US 9,697,913 B1; US 10,403,389 B2; US 9,941,021 B2; US 10,418,084 B2; US 10,290,341 B2; US 10,446,502 B2) plus a later citing patent (US 10,984,852 B2). I could not confirm whether these sit in the "cited" or "citing" column. The litigation conclusion is unaffected, but the prior-art list cannot be confirmed from what was fetched.

1. The claims to be analyzed

U.S. 10,431,282 is a continuation (filed 2018-07-13) in the chain US 15/188,890 (→ US 9,715,919) → US 15/641,020 (→ US 10,043,566) → US 16/035,135 (→ the '282 patent) → US 16/544,587 (→ US 10,748,596) → US 16/921,868 (→ US 11,062,753) → US 17/370,515 (→ US 11,636,890). All share priority date 2016-06-21. The '282 patent's own claim set was not captured; the family claim sets (from US 2017/0365318 A1 / US 10,043,566 and US 2020/0043541 A1 / US 10,748,596) are representative and are what I analyze:

• Independent method claim (family '566): apply a first voltage across a memory cell → deactivate a first transistor that couples a first input of a sense component to the memory cell → activate the sense component → activate a second transistor coupling a second input of the sense component to the memory cell → apply a second voltage across the memory cell.
• Dependent claims: third/fourth transistors coupling the second/first input to a reference cell; plate-line bias overlap; memory cell ends in the opposite logic state (claim 7) and is returned to the original state by a second inversion cycle (claim 8); read performed through the second transistor set (claim 9); counter updated with the address (claim 10) and compared to the access address to select the transistor set (claim 11).
• Independent apparatus claim 12: access line; reference line; sense component with first/second input lines; four transistors — two coupling the access line to the first and second sense inputs, two coupling the reference line to the first and second sense inputs; claim 14 adds two sets of control lines.
• Later family claims (’596): storing a first voltage in a first access operation via a first sense contact; applying an opposite voltage in a second access operation via the second sense contact; reading the inverted state back as the intended value via the second contact; "indicating that the memory cell is storing an inverted logic state."

Core inventive concept: periodically physically inverting the charge stored in a ferroelectric cell (to defeat imprint/domain drift) while logically preserving the intended bit — implemented by swapping which sense-amplifier input is coupled to the digit line, so the sense amp itself outputs/writes the complement without extra data-path inversion, and tracked by a counter/address comparison.

2. Person of ordinary skill in the art (POSITA)

A POSITA at the 2016-06-21 priority date would have a B.S. in electrical engineering or equivalent and 2–3 years of experience in memory circuit design (DRAM/FeRAM sense-amplifier and array architecture), including familiarity with: (i) ferroelectric hysteresis, imprint, and fatigue; (ii) latching sense amplifiers and their differential inputs; (iii) bit-line isolation/equalization transistors; and (iv) data-inversion and refresh-tracking schemes.

3. Candidate prior art and what each teaches

4. Obviousness combinations

Combination A — R1 (+ R5, R2) ⇒ claims directed to the isolation/read-then-invert method

• R1 discloses the FeRAM bit line, differential sense amplifier, and isolation transistors that decouple the cell/bit-line from the sense amp during sensing and re-couple it afterward — i.e., "apply first voltage → deactivate first transistor → activate (fire) sense component."
• R5 supplies the reason to then write the opposite state back (anti-imprint).
• Coupling the cell to the other sense-amp input on re-coupling requires only adding a second isolation transistor to the complementary input — the apparatus claim 12's four-transistor configuration. Building a symmetric set of isolation transistors, one per sense input, is a predictable, mechanical duplication of R1's single isolation device; the fourth transistor (reference-line side) is the identical duplication for the reference path. In re Harza/KSR make such duplication obvious absent a teaching away, and R1's own isolation rationale (avoid loading the sense amp during fire) applies equally to both inputs.
• R2 supplies the "true path vs. invert path" selection concept and its control bit.

Combination B — R2 (+ R5/R1) ⇒ the true-transistor / inverting-transistor architecture

• R2 teaches selecting between a true data path and an inverted data path using a control/indicator, with the express purpose of changing the physical bit stream without changing the logical value.
• Applying R2's two-path selection to an FeRAM sense amplifier's differential inputs (swap which input sees the digit line) is a design choice within the ordinary skill level: the sense amplifier's output polarity is already defined as (input A − input B), so swapping the coupling reverses the output/write polarity for free — precisely the patent's stated advantage ("the sense component may generate a voltage corresponding to the intended logic state … without having to determine whether to change the resulting voltage").
• Motivation: R5 (avoid imprint by periodic inversion) supplies the why; R1 supplies the where (isolation transistors already exist at the sense inputs); R2 supplies the how (selectable true/invert path). The three references are all in the same field (semiconductor memory), and the combination yields the predictable result of an inverted write with an unchanged logical value.

Combination C — R2/R1 + R6/R7 ⇒ periodic inversion and counter/address tracking

• Claim set limitations requiring updating a counter with the inverted page's address and comparing it to the access address are met by ordinary refresh-tracking practice: the DRAM art routinely stores a counter/last-refreshed address and compares it to a requested address to decide how to service that row. Substituting "last inverted page" for "last refreshed row" is a mere change of the tracked quantity, with the same predictable operation — obvious under KSR ("a known technique … using a known method to produce a predictable result").
• Claimed periodicity based on temperature, access rate, or access count is squarely met by DRAM temperature/usage-compensated refresh practice (R6). The patent's own specification concedes the period is set by "internal characteristics … a temperature … an age … a sensing window" — i.e., it describes the conventional refresh-trigger criteria rather than claiming an unexpected one.

Combination D — Method-claim "second voltage = opposite state" (claim 7) and return-to-original (claim 8)

• Once the inverted write-back of Combination B is available, alternating the write-back between true and inverted on successive maintenance cycles (claim 8's "first logic state after the fourth voltage is applied") is the straightforward consequence of a toggle/counter-based maintenance schedule (R7), and is expressly suggested by R5's premise that repeated same-state storage is the harm to be avoided.

Combination E — Apparatus claim 12/14 (four transistors + two control-line sets)

• R1 (isolation transistors in FeRAM), plus routine engineering to share gate control lines across a pair (so that a single control node drives one transistor ON and its complement OFF — the patent itself describes a "common control node" inverting one control line relative to the other). Complementary control-line pairs are ubiquitous in memory (true/complement clocking), so claim 14 adds nothing beyond the predictable.

5. Why a POSITA would have been motivated to combine (the §103 "articulated reasoning")

1. Same field, same problem. R1, R2, R5–R7 are all semiconductor-memory references addressing sense-amplifier operation, data inversion, or periodic maintenance. KSR makes combination of familiar elements according to known methods obvious when the improvement is predictable.
2. Design incentive: reduce imprint without a data-path inverter. R5 establishes the need; R1 shows the isolation-transistor hardware already sits at the sense inputs; the sense amp's inherent differential polarity means the reverse write is free. Combining avoids adding a separate inverter/ECC re-mapping — the very benefit the patent touts in its "Brief" passages.
3. Reasonable expectation of success. Swapping an input to a latching differential amplifier is a known polarity-reversal technique; no new physics is needed. Predictable result → obvious.
4. Counter/address comparison is a known latency/control optimization in refresh; repurposing it to track inverted pages is a predictable substitution.

6. Anticipated patentee counterarguments and rebuttals

• "Secondary considerations / unexpected results": the specification's own rationale (preserved logical value, no sense-amp output modification) is a design consequence of input-swapping, not an unexpected result. There is no evidence in the record retrieved of commercial success, licensing, or copying attributable to the claimed features.
• "R2's DBI is for power/transition reduction, not imprint": motivation need not be the same as the applicant's; KSR permits using a reference for a different purpose than its principal one when the disclosed elements work as claimed.
• "R1 is old (1994) FeRAM art": age is irrelevant; the field is the same and the isolation structure is directly analogous.
• Common-ownership defense against R4: any Micron document relied on solely under §102(a)(2) that shares ownership at the effective filing date is removed by §102(b)(2)(C) — this is the strongest defense the patentee has against the family documents, so an invalidity position should lean on R1/R2/R5–R7 (independent third-party/printed-publication art) rather than on same-assignee Micron documents.

7. Bottom line

• Primary §103 combination: EP 0 631 287 A2 (FeRAM bit-line/sense-amp isolation) + Hollis DBI (true/invert data-path selection, with control bit) + the admitted imprint problem in the '282 background, optionally + temperature/usage-compensated refresh and refresh-address-counter practice. On the claim sets analyzed, this combination teaches every element of the independent method and apparatus claims and would have been obvious to a POSITA; the counter/address-comparison and periodicity limitations (claims 10–11 and the corresponding method steps) are met by routine refresh-tracking art.
• Confidence: I am confident about the legal framework and the claim-element mapping; I am not confident about the reference-level disclosure of R3 and R4, and I could not retrieve the patent's actual cited-reference list, so the specific "cited prior art" combinations cannot be confirmed from this workflow.

Recommended next step for a definitive analysis: pull the "References Cited" list directly from USPTO PatentCenter for application 16/035,135, then map each cited reference (especially any foreign/EP document and any non-patent literature) to the claim charts above. Until that list is obtained, treat the reference set above as candidate rather than certified prior art.