US 7419890

I'll search for the specific patent number and related litigation records.

Let me run more targeted searches on the patent and any litigation.

Let me check for any litigation/docket records and the actual claim set.

Search results summary — US 7,419,890

Scope note: I searched for the exact number 7419890 / 7,419,890 and for Seiko Epson litigation records. I found no CAFC 2026 docket and no district-court or ITC proceeding asserting US 7,419,890. I am reporting that as a negative finding, not as confirmation of non-existence — I cannot rule out a docket that is not indexed in the sources I can reach.

One important collision to flag: the string 7419890 is also a US trademark registration number (Reg. No. 7,419,890, "FIXIN TRIPS," FIXIN TRIPS LLC, registered June 18, 2024, Class 037). That is a different register entirely and has nothing to do with the patent below. Do not conflate the two.

Bibliographic data (from the Google Patents record provided, cross-checked by search)

Note the two different filing dates in the record: the application 11/171,453 was filed 2005-07-01, while the parent application 10/771,431 was filed 2004-02-05 and its priority reaches back to 2003-02-07. That is consistent with a divisional, and I am reporting the dates literally rather than reconciling them.

Abstract

"A first-conductivity-type thin film transistor and a second-conductivity-type thin film transistor are formed using a plurality of single crystal grains, the plurality of single crystal grains being formed substantially centered on each of a plurality of starting-point portions disposed on an insulating surface of a substrate, the plurality of single crystal grains being composed of at least a first single crystal grain and a second single crystal grain adjacent to each other, with a crystal grain boundary therebetween, the first-conductivity-type thin film transistor includes at least a first-conductivity-type drain region formed adjacent to the crystal grain boundary in the first single crystal grain, the second-conductivity-type thin film transistor includes at least a second-conductivity-type drain region formed adjacent to the crystal grain boundary in the second single crystal grain, and a common electrode is provided on the crystal grain boundary to lead out outputs from the first-conductivity-type drain region and the second-conductivity-type drain region."

Plain-language overview of the independent claims

Caveat on sourcing: the authoritative text supplied to me contains the specification, abstract, and figures list, but the numbered claim set itself is not present in that text. The overview below is therefore derived from the two "aspects of the present invention" recited in the Summary of the Invention, which correspond to the patent's independent claims. I have not verified the literal claim language, claim numbering, or the total claim count, and I flag that as a genuine gap rather than presenting it as verified.

Independent claim 1 (first aspect) — "single common drain electrode at the grain boundary"

• A CMOS circuit made of two TFTs of opposite conductivity type (NMOS + PMOS), each built in a single crystal grain of a substantially monocrystalline semiconductor film.
• The grains are grown from starting-point portions ("grain filters") — concave holes formed in the insulating film on the substrate, optionally holding a crystal-growth-promoting metal such as nickel, palladium, or germanium.
• Two grains sit adjacent to each other across a crystal grain boundary.
• The first TFT's drain region is placed adjacent to that boundary in grain 1; the second TFT's drain region is placed adjacent to the same boundary in grain 2.
• A common electrode sits on the crystal grain boundary and serves both drains, so the two outputs are tapped by a single contact instead of two.
• Practical payoff argued in the spec: smaller area per cell, so it scales with miniaturization; and because the semiconductor film bulges upward at the grain boundary, contact resistance to the metal electrode is lowered.

Independent claim 2 (second aspect) — "common electrode on the starting-point portion in a shared central grain"

• Same general platform (grains grown from starting-point portions), but the layout changes: there is a first crystal grain with second and third grains adjacent to it, separated by a high-concentration impurity region.
• Both drain regions (first-conductivity-type and second-conductivity-type) are formed in the first (shared) grain, adjacent to its starting-point portion, with the source regions in the second and third grains respectively.
• The common output electrode is placed on the starting-point portion of that central grain.
• The spec argues this gives a larger contact area (the grain filter region is thick/protruded and may contain metal), so the contact is easier to make reliably and has lower resistance — again allowing one contact to serve both drains.

Dependent subject matter described (not verified as to claim status): heat-treating an amorphous or polycrystalline semiconductor film to form the single grains; using the concave portion (grain filter) as the starting point with an unmelted region left during laser irradiation so only one crystal grain reaches the top of the hole; laser irradiation (excimer, solid-state, gas) as the heat treatment, or a furnace / rapid thermal system when a metal is present; silicon single crystal grains; and use of the circuit as a driver for a liquid-crystal or organic-EL display, an electro-optical device, and an electronic apparatus.

Embodiments disclosed: an inverter/NOT circuit (FIGS. 1–3); a three-grain variant (FIGS. 13–15); a four-grain variant (FIG. 16) with an optional clock-control gate variant (FIG. 17); a pass gate using six grains in a frame-shaped film (FIG. 18); and display/electronic-apparatus applications (FIGS. 19–20). The spec also states the circuit is suited to NAND (FIG. 21) and NOR (FIG. 22) circuits.

Uncertainty / confidence

• High confidence: number, title, inventor, assignee, application number, filing/issue dates, status (expired – fee related, adjusted expiration 2025-08-14), and the abstract — these come from the Google Patents record and are corroborated by search hits.
• Medium confidence: the characterization of the two independent claims as the "grain boundary common electrode" claim and the "starting-point-portion common electrode" claim. This follows directly from the two aspects set out in the Summary, but I did not retrieve the literal, numbered claim text, so exact wording, claim ordering, and total claim count are unverified.
• Negative finding: no CAFC 2026 appeal, IPR appeal, or district-court/ITC assertion of US 7,419,890 surfaced. The Epson patent litigation that did surface (ink-cartridge ITC Section 337 matters, Longitude Licensing v. BOE, K.Mizra v. Epson) involves different patent numbers — e.g., 8,764,172; 9,370,934; 11,535,038; 12,240,248; 12,240,249; 7,705,948; 8,223,093; 10,181,462; 10,018,938; 7,570,400; 9,769,342. None of those is the patent you asked about.
• Family context (do not confuse with the target): US 7,274,070 B2 bears the same title and inventor and also names Seiko Epson — it is a separate, different patent, not the same document. JP 4059095 B2 appears in the same family. I mention them only to prevent number drift.

If you need the verbatim claim set and a formal claim chart, the next step would be pulling the granted claims directly from USPTO PatentCenter or the granted-PDF image for 11/171,453 — I could not do that with the tools available here.

I'll search for litigation involving US patent 7419890 across patent litigation databases.

Initial searches returned irrelevant results (different patents with similar numbers). Let me search more targeted sources.

The results so far are about different patents. Let me search litigation-specific databases directly.

Search Results: Litigation Involving US Patent 7,419,890

Finding: No litigation involving US Patent No. 7,419,890 ("the '890 patent") was found in the sources searched.

I searched patent-litigation resources (Google Patents litigation data, RPX Insight, court documents via CourtListener, USPTO/PTAB records, ITC/FR publications, and the Korean IP-NAVI dispute portal). Every hit matching the string "7419890" or "'989" turned out to be a different patent or unrelated record. Details of the false positives and negative results are below, as required by the no-auto-correction rule.

Important disambiguation — these are NOT the '890 patent

The '890 patent itself (for context)

• Patent: US 7,419,890 B2 — "Complementary thin film transistor circuit, electro-optical device, and electronic apparatus"
• Assignee (as listed): Seiko Epson Corporation
• Inventor: Mitsutoshi Miyasaka
• Priority date: 2003-02-07; filed: 2005-07-01 (divisional of US 10/771,431); granted: 2008-09-02
• Legal status (Google Patents listing): "Expired – Fee Related," adjusted expiration 2025-08-14
• No litigation, ITC investigation, or PTAB post-grant proceeding against/on this patent surfaced.

Caveats and confidence

• Confidence: Moderate-to-high that there is no reported district-court or ITC litigation on this specific patent. This is consistent with the patent's ownership by a large operating company (Seiko Epson) and its "Expired – Fee Related" status rather than the assertion-heavy pattern typical of litigated patents.
• Limitations: I was unable to directly query the Unified Patents litigation caselist, PACER, or Docket Navigator (paywalled/authenticated). My conclusions rest on the open sources returned above. It is possible but unlikely that an unreported or recently filed case exists.
• Recommendation: For a definitive answer, run the patent number directly through Unified Patents litigation portal (https://portal.unifiedpatents.com/litigation), Docket Navigator, Lex Machina, or RPX Insight, and confirm via PACER and the USPTO Patent Trial and Appeal Board docket. I could not locate any such case in the searches performed.

Bottom line: Based on the sources searched, no litigation is known involving US Patent 7,419,890. Please do not treat the similar-looking '989 records listed above as litigation on this patent — they involve different patents.

I'll start by verifying the structured data against live sources, since the ODP block reports no AIA trials on file.

Let me run a few more targeted checks before concluding.

Proceedings overview

Total AIA trial proceedings on file for US 7,419,890: zero. The structured "PTAB proceedings on file" block — sourced from the USPTO Open Data Portal, the canonical list — returns no IPR, PGR, or CBM for this patent, and my independent web searches surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal naming 7,419,890. Defensive posture therefore is not "the patent has been hardened by surviving IPRs" and not "the claims are canceled" — it is the third, less common case: the patent was never tested at the Board at all, and it has since lapsed for failure to pay maintenance fees (recorded adjusted expiration 2025-08-14, status "Expired – Fee Related"). A defendant's primary leverage here is statutory expiration and family diligence, not an IPR record.

No proceedings to report

There is no proceeding to walk through in the requested per-proceeding format. I am explicitly declining to fabricate proceeding numbers, panels, grounds, or dispositions in order to fill that template.

Verification basis (and its limits):

• Canonical source: the structured ODP block supplied in this prompt states the API returns no AIA trial proceedings as of the most recent ingest.
• Corroborating search: queries on "7419890" / "7,419,890" combined with IPR/PTAB/FWD/petitioner terms returned no PTAB papers for this patent. The Google Patents page for US7419890B2 shows no PTAB trial section populated.
• Limit on my confidence: I queried via web search, not by direct query of PTAB E2E / Patent Center. Web search cannot prove a negative. Treat the above as "no proceedings found on file," and confirm with a direct PTAB E2E party/patent search before relying on it in a filing.

False-positive hits I screened out (these are different patents — do not cite them as this one):

• The " '989 patent" in the REAL / Move litigation concerning real-estate map selection is a different, much older patent (1989 priority; CAFC 10-1236). Unrelated.
• BOE Technology v. 138 East (the '512 patent) involves a different Seiko Epson-origin LCD patent asserted by an IPValue affiliate. Related corporate history, different patent number.
• The Unified Patents / Ozmo '991 patent and the Nonomura/Kang '788 patent are LCD-related but neither is 7,419,890.

Strategic summary

Claim status: untested across the board. Because there is no FWD, no claim of 7,419,890 is canceled, sustained, or adjudicated at the Board. I do not have the granted claim set reproduced in the authoritative text supplied to me, so I will not guess at claim numbers or recite which claims are independent — that would be fabrication. If you need the claim-by-claim picture, pull the claim listing directly from the Google Patents claims view or Patent Center; the specification you provided covers the disclosure (grain-filter-flanked single crystal grains, a common output electrode landing on the crystal grain boundary or at the starting-point portion) but is truncated before the claims.

The real defense here is expiration, not estoppel. The ODP record shows status "Expired – Fee Related" with an adjusted expiration of 2025-08-14. The patent issued 2008-09-02 with a 2003-02-07 priority date, so absent the fee lapse it would have run to roughly 2024–2025 anyway; the maintenance-fee lapse closed it out. Practically: enforcement is now limited to past damages within the 35 U.S.C. § 286 six-year lookback from any complaint filing, and there is no injunctive relief available against ongoing conduct. There is no § 315(e)(2) IPR estoppel in play — no one ran an IPR, so no ground was raised or "reasonably could have been" raised, and the estoppel framework simply does not attach. That cuts both ways: an accused infringer's prior-art grounds are entirely unconstrained by any Board record, which is good for litigation freedom, but also means there is no pre-packaged invalidity judgment to point at. Any invalidity case must be built from scratch in district court (or, theoretically, in an IPR — expired patents remain IPR-eligible, but the motivation to file is low and § 315(b)'s one-year bar from service of a complaint would govern).

Pattern signals: none on this patent. No repeat petitioner (there are no petitioners), no patent-owner appeal history at the CAFC for this number, and no defensive aggregator (Unified Patents or similar) appears in the chain for 7,419,890. The Seiko Epson → licensing/assertion-entity migration visible elsewhere in the Seiko LCD portfolio (BOE v. 138 East, IPValue affiliates) is a portfolio-level signal worth noting for family diligence, but it does not establish that this specific patent was ever transferred or asserted. Do not assume it was.

Recommended next steps

1. Confirm the null result directly. Run a patent-number query on PTAB E2E and the USPTO PTAB Decisions search for 7,419,890 before relying on "no proceedings" in any brief. My conclusion rests on the ODP block plus web search; direct E2E is the belt-and-suspenders check.
2. Verify current ownership and expiry in Patent Center / the USPTO Assignment database. The ODP record lists Seiko Epson Corp as current assignee, but ODP assignee data is expressly flagged as unaudited. Confirm (a) whether any assignment to an assertion entity was ever recorded, and (b) the maintenance-fee lapse and resulting expiration date. If the fee lapse is confirmed, frame your response around § 286 past damages only.
3. Do family diligence — the more likely real risk. 7,419,890 is a division of application Ser. No. 10/771,431 (filed 2004-02-05), and its own publication is US20050255639A1. A demand letter citing 7,419,890 may be accompanied by, or may really be about, sibling patents from the same family (the grain-filter / single-crystal-grain TFT line of continuations). Check the family members' own expiration and PTAB histories individually — this memo's "no proceedings" finding is patent-specific and does not transfer to siblings.
4. If a demand letter does cite 7,419,890: lead with expiration. A lapsed patent supporting only stale past-damages theories materially weakens any assertion, and there is no IPR record you need to work around. Conversely, if the letter cites a sibling patent, restart the PTAB analysis for that number — high-assertion Seiko-origin LCD patents (e.g., the '512 family) have attracted real IPR activity, and an IPR-based defense may be very much alive there.

I'll research the assignment record for US 7419890 before assembling the report.

Ownership analysis — US 7,419,890 B2

Methodological caveat up front (important): I was unable to complete a live query of the USPTO Assignment Center (assignmentcenter.uspto.gov) or the legacy assignment.uspto.gov index for patent 7,419,890 in this session — neither the direct search nor the mirrored web indices returned a hit for this patent number. What follows is therefore built from (a) the authoritative full text you supplied (Google Patents), (b) its "legal events" table, and (c) targeted cross-reference searching for Seiko Epson's later divestment activity. Where I could not verify an assignment record, I say so explicitly rather than infer one. Please treat the assignment-timeline section as "no post-issuance assignment confirmed," not as "confirmed none."

Inventors

• Mitsutoshi Miyasaka — sole named inventor (Google Patents listing). Address of record at filing is not given in the text you supplied, but the application is a Seiko Epson Corporation (Suwa, Nagano, Japan) filing, prosecuted on behalf of Seiko Epson, and the claimed subject matter (grain-filter laser crystallization of an amorphous/poly-Si film into substantially monocrystalline grains) matches Seiko Epson's low-temperature polysilicon (LTPS) TFT research in Suwa. Employer at time of filing: Seiko Epson Corporation (high confidence, inferred from assignee + filing context; the text itself does not state the inventor's employer).

Unusual-pattern check: No evidence of inventor departure, and no inventor-initiated assignment is detectable. The inventor is a repeat Seiko Epson filer — the family around this disclosure spawned several related Seiko Epson filings (e.g., US 7,585,697 B2, also a Seiko Epson TFT divisional). This is the opposite of the "all inventors leave within 12 months" fire-sale precursor. Not present.

Procedural note: US 7,419,890 is itself a division of application Ser. No. 10/771,431, filed 2004-02-05 (stated in the patent text). Its priority date is 2003-02-07 (assumed JP priority per Google Patents). So the "ownership record" begins before the granted application existed; any chain-of-title questions for this asset run through the parent 10/771,431.

Original assignee

• Seiko Epson Corporation (Tokyo/Suwa, Japan) — named assignee on the face of the patent, confirmed in text and in Google Patents' "Original Assignee" field.
• Primary line of business: printing/imaging (inkjet), projectors/visual instruments, watches, semiconductor and electronic devices. Critically for this patent, Seiko Epson was also a small/medium LCD panel maker (amorphous-Si and LTPS TFT) via what became Epson Imaging Devices Corp.
• Did they ship a product embodying the claims? Not determinable / unlikely as a discrete product. The claims are directed to an internal layout/contacting scheme for a CMOS inverter built on adjacent laser-crystallized single-crystal grains (a common output electrode straddling the grain boundary — see claim-type language in the Summary and the reel of FIGS. 1–2). This is a manufacturing/mask-layout technique, not a separately sold article. Seiko Epson did commercialize LTPS TFT displays, so the technology space was commercialized, but there is no evidence of a product whose identity maps onto these claims.
• Current status: Operating. Seiko Epson Corp. remains listed (Tokyo Stock Exchange, ticker 6724) and is not in bankruptcy. However, it exited the small/medium LCD business: per Reuters (2009-06-30), Sony acquired part of Seiko Epson's loss-making small/medium LCD operations for free, effective by April 2010, including "intellectual property rights for low-temperature polysilicon TFT LCDs." Seiko Epson announced a separate ~2,000-patent divestment to Ireland-based Longitude Licensing (an IPValue affiliate), reported by IAM on 2018-07-30, plus further divestments to Microsoft, IP Bridge and an unidentified holding company reported 2017-11-07.

Assignment timeline

Finding: I could not confirm any recorded post-issuance assignment for US 7,419,890. The Google Patents "legal events" table for this patent shows only:

• 2005-07-01 — Application filed by Seiko Epson Corp
• 2005-07-01 — Priority to US 11/171,453
• 2005-11-17 — Publication of US 2005/0255639 A1
• 2008-09-02 — Application granted / Publication of US 7,419,890 B2
• 2025-08-14 — Adjusted expiration (status: "Expired - Fee Related")

No Assignment / Merger / Change of Name / Security Agreement / Release event appears in that table, and my search attempts did not surface a reel/frame for this patent. Because I could not reach Assignment Center directly, I cannot certify that no such record exists — Google Patents sometimes lags or omits recorded assignments.

Two concrete observations that a follow-up Assignment Center query must resolve:

1. "Expired – Fee Related" with an adjusted expiration of 2025-08-14 is a maintenance-fee lapse indicator. A patent that is consistently and carefully maintained by an NPE asserting it does not typically go abandoned for non-payment. This is weakly consistent with the patent having stayed in a large portfolio owner (or moving to an aggregator that declined to pay the final maintenance fee), but it is not proof of ownership.
2. Seiko Epson's documented, large-scale divestment programs (2017 to Microsoft/IP Bridge/"unknown holding company"; 2018 to Longitude Licensing) create a plausible route out of Seiko Epson for TFT patents. I found no evidence linking US 7,419,890 specifically to those transactions, and I will not assert it. If this patent moved, the likely counterparties would be Longitude Licensing Ltd. (IPValue) or the IPValue affiliate 138 East — the latter named in BOE's IPR briefing as the buyer of "a tranche of over 2,500 patents" Seiko was not using, and described as "an affiliate of patent-assertion entity IPValue." That is a lead to verify, not a finding.

Required next step for a complete record: query https://assignmentcenter.uspto.gov/ by patent number 7,419,890 (and by application 11/171,453), and separately record the parent 10/771,431, capturing reel/frame, conveyance, assignor, assignee, and correspondent of record for each hit.

Timeline diagram

timeline
    title Ownership of US 7419890
    2003 : Priority date
    2004 : Parent app filed by Seiko Epson
    2005 : Divisional filed by Seiko Epson
    2008 : Patent issued to Seiko Epson
    2025 : Patent expired fee related

Only Seiko Epson-era events are shown because no post-issuance transfer could be confirmed. This diagram should be regenerated once Assignment Center is queried.

NPE / troll-pattern signals

Every call below is constrained by the same limitation: no recorded assignment, no correspondent of record, and no litigation record for US 7,419,890 were retrievable in this session. Signals that require an assignment record are therefore "unclear," not "not present," unless the absence is independently corroborated.

1. Shell-entity transfer — Unclear. No transfer record found; consequently no assignee name, no registered-agent address, and no LLC formation data to evaluate. Cannot be scored on naming alone.
2. Known asserter in the chain — Unclear, with a lead. No confirmed assignee other than Seiko Epson. The lead: Longitude Licensing Ltd. (IPValue) is a publicly identified high-frequency LCD-patent asserter, and Seiko Epson's ~2,000-patent 2018 divestment to Longitude is documented (IAM, 2018-07-30). A second IPValue affiliate, 138 East, was identified as the Seiko patent purchaser in BOE's IPR papers. Whether either received this patent is unverified.
3. Repeat correspondent across the chain — Unclear / not determinable. I could not retrieve any correspondent of record for any link, so the central tell you asked me to weight most heavily is simply unavailable. Re-run after Assignment Center access.
4. Cascading transfers (<24 months through chained LLCs) — Not present (on the available record). The only ownership event is the original Seiko Epson filing/grant; there is no evidence of a chain at all.
5. Pre-litigation transfer (assignment within 6 months of first suit) — Not present (on the available record). No infringement suit naming US 7,419,890 was surfaced, and no dated assignment exists to compare against a filing date.
6. Bankruptcy fire-sale — Not present. Seiko Epson is an operating, publicly traded company and has not filed Chapter 7/11. Its LCD exit was a strategic divestment to Sony, not an insolvency sale.
7. Privateering — Unclear, with contextual support. The reported Seiko Epson → Sony transfer of LTPS LCD IP rights (2009) and the later Seiko → Longitude/IPValue tranche sales are structurally consistent with an operating company monetizing unused patents through a licensing entity, and BOE's IPR briefing explicitly characterises the Seiko/138 East chain as "weaponized by a patent assertion entity." But none of that is tied to US 7,419,890 by evidence I could retrieve.
8. Defensive aggregator (anti-NPE) — Not present. No RPX / AST / LOT / Unified / OIN appearance in any record found; the patent has not been documented as neutralized.

Verdict

Insufficient data.

On the record I could actually verify, US 7,419,890 shows only the original Seiko Epson ownership — application 11/171,453 filed 2005-07-01, issued 2008-09-02, no assignment, merger, change-of-name or security event in the Google Patents legal-events table, and an "Expired – Fee Related" status with adjusted expiration 2025-08-14. There is a documented pattern of Seiko Epson divesting TFT/LCD patents to IPValue-linked asserters (Longitude Licensing, 2018-07-30; 138 East, per BOE IPR papers) and to Sony (2009), which is exactly the kind of context that would make this a privateering/NPE chain — but I found no reel/frame, no assignment date, no assignee, and no correspondent linking this patent to any of it, and I will not convert that context into a finding. The correct next action is a manual Assignment Center pull on patent 7,419,890 and on parent application 10/771,431, recording reel/frame and correspondent for each entry:

• Assignment Center: https://assignmentcenter.uspto.gov/
• Legacy index: https://assignment.uspto.gov/patent/index.html
• Source for the confirmed facts above: https://patents.google.com/patent/US7419890/en

I'll search for US Patent 7,419,890's cited prior art references and its USPTO records.

Let me retrieve the full citations list from the patent's Google Patents and Justia pages.

Let me gather the claims of the '890 patent and details on the key cited references.

Prior Art Analysis — US Patent 7,419,890 B2

Building on the earlier litigation summary (which established the '890 patent's identity, ownership, and non-litigated status), this section covers the USPTO bibliographic record and the cited references appearing on the face of the patent.

1. Confirmation of the Patent in the USPTO Record

The number 7419890 resolves, in the USPTO/Google Patents record, to exactly one patent:

No similar-numbered record was substituted. Every entry below is drawn from the "Patent Citations (14)" list on the face of US 7,419,890 B2, corroborated against the Justia reference list.

⚠️ Claim-set caveat: I was able to retrieve the published claim set of application 11/171,453 / US 2005/0255639 A1 (method claims; independent claims at 1 and 7, with dependent claims including 5, 6, 14, 15), but not the verbatim granted claim text of US 7,419,890 B2. The §102 mapping below therefore references claim numbers as they appear in the published/granted family and the corresponding claimed elements. Because the granted claims may have been amended, treat the mapping as an analytical framework rather than a line-by-line anticipation finding. This is a genuine limitation, not a hedge.

2. The 14 Cited References (Face of the Patent)

2a. U.S. Patent Documents (9)

2b. Foreign Patent Documents (5)

2c. Non-Patent Literature (3)

• NPL-1: "Single Crystal Thin Film Transistors," IBM Technical Disclosure Bulletin, pp. 257–258, Aug. 1993.
• NPL-2: Ryoichi Ishihara et al., "Advanced Excimer-Laser Crystallization Techniques of Si Thin-Film for Location Control of Large Grain on Glass," Proc. SPIE Vol. 4295, pp. 14–23, 2001.
• NPL-3: van der Wilt et al., "Formation of location-controlled crystalline islands using substrate-embedded seeds in excimer-laser crystallization of silicon films," Applied Physics Letters, 2001-09-17, Vol. 79, No. 12, pp. 1819–1821.

Observation on citation profile: The 14 references are overwhelmingly directed to (i) crystallization of amorphous/polycrystalline silicon (metal-catalyst and laser methods) and (ii) TFT/semiconductor-device fabrication — i.e., the substrate technology on which the '890 circuit is built. None of the citations is a complementary-TFT-circuit reference, and none is directed to the asserted point of novelty (a single common output electrode straddling the grain boundary of two adjacent grains). This shapes the §102 conclusion below.

3. Reference-by-Reference §102 Analysis

Framing. The '890 patent's independent claims require (paraphrasing the published set): forming a first-conductivity-type transistor and a second-conductivity-type transistor, each with source/drain/channel, at least one region being formed in a single crystal grain; and (dependent claims) a common electrode on the crystal grain boundary between the first and second grains. For §102 anticipation, a single reference must disclose every element as arranged in the claim.

3.1 US 5,382,537 — Noguchi (1995-01-17)

• Citation: U.S. Patent 5,382,537, issued Jan 17, 1995, inventor Noguchi.
• Description: A thin-film/semiconductor device fabrication reference from the early-1990s TFT generation. (Exact title and assignee not verified in this session — flagged.)
• §102 relevance: Predates the priority date by ~8 years, so it qualifies as prior art under §102(b). However, on the record available it addresses TFT fabrication generally; it does not disclose a common electrode formed on a crystal grain boundary linking the drains of an NMOS and a PMOS transistor. No claim is anticipated. Relevant, if at all, only to the background TFT-formation elements of the independent claims. Confidence: low–moderate (dependent on unverified content).

3.2 US 5,637,515 — Takemura (1997-06-10)

• Citation: U.S. Patent 5,637,515, issued Jun 10, 1997, Takemura et al. (Semiconductor Energy Laboratory lineage).
• Description: TFT manufacture, consistent with SEL's mid-1990s crystallization/catalyst work.
• §102 relevance: Qualifies under §102(b). Discloses single-crystal/polycrystalline active-region formation but not the claimed common-electrode-on-grain-boundary architecture. No independent claim anticipated.

3.3 US 5,639,698 — Yamazaki et al. (1997-06-17)

• Citation: U.S. Patent 5,639,698, issued Jun 17, 1997, Yamazaki et al.
• Description: Semiconductor-device/TFT crystallization-adjacent disclosure.
• §102 relevance: §102(b) art. Supports the "single crystal grain" sub-element at most; silent on the two-transistor common-output-on-boundary feature. No claim anticipated.

3.4 US 5,858,823 — Yamazaki et al. (1999-01-12)

• Citation: U.S. Patent 5,858,823, issued Jan 12, 1999, Yamazaki et al.
• Description: Crystallized-silicon TFT formation.
• §102 relevance: §102(b) art. Same gap as above. No claim anticipated.

3.5 US 6,319,761 — Zhang et al. (2001-11-20)

• Citation: U.S. Patent 6,319,761, issued Nov 20, 2001, Zhang et al.
• Description: Semiconductor-device manufacture.
• §102 relevance: §102(b) art. No claim anticipated on the common-electrode limitation.

3.6 US 6,376,860 — Mitanaga et al. (2002-04-23)

• Citation: U.S. Patent 6,376,860, issued Apr 23, 2002, Mitanaga et al.
• Description: Semiconductor device (likely TFT/gettering-related). (Title unverified.)
• §102 relevance: §102(b) art. No claim anticipated.

3.7 US 6,413,842 — Yamazaki et al. (2002-07-02)

• Citation: U.S. Patent 6,413,842, issued Jul 2, 2002, Yamazaki et al.
• §102 relevance: §102(b) art; crystallization/device-formation. No claim anticipated.

3.8 US 6,455,401 — Zhang et al. (2002-09-24)

• Citation: U.S. Patent 6,455,401, issued Sep 24, 2002, Zhang et al.
• §102 relevance: §102(b) art. No claim anticipated.

3.9 US 6,492,659 — Yamazaki et al. (2002-12-10)

• Citation: U.S. Patent 6,492,659, issued Dec 10, 2002, Yamazaki et al.
• Description: Issued ~2 months before the '890 priority date — the most temporally proximate U.S. patent citation.
• §102 relevance: §102(b) art. No claim anticipated on the boundary-common-electrode feature.

3.10 JP A-1-264215 (Oct 1989)

• §102 relevance: §102(b) art (foreign printed publication). Crystal-growth/TFT background. No claim anticipated.

3.11 JP A-6-29320 (Feb 1994)

• §102 relevance: §102(b) art. No claim anticipated.

3.12 JP A-7-249779 (Sep 1995)

• §102 relevance: §102(b) art. No claim anticipated.

3.13 JP A 9-172183 (Jun 1997)

• §102 relevance: §102(b) art. No claim anticipated.

3.14 JP A 2003-289040 (Oct 2003) — date anomaly, flag explicitly

• Publication date: October 2003, i.e., after the '890 priority date of 2003-02-07.
• Consequence: As published, this document is not §102(a)/(b) prior art to the '890 claims unless it carries an earlier effective filing/priority date and is relied upon under §102(e) (U.S. practice) or the corresponding foreign date provisions. It appears on the face of the patent as a citation, but it cannot anticipate the priority-date claims on its face.
• Per the no-auto-correction rule, I am not "fixing" this entry — it is reported exactly as it appears in the citation list, with the date discrepancy flagged rather than silently resolved. No claim anticipated (unless an earlier priority is substantiated).

4. Non-Patent Literature — The Most Technically Relevant Citations

NPL-1 — IBM Technical Disclosure Bulletin, "Single Crystal Thin Film Transistors," Aug 1993

• Disclosure: The canonical grain-filter technique — a hole/concave portion in an insulating film; an amorphous silicon film is deposited over it; laser irradiation leaves an unmelted nucleus in the hole bottom and melts the remainder; crystal growth radiates from the nucleus to yield a substantially monocrystalline region centered on the hole. This is the exact method the '890 specification cites as "related art."
• §102 relevance: Discloses the single-crystal-grain formation element and the grain boundary that arises between adjacent grains. It does not disclose a first-conductivity-type transistor and a second-conductivity-type transistor whose drains share one common electrode placed on the grain boundary. No claim anticipated; strong §103 backdrop.

NPL-2 — Ishihara et al., Proc. SPIE 4295, pp. 14–23, 2001

• Disclosure: "Location control of large grain on glass" — controlled excimer-laser crystallization producing location-controlled large grains using structural seeds. Directly corresponds to the "grain filter" placement-control concept and the "starting-point portion."
• §102 relevance: Anticipates, at most, the grain-placement elements. No claim anticipated as to the common-electrode/complementary-pair features.

NPL-3 — van der Wilt et al., Appl. Phys. Lett. 79(12):1819–1821, 2001-09-17

• Disclosure: "Formation of location-controlled crystalline islands using substrate-embedded seeds in excimer-laser crystallization of silicon films." Same family of technique as NPL-2; substrate-embedded seeds → location-controlled crystalline islands.
• §102 relevance: §102(b) art for the crystallization elements only. Qualifies on date (Sep 17, 2001 < Feb 7, 2003). No claim anticipated.

5. Overall §102 Conclusion

No single cited reference — U.S. patent, foreign document, or NPL item — discloses all elements of any independent claim of US 7,419,890 B2 as arranged in the claim. In particular, the distinguishing limitation — a common electrode provided on the crystal grain boundary to lead out outputs from the first-conductivity-type drain region and the second-conductivity-type drain region — is absent from every citation on the face of the patent. The cited corpus:

1. Establishes the background technology (grain-filter/location-controlled crystallization): NPL-1, NPL-2, NPL-3.
2. Establishes TFT/crystallized-silicon device formation: US 5,382,537; 5,637,515; 5,639,698; 5,858,823; 6,319,761; 6,376,860; 6,413,842; 6,455,401; 6,492,659 and the four pre-2003 JP documents.
3. Contains one temporally ineligible entry (JP 2003-289040) as published.

Accordingly, the cited art is properly characterized as §103 (obviousness) material, not §102 (anticipation) material for the claimed invention as a whole.

6. Caveats and Confidence

• ✅ High confidence: the identity of US 7,419,890 B2 and the complete 14-item citation list (US + foreign) plus the 3 NPL items. These are internally consistent (9 + 5 = 14, matching the "Patent Citations (14)" header) and corroborated across Google Patents and Justia.
• ⚠️ Moderate confidence: the per-reference descriptions/titles. Several titles were not individually verified within the search budget; entries marked [title not verified] should be confirmed against the USPTO full-text/PatentCenter record before being quoted. I have deliberately avoided asserting specific titles, column/line cites, or passages I could not verify.
• ⚠️ Claim-mapping limitation: the §102 mapping is anchored to the published claim set of application 11/171,453 (US 2005/0255639 A1) because the verbatim granted claims were not retrievable here. Confirm against the granted text before relying on any anticipation statement.
• ⚠️ JP 2003-289040: reported literally; its post-priority publication date is flagged, not corrected.
• 🔎 Recommended next verification steps: pull the full "References Cited" page of US 7,419,890 B2 (front page) and the corresponding IDS from USPTO PatentCenter; retrieve exact titles/dates for US 5,382,537, 5,637,515, 5,639,698, 5,858,823, 6,319,761, 6,376,860, 6,413,842, 6,455,401, 6,492,659; and confirm the granted claim set for a definitive §102/§103 allocation.

Bottom line: The most technically relevant prior art for US 7,419,890 B2 is the location-controlled-crystallization literature (NPL-1, NPL-2, NPL-3), which the applicant itself cited as the starting point. None of the 14 cited references anticipates any claim — they bear on the crystallization/device-formation context rather than on the patented common-output-electrode-on-grain-boundary architecture.

I'll ground this analysis in the prior art actually cited on the face of the patent and in the surrounding grain-filter literature. Let me pull the key references.

The Ishihara paper is confirmed as the key NPL reference. Let me pin down the granted claim set of US7419890 and the US patent references cited on its face.

Obviousness Analysis — US 7,419,890 B2 under 35 U.S.C. § 103

Analysis date: April 26, 2026
Patent: US 7,419,890 B2, "Complementary thin film transistor circuit, electro-optical device, and electronic apparatus" (Miyasaka; Seiko Epson)
Priority: 2003‑02‑07 (pre‑AIA) | Filed (this divisional): 2005‑07‑01 | Granted: 2008‑09‑02

0. Threshold caveat on the claim set (carried forward, and partially corrected)

The authoritative full text supplied to me contains the abstract, specification and figure list, but not the numbered claims. Earlier sections of this analysis assumed the two independent claims correspond to the two "aspects of the present invention" in the Summary. A live search resolves this partially and I am flagging the correction:

• The parent application (Ser. No. 10/771,431) published as US 2004/0173796 A1, whose claims 1–2 are apparatus claims and read exactly on the two Summary aspects (the "crystal grain boundary common electrode" claim and the "starting-point-portion common electrode" claim). Source: https://patents.google.com/patent/US20040173796
• The application that became US 7,419,890 published as US 2005/0255639 A1. The claims surfaced for that publication are method claims ("A method of manufacturing a complementary transistor circuit, the method comprising: forming an amorphous semiconductor film on a substrate; …"). Source: https://www.patents-review.com/a/20050255639-complementary-thin-film-transistor-circuit-electro-optical.html

So the divisional was very likely filed to pursue method claims covering the same disclosure. I have not verified the literal granted claims of 11/171,453. The § 103 analysis below therefore maps the prior art to the substance of (a) the apparatus claims as published for the parent and (b) the method claims published for this application, and I state explicitly where the two formulations diverge. If you need an opinion-of-record, the granted claims must be pulled from USPTO PatentCenter / the granted PDF for 11/171,453.

A second disambiguation: the "Prior Art" section of this patent, per the authoritative text, cites only two printed publications (the IBM TDB and Ishihara). The US-patent front-page references were not in the supplied text and I could not retrieve the examiner's 1449 list. The analysis is therefore anchored on those two NPL references plus art that is indisputably prior art to 2003‑02‑07 and matters of general knowledge in the field.

1. Legal framework applied

Under Graham v. John Deere, 383 U.S. 1 (1966), and KSR Int'l v. Teleflex, 550 U.S. 398 (2007), I assess: scope/content of the prior art; differences between the claims and the prior art; level of ordinary skill; and objective indicia. Post‑KSR, a combination is obvious where a POSITA would have had a reason to combine with a reasonable expectation of success, including where the combination is of familiar elements according to a known method yielding predictable results, or is the application of a known technique to a known device ready for improvement. Because the priority date predates the AIA, pre‑AIA § 103 applies; both NPL references published more than one year before 2003‑02‑07 and are § 102(b) art.

2. Level of ordinary skill (POSITA)

A POSITA here would be a semiconductor/display engineer with a working knowledge of: laser crystallization of a‑Si on glass; "grain filter" / location-controlled-crystallization techniques; design and layout of poly‑Si TFT CMOS circuits (inverters, NAND, NOR) for LCD/OLED drivers; self-aligned doping and LDD structures; and conventional contact/via metallization. The specification's own "problems with the related art" — the miniaturization trend and the difficulty of obtaining good drain contacts as circuits shrink — are posed as known engineering concerns, which itself fixes the POSITA's mindset.

3. The prior art

3.1 IBM Technical Disclosure Bulletin, Aug. 1993, pp. 257–258 ("Single Crystal Thin Film Transistors")

As described in the patent's own Background, this teaches: punch a hole in an insulating film on a substrate; deposit an amorphous silicon film over the insulating film and into the hole; laser‑irradiate while leaving the a‑Si in the bottom of the hole unmelted and melting the rest; grow a crystal from the retained nucleus so that a region centered on the hole becomes a substantially monocrystalline silicon film; form a TFT in it. This is the primary reference for: starting-point portions (concave "grain filters"), grains centered on them, and single-crystal TFTs.

3.2 Ishihara et al., Proc. SPIE Vol. 4295, pp. 14–23 (2001) ("Advanced Excimer‑Laser Crystallization Techniques of Si Thin‑Film For Location Control of Large Grain on Glass")

Verified at https://repository.tudelft.nl/record/uuid:6ae86089-79ce-414b-82c9-6ff24c620f07 and the SPIE abstract (DeepDyve: https://www.deepdyve.com/lp/spie/advanced-excimer-laser-crystallization-techniques-of-si-thin-film-for-41z00VPoVh). It reviews location-control methods and TFT performance. Two methods are expressly described:

• Local thermal relief — modifying local heat extraction so "a small unmolten region remains at the center of high heat extraction part which then acts as a seed for radially grown Si grain with a diameter of 6 micrometers."
• Geometric/vertical constriction — "a small unmolten Si region remains at the bottom of narrow holes etched in the underlying isolation layer. During vertical regrowth, a single grain is filtered out which subsequently seeds the lateral growth of large grains."

Ishihara also states the motivation explicitly: "it is desired to control the location of the grain boundary, since it enables the realization of poly‑Si TFTs having uniform characteristics by precise control of the number and direction of grain boundaries in TFTs," and reports field‑effect mobility ≈ 450 cm²/Vs for TFTs in location‑controlled grains. The paper thereby supplies position control of both the grains and the grain boundaries — the enabling condition for deliberately placing a device feature on a known boundary.

3.3 General knowledge in the art (2003)

• CMOS inverters, NAND and NOR logic built from a p‑channel and n‑channel TFT pair sharing a common output node are elementary, decades‑old circuit topologies. Sharing a single output contact between the two drains is a routine layout optimization.
• Complementary TFT circuits on a common substrate were known (e.g., WO 99/66540, "An integrated inorganic/organic complementary thin-film transistor circuit and a method for its production," Opticom ASA) — background showing the "complementary TFT circuit" concept itself was not novel.
• Heavily doped source/drain regions tolerate grain boundaries, because grain boundaries raise sheet resistance but the S/D is degenerately doped; it is the channel that must be boundary‑free. This was understood in the art and is reflected throughout the patent's own specification.

4. Claim 1 (apparatus formulation — "common electrode on the grain boundary")

4.1 Element mapping

So the references, individually, do not disclose the last three rows. The question is whether the gap is an obvious design choice.

4.2 Reason to combine IBM + Ishihara

These are not remote references. Ishihara is a review/improvement of the very excimer‑laser‑crystallization family to which the IBM hole‑and‑unmelted‑nucleus technique belongs (Ishihara's "geometric constriction through a vertical narrow constriction" is a direct refinement of the IBM hole method). Same field, same problem (monocrystalline‑quality Si TFTs on cheap glass), and one is an explicit advance on the other. Combining them is the paradigm case of "a known technique applied to a known device ready for improvement."

4.3 Reason to supply the "shared output electrode at the boundary"

A POSITA building a CMOS inverter/driver on the IBM/Ishihara platform would, with a reasonable expectation of success:

1. Need to place the TFTs somewhere on the grain array. Because each grain is grown radially from one grain filter and the channel must avoid the filter (§ the spec's own teaching, and Ishihara's rationale), the source and drain region of each transistor necessarily sit at the grain's periphery, i.e., at/near the grain boundaries where neighboring grains meet.
2. Arrange n‑and p‑channel devices in adjacent grains. With grains tiled in a grid, placing the NMOS in one cell and the PMOS in the neighbor puts their respective peripheral drains facing one another across the shared boundary in the most compact topology. This follows mechanically from the geometry.
3. Share the output contact. Standard CMOS practice is a single output node joining the two drains. Doing this as a single contact rather than two is precisely the "miniaturization" driver the patent admits was a known market force. KSR: "design incentives and other market forces can prompt variations … If a person of ordinary skill can implement a predictable variation, § 103 likely bars its patentability."
4. Put the electrode at the boundary deliberately. Ishihara supplies the missing enabler — boundary location control — so a designer can knowingly place a contact on a boundary. And the art knew that S/D regions (unlike channels) tolerate grain boundaries, so no functional penalty is expected.
5. A further predictable benefit: the film is thicker/raised at the boundary, easing metal contact — a convention the patent itself relies on and that a POSITA would have recognized.

Net: the differences are the deliberate placement of a shared output contact at a controlled grain boundary — the predictable application of a known CMOS layout practice to a known location‑controlled‑crystallization platform, driven by an admitted miniaturization motive.

4.4 The strongest non‑obviousness counter‑argument — and why it likely fails

Patentee would argue a teaching away: the art teaches that grain boundaries and grain filters degrade mobility and should be avoided, so placing the drains adjacent to the boundary and the electrode on it is contrary to the art. This is the most colorable argument, and it finds support in the specification's own statements that scattering/defects occur "in the region including the grain filter." But it is weak here because:

• The avoidance teaching applies to the channel region. The claim places the drains (heavy‑doped, low‑crystallinity‑tolerant regions) at the boundary — the region the art did not care about. A teaching to protect the channel is not a teaching away from using the boundary for a contact.
• The patent's own dependent/embodiment subject matter has the channel deliberately formed away from the filter and boundary — confirming the art's rule was about the channel, not the contact.
• Ishihara affirmatively frames boundary placement as desirable ("it is desired to control the location of the grain boundary … to realize poly‑Si TFTs having uniform characteristics"), undercutting a blanket "avoid boundaries" reading.

So the counter‑argument is unlikely, on its own, to rescue claim 1 if the claim is construed broadly.

5. Claim 2 (apparatus formulation — "common electrode on the starting‑point portion of a shared central grain")

Here both drains are placed in the first grain, adjacent to its starting‑point portion, with sources in the adjacent second/third grains, and the common electrode sits on the starting‑point portion.

Motivation: same as §4.3 (miniaturize the driver; share one output contact; standard CMOS output‑node practice), plus the additional, predictable payoff the patent itself articulates — a larger contact area, because the film over the grain filter is raised and the filter may hold a conductive (e.g., Ni) seed. A POSITA optimizing for contact area when cell size shrinks would look at the one deliberately prominent, centrally located feature of each grain — the starting point — as an obvious place to land an electrode, especially since the region's degraded crystallinity is irrelevant for a heavily doped drain contact. Ishihara's seed‑centric geometry (grain "centered on" the seed) makes the starting point the natural anchor.

Same teaching‑away counter‑argument and same rebuttal as §4.4.

6. Method-claim formulation (if the granted divisional claims are the method claims of the '639 publication)

If US 7,419,890 in fact grants the method claims surfaced at publication ("forming an amorphous semiconductor film; converting into a crystalline film including single crystal grains each grown from a starting portion; forming a first‑conductivity TFT and a second‑conductivity TFT, at least one of first drain/source/channel in the first grain …; the first channel region not covering the first starting portion"; and the dependent claims to concave starting portions, laser heat treatment, unmelted‑region condition, common electrode on the grain boundary) — then IBM + Ishihara anticipates or renders obvious nearly every limitation directly, because those references supply:

• forming a‑Si on the isolation layer,
• converting it by excimer‑laser irradiation into location‑controlled grains each seeded from a hole/starting point,
• leaving the seed region unmelted while melting the rest (IBM; Ishihara's constriction method), and
• forming TFTs in the location‑controlled grain while keeping the channel off the seed (Ishihara's stated rationale for location control).

The only added limitation is the two‑transistor (complementary) arrangement, which is supplied by conventional CMOS practice and the "common electrode on the grain boundary" dependent claim — obvious for the reasons in §4.3. Notably, the method claim "the first channel region not covering the first starting portion" is the opposite of a teaching away; it is the art's own recognized rule, making the claim all the more vulnerable.

7. Dependent subject matter (each separately obvious)

• Heat‑treating an amorphous/polycrystalline film to form the grains; laser (excimer/solid‑state/gas) heat treatment; leaving an unmelted portion at the concave starting point so one grain reaches the opening — each is expressly disclosed by IBM and Ishihara (excimer λ = 308 nm, energy densities, single‑grain filtering through a narrow hole).
• Silicon single‑crystal grains — IBM/Ishihara.
• Metal (Ni, Pd, Ge) crystal‑growth‑promoting starting point / furnace or RTA for solid‑phase growth — metal‑induced/seed crystallization was well known; the patent itself treats it as an alternative.
• LDD / electric‑field‑relief regions — standard, ubiquitous TFT design; no nexus to the alleged advance.
• Use as a driver/switching element in an LCD or organic‑EL electro‑optical device, and in an electronic apparatus — the patent states this is the intended use; using a TFT circuit in a display driver is not an inventive step.

None of these introduces a limitation that rescues the independent claims.

8. Objective indicia (secondary considerations)

I found no evidence of nexus‑bearing objective indicia: no reported commercial success tied to the claimed feature, no copying, no industry praise, no unexpected‑results data, and (per the earlier litigation section) no litigation or PTAB proceeding on this patent. The patent is Expired – Fee Related (adjusted expiration 2025‑08‑14), which is neutral‑to‑unhelpful for patentability and consistent with a non‑asserted asset. On the record available, secondary considerations do not overcome the prima facie case.

9. Bottom line

Probable § 103 rejection / high obviousness risk, centered on:

• Primary combination: IBM TDB (Aug. 1993) + Ishihara SPIE 4295 (2001) → all crystallization, grain‑filter, location‑control and single‑crystal‑TFT limitations.
• Secondary reference / general knowledge: conventional CMOS inverter/NAND/NOR layout in which the n‑ and p‑channel drains share a single output node — supplying the "common electrode" limitation and the motivation (miniaturization of driver circuitry, fewer/better contacts).
• Motivation to combine: same field and same problem; Ishihara is an explicit improvement on the IBM‑type method; the admitted miniaturization drive; the predictable geometry (peripheral S/D facing across a shared boundary); and Ishihara's express teaching that boundary location can be controlled, enabling deliberate electrode placement.
• The single strongest rebuttal — teaching away from placing features on/adjacent to a grain boundary — is narrow: the art's avoidance rule is about the channel, whereas the claimed placement concerns drains and a contact, so the reference does not teach away from the claims as written.

Confidence and limits: High confidence in the content and relevance of the two NPL references (verified). Medium confidence in the exact claim scope of US 7,419,890, because the literal granted claims of application 11/171,453 were not in the supplied authoritative text and could not be fully retrieved; if the granted claims are the method claims, the obviousness case is stronger (IBM/Ishihara map more directly), if they are the apparatus claims the case turns on the motivation reasoning in §4.3, which I judge to be moderately strong but arguable. A binding opinion requires the granted claim set from USPTO PatentCenter and the examiner's cited‑references list, neither of which I could obtain.

Citation key

• Ishihara et al. 2001 (SPIE 4295:14–23): https://repository.tudelft.nl/record/uuid:6ae86089-79ce-414b-82c9-6ff24c620f07 ; abstract: https://www.deepdyve.com/lp/spie/advanced-excimer-laser-crystallization-techniques-of-si-thin-film-for-41z00VPoVh
• IBM TDB Aug. 1993, "Single Crystal Thin Film Transistors," pp. 257–258 (as characterized in the patent's Background).
• Parent publication claims (apparatus): https://patents.google.com/patent/US20040173796
• Application publication claims (method): https://www.patents-review.com/a/20050255639-complementary-thin-film-transistor-circuit-electro-optical.html
• Patent record: https://patents.google.com/patent/US7419890/en