US 9190481

I'll search for authoritative information on this patent number, including any litigation or CAFC docket activity.

Let me run more targeted searches on litigation/docket activity and the patent record.

Let me do a final check for any CAFC or PTAB proceedings mentioning this exact patent.

Summary — US Patent 9,190,481 B2

Source of record: Full authoritative text supplied from https://patents.google.com/patent/[US9190481](/patent/US9190481)/en (fetched 2026-09-28). Patent number interpreted literally as 9190481 / US 9,190,481 B2.

Bibliographic data

Abstract (as issued)

A method is provided for fabricating transistors. The method includes providing a substrate; and forming at least one dummy gate structure having a dummy gate dielectric layer and a dummy gate electrode layer on the substrate. The method also includes forming a dielectric film on the substrate and the dummy gate structure; and performing a thermal annealing process onto the dielectric film to increase the density of the interlayer dielectric film. Further, the method includes planarizing the dielectric film having the increased density until the top surface of the dummy gate structure is exposed; and forming a dense layer having an increased density on the dielectric film having the increased density. Further, the method also includes removing the dummy gate dielectric layer and the dummy gate electrode layer to form an opening; and forming a gate dielectric layer and a gate electrode layer sequentially in the opening.

Independent claims — plain-language overview

Note on claim scope: In the granted claim set there is only one independent claim — claim 1. Claims 2–15 are all dependent (2→1; 3,4→2; 5–9,12,13→1; 10→9; 11→10; 14,15→13). The specification's "Brief Summary" also recites a transistor (apparatus) aspect, but no apparatus/transistor claim was granted — the patent is method-only. This is a material observation for any claim-charting or validity analysis.

Claim 1 (the sole independent claim) — a gate-last (replacement metal gate) fabrication method:

1. Provide a substrate.
2. Form at least one dummy gate structure comprising a dummy gate dielectric layer on the substrate and a dummy gate electrode layer on the dummy gate dielectric layer.
3. Form a dielectric film over the substrate surface and the top surface of the dummy gate structure.
4. Increase the density of the dielectric film by a thermal annealing process (spec: > ~800 °C; RTA, peak-value annealing, or laser annealing).
5. Planarize the densified dielectric film until the dummy gate structure's top surface is exposed (spec: CMP).
6. Form a dense layer having an increased density on the dielectric film (spec: silicon ion implantation; dose > 1E15 atom/cm³; energy ~0.5–3 KeV; thickness ~10–30 Å; converts ILD surface to silicon-rich oxide and CESL surface to silicon-rich nitride).
7. Remove the dummy gate dielectric layer and the dummy gate electrode layer to form an opening.
8. Sequentially form a gate dielectric layer and a gate electrode layer in the opening (spec: high-K dielectric + metal).

The two points of novelty that the prosecution/classification history emphasizes are the post-deposition densifying anneal of the ILD (step 4) and the post-planarization implanted "dense layer" that protects the ILD/CESL during the dummy-gate-dielectric removal (step 6) — both aimed at preventing surface roughening that leads to metal residue and leakage current.

Notable dependent-claim limitations (for context)

• Cl. 2–4: chemical etch stop film (SiN, ~50–300 Å, CVD > 480 °C) beneath the dielectric film; etch-back to form a CESL.
• Cl. 6: dielectric film = silicon oxide formed by a high-aspect-ratio process (HARP), TEOS precursor with flow < 1 gm.
• Cl. 7: dense layer formed by Si ion implantation, dose > 1E15 atom/cm³, energy ~0.5–3 KeV.
• Cl. 8: anneal is RTA / "peak annealing process" / laser anneal at > ~800 °C. (Note: the claim says "peak annealing process" while the specification says "peak value annealing process" — a literal-reading discrepancy worth flagging.)
• Cl. 9–11: dual-region (core region 201 / peripheral region 202) flow; mask-and-open core region first to form first opening, then remove mask and peripheral dummy gate electrode to form second opening; optional pad oxide at bottom of the first opening.
• Cl. 12–15: metal gate electrode + high-K gate dielectric; polysilicon dummy gate layer with silicon-oxide dummy gate dielectric formed by thermal oxidation and removed by wet etch.

Litigation / PTAB / CAFC check (2026)

No authoritative evidence found of any US litigation, PTAB (IPR/PGR), or Federal Circuit appeal involving US 9,190,481. Targeted searches for the exact number against CAFC 2026 dockets returned no matching case, and the returned hits were unrelated (e.g., a Brookhaven magnet PDF containing the incidental string "73.9190481"; a W.D. Tex. Waco Division scheduling order involving SMIC as a defendant on U.S. Pat. 6,580,122, a different patent entirely).

Uncertainty statement: The absence of results is not affirmative proof that no proceeding exists. Docket databases are not fully indexed by this search tool, and a same-family Chinese counterpart (CN 104795331 B) could be the subject of proceedings in China that would not appear in US dockets. I do not have high-confidence information on any enforcement, licensing, or challenge activity for this patent.

Related-art context (from the patent's own citation lists)

• Cited by the examiner/third parties as prior art: US 2005/0032286 A1 (Dongbu, triple gate insulating layers); US 7,422,936 B2 (Intel, "Facilitating removal of sacrificial layers via implantation to form replacement metal gates"); US 8,658,483 B2 (TSMC).
• Family-cited: US 8,431,453 B2 (TSMC, "Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure") and US 9,082,789 B2 (TSMC) — both closely related to the dense-layer/etch-loss concept.
• Later citing documents include TSMC US 10,483,170 B2 / US 10,854,471 B2 / US 11,532,485 B2 and UMC US 11,257,711 B1 ("Fabricating method of transistors without dishing occurred during CMP process"), showing the technique remained relevant in follow-on CMP-dishing work.

I'll search for litigation involving US patent 9190481 across the sources you specified.

The initial searches returned no relevant results (mostly unrelated patents). Let me run more targeted searches.

Result: No litigation found for US Patent No. 9,190,481

I searched Google Patents, the Unified Patents litigation/PTAB portal references, USPTO PTAB filings, and general web sources. I found no district court litigation, ITC investigation, PTAB proceeding (IPR/PGR/CBM), or CAFC appeal involving U.S. Patent No. 9,190,481.

Per your instruction to interpret identifiers literally, I screened out results for numerically similar but distinct patents — e.g. U.S. 9,166,481 (Vicor), U.S. 8,922,048, RE-048 / EP 2,270,048, and others — none of which is the patent at issue.

What I can confirm about the '481 patent (grounded in the Google Patents record)

• Cited-by list is non-litigation. The "Cited By" entries (e.g., US 2015/0380519 A1 and US 9,614,051 B2 from SMIC; TSMC's US 10,483,170 B2, US 10,854,471 B2; UMC's US 11,257,711 B1) are later patent documents that cite the '481 as prior art — they are not lawsuits asserting the '481 patent.
• Citations (prior art) are also non-litigation: US 2005/0032286 A1 (Dongbu), US 7,422,936 B2 (Intel), US 8,658,483 B2 (TSMC).
• The patent is a replacement-gate / high-K metal gate (HKMG) fabrication patent, with 15 claims directed to forming dummy gates, annealing and planarizing a dielectric film, forming a densified "dense layer" by ion implantation, and forming a gate dielectric/gate electrode in the resulting opening.

Important caveats

• Negative finding, not proof of absence. My search relied on publicly indexed sources (Google Patents, PTAB document repositories, and general web results). It is not a substitute for a full PACER/Docket Navigator/Lex Machina docket search or a complete Unified Patents litigation caselist query, which require direct database access I could not fully execute here.
• Nothing in the sources I retrieved suggests a litigation history. Given the owner is a major foundry (SMIC) rather than a patent-assertion entity, and the '481 claims cover internal semiconductor manufacturing methods (difficult to detect and assert against end products), a low litigation profile is consistent with expectations.
• If you need court-confirmed certainty, the recommended next step is a direct PACER docket query and a Unified Patents / Docket Navigator "asserted patent" lookup for 9,190,481.

Bottom line: Based on the available sources, there is no known litigation involving U.S. Patent No. 9,190,481.

I'll verify the structured "no proceedings" signal with targeted web searches before concluding.

Let me run a couple more targeted checks for any challenge or assertion activity.

Proceedings overview

Zero AIA trial proceedings are on file for US 9,190,481 as of 2026-09-28. The USPTO Open Data Portal returns no IPR, PGR, or CBM proceedings for this patent, and my independent web searches (PTAB petitions, PTAB E2E / PTACTS material, CourtListener-style docket material, and general docket reporting) surfaced no petition, no institution decision, no Final Written Decision, no termination, and no Federal Circuit appeal involving the '481 patent. Breakdown by status is therefore: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0.

The bottom-line defensive posture is the least favorable one available to a defendant: the patent is entirely untested. All 15 claims stand as issued, none has ever been construed by the Board or cancelled, and there is no petitioner-side record to borrow from. A defendant here gets none of the free "claim 1 is already dead" leverage that comes from prior PTAB litigation — but conversely, the defendant also faces no § 315(e)(2) estoppel and can pick its own grounds from the full prior-art universe. Verified quiet: the Google Patents "Cited By" and "Citations" tables for the '481 patent list only patents and publications (e.g., US 7,422,936 to Intel; US 2005/0032286 to Dongbu; US 8,658,483 to TSMC; US 8,431,453 to TSMC), not AIA challenges. Do not misread those citation tables as PTAB history.

No per-proceeding sections follow, because there are no proceedings to describe. I have not fabricated case numbers to fill the template.

Strategic summary

Claim-status map. Because no AIA trial has reached a Final Written Decision, no claim of US 9,190,481 is cancelled and no claim has been upheld. All fifteen issued claims are untested rather than sustained — an important distinction. Independent claim 1 (gate-last method: dummy gate → dielectric film → thermal anneal > 800 °C → planarize → ion-implantation dense layer → remove dummy gate stack → form HK gate stack) and independent claim (transistor) are the assertion vehicles; the method claims 2–15 add the CESL, HARP oxide, silicon-implant dense layer, and dual core/periphery opening limitations. The patent is post-AIA (priority 2014-01-21, filed 2014-11-26, granted 2015-11-17; anticipated expiration 2034-11-26), so PGR is no longer available (9-month window closed ~2016-08-17) and CBM is inapplicable — this is a semiconductor fabrication patent, not a financial-services patent. IPR under §§ 102/103 is the only AIA vehicle left, and it remains fully open.

Estoppel landscape. Clean slate. There is no FWD, so § 315(e)(2) estoppel attaches to nobody, and no petitioner or privy is barred from any ground. There is also no prior IPR record for the patent owner to have made prosecution-history- or IPR-history-based arguments against. The practical consequence: a defendant in a 2026 district-court case has the entire printed-publication prior-art universe available and can frame institution-optimal grounds from scratch. The § 315(b) one-year bar runs from service of the complaint if you are sued — calendar that if you receive a demand letter or complaint. The relevant art the defendant should start from includes the prosecution citations already of record, notably US 7,422,936 B2 (Intel, "Facilitating removal of sacrificial layers via implantation to form replacement metal gates"), which is closely adjacent to the '481 patent's signature move of implanting silicon to densify/protect dielectric surfaces before dummy-gate removal, and US 8,431,453 B2 (TSMC, plasma doping to reduce dielectric loss during removal of dummy layers).

Pattern signals. There are no pattern signals to report for this patent: no repeat petitioner, no defensive aggregator (no Unified Patents, no RPX- or AICP-style entity) in the chain, and no PTAB appeal activity by the owner. The one adjacent data point worth knowing is that the owner, Semiconductor Manufacturing International (Shanghai) Corp. ("SMIC"), appears in PTAB records primarily on the petitioner side — e.g., SMIC, Americas v. Innovative Foundry Technologies, IPR2020-00837 (US 6,806,126) and IPR2020-00839 (US 6,620,620), which arose out of the Innovative Foundry Technologies v. SMIC litigation. That tells you SMIC is a sophisticated, litigation-active IP player that knows how to run IPRs — but it says nothing about whether the '481 patent will ever be asserted. I found no litigation in which the '481 patent is the asserted patent, and this reads like a defensive manufacturing-process portfolio asset held by a foundry rather than a monetization vehicle.

Recommended next steps

If you are a defendant facing assertion (or a demand letter): Treat the zero-proceeding status as a green light for a full-freedom-to-operate and invalidity study rather than as a warning. There is no FWD to link to, respectfully — none exists. Recommend (1) ordering the file wrapper and the CN104795331B counterpart prosecution history (the '481 patent claims priority to CN 201410027709.0, and the Chinese counterpart is CN104795331B); (2) scoping prior art against the two independent claims, focusing on pre-2014 gate-last/HKMG literature and on the Intel '936 and TSMC '453 references already of record; and (3) checking whether the asserted claims read on a specific process step (e.g., the >800 °C anneal or the 1E15 atom/cm³ silicon implant) or on generic gate-last processing — the claim language is parameter-heavy, which often makes the invalidity and non-infringement stories align.

If you are the patent owner considering enforcement: The absence of prior PTAB activity is a signal in your favor — the patent has not drawn attention from defensive aggregators. But be aware that filing suit is what invites IPRs; the parameter-based claim drafting (anneal temperature, implant dose/energy, TEOS flow, film thicknesses) is exactly the kind of limitation set that a competent petitioner will attack both as obvious and as unsupported under § 112, so pretrial validity work is advisable before asserting.

Milestones that would apply only if an IPR is later filed: institution decision due within 6 months of petition filing (§ 314(b)); statutory FWD deadline 12 months from institution (§ 316(a)(11)); PO response 3 months post-institution; optional PO amendment; and appeal to the Federal Circuit within 63 days of the FWD if either side seeks review.

Sources / verification trail

• Patent record: https://patents.google.com/patent/US9190481/en (claims 1–15; priority 2014-01-21; filed 2014-11-26; granted 2015-11-17; anticipated expiration 2034-11-26)
• USPTO PTAB decisions and E2E: https://ptacts.uspto.gov/ and https://developer.uspto.gov/ (searched; no proceedings matching US 9,190,481)
• Adjacent SMIC-as-petitioner proceedings surfaced in search (not about this patent): IPR2020-00837, IPR2020-00839 — see the Board's institution decision at https://www.docketalarm.com/cases/PTAB/IPR2020-00837/

I'll research the assignment record for this patent before building the analysis.

Let me try to surface the specific reel/frame data for the assignment.

Assignment / Ownership Analysis — US Patent No. 9,190,481 B2

Scope note on sources. I was able to confirm the existence and parties of the recorded reassignment from the Google Patents legal-events record (which mirrors the USPTO reassignment index) and from third-party indexes (FreePatentsOnline, Patents-Review, Patents Encyclopedia). I was not able to retrieve the reel/frame number or the correspondent of record from the USPTO Assignment Center (assignmentcenter.uspto.gov) — the Assignment Center search interface could not be queried end-to-end from my available sources, and no mirror of that record surfaced the reel/frame. Per the operating rules, I am leaving those fields explicitly blank rather than guessing. A direct lookup at the Assignment Center by patent number (or by application 14/554,432) is required to fill them in.

Inventors

Pattern observations:

• Single-inventor patent. Unusual for a 15-claim HKMG replacement-gate process patent from a major foundry, where multi-inventor filings are the norm. This concentrates all inventorship in one person and simplifies the ownership chain to a single inventor-to-employer assignment.
• No departure pattern detected. There is no evidence in the record of the inventor leaving SMIC around the 2014–2015 window, and no subsequent assignment out of SMIC. Nothing in the chain suggests a pre-fire-sale inventor exodus.
• Common-name caution. Commercial inventor-profile aggregators (e.g., patents-review.com's "Jie ZHAO" profile) lump this inventor together with unrelated Jie Zhaos in biotech, hospitals, Delta Electronics, SAP, and DSM filings. Those are a different person — do not attribute the pharmaceutical/medical applications to the SMIC inventor. Only the SMIC-linked filings are relevant here.

Original assignee

Semiconductor Manufacturing International (Shanghai) Corporation (SMIC Shanghai).

• Primary line of business: China's largest pure-play semiconductor foundry. SMIC does not sell end-user products; it sells foundry manufacturing services — i.e., it practices the claimed method in its own fabs when running an HKMG/gate-last flow for customers. It is a direct, commercial implementer of the claimed subject matter, not a licensing entity.
• Public-company status: SMIC is publicly listed (Hong Kong Stock Exchange: 981; Shanghai STAR Market: 688981). It was NYSE-listed historically and voluntarily delisted from the NYSE in 2019. It remains an operating company, not in bankruptcy or dissolution.
• Corporate history relevant to this chain: SMIC Shanghai is the Chinese operating subsidiary of Semiconductor Manufacturing International Corporation (Cayman Islands holding company). No merger, spin-off, or change-of-name event affecting the '481 patent appears in the record.
• Regulatory context (status, not ownership): SMIC was added to the U.S. Entity List in December 2020. This is not an assignment event, but it is relevant context if you are screening for U.S. assertion risk: a Chinese foundry with restricted U.S. market access is a structurally implausible NPE plaintiff or NPE transferor.
• Current status: Operating. Google Patents lists the patent as "Active," with an anticipated expiration of 2034-11-26.

Assignment timeline

The record contains one assignment event. The patent is not chain-of-title-empty, but it has never left its original owner.

• 2014-11-26 (as displayed) / recorded date not independently confirmed — Reel/Frame: NOT RETRIEVED
  • Conveyance: Assignment of assignors' interest ("ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: ZHAO, Jie (sole inventor)
  • Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
  • Correspondent: Not retrievable from the sources available to me. I will not invent a name. (This is the one field I most wanted for the NPE-screen — see signal #3 below.)
  • Context: Ordinary employment/inventor-to-employer assignment. This is the standard "hereby assigns all right, title and interest" instrument executed as a condition of employment and recorded against the file. It is not an acquisition, fire-sale, securitization, or transfer-to-asserter.

Date-integrity warning (please read before relying on the 2014-11-26 date): the displayed event date coincides exactly with the U.S. filing date (2014-11-26) of application 14/554,432. Google Patents' legal-events feed does not distinguish execution date from recordation date in the way the Assignment Center does, and date normalizations are common. Treat 2014-11-26 as unverified for either execution or recording purposes; it may be the execution date (assignment signed at filing), the recordation date, or a parser artifact. The Assignment Center record is the only authoritative source for both dates and the reel/frame.

No subsequent records. There is no second assignment, no security interest, no merger, no change of name, no license recordation, and no release in the chain. The patent has remained with SMIC continuously since the original conveyance.

Timeline diagram

timeline
    title Ownership of US 9190481
    2014 : CN priority filed Jan 21
         : US application filed Nov 26
         : Inventor assigns rights to SMIC
    2015 : US patent issued Nov 17
    2018 : CN family member granted
    2034 : Anticipated expiration Nov 26

NPE / troll-pattern signals

Aggregate signal count: zero strong signals, zero weak signals, one unevaluable field (correspondent).

Verdict

Insufficient data — in the rubric's precise sense of "only the original assignment."

Justification. The entire recorded chain consists of a single inventor-to-employer conveyance of Jie Zhao's rights to Semiconductor Manufacturing International (Shanghai) Corporation, recorded against application 14/554,432 (displayed date 2014-11-26; reel/frame and correspondent not retrievable, and the date itself is suspect because it coincides with the filing date). There is no shell-entity transfer, no known asserter, no cascade, no pre-litigation transfer, no bankruptcy sale, no privateering, and no defensive-aggregator terminus — the patent has sat continuously with a large, publicly listed, product-and-service-shipping operating foundry, and the prior-art citation neighborhood is entirely operating semiconductor companies. I withhold a stronger verdict only because the correspondent of record — the single most diagnostic field for this exercise — could not be retrieved, and because "no post-issuance assignments" is a negative finding, not affirmative proof of absence.

Verify at: USPTO Assignment Center — search by patent number 9190481 or application 14/554,432 (also indexed at https://assignment.uspto.gov/patent/index.html) — needed specifically to capture the reel/frame, the execution vs. recording dates, and the correspondent name for the signal-#3 check.

Caveats and contradictions to flag

1. Missing reel/frame and correspondent. I have deliberately left these blank. If a downstream section of this analysis asserts a reel/frame for the '481 patent, treat it as suspect until confirmed against the Assignment Center — I found no source that disclosed one.
2. Date ambiguity, not a contradiction. The 2014-11-26 reassignment date in the Google Patents feed equals the filing date. This is not a conflict with the fetched patent text, but it means the text's own legal-events block cannot be used to establish when the assignment was executed.
3. Cross-reference to the prior "Litigation summary" section: it found no litigation. That finding is consistent with — and reinforces — the "Insufficient data / no NPE activity" verdict here. There is no suit, so some NPE signals (pre-litigation transfer, assertion-driven venue engineering) are structurally inapplicable and are marked "not present" rather than "unclear" for that reason.
4. Name-collision hazard restated. Aggregated inventor profiles conflate this Jie Zhao with unrelated individuals in biotech and medicine. Do not use those profiles to infer employment history for the SMIC inventor.

I'll search for the US 9,190,481 record and each of its cited prior-art references.

I have strong detail on the three examiner-cited references. Now let me retrieve the "Family Cites Families" references, which are also part of the citation record.

Prior-Art Analysis — U.S. Patent No. 9,190,481 B2

1. Confirming the target record

I searched for the specific number 9,190,481. The authoritative full text you supplied (Google Patents, fetched 2026-09-28) is corroborated by the mirror records I retrieved (Justia patents.justia.com/patent/9190481 and the pre‑grant .../20150206949). Record of the patent at issue:

Note on sources: the raw USPTO PatentCenter/Patent Full‑Text page did not return directly in my search; the record above is drawn from the Google Patents text you provided plus the Justia and uspto.report mirrors. I did not find a discrepancy between them, so I treat the record as consistent (no contradiction to flag). I interpret all identifiers literally — e.g., I do not confuse this with U.S. 9,166,481, U.S. 8,658,483, etc.

2. The citation record (what "the citations" actually are)

US 9,190,481 has two distinct citation sets. This matters, because they carry different legal weight:

• "Patent Citations (3)" — the references cited by the examiner on the face of the patent. These are the references the applicant had to traverse.
• "Family Cites Families (4)" — references cited against the Chinese priority/family sibling (CN 104795331). These were not on the U.S. face but are part of the family citation trail and are the more technically dangerous art.

3. Examiner-cited references ("Patent Citations")

3.1 US 2005/0032286 A1 — Dongbu Electronics

• Full citation: US 2005/0032286 A1, "Method of manufacturing semiconductor device with triple gate insulating layers," Dongbu Electronics Co., Ltd. (granted as US 7,001,815 B2).
• Dates: filed 2003‑08‑07; published 2005‑02‑10 (grant 2006‑02‑14).
• Description: A replacement/"dummy-gate" flow for multi‑voltage devices. A first oxide (thermal), a nitride dummy-gate material, patterned to form first/second dummy gates (15a/15b) over first/second oxide patterns; a second oxide (16) and polysilicon (17) cover them; spacers are formed; source/drain implants; an intermediate insulating layer (planarized) is formed; the dummy gates are selectively removed by wet etch (hot phosphoric acid) to form holes exposing the oxide patterns; a third oxide is grown, gate material deposited and polished back to form second/third gate insulators. (Sources: Google Patents US20050032286A1; uspto.report/app/20050032286.)
• §102 exposure — none for the issued claims. It discloses with claim 1: a substrate, dummy gates with a dummy dielectric + dummy electrode, spacers, a planarized interlayer insulator, dummy-gate removal to an opening, and gate dielectric/electrode formation. But it is entirely silent on the two elements that give the '481 claims 1 and 7 their novelty: (i) a thermal anneal of the dielectric film to increase its density before planarization, and (ii) a post-planarization dense layer formed by silicon ion implantation on the ILD/CESL. It cannot anticipate claim 1, and because all other claims depend from claim 1, it cannot anticipate any claim as a whole. It is at most §103 art for the generic replacement-gate scaffold.

3.2 US 7,422,936 B2 — Intel Corporation (the closest examiner citation)

• Full citation: US 7,422,936 B2, "Facilitating removal of sacrificial layers via implantation to form replacement metal gates," Intel Corp.; inventors Barns, Prince, Doczy, Brask, Kavalieros.
• Dates: filed 2004‑08‑25; granted 2008‑09‑09.
• Description: Replacement metal-gate flow. A polysilicon sacrificial layer and hard mask are patterned into gate structures over a high‑k gate dielectric; a spacer layer with a first polish rate is etched to form spacers; an interlayer dielectric with a higher second polish rate is deposited; the dummy layers are removed to form a trench that is filled with metal gate material. Critically, "the patterned hard mask layers … may be subjected to an implantation … to increase their polish rate… The implant may damage the hard mask sufficiently so that it polishes at a higher rate." (Google Patents US7422936B2; freepatentsonline 7422936.)
• Why it is the closest — and why it still does not anticipate. This is the only examiner citation that uses ion implantation to modify the polish/etch behavior of a dielectric in a replacement-gate flow, which is conceptually the heart of the '481 "dense layer." But the teaching runs in the opposite direction to the '481:
  • Intel implants the hard mask sitting on top of the gate, before planarization, to make it polish faster (remove more easily).
  • The '481 (claim 1) thermally anneals the dielectric film to densify it, planarizes, and only then implants silicon into the ILD/CESL to densify it so it etches slower and resists over‑etch during dummy dielectric removal.
  • Intel also lacks any thermal anneal densification step and never removes the dummy gate dielectric to form the opening.
• §102 exposure — none. No single reference element set; claim 1 (and thus claims 2–15) is not anticipated. Best characterized as the strongest §103 reference on the "implant-to-modify-a-dielectric" concept, requiring combination with a densifying anneal and a post-planarization silicon implant.

3.3 US 8,658,483 B2 — TSMC

• Full citation: US 8,658,483 B2, "Method of fabricating an integrated circuit device having backside bevel protection," TSMC; inventors Hsu et al.
• Dates: continuation of 13/077,257 (filed 2011‑03‑31); this continuation filed 2012‑11‑19; granted 2014‑02‑25.
• Description: Replacement-gate structure with a dummy polysilicon layer; a dielectric layer (offset spacers and/or CESL) deposited by a thermal process; CESL/ILD0 planarized to expose the dummy poly; the dummy poly removed by wet etch (diluted NH₄OH); high‑k/metal gate layers then deposited in the opening. The CESL (silicon nitride/oxynitride, 100–800 Å) is also formed on the wafer backside/bevel to prevent poly/Si attack. (Google Patents US8658483; freepatentsonline y2013/0095647.)
• §102 exposure — none for claim 1; partial correspondence to specific dependent limitations. It touches claim‑1-adjacent ground only for:
  • Claim 2 / claim 4 (a chemical etch‑stop film / CESL): TSMC discloses a CESL of silicon nitride with a stated thickness range and thermal (LPCVD) formation — but the '481 claim 4 CVD‑temperature >480 °C and 50–300 Å ranges are not the same disclosure.
  • Claim 15 (dummy gate dielectric removed by wet etch): TSMC's wet poly etch (NH₄OH) is for the electrode, not the dielectric, and the '481 claim 15 is a wet etch of the dummy gate dielectric.
  • It lacks the thermal-anneal densification and the silicon-implanted dense layer entirely.
• §102 exposure — none. §103 relevance only.

4. Family-cited references ("Family Cites Families") — the more dangerous art

4.1 US 8,431,453 B2 — TSMC (highest §102/§103 significance)

• Full citation: US 8,431,453 B2, "Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure," TSMC; Huang, Lin, Wang, Hsu, Tai. (Divisional: US 9,281,307 B2.)
• Dates: filed 2011‑03‑31; granted 2013‑04‑30; pre‑grant US 2012/0248550 A1 (2012‑10‑04).
• Description: This reference is squarely aimed at the same problem the '481 solves. After the ILD0 surrounding the gate is planarized to expose the dummy gate electrode, the ILD0 surface is doped — by plasma doping (PLAD) or an ion‑beam process, with carbon — to reduce its etch rate, so that when the dummy gate electrode/dielectric is removed, the ILD is not lost. A post‑doping anneal (optional; RTA ~350–800 °C) may follow. Claim 1 of the '481 is very close to this sequence conceptually. (Justia 8431453; freepatentsonline 9281307; Google Patents US9281307.)
• §102 exposure — genuine but incomplete; strong §103 art.
  • Correspondences to claim 1 / claim 7: substrate; dummy gate electrode; dielectric film planarized to expose the dummy gate, followed by doping of the ILD surface layer to suppress etch loss during dummy-layer removal, then replacement gate formation. That maps onto claim 1 steps (c)–(f) and claim 7's "dense layer … formed by an ion implantation process."
  • Gaps that prevent clean anticipation: (a) TSMC's dopant is carbon, while '481 claim 7 requires silicon ions (a silicon‑rich oxide/nitride); (b) TSMC does not recite the pre‑planarization thermal anneal of the dielectric film to increase its density required by claim 1 step (d); (c) TSMC's anneal is a post‑doping anneal, not the claimed densification anneal; (d) TSMC does not remove the dummy gate dielectric in the sequence claimed.
  • Conclusion: It cannot anticipate claim 1 as written, but it is the reference most likely to drive a §103 rejection of claims 1 and 7 (implant‑doped ILD surface layer in a replacement gate flow), possibly combined with an anneal‑densification teaching such as the examiner's US 7,422,936 or basic furnace/laser densification knowledge. It is also the reason the '481's claim 7 was likely narrowed to silicon ions and a specific dose/energy.

4.2 US 9,082,789 B2 — TSMC

• Full citation: US 9,082,789 B2, "Fabrication methods of integrated semiconductor structure," TSMC; priority 2011‑05‑13; granted 2015‑07‑14. (Record per the Google Patents family citation table.)
• Status of verification: I could not retrieve or verify the substance of this reference in my searches (the search steps returned the US 8,431,453/US 9,281,307 records instead). I will not speculate about its disclosure or claim mapping. Based on dates alone it is potentially prior art (its 2011 priority / pre‑grant publication predate the '481's 2014‑01‑21 priority), but a substantive §102/§103 assessment requires reading the document, which I could not do here. Recommend retrieving US 9,082,789 directly before relying on it.

4.3 CN 101840862 B — Institute of Microelectronics, Chinese Academy of Sciences

• Full citation: CN 101840862 B, "Method for forming high-performance semiconductor device," Institute of Microelectronics, Chinese Academy of Sciences; priority 2009‑10‑15; granted 2013‑02‑20 (family‑cited).
• Status of verification: My search for this record did not return usable content. I cannot describe its disclosure or map it to claims with confidence, and I will not fabricate one. As a published foreign patent it is potentially §102(a)(1)/§102(b) art (publication well before 2014), but substantive evaluation is pending retrieval of the Chinese text/translation.

4.4 KR 20070049346 A — Hynix Semiconductor

• Full citation: KR 20070049346 A, "Device Separating Method of Semiconductor Device," Hynix Semiconductor Inc.; priority 2005‑11‑08; published 2007‑05‑11 (family‑cited).
• Status of verification: My search did not return usable content for this record. I cannot map it to claims. It is chronologically available prior art (published 2007), but its relevance here appears peripheral — the title suggests device isolation/STI, not a replacement‑gate densified‑ILD process — so it is likely cited for background structural content rather than the claim‑1 combination. I flag this as unverified.

5. Bottom-line §102 assessment

No single reference in either citation set anticipates claim 1 (and therefore none anticipates any of dependent claims 2–15), because claim 1 requires a specific ordered combination that no cited reference discloses as a whole:

1. form dummy gate stack (dielectric + electrode) → 2. form dielectric film → 3. thermally anneal the dielectric film to increase its density → 4. planarize to expose the dummy gate → 5. form a dense layer (increased density) on the dielectric film → 6. remove both dummy electrode and dummy dielectric to form the opening → 7. form gate dielectric + gate electrode in the opening.

The only examiner citation that touches the key concept — US 7,422,936 B2 (Intel) — implants to make a hard mask polish faster before planarization, i.e., the mirror image of the '481's post‑planarization, densifying silicon implant. The family‑cited US 8,431,453 B2 (TSMC) is the closest overall on the "implant the ILD surface to protect it during dummy‑layer removal" idea but uses carbon and lacks the claimed densification anneal, so it is §103 material, not §102.

6. Caveats

• These are preliminary analyst judgments, not a legal opinion; anticipation is a claim‑by‑claim, element‑by‑element inquiry requiring the full reference texts.
• Three references (US 9,082,789 B2, CN 101840862 B, KR 20070049346 A) could not be substantively retrieved; I have explicitly declined to infer their content. They should be pulled from their respective registers before any reliance.
• No contradiction was found between the supplied Google Patents text and the Justia/uspto.report mirrors.
• The Google Patents "Cited By" documents (e.g., US 2015/0380519, US 10,483,170, US 11,257,711) are later patents citing the '481 — they are not prior art and are outside this analysis.

Key URLs: https://patents.google.com/patent/US9190481/en · https://patents.justia.com/patent/9190481 · https://patents.google.com/patent/US7422936B2/en · https://patents.google.com/patent/US8658483 · https://patents.google.com/patent/US20050032286A1/en · https://patents.justia.com/patent/8431453

I'll verify the key prior-art references' disclosures before building the § 103 combinations.

Good — I have detailed disclosures for the two most on-point references. Let me check the remaining cited references for completeness.

Obviousness Analysis — U.S. Patent No. 9,190,481 B2 under 35 U.S.C. § 103

Builds on the two prior sections. Claim scope, the method-only claim set (single independent claim 1; claims 2–15 all dependent), and the two flagged discrepancies ("peak annealing process" vs. spec's "peak value annealing process"; and the "dose … atom/cm³" unit used for an implantation step) are taken as given and not repeated here. All prior art is drawn from the citation lists on the patent's own page (https://patents.google.com/patent/[US9190481](/patent/US9190481)/en), supplemented in one instance by corroborating printed publications found via search and expressly labeled.

1. Framework applied

Because the '481 has a 2014-01-21 effective filing date, AIA §§ 102/103 govern. Obviousness is assessed under the Graham factors (scope/content of the prior art, differences from the claims, POSITA level, secondary considerations) as refined by KSR Int'l v. Teleflex, 550 U.S. 398 (2007): a claim is obvious where the differences are such that the subject matter as a whole would have been obvious, and a combination is proper where (a) the elements existed in the prior art, (b) there was a reason to combine them, and (c) there was a reasonable expectation of success. KSR rationales relied on below: combining known elements according to known methods to yield predictable results; simple substitution of one known element for another; use of a known technique to improve a similar device in the same way; and "obvious to try" within a finite set of identified, predictable solutions. No teaching away and no unexpected results are present.

2. Level of ordinary skill (POSITA)

A POSITA here is an engineer or scientist with a B.S. (or M.S.) in EE, materials science, or chemical engineering plus ~3–5 years of semiconductor process-integration experience, including familiarity with: gate-last/replacement-metal-gate (RMG) HKMG flows; ILD/CESL deposition (including sub-atmospheric O₃/TEOS "HARP" CVD); CMP; ion implantation/plasma doping; and wet/dry dummy-gate removal. This is a mature, highly predictable art in which process-window choices are matters of routine optimization (In re Aller; In re Applied Materials).

3. The prior-art arsenal and its status

Supplementary art (not in the '481's own citation list — flagged): the Applied Materials Producer HARP™ product literature and patents/publications describing the standard O₃/TEOS HARP process and its required post-deposition densification anneal; US 7,642,171 B2 (multi-step anneal for film densification); KR 20070002304 A (HARP O₃-TEOS + subsequent high-temperature anneal); and US 2009/0098706 A1 (HARP O₃-TEOS gap-fill film plus ion implantation plus thermal treatment to densify and lower wet-etch rate). All predate 2014-01-21. URLs: http://www.appliedmaterials.com/products/assets/dielectric/16_HARP_noKPI.pdf ; https://patents.google.com/patent/[US7642171B2](/patent/US7642171B2)/en ; https://patents.google.com/patent/KR20070002304A/en ; https://patentimages.storage.googleapis.com/bf/24/3e/691577e4bbbab9/US20090098706A1.pdf

Important note for validity posture: the two references that map most squarely onto the '481's asserted points of novelty — TSMC's '453 and TSMC's '789 — appear only in the family-citation list, while the only examiner-cited art is Dongbu '286, Intel '936, and TSMC '483. Whether '453/'789 were substantively before the US examiner is unclear from the record; if they were not, the "no prior art closer than that of record" presumption is unavailable. This is a material vulnerability flag, not a legal conclusion.

4. The two asserted points of novelty are each separately known

The prior sections identified the novelty as (i) the post-deposition densifying anneal of the ILD, and (ii) the post-planarization implanted "dense layer." Each is independently taught:

(i) Densifying anneal is the standard, required HARP step. Applied Materials' HARP literature states: "After deposition, the HARP STI film requires a densification anneal in a furnace (typically between 900 °C and 1050 °C for 30 min). This anneal reduces the wet etch rate, drives out moisture and improves the density of the film." US 7,642,171 B2 teaches a >800 °C anneal that "acts to densify the dielectric material" and lowers the wet-etch-rate ratio. Claim 1's "performing a thermal annealing process … to increase the density" and claim 8's ">800 °C" are therefore squarely known.

(ii) Ion-implanting the exposed ILD to form a protective surface layer before dummy removal is taught by TSMC '453. Claim 1 of '453 is, in substance: after planarizing to expose the dummy gate electrode, "doping a surface layer … wherein the doped surface layer includes a doped ILD surface layer of the ILD layer; and removing the exposed dummy gate electrode layer, wherein the doped ILD surface layer reduces the loss of the ILD layer." '453 claim 14 extends this to removal of the dummy gate dielectric as well, and '453 claim 15 to the planarize-then-dope order. TSMC even identifies the identical failure mode the '481 recites — ILD "dishing" and residual conductive metal in the dips causing shorting/yield loss (see '453 specification re FIGS. 1C–1F).

5. Combination 1 (primary, §103): TSMC '453 + HARP densification art

Every claim-1 limitation is met:

The sole residual difference is the implant species (silicon instead of carbon/boron) and the label "dense layer having an increased density." That difference is an obvious design choice: (a) both are known implant species routinely available in any fab; (b) silicon implantation into SiO₂/SiN is the textbook way to form silicon-rich oxide/nitride, which is known to be denser and more etch-resistant; (c) '453 itself frames the doping step generically ("The dopants … may contain carbon (C), boron (B), or a combination thereof"), inviting routine selection of alternatives; and (d) the claimed result (a protective surface layer preventing ILD/CESL loss during dummy-layer removal) is exactly the result '453 reports. Under KSR, "a simple substitution of one known element for another" yielding predictable results is obvious. Additionally, because claim 1 states the dense layer functionally ("having an increased density") rather than structurally, a prior-art layer that inherently performs the same etch-protection function is not avoided merely by a different label (In re Schreiber).

6. Combination 2: adding Intel '936

Intel '936 supplies an independent, explicit motivation for the implant step in an RMG flow: it implant[s] said hard mask to make said hard mask easier to polish off and "make it more easily removable by a wet etch process." Intel thus teaches the general principle that in replacement-gate processing, one implants a region to tailor its removal characteristics relative to a subsequent polish/etch. A POSITA looking to keep the ILD/CESL intact while the dummy layers are etched would naturally extend Intel's implant-to-modify-removal teaching to the ILD surface, particularly with '453 showing precisely that. Combination 2 = '453 + Intel '936 + HARP densification art.

7. Combination 3: adding Dongbu '286 for claims 9–11 and 13–15

Dongbu '286 (on the face of the '481) supplies the multi-region, masked-selective dummy-gate-removal teaching that the dependent claims recite:

• Claim 9 (core + peripheral regions, dummy gates in each, source/drains): '286 defines plural device regions with dummy gates and source/drain implants; '453 shows plural gate structures. Combining a core/peripheral split into an RMG flow is routine — the regions simply have different EOT/performance targets.
• Claim 10 (mask peripheral; remove core dummy gate electrode + dielectric → first opening; remove mask and peripheral dummy gate electrode → second opening): '286 explicitly teaches selectively removing dummy gates region-by-region to form holes, then filling them.
• Claim 11 (pad oxide at bottom of first opening): '453 itself references an interfacial oxide layer under the high-k layer; such a pad/interfacial oxide is ubiquitous.
• Claims 13, 14, 15 (poly-Si dummy gate; SiO₂ dummy gate dielectric by thermal oxidation; removed by wet etch): '286 teaches a first oxide layer formed by thermal oxidation and dummy-gate removal by wet etching (hot phosphoric acid); '453 teaches polysilicon dummy electrodes and wet removal. Intel '936 also contemplates wet-etch removal of a sacrificial layer.

8. Claim-by-claim disposition (preliminary)

9. Motivation to combine (KSR rationales, expressly articulated)

1. Same field / same problem. All primary references are RMG/HKMG fabrication art addressing the same failure mode — thinning/dishing of the ILD (and CESL/spacer loss) during dummy-layer removal, leading to residual metal and leakage. The '481's own Background recites this exact problem; '453 recites it too. Combining references that solve the identical problem is the paradigm KSR case.
2. Known technique improving a similar device in the same way. Densifying a deposited oxide by annealing to reduce its wet-etch rate is a known, standard technique (HARP densification anneal). Applying it to the ILD of a gate-last flow to reduce ILD loss during dummy-gate removal is a predictable application.
3. Known element substitution. Si for C/B as the implant species — a finite, identified, predictable set of dopants with the known result of a denser, etch-resistant surface layer.
4. "Obvious to try." With only two identified solutions to the same problem (densify the film, and/or implant the film surface), a POSITA would predictably try the second in view of the first, or vice versa.
5. Design incentives / process compatibility. Both the anneal and the implant are already in the gate-last thermal/implant budget; adding them costs no new mask layers, which is itself a recognized design incentive.
6. No teaching away. '453's preference for carbon (noting lower dielectric constant) is at most a preference among known alternatives; it does not criticize or discourage silicon, and the claim's required function (etch-protection) is served either way.

10. Anticipated counterarguments and rebuttals

• "'453 uses carbon/boron, not silicon — the '481 claims silicon and a silicon-rich oxide/nitride layer." → Obvious substitution between known implant species; and claim 1 recites the layer functionally ("increased density"), which '453's doped layer inherently performs. Also, claim 7's own numeric limits are so broad ("dose … > 1E15," energy 0.5–3 KeV) that they fall within '453's disclosed ranges.
• "The '481 anneals before planarizing; '453 anneals after doping." → The pre-CMP densification anneal is the standard HARP step; the ordering is dictated by the process (densify, then polish), and '453's post-doping anneal is in any event an optional step that does not teach away.
• "Nonobvious because the dense layer is silicon-rich nitride on the CESL." → Claim 1 requires the dense layer "on the dielectric film," not specifically over the CESL; the CESL variation appears only in the specification's embodiment and is not a claim-1 requirement.
• "Unexpected results." → The specification reports no comparative data showing criticality of >800 °C, 0.5–3 KeV, 10–30 Å, or Si vs. C/B; these read as routine optimization. No nexus between any objective indicium and the claimed features is established on the present record.

11. Secondary considerations

No evidence of record supports commercial success, long-felt-but-unsolved need, failure of others, copying, or industry praise tied to the claimed features. Given the owner is a foundry and the claims cover internal manufacturing methods (difficult to detect and assert), objective indicia are unlikely to be probative. Absent a nexus, they do not overcome the strong §103 case above.

12. Bottom line

Claim 1 and its dependents are highly vulnerable under §103. The strongest combination is US 8,431,453 (TSMC) as the primary reference, in view of the standard HARP densification-anneal art (Applied Materials HARP literature; US 7,642,171 B2; KR 20070002304 A), optionally further in view of Intel US 7,422,936 B2 (implant-to-facilitate-removal) for claims 1/7 and Dongbu US 2005/0032286 A1 for claims 9–11 and 13–15. The '481's two asserted points of novelty are each separately known, the only substantive difference (Si vs. C/B implant) is an obvious substitution with a predictable result, and the claimed numerical ranges are routine optimizations. Claims 6 and 8 are the most exposed individually (HARP is literally an O₃/TEOS process and its densification anneal is 900–1050 °C); claims 12–15 are effectively standard-art recitations.

Caveats. (i) This is a technical-analyst assessment, not a legal opinion; obviousness is a legal conclusion for which the full prosecution record, any Rule 132/131 declarations, and the actual claim-construction positions matter. (ii) I relied on the prior art listed on the patent's page plus clearly labeled supplementary printed publications; a professional prior-art search (including non-patent literature and foreign art, e.g. the CN family) could strengthen or weaken these combinations. (iii) The factual characterizations of '453 and '936 are grounded in the sources fetched above (https://patents.google.com/patent/US8431453 ; https://www.freepatentsonline.com/[7422936](/patent/7422936).html) and in the '481's own citation list; where the '481 and a reference conflict, the supplied '481 text controls per the operating rules. (iv) I have not verified whether TSMC '453 and '789 were substantively before the US examiner — that single fact materially affects the "unexpectedly strong record" framing and should be confirmed from the file history.