US 8984228

I'll search for authoritative information on US 8984228, including any 2026 CAFC activity.

Let me check for CAFC activity and the PTAB/litigation status specifically.

Let me do one final targeted check for any Federal Circuit 2026 docket tied to this patent or the IPR.

US Patent 8,984,228 — Analyst Summary

Important caveat on search scope: I was able to retrieve the Google Patents full text (authoritative, cited below) plus USPTO PTAB records and district-court docket data. However, I found no Federal Circuit (CAFC) 2026 docket or appeal for this patent or for IPR2025‑00207. Multiple targeted searches for a 2026 CAFC appeal returned nothing. I therefore cannot confirm any Federal Circuit activity in 2026 — treat that as an explicit uncertainty rather than a negative fact.

Bibliographic data (per the authoritative patent text)

Note: Several third‑party case summaries label the title "Multiprocessor Cache Coherency." That is a paraphrase used in PTAB‑summary databases, not the patent's actual title.

Abstract (verbatim)

"In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed."

Plain-language overview of the independent claims

Claim 1 (apparatus) — A multicore processor with (a) multiple cores, (b) a shared cache, (c) an integrated I/O ("IIO") module that interfaces the processor to an external I/O device, and (d) one caching agent that handles cache coherency for both the cores and the IIO module. The agent is a single caching agent made up of distributed portions, each tied to a corresponding core. The core idea: instead of giving the integrated I/O block its own dedicated coherency/caching agent (which multiplies the number of agents in a multi‑socket system and hurts scaling), the I/O traffic is proxied through the CPU's own caching agent.

Claim 11 (method) — A three‑step flow: (1) the IIO module receives an "allocation transaction" from an I/O device; (2) that transaction is forwarded to a caching agent shared by the processor's cores and the IIO module; and (3) the data is stored directly into the shared cache. This is the "direct push" concept — I/O data lands in cache without first going to system memory and without a DCA hint to a core.

Claim 16 (system) — A two‑socket system: first and second multicore processors, each with cores, a shared cache, an IIO module, and its own caching agent performing coherency for its cores and IIO module, plus a peripheral controller coupled to at least one processor. The first caching agent's table of requests has multiple entries for pending core/IIO requests, including at least one dedicated entry reserved for a posted transaction (the anti‑deadlock mechanism).

Representative dependent claims: cl. 3 (dedicated TOR entry for a posted transaction); cl. 4/5 (LLC with distributed portions coupled via a ring interconnect); cl. 7 (direct store without initiating a memory transaction); cl. 8 (sending a "drop ownership" indication to the IIO on a snoop hit — the deadlock‑avoidance mechanism); cl. 12/13/14 (data accessed by cores repeatedly without memory traffic; write‑back only on eviction of modified data).

2024–2026 enforcement / validity activity

PTAB — IPR2025‑00207, Arm Ltd. and MediaTek Inc. v. Daedalus Prime LLC (filed Dec. 13, 2024; challenged claims 1‑7, 11‑14, 16‑19):

• Grounds: obviousness over Agarwal (US 7,805,575); over Sinharoy (IBM POWER7 article, 2011); Sinharoy + Blumrich (US 2011/0219188); Sinharoy + Sistla; etc.
• May 16, 2025: Acting Director Stewart granted Daedalus's Fintiv discretionary‑denial request (Paper 10).
• Aug. 6, 2025: Acting Director granted Director Review, vacated the denial, and referred the petition to the Board (Paper 14) — because the parallel EDTX case had settled. This was the first reversal of a bifurcated‑process discretionary denial. Source: https://www.uspto.gov/sites/default/files/documents/IPR2025_00207_paper_14_.pdf
• Sept. 25, 2025: Institution granted (35 U.S.C. § 314).
• Oct. 27, 2025: MediaTek settled/terminated as petitioner; Arm remains as sole petitioner.
• Dec. 17, 2025: Patent Owner Response filed. Mar. 10, 2026: Stipulation to modify due date. → Still pending in 2026 (per IP Verse case tracker).

District court:

• Daedalus Prime LLC v. MediaTek Inc., 2:24‑cv‑00235 (E.D. Tex.) — terminated (settled May 2025).
• Daedalus Prime LLC v. Google LLC, 7:25‑cv‑00313 (W.D. Tex.) — pending.
• Daedalus Prime LLC v. Marvell Technology, Inc., 7:25‑cv‑00413 (W.D. Tex.) — pending.

Related child patent: US 9,575,895 was held unpatentable over Sinharoy in IPR2023‑01344 (Final Written Decision, Jan. 24, 2025); Daedalus did not appeal, which the IPR2025‑00207 petitioner argued creates estoppel‑type effects. This is the Board's statement that "substantially identical claims" in the child are unpatentable.

Bottom line / uncertainties

• The patent is a 2011 Intel processor/cache‑coherency filing now owned by Daedalus Prime LLC, asserted in multiple 2024–2025 district‑court suits and under live IPR attack in 2026.
• No 2026 Federal Circuit appeal was found. If you need a definitive CAFC check, I would verify directly via the Federal Circuit's PACER/CM‑ECF docket and the USPTO Patent Trial Appeal Board's appeal docket, since my web searches did not surface any 2026 CAFC case tied to US 8,984,228 or IPR2025‑00207.
• The PTAB summary databases describe the title as "Multiprocessor Cache Coherency"; the official title per the patent itself is the one given in the bibliographic table above.

I'll search for litigation involving US patent 8984228. Let me run several targeted searches.

Let me gather more details on each case, including filing dates and outcomes.

Litigation Involving U.S. Patent No. 8,984,228

Patent identified as: US 8,984,228 B2 (application 13/324,053, "Providing common caching agent for core and integrated input/output (IO) module"), filed December 13, 2011, granted March 17, 2015, originally assigned to Intel Corporation, reassigned to Daedalus Prime LLC on June 6, 2022. Daedalus Prime is the plaintiff/patent owner in the infringement suits below.

The most authoritative source for the asserted-patent litigation history is the Patent Owner's mandatory notice filed by Daedalus Prime in the PTAB proceeding IPR2025-00207 (dated September 25, 2025), which expressly lists the district court cases in which the '228 patent "is/was at issue." I've combined that with docket and PACER-derived records.

1. Daedalus Prime LLC v. MediaTek Inc.

• Plaintiff: Daedalus Prime LLC
• Defendant: MediaTek Inc. (also MediaTek USA in related actions)
• Jurisdiction: U.S. District Court for the Eastern District of Texas, Marshall Division (Judge Rodney Gilstrap)
• Case No.: 2:24-cv-00235-JRG
• Filing date: April 8, 2024 (complaint alleging infringement of eight U.S. patents)
• Outcome/status: Terminated. On August 5, 2024 MediaTek moved to dismiss in part. Judge Gilstrap granted the motion in part by Memorandum Opinion and Order dated March 12, 2025, dismissing (i) the § 271(f) infringement allegations and (ii) the pre-suit willfulness allegations for failure to plead sufficient facts. The case is listed as terminated; the '228 patent was among the patents placed at issue.

2. Daedalus Prime LLC v. Google LLC

• Plaintiff: Daedalus Prime LLC
• Defendant: Google LLC
• Jurisdiction: U.S. District Court for the Western District of Texas, Waco Division
• Case No.: 7:25-cv-00313
• Filing date: July 14–15, 2025
• Outcome/status: Pending / Open. Google filed a Rule 12(b)(6) motion to dismiss the claims for pre-suit willful and indirect infringement on September 26, 2025; numerous pro hac vice appearances (Silbert, Sun, Bruns, Concilla, Sachdeva, etc.) were entered in late September 2025. Still open as of the available records.

3. Daedalus Prime LLC v. Marvell Technology, Inc.

• Plaintiff: Daedalus Prime LLC
• Defendant: Marvell Technology, Inc.
• Jurisdiction: U.S. District Court for the Western District of Texas, Waco Division (initially assigned to Judge David Counts; reassigned to Judge Alan D. Albright)
• Case No.: 7:25-cv-00413
• Filing date: September 7–8, 2025 (complaint for patent infringement and damages; accusatory products include the Marvell OCTEON 10 DPU)
• Outcome/status: Conflicting records. Daedalus Prime's Sept. 25, 2025 mandatory notice in IPR2025-00207 lists this case as "Pending." However, the Unified Patents litigation portal (searching patents-in-case) shows this case as Closed, and the Ex Parte AI-Lab tracker also shows status "Closed." I could not determine from the available records whether the "Closed" status reflects a dismissal/settlement or simply a data-update artifact; treat the closure with caution and verify against PACER.

Related PTAB (post-grant) proceeding — IPR2025-00207

Not a district court case, but directly involves the '228 patent:

• Proceeding: IPR2025-00207 (inter partes review)
• Petitioners: Arm Ltd. and MediaTek, Inc.
• Patent Owner: Daedalus Prime LLC
• Filed: December 13, 2024
• Status: Instituted / Trial ongoing (as to Arm). The Board issued an Order (Aug. 6, 2025) granting Director Review, vacating the earlier denial of institution, and referring the petition to the Board; institution was granted September 25, 2025. A Joint Motion to Terminate as to Petitioner MediaTek, Inc. (with a sealed settlement agreement) was filed October 27, 2025, and the proceeding continues as to Arm Ltd. Google Patents characterizes the family's PTAB proceeding as "filed (Settlement)" for MediaTek. Patent Owner's Response was filed December 17, 2025; a stipulation to modify due dates followed in March 2026.

Notes / caveats

• Two of the three district court suits (Google and Marvell) assert multiple patents; the '228 patent's inclusion in those cases is confirmed by Daedalus Prime's own mandatory notices and by the Google Patents family litigation links (which cite the W.D. Tex. cases 7:25-cv-00413 and 7:25-cv-00313 and the E.D. Tex. case 2:24-cv-00235).
• Separate-but-related: Daedalus Prime's other suits (e.g., v. Samsung, 2:22-cv-00352 E.D. Tex.; v. Taiwan Semiconductor Mfg. Co., 2:23-cv-00299 E.D. Tex.; v. Mazda/Mercedes-Benz/MediaTek/Visteon, 1:22-cv-01108 D. Del.; TSMC v. Daedalus Prime/Intel, 1:22-cv-01647 D. Del.) asserted different patents (e.g., 8,775,833; 8,898,494; 10,049,080; 10,705,588; 9,831,306; 10,319,812; 10,700,178; 11,251,281). Do not attribute those to the '228 patent. Likewise, IPR2023-01344 (Mercedes-Benz USA, LLC v. Daedalus Prime LLC, now terminated) involved the child patent US 9,575,895, not the '228 patent itself.
• I did not find any Court of Appeals for the Federal Circuit appeal involving the '228 patent.
• Because docket databases lag or conflict (note the Google/Marvell status discrepancies), the definitive current status should be confirmed on PACER and on the Unified Patents litigation portal (https://portal.unifiedpatents.com/litigation/caselist) at the time of use.

Primary grounding sources: IPR2025-00207 mandatory notice (PTAB, Sept. 25, 2025, Patent Owner Daedalus Prime via counsel Tarek N. Fahmi); ipverse.greyb.com IPR2025-00207 case page; law.justia.com Memorandum Opinion & Order, Daedalus Prime LLC v. MediaTek Inc., 2:24-cv-00235 (E.D. Tex. Mar. 12, 2025); dockets.justia.com and PACER Monitor dockets for 7:25-cv-00313 (Google) and 7:25-cv-00413 (Marvell); Google Patents US 8,984,228 page.

I'll start by reconciling the structured ODP block (which reports no AIA trials) against the litigation/legal-events data embedded in the patent record, which shows an IPR. Let me search.

Good — substantive material found. Let me pull the institution decision details, the related child-patent FWD, and any 2026 developments.

Let me check the most recent status (any FWD in 2026) and the panel composition.

⚠️ Threshold flag: the structured ODP block and the record disagree

The canonical "PTAB proceedings on file" block in this prompt reports no AIA trial proceedings returned by the USPTO Open Data Portal for US 8,984,228. That is wrong as a matter of fact, and the error is material to a defendant's strategy. Two independent sources inside the very same patent record contradict it:

• The Google Patents Legal Events table lists: "2025-01-21 — IPR — AIA trial proceeding filed before the patent and appeal board: inter partes review, TRIAL NO: IPR2025-00207, Opponent name: ARM LTD., AND MEDIATEK, INC., Effective date: 20241213."
• The "Family has litigation" block lists "PTAB case IPR2025-00207 filed (Settlement)" and links to https://portal.unifiedpatents.com/ptab/case/IPR2025-00207.

Web search confirms the proceeding is real, actively litigated, and instituted — see the Acting Director's institution-vacatur order at https://www.ptablitigationblog.com/wp-content/uploads/2025/05/IPR2025-00207.pdf and the docket summary at https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2025-00207. Do not rely on the ODP block for this patent. The ODP ingest is stale; the Google Patents "Settlement" tag appears to reflect the MediaTek settlement/termination, not the death of the whole proceeding.

Proceedings overview

One AIA trial proceeding is on file against US 8,984,228 — IPR2025-00207 (Arm Ltd. + MediaTek Inc. v. Daedalus Prime LLC), filed 2024-12-13, instituted 2025-09-25, and still active at the trial stage with no Final Written Decision as of 2026-09-10; no challenged claim has been canceled, and MediaTek was terminated on settlement while Arm carries the case alone — so the defensive posture is "the patent is under live, serious § 103 attack but presently fully intact," and the single most useful fact for a defendant is that the Board already invalidated substantially identical claims of the child patent 9,575,895 over the same Sinharoy reference.

Status breakdown: active: 1 | claims invalidated: 0 | claims sustained: 0 | settled (as to one petitioner only): 1 | institution denied: 1 (denial subsequently vacated by the Director and superseded by institution).

IPR2025-00207 — Arm Ltd. and MediaTek Inc. v. Daedalus Prime LLC

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2024-12-13 (notice of filing date accorded 2024-12-30)
• Status: Trial instituted. Structured-source gloss: "Trial Instituted" (IP Verse, data current 2026-08-05); Google Patents tags the family entry "(Settlement)," which reflects only the MediaTek settlement/termination. No FWD has issued; no claims have been canceled.
• Judge panel: Not confirmed from the sources retrieved. The docket shows a Panel Change Order dated 2025-10-31, but I could not retrieve the APJ names for this panel and will not guess them. (Verify on PTAB E2E / PTABIS before any filing that depends on panel composition.) Counsel of record: for Petitioner — Kevin Anderson and Patrick McPherson (Duane Morris LLP) and Cory Bell, Joseph Long, Alexander Boyer (Finnegan); for Patent Owner — Tarek Fahmi and Jonathan Tsao (Ascenda Law Group PC).
• Petition grounds: All grounds are § 103 obviousness. Challenged claims: 1–7, 11–14, and 16–19 (i.e., every claim except 8–10 and 15).
  • Ground 1: claims 1–2, 4–7, 11–14 obvious over Agarwal (US 7,805,575) — Agarwal's distributed "proxy cache coherence" directory controllers across tiles read on the claimed "single caching agent … including a plurality of distributed portions."
  • Ground 2: claims 1, 4, 6, 7, 11–14 obvious over Sinharoy ("IBM POWER7 Multicore Server Processor," IBM J. Res. & Dev., vol. 5, no. 3 (2011)) — POWER7's distributed L3/coherence fabric as the single distributed caching agent, plus "cache injection" for the direct-to-cache IIO write limitations.
  • Ground 3: claims 2, 3, 16–18 obvious over Sinharoy in view of Blumrich (US 2011/0219188) — request queue teaching for the "table of requests" and "dedicated entry … for a posted transaction."
  • Additional grounds: claim 5 over Sinharoy + Sistla (US 2008/0126750) for the ring interconnect; claim 19 over Sinharoy + Sistla + Blumrich.
  • Supporting declaration of Dr. Marwan Hassoun. Full exhibit list and petition attachments are on PTABIS at https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556969](/patent/1556969)/download-documents?artifactId=kziqrocmlConxMKbr0b9xpJhY5svzQ19GUCJ4o-ROPRLdpGIhv_YpUA
• Institution decision: Denied, then vacated, then granted — a genuinely unusual sequence.
  1. 2025-05-16 — Acting Director Coke Morgan Stewart granted Patent Owner's Request for Discretionary Denial and denied institution (Paper 10), one of the first four decisions under the new bifurcated pre-institution process. Reasoning: the projected FWD was June 2026 while the parallel E.D. Tex. trial was set for 2026-01-26 with time-to-trial statistics pointing to a March–May 2026 trial; the FWD would not land before trial, and there was insufficient evidence the district court would stay. Decision: https://www.ptablitigationblog.com/wp-content/uploads/2025/05/IPR2025-00207.pdf
  2. 2025-08-06 — Acting Director granted Arm's Request for Director Review, vacated the denial, and referred the petition to the Board (Paper 14), citing changed circumstances: Daedalus and MediaTek filed a notice of settlement on 2025-05-15 (one day before the denial) and the district court dismissed about a week later. She wrote: "Now that the litigation has been dismissed, the balance of factors weighs in favor of referral," and "[b]ecause the Board already has determined that 'substantially identical claims' in a related patent to the challenged patent are unpatentable … it is efficient for the Board to take up this case." This was the first time the Acting Director reversed her own bifurcated-process discretionary denial. Analysis: https://www.jonesday.com/en/insights/2025/09/acting-director-reverses-previous-discretionary-denial
  3. 2025-09-25 — Decision Granting Institution of Inter Partes Review (35 U.S.C. § 314), with a Scheduling Order issued the same day. I could not verify from the retrieved sources whether institution was granted on all challenged claims or a subset; treat the instituted claim set as unconfirmed and check the decision itself.
• Final Written Decision: None issued as of 2026-09-10. No claim of US 8,984,228 has been canceled or sustained; the patent stands with all 19 claims.
• Settlement / termination: As to MediaTek only. On 2025-10-27 Petitioner filed a Joint Motion to Terminate Proceeding as to Petitioner MediaTek Inc., together with a Joint Request to Treat Settlement Agreement as Business Confidential Information under 35 U.S.C. § 317(b) and a [SEALED] Confidential Settlement Agreement exhibit. Terms are confidential. I could not retrieve the order granting the termination from the sources searched; the docket continues to list the proceeding as instituted, and Arm is proceeding alone.
• Appeal: None possible yet — no FWD. The only "appellate" event to date is the Director Review under 37 C.F.R. § 42.75 (request filed 2025-06-11 / Arm's request 2025-06-13; PO authorized response 2025-06-20; order 2025-08-06). A § 141/§ 142 Federal Circuit appeal would lie only after an FWD.
• Trial-stage milestones:
  • PO Response filed 2025-12-17 (with Ex. 2006, Declaration of Dr. Bagherzadeh, and Ex. 2007, transcript of the deposition of Dr. Hassoun). Notice of deposition of Dr. Hassoun was served 2025-11-10.
  • Stipulation to Modify Due Date filed 2026-03-10 (Petitioner) — the schedule has been adjusted; confirm the operative due dates.
  • Statutory FWD deadline: 35 U.S.C. § 316(a)(11) — 2026-09-25 (one year from the 2025-09-25 institution), extendable for good cause by up to six months to roughly 2027-03-25. The original pre-vacatur projection was June 2026. Oral hearing should be expected in the weeks before the FWD deadline; check PTABIS for the hearing notice.
• Defensive value: Arm has not won anything yet, so nothing here kills a claim — but the reason the Director revived this case is the whole ballgame: the Board has already held "substantially identical" claims of the child patent 9,575,895 unpatentable over Sinharoy, and the Director called it "efficient" to take up the same question. A defendant facing assertion of the '228 patent should treat this record as a roadmap, not a reprieve. Conversely, MediaTek's settlement means MediaTek is not estopped (§ 315(e) estoppel attaches only after an FWD), so MediaTek retains a full set of grounds notwithstanding its own petition.

Related proceeding on the child patent (NOT a proceeding on 8,984,228 — but decisive context)

IPR2023-01344 — Mercedes-Benz USA, LLC et al. v. Daedalus Prime LLC (U.S. Patent 9,575,895)

• Type: Inter Partes Review
• Filed: 2023-08-23 | Instituted: 2024-03-05
• Patent: US 9,575,895 B2 — the continuation of Application 13/324,053, which issued as US 8,984,228. The two share specification and substantially identical claim 1.
• Status: Final Written Decision issued 2025-01-24 (Paper 31).
• Judge panel: Administrative Patent Judges Gregg I. Anderson (writing), James P. Calve, and Arthur M. Peslak.
• Petition grounds: challenged claims 1–17 of the '895 patent; the FWD turned on Sinharoy.
• Final Written Decision: "Petitioner has proven by a preponderance of the evidence that all of the challenged claims of the '895 patent are unpatentable." The Board also rejected Patent Owner's claim-construction arguments on the "single caching agent" term (FWD at 23–28) — the same term that is claim 1 of the '228 patent. A hearing was held 2024-12-09 (Paper 30). Document: https://bannerwitcoff.com/wp-content/uploads/2025/01/IPR2023-01344.pdf
• Appeal: I found no Federal Circuit appeal. Petitioner's Director Review request in IPR2025-00207 represents that "the PO did not appeal the findings in the FWD." I could not independently confirm a CAFC docket; verify on CourtListener before relying on it.
• Defensive value: This is the single most powerful prior-art asset against the '228 patent. Claim 1 of the '895 was invalidated over Sinharoy notwithstanding the same "single caching agent" construction fight, and Arm is now running Sinharoy (Ex-1006) against claim 1 of the '228 patent in IPR2025-00207 because of this FWD.

Strategic summary

Claim status on US 8,984,228. Every claim is live and enforceable. The IPR challenged claims 1–7, 11–14, and 16–19 and the proceeding is at the PO-Response stage with no FWD; nothing has been canceled or sustained. The claims never put at issue in IPR2025-00207 are 8, 9, 10, and 15 — the "drop ownership indication" family (claim 8 apparatus, claim 9 the prefetched-cache-line limitation, claim 10 the "another agent is one of the plurality of cores" limitation, claim 15 the method counterpart). That is a double-edged sword: Daedalus cannot lose those claims at the PTAB, but they also have no PTAB-ready invalidity record, so a defendant must build that ground from scratch. By contrast, claims 1–7, 11–14, and 16–19 face a pending § 103 record built on Agarwal and Sinharoy, and the Sinharoy theory has already succeeded against the mirror-image claims of the '895 patent. Note also the substantive weakness on the face of the record: claims 8–10 and 15 are the only claims that capture the drop-ownership deadlock-avoidance feature the specification itself stresses — the challenged independent claims are largely architecture claims that the Board has already read narrowly on "single caching agent."

Estoppel landscape. There is no § 315(e)(2) estoppel yet — estoppel applies only after an FWD. Arm remains in the case, so Arm will be estopped post-FWD as to grounds raised or reasonably raisable; MediaTek exits the IPR via settlement without estoppel and retains its full invalidity case (including its E.D. Tex. contentions, which per PO's exhibits included both Agarwal and Sinharoy — see Ex. 2003/Ex. 2004 in IPR2025-00207). For a defendant being asserted today: all prior-art grounds are available, including § 102 art, system art, and combinations beyond Agarwal/Sinharoy/Blumrich/Sistla. But be candid about the risk of issue overlap — a district court facing the same Sinharoy argument that already killed the '895 claims will scrutinize it closely, and a defendant that sits out of the IPR while Arm wins one will be litigating against a strengthened record rather than a weakened one.

Pattern signals. Daedalus Prime is a high-volume, well-funded monetization program: PTAB Track records show roughly 30 PTAB cases faced, with a 2023 wave of Mercedes-Benz IPRs (IPR2023-01333, -01335, -01343, -01344, -01345), a TSMC IPR settled (IPR2023-01120), and a 2024–2025 MediaTek wave (IPR2024-01488 and IPR2025-00100 terminated-settled; IPR2025-00207 settled as to MediaTek but alive as to Arm; IPR2025-00243 pending). Daedalus litigates in E.D. Tex. and W.D. Tex. (assertion metadata in the patent record points to 2:24-cv-00235 (E.D. Tex., dismissed after settlement with MediaTek) and W.D. Tex. cases 7:25-cv-00413 and 7:25-cv-00313). Note the asymmetry Daedalus is managing: it has repeatedly used settlement to knock petitioners out of IPRs, and here that tactic failed because a non-settling joinder petitioner (Arm) had independent interests — the first judicially recognized limitation on that playbook. There is no defensive aggregator in this specific chain; Unified Patents appears only as a docket-data aggregator in the Google Patents metadata, not as a petitioner.

Recommended next steps

1. Correct the record internally. If your file says "no PTAB activity on US 8,984,228," it is wrong. Pull the live docket at https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2025-00207 and PTABIS/PTAB E2E before you draft anything. The Google Patents "(Settlement)" tag is a trap — it describes the MediaTek leg only.
2. Calendar the FWD deadline: 2026-09-25, extendable to ~2027-03-25 for good cause, with the schedule already modified by the 2026-03-10 stipulation. If the FWD is imminent, a defendant weighing an IPR or a stay motion needs to know whether Arm wins or loses this month — and whether Arm's institution covered all of claims 1–7, 11–14, 16–19 or a subset.
3. Obtain the 2025-09-25 institution decision and determine exactly which claims were instituted. It is the one document I could not fully verify. Everything about a parallel IPR or a § 315(b) one-year bar analysis depends on it.
4. If you are a defendant with claims being asserted: your strongest near-term invalidity theory is Sinharoy against claim 1 and its dependents, backed by the IPR2023-01344 FWD invalidating the "substantially identical" claims of the child patent under the same "single caching agent" construction. Quote the disposition directly: "Petitioner has proven by a preponderance of the evidence that all of the challenged claims of the '895 patent are unpatentable" (IPR2023-01344, Paper 31 at 1). Anchor it to the FWD at https://bannerwitcoff.com/wp-content/uploads/2025/01/IPR2023-01344.pdf and, if a CAFC appeal exists, to the CourtListener docket.
5. If Daedalus is asserting claims 8–10 or 15, recognize that you have no PTAB record to borrow. Build the drop-ownership invalidity theory independently, or consider a follow-on IPR — the § 315(b) clock turns on service of the complaint in your case, not Arm's.
6. Watch for the FWD and for any appeal. If Arm loses, the patent is hardened and § 315(e)(2) will bar Arm (and potentially its privies) while leaving non-parties untouched. If Arm wins, claims 1–7, 11–14, and 16–19 are in serious jeopardy and a defendant's calculus flips hard toward a stay motion. Either outcome is worth a written watch instruction; the FWD will be public at PTAB E2E and the CAFC docket at CourtListener.

Caveats I will not paper over: I could not verify the APJ panel names for IPR2025-00207 (there was a 2025-10-31 Panel Change Order), the precise claim-level scope of institution, or the order granting MediaTek's termination. Verify all three on PTABIS before relying on them.

I'll start by verifying the assignment records and cross-referencing the assignees.

Good context on Daedalus Prime. Now let me pin down the specific assignment records and correspondents.

Let me look for the specific assignment record details and the correspondent of record.

Ownership & Assignment Analysis — US 8,984,228 B2

Patent: US 8,984,228 B2 — "Providing common caching agent for core and integrated input/output (IO) module"
App. No.: 13/324,053 · Filed: 2011-12-13 · Issued: 2015-03-17 · Adjusted expiry: 2033-07-30
Family: US 2013/0151782 A1 (pub.), US 9,575,895 B2 (continuation, app. 14/609,620), WO 2013/090297 A1, DE 112012005210 B4

Sourcing note (read first). I could not retrieve the raw assignmentcenter.uspto.gov / assignment.uspto.gov record pages for this patent — the Assignment Center UI is not retrievable by the search tools available to me, and queries returned no hits. Everything below is reconstructed from (a) the USPTO assignment data as republished in the patent's legal-events record, (b) the TSMC v. Daedalus Prime declaratory-judgment complaint (D. Del. 1:22-cv-01647) which quotes the assignment documents by frame number, and (c) PTAB filings. The correspondent of record on the recorded assignments is not disclosed in any source I could retrieve — see Signal 3, where I explicitly decline to guess. Verify the reel/frame entries directly at the Assignment Center link in the Verdict section.

Inventors

All seven are listed as assignors on the original Intel assignment (signed 2011-12-08 through 2012-04-04), which confirms Intel employment for each at filing. Two names are independently corroborable as Intel architecture personnel: Yen-Cheng Liu appears as sole inventor on US 2006/0053258 A1 ("Cache filtering using core indicators"), also Intel-assigned, and Sridhar Muthrasanallur / Bahaa Fahim are recurring names on Intel cache-coherency and interconnect filings.

Unusual-pattern check — negative. There is no evidence of the "all inventors depart the original assignee within 12 months of filing, pre-fire-sale" pattern. Intel retained the patent for ~10.5 years and the inventors are not named on any subsequent assignee-side record. I have no reliable data on inventor departure dates and decline to speculate.

Original assignee

Intel Corporation (Delaware), Santa Clara, CA — named on the issued patent as assignee.

• Primary line of business: fab and fabless design/manufacture of microprocessors, chipsets, and platform silicon. The claimed subject matter (a combined CPU/IIO caching agent in a multicore socket) is Intel's core server-processor architecture — this is a genuine product-embodying invention, not a paper patent. The claimed structure (single caching agent serving CPU cores and an integrated IIO module, ring-coupled distributed LLC slices) maps to Intel's server/CPU platform designs of that era.
• Product shipped? Yes — the assignee is an operating chipmaker and the patent is a platform-architecture patent arising from Intel's QPI/ring-interconnect server roadmaps. Note, however, that Intel's own practice of the claims is separate from whether the patent was thereafter monetized; Intel did not assert this patent. Intel divested it in 2022.
• Current status: Operating company; listed on Nasdaq (INTC). Not in bankruptcy. Intel has been under significant financial pressure and restructuring since 2024 (layoffs, foundry spin-out discussions), which is relevant background to the 2022 portfolio sale but does not make this a bankruptcy estate transfer.
• Note on the record: Intel Corporation is also the original assignee assignor on the 2022 transfer, and was named as a co-defendant in TSMC's D. Del. declaratory-judgment action (1:22-cv-01647) over the scope of the Intel→Daedalus transfer.

Assignment timeline

Two recorded assignments touch this patent post-issuance chain (plus the original prosecution assignment). There are no cascading multi-hop LLC transfers for this patent — the chain is a single hop from Intel to Daedalus Prime.

• 2011-12-08 → 2012-04-04 (executed, inventors' signing dates) / recorded 2012-04-09 — Reel 028011/0132

  • Conveyance: Assignment
  • Assignor: Yen-Cheng Liu; Robert G. Blankenship; Geeyarpuram N. Santhanakrishnan; Ganapati N. Srinivasa; Kenneth C. Creta; Sridhar Muthrasanallur; Bahaa Fahim
  • Assignee: Intel Corporation (California)
  • Correspondent: not disclosed in any retrievable source. This is the standard employee-invention assignment filed via Intel's in-house/docketing operation; the record does not surface a named attorney in the data I can reach.
  • Context: standard employment assignment — invention assigned to the operating-company employer at filing.

• 2022-06-03 (effective/executed) / recorded 2022-06-06 — Reel 060392/0594

  • Conveyance: Assignment
  • Assignor: Intel Corporation
  • Assignee: Daedalus Prime LLC (New York)
  • Correspondent: not disclosed in any retrievable source. (See Signal 3 — I have identifiable Daedalus-side litigation counsel, but not the recording correspondent, and I will not conflate the two.)
  • Context: bulk portfolio divestiture to a monetization vehicle — the same Reel 060392 carries frames ~0594–0603 for the other Intel patents in the same June 2022 transfer (e.g., frame 0603 for the sibling assets; TSMC's complaint cites "Frame 0603" for the executed Patent Assignment Agreement). Reported elsewhere as 122 Intel patents acquired by Daedalus Prime.
  • Related record (different patent): Reel 063695/0134 is a corrective assignment recorded 2023-05-18 correcting a patent number mis-identified at Reel 060392/0603 — it does not affect US 8,984,228 but shows active clean-up of the same bulk transfer.

No further recorded assignment to this patent appears in the legal-events record. The sibling continuation US 9,575,895 B2 follows the same Intel → Daedalus Prime path.

Timeline diagram

timeline
    title Ownership of US 8984228
    2011 : Filed by Intel inventors
    2012 : Assigned to Intel Corp
    2015 : Patent issued
    2022 : Intel assigns to Daedalus Prime LLC
         : Daedalus launches assertion campaign
    2024 : Daedalus sues MediaTek naming this patent
         : Arm and MediaTek file IPR2025-00207
    2025 : PTAB institutes inter partes review

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Reel 060392/0594, effective 2022-06-03, recorded 2022-06-06: Intel Corporation → Daedalus Prime LLC, a licensing-only entity. Concretely (not by name inference): (a) Daedalus Prime holds patents but sells/licences rather than ships — RPX describes it as an NPE plaintiff, IAM classifies it as an NPE, and TSMC's D. Del. complaint states flatly "Daedalus is an NPE"; (b) it operates from small-office addresses (75 South Riverside Avenue, Unit B, Croton-on-Hudson, NY 10520 per its PTAB power of attorney; Bronxville, NY per contemporaneous press); (c) it has no products in commerce and no foundry/design activity; (d) it is a single-purpose assertion vehicle related to Daedalus Group LLC and Daedalus Blue LLC, all managed under one principal (Ed Gomez, "Managing Principal"). Registered-agent-service status is not established by the sources I have — I mark the address element as unverified, but the no-products + multi-LLC-single-principal facts are documented.

2. Known asserter in the chain — PRESENT.
Daedalus Prime LLC is not on the enumerated classic list (Acacia, Marathon, IV, IPNav, Wi-LAN/Mosaid-Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg), but the instruction includes "any entity surfaced by Unified Patents or RPX as a high-frequency plaintiff," and it qualifies:

• Unified Patents PTAB data on the patent page itself links an IPR campaign (IPR2025-00207).
• RPX ("Semiconductor Litigation Surged in Q3") names Daedalus Prime as a top Q3-2022 semiconductor NPE plaintiff.
• Independent counts: #1 US plaintiff against Korean companies in 2022 (10 filings; 122 Intel patents held), per the Korean Intellectual Property Office as reported by KED Global.
• ES-District docket evidence: Daedalus Prime LLC v. MediaTek, No. 2:24-cv-00235 (E.D. Tex., filed 2024-04-08); D. Del. DJ action 1:22-cv-01647; ITC complaints against TSMC and others (Sept. 2022).

3. Repeat correspondent across the chain — UNCLEAR (and deliberately not asserted).
There is only one post-issuance assignment in this chain (Reel 060392/0594), so there is no in-chain recurrence to cite. I could not identify the attorney/agent of record who filed either the 2012-04-09 Intel recording (028011/0132) or the 2022-06-06 Daedalus recording (060392/0594) — the correspondent field is not exposed in the sources I could retrieve. Separately, and not a substitute for that finding: Tarek N. Fahmi (USPTO Reg. No. 41,402), Ascenda Law Group, PC, San Jose, CA is Daedalus Prime's recurring PTAB counsel — Appearing on IPR2025-00243 and identified as respondent counsel on IPR2025-00207 (this patent); Mintz Levin (Peter F. Snell et al.) appears for Daedalus Prime in IPR2023-00567. A litigator recurring across an NPE's IPRs is a real pattern, but it is not the assignment-record correspondent signal the brief asks about. Flagged as a lead to verify against the Assignment Center correspondent fields, not as a finding.

4. Cascading transfers — NOT PRESENT (for this patent).
US 8,984,228 moves through exactly two recorded assignments: employees→Intel (2012, Reel 028011/0132) and Intel→Daedalus Prime (2022, Reel 060392/0594). No chained LLC hops, no <24-month multi-link sequence. The 2022 event is a bulk single-reel portfolio transfer (Reel 060392 spanning many patents/application numbers), not a cascade.

5. Pre-litigation transfer — PRESENT.
The Intel→Daedalus assignment is effective 2022-06-03 (recorded 2022-06-06). Daedalus Prime's first assertion campaign followed within roughly 10 weeks — suits against MediaTek, NXP and Qualcomm (automotive infotainment) in August 2022, and ITC/E.D. Tex. actions in September 2022. That timing is what a pre-litigation acquisition looks like: the portfolio was acquired specifically to enable assertion. Caveat for precision: the suit that actually names this patent (Daedalus Prime v. MediaTek, 2:24-cv-00235) was filed 2024-04-08, which is ~22 months after the transfer — so the strict "within 6 months of the first suit naming this patent" test is not met at the per-patent level; it is met at the portfolio level, and the transfer plainly enabled the campaign.

6. Bankruptcy fire-sale — NOT PRESENT.
No Chapter 7/11 proceeding involving Intel or Daedalus Prime appears in any source. Intel is a going concern. This is a negotiated portfolio divestiture during financial stress, which is materially different from a bankruptcy estate sale (Kodak, Nortel, Polaroid). Do not classify it as a fire-sale.

7. Privateering — UNCLEAR.
Tempting on the surface: Intel transferred the assets, and Daedalus then attacked Intel's competitors (TSMC, Samsung, Qualcomm, MediaTek, NXP) — a pattern consistent with privateering. But the evidence is genuinely mixed and I will not assert it: (a) TSMC's complaint alleges Intel and Daedalus gave inconsistent accounts of the transfer date (June 3, 2022 vs. a separate April 21, 2021 agreement) and that Intel allegedly granted TSMC a license the parties then denied; (b) IAM reports Daedalus Prime subsequently sold patents to Qualcomm and TSMC shortly after settlements — behaviour of an independent monetizer cashing out, not an Intel proxy; (c) no SEC filing, Patent Progress or EFF report documents an Intel→Daedalus assertion-services arrangement. Absent a funding/direction link, this is a straight sale with follow-on suppression risk, not proven privateering.

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. Note the asymmetry: Unified Patents is on the other side — it surfaced the IPR2025-00207 campaign against Daedalus Prime. A defensive aggregator is challenging this patent; it does not own it.

Verdict

NPE — high confidence.

The chain terminates at Daedalus Prime LLC via Reel 060392/0594, effective 2022-06-03 / recorded 2022-06-06 — a bulk transfer of ~122 Intel patents to a no-product licensing vehicle (Signal 1, present). Daedalus Prime is independently documented as a high-frequency NPE plaintiff by RPX, by IAM, and by TSMC's own pleading in D. Del. 1:22-cv-01647 ("Daedalus is an NPE"), and by the KIPO count placing it first among US plaintiffs against Korean companies in 2022 (Signal 2, present). The acquisition directly preceded the assertion campaign by roughly ten weeks (Signal 5, present at portfolio level). I have not relied on the absence of a correspondent finding (Signal 3, unclear) or on any naming inference. Two strong signals plus one portfolio-level signal comfortably clear the high-confidence bar.

Verify the reel/frame records here: https://assignmentcenter.uspto.gov/ (search patent no. 8984228) — also mirrored at https://assignment.uspto.gov/patent/index.html and at https://patents.google.com/patent/US8984228/en under "Legal Events."

Two open items I could not close, stated plainly rather than guessed: (i) the correspondent/recording attorney of record on Reels 028011/0132 and 060392/0594; and (ii) whether US 8,984,228 was among the patents asserted in the August/September 2022 first-wave suits, versus first appearing in the April 2024 MediaTek action. Both should be checked against the Assignment Center and the respective dockets.

I'll search for US patent 8984228 and its prior art citations. Let me run several searches.

Let me gather more detail on the key patent citations.

Prior Art Analysis — US 8,984,228 B2

Patent identified (literal): US 8,984,228 B2 — "Providing common caching agent for core and integrated input/output (IO) module." Application No. 13/324,053; filed 2011‑12‑13; granted 2015‑03‑17; priority 2011‑12‑13; assignee (original) Intel Corp., current Daedalus Prime LLC. Inventors: Yen‑Cheng Liu, Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur, Bahaa Fahim. 19 claims (3 independent: 1 apparatus, 11 method, 16 system).

Note on scope. I retrieved the patent and its front‑page/report citations from Google Patents and corroborating databases. The references below are the 13 U.S. patent citations and 2 non‑patent citations listed on the face of US 8,984,228 (examiner/third‑party cited). US 9,575,895 B2 and US 2015/0143051 A1 are the same family (continuation of 13/324,053) and are not prior art. I flag per reference whether it more plausibly supports § 102 anticipation or § 103 obviousness; true § 102 anticipation requires a single reference disclosing every element of a claim as arranged, which most of these do not do on their own.

Claim map used below (abbreviated):

• Cl. 1 — multicore processor: cores + shared cache + IIO module + caching agent doing coherency for cores and IIO; single caching agent with distributed portions each tied to a core.
• Cl. 2–3 — table of requests (TOR) for cores and IIO; ≥1 dedicated entry for a posted transaction.
• Cl. 4–5 — shared cache = LLC with distributed portions; portions coupled via ring interconnect.
• Cl. 6–7 — caching agent receives allocation transaction from IIO module and directly stores the data into shared cache (no memory transaction).
• Cl. 8–10 — caching agent sends a drop‑ownership indication to the IIO module for a cache line it owns, responsive to a snoop from another agent (e.g., a core; IO device prefetched the line).
• Cl. 11–15 — method version of the above (receive allocation transaction at IIO → forward to shared caching agent → direct store; access without memory transaction; writeback on eviction; drop‑ownership).
• Cl. 16–19 — system: two multicore processors (each with cores, shared cache, IIO module, caching agent; TOR with dedicated posted entry) + a peripheral controller; plus distributed single caching agent/LLC + ring.

A. U.S. Patent Citations (13)

1. US 6,009,488 A — "Computer having packet-based interconnect channel"

• Assignee: Microlinc, LLC. Filed 1997‑11‑07; granted 1999‑12‑28.
• Description: A packet-based data channel between a microprocessor and device interfaces; packet sizes varied by actual data‑transmission requirements.
• Relevance: General interconnect architecture only. Does not disclose an IIO module or a common CPU/IO caching agent. No § 102 anticipation of any claim; background art. (Mapped by applicant/examiner to the interconnect‑channel concept underlying cl. 5/19.)

2. US 2004/0139283 A1 — "Cache coherent I/O communication"

• Applicant: International Business Machines Corp. (Arimilli et al.). Filed 2003‑01‑09; published 2004‑07‑15.
• Description: A processing unit with a processor core, an I/O communication adapter, and a cache system; the cache controller snoops I/O communication and invalidates corresponding cached data on an exclusive‑state I/O write.
• Relevance: Closest to the "cache coherency for I/O" concept and to coherency‑state bookkeeping for I/O transactions. Potentially supports § 103 against cl. 1 and cl. 8 (coherency operations responsive to snooping I/O traffic). It does not disclose a single caching agent shared by cores and an integral IIO module, so § 102 anticipation of cl. 1 is not sustainable on this reference alone.

3. US 2006/0053258 A1 — "Cache filtering using core indicators"

• Inventor: Yen‑Cheng Liu (a named inventor of the '228 patent). Filed 2004‑09‑08; published 2006‑03‑09.
• Description: Filtering cache/snoop activity using core indicators.
• Relevance: Snoop‑filtering / snoop‑traffic reduction context (motivation for reducing coherency agents). § 103 support for the "reduce snoop traffic" rationale behind cl. 1. Not anticipatory.

4. US 2006/0085602 A1 — "Method and apparatus for initiating CPU data prefetches by an external agent" (granted as US 7,360,027 B2)

• Applicant: Intel Corp. (Huggahalli, Batson, Tetrick, Blankenship). Filed 2004‑10‑15; published 2006‑04‑20; granted 2008‑04‑15.
• Description: Direct Cache Access (DCA) — an external agent (I/O device, chipset, other CPU) issues a prefetch directive that causes a hardware prefetcher associated with a target processor to bring data into a target (CPU) cache, with DCA attributes controlling target/target‑cache and cache placement; prefetch directive can ride along with coherency (invalidate) transactions.
• Relevance: Most relevant DCA reference. Directly bears on the "IO device pushes data into processor cache" concepts of cl. 6, 7, 11, 12, 14, 17, 18. Important distinction: this reference has the hardware prefetcher fetch the data (from memory) into cache, rather than the caching agent directly storing an allocating transaction's data into the shared cache without a memory transaction. That distinction argues for § 103 (obviousness), not clean § 102, against cl. 6/7/11/14/17.

5. US 7,165,131 B2 — "Separating transactions into different virtual channels"

• Assignee: Intel Corp. (Creta et al.). Filed 2004‑04‑27; granted 2007‑01‑16.
• Description: Separating incoming transactions to an agent of a coherent system into distinct virtual channels by transaction type.
• Relevance: Handling mixed (posted/non‑posted) traffic at an agent — supports the queueing/ordering rationale underlying cl. 2–3 and the deadlock‑avoidance discussion. § 103, not anticipation.

6. US 7,210,000 B2 — "Transmitting peer-to-peer transactions through a coherent interface"

• Assignee: Intel Corp. (Blankenship, Muthrasanallur, Ajanovic). Filed 2004‑04‑27; granted 2007‑04‑24.
• Description: Routing peer‑to‑peer transactions (with header information) through a coherent interface between peer devices.
• Relevance: Coherent routing/proxying of I/O‑type transactions through a coherency fabric — context for cl. 1/16 (IIO proxying through the caching agent). § 103.

7. US 2007/0150664 A1 — "System and method for default data forwarding coherent caching agent"

• Inventor: Chris Dombrowski et al. Filed 2005‑12‑28; published 2007‑06‑28.
• Description: Default data‑forwarding behavior in a coherent caching agent.
• Relevance: Caching‑agent coherency behavior (data forwarding), relevant to cl. 1 and cl. 8 coherency operations. § 103.

8. US 2008/0320236 A1 — "System having cache snoop interface independent of system bus interface"

• Inventor: Makoto Ueda. Filed 2007‑06‑25; published 2008‑12‑25.
• Description: A cache snoop interface separate from the system‑bus interface.
• Relevance: Snoop handling separate from the main bus — context for cl. 8 (snoop handling) and the "common" caching agent architecture. § 103.

9. US 7,689,778 B2 — "Preventing system snoop and cross‑snoop conflicts"

• Assignee: Intel Corp. (Liu et al.). Filed 2004‑11‑30; granted 2010‑03‑30.
• Description: Techniques to prevent system‑snoop and cross‑snoop conflicts.
• Relevance: Snoop‑conflict/ordering handling, supporting the deadlock‑avoidance rationale behind cl. 8/15. § 103.

10. US 2010/0274975 A1 — "Forming Multiprocessor Systems Using Dual Processors"

• Inventor: Krishnakanth Sistla et al. Filed 2009‑04‑27; published 2010‑10‑28.
• Description: Building multiprocessor systems from dual‑processor components.
• Relevance: Multi‑socket system topology — context for the two‑processor‑plus‑peripheral‑controller system of cl. 16. Potentially § 103; does not disclose the IIO/common‑agent features, so not § 102.

11. US 7,937,534 B2 — "Performing direct cache access transactions based on a memory access data structure"

• Assignee: Intel Corp. (Madukkarumukumana, Muthrasanallur, Huggahalli, et al.). Filed 2005‑12‑30; granted 2011‑05‑03.
• Description: DCA transactions driven by a memory‑access data structure; DCA attributes (enable indicator, target processor/cache identification, cache‑placement attributes) allow I/O data to be placed into a processor cache, including directly (before/instead of/parallel with memory).
• Relevance: Second key DCA reference. Closely tied to the "IO data lodged directly into the LLC" concepts of cl. 6/7/11/14/17 and the DCA alternative expressly distinguished in the '228 specification. Supports § 103 against those claims; whether it is § 102 depends on whether its disclosure reaches direct store without any memory transaction as claimed.

12. US 2011/0153924 A1 — "Core snoop handling during performance state and power state transitions in a distributed caching agent"

• Applicant: Intel Corp. (Vash et al.). Filed 2009‑12‑18; published 2011‑06‑23.
• Description: Detecting a core performance‑state transition and bouncing core snoop messages on a shared interconnect ring in a distributed caching agent.
• Relevance: Directly bears on the "single caching agent with a plurality of distributed portions" and ring‑interconnect features of cl. 1, 5, 19. Strong § 103 reference; arguably relevant to § 102 for the "distributed caching agent over a ring" sub‑feature, though it is directed to core (not IIO) snoop handling.

13. US 2011/0191542 A1 — "System‑wide quiescence and per‑thread transaction fence in a distributed caching agent"

• Applicant: Intel Corp. (Vash et al.). Filed 2009‑12‑26; published 2011‑08‑04.
• Description: System‑wide quiescence and per‑thread transaction fence operations in a distributed caching agent.
• Relevance: Distributed caching agent architecture — context for cl. 1/4/5/19. § 103.

B. Non‑Patent Citations (2)

N1. Intel Corporation, "An Introduction to the Intel QuickPath Interconnect," Jan. 2009, pp. 1–22.

• Relevance: QPI point‑to‑point interconnect background (the '228 spec references QPI for socket‑to‑socket links, FIGS. 1 & 7). Background for the multi‑socket/interconnect context of cl. 1, 5, 16, 19. Not anticipatory.

N2. International Searching Authority, "Notification of Transmittal of the International Search Report and the Written Opinion," mailed May 1, 2013, in PCT/US2012/069018.

• Relevance: The ISR/WO for the PCT counterpart of this application. Procedural/associated document; it is the search opinion, not technical prior art. (The corresponding WO publication is WO 2013/090297 A1.)

C. Assessment — Most Relevant Prior Art

1. Huggahalli et al., US 2006/0085602 A1 / US 7,360,027 B2 and Madukkarumukumana et al., US 7,937,534 B2 — the two DCA references most pertinent to the direct‑cache‑allocation claims (cl. 6, 7, 11, 12, 14, 17, 18). Best characterized as § 103 art because they route I/O data into a CPU cache via prefetch/DCA directives rather than having the caching agent directly store an allocation transaction's data into the shared cache with no memory transaction (the '228 point of novelty).
2. Arimilli/IBM, US 2004/0139283 A1 — strongest single reference for the "cache coherency applied to I/O traffic" idea (cl. 1, 8); still § 103-grade, since it lacks the single common CPU/IO caching agent and the IIO module.
3. Vash et al., US 2011/0153924 A1 and US 2011/0191542 A1 — most relevant to the distributed caching agent / ring interconnect limitations (cl. 1, 4, 5, 19); § 103 against those dependent features.
4. Sistla et al., US 2010/0274975 A1 — nearest to the multi‑processor‑system + peripheral‑controller subject matter of cl. 16.

Distinguishing feature to watch: Claims 8, 9, 10, 15 (the "drop ownership indication" sent to the IIO module for an IIO‑owned cache line on a snoop, e.g., for a prefetched line) appear not clearly disclosed by any of the 13 cited references — none of the located citations expressly show the caching agent signaling the integrated I/O module to relinquish line ownership in response to a conflicting snoop. This is the feature most likely to survive the cited art.

Caveats (stated explicitly): (i) A definitive § 102/§ 103 determination requires full element‑by‑element claim charts against each reference's complete specification; the summaries above are based on the references' abstracts/claims/selected passages and are not a legal conclusion. (ii) References 3 and 4 share inventors with the '228 patent (Y.‑C. Liu; Huggahalli/Blankenship), which matters for § 102/§ 103 date and "same inventor" analysis. (iii) US 9,575,895 B2 and US 2015/0143051 A1 are the same family as US 8,984,228 and are excluded as prior art. (iv) An IPR (IPR2025‑00207, petitioners ARM Ltd. and MediaTek, Inc.) was filed against this family; the petition's asserted grounds would be the definitive current source for how these references are actually applied, and I have not independently verified the petition's prior‑art set.

Sources: Google Patents US8984228B2 (patents.google.com/patent/US8984228B2/en); US9575895B2; US2015/0143051 A1; US20040139283A1 (patents.google.com/patent/US20040139283); US20060085602A1 / US7360027B2; US7937534B2; USPTO PTAB document for IPR2025‑00207.

I'll ground this analysis in the actual cited prior art. Let me verify the key references.

Obviousness Analysis — U.S. Patent No. 8,984,228 B2

"Providing common caching agent for core and integrated input/output (IO) module"
Inventors: Liu, Blankenship, Santhanakrishnan, Srinivasa, Creta, Muthrasanallur, Fahim · Original assignee: Intel Corp. · Priority/filing: 2011‑12‑13 · Granted: 2015‑03‑17 · Current assignee: Daedalus Prime LLC · 19 claims (independent claims 1, 11, 16)

Scope note: per instruction, I use only the prior-art references listed in the "Patent Citations" / "Non-Patent Citations" sections of the page (13 U.S. references + 2 NPL items), and I treat the specification's own Background as an admission of known art. Identifiers are reproduced exactly as they appear on the page.

1. Person of ordinary skill in the art (PHOSITA)

A practitioner with a B.S./M.S. in electrical engineering or computer science and ~3–5 years in cache-coherent multiprocessor architecture and I/O interconnect design, familiar with MESI/MESIF coherency, directory/snoop filtering, Intel® Quick Path Interconnect (per the Intel QPI NPL, Jan. 2009) and PCI Express™ ordering rules. This is a mature, highly incremental art (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007)).

2. What the cited art already discloses

3. The specification's own admissions (highly relevant to §103)

The Background does the applicant's work on several limitations:

• "One integration trend is to integrate an IO component such as functionality of an IOH into a central processing unit (CPU) die." → an on-die IIO is admitted prior art.
• "Traditional IO integration treats the IO component as a separate caching agent… In MP systems, this becomes a major scaling problem. For example, in an 8 socket system, there are effectively 16 caching agents…" → the problem (too many caching agents, snoop overhead, poor scaling) and the motivation to reduce caching-agent count are conceded.
• It further credits the resulting benefit (fewer home-agent tracker entries, less snoop overhead) to the sheer reduction in caching agents — a predictable, arithmetical consequence.

Under KSR, an admitted known problem plus a known integration trend is strong evidence of a "design incentive" and "market force" to reach the claimed arrangement.

4. Independent claim 1 — proposed combination

Primary combination: Vash US20110153924A1 + Huggahalli US20060085602A1 (US 7,360,027) + IBM US20040139283A1 (+ the Background admission re: on-die IOH, and Intel QPI NPL for the socket/multicore context).

KSR rationales: (i) Known technique applied to a known device ready for improvement (KSR; MPEP 2144.04) — route the integrated IO's transactions through the already-existing per-socket distributed caching agent rather than adding a dedicated IO caching agent; (ii) Design incentive / market force — the Background identifies the scaling penalty of additional caching agents and the BOM/area cost of a separate IO agent, and the IO-on-die trend; (iii) Predictable result — reduced snoop traffic and reduced resource partitioning follow directly from the admitted mechanism. No reference needs to teach the elimination of the IO caching agent expressly, because a negative limitation is obvious where the art renders the omitted element's function dispensable (In re Harza; MPEP 2144.04).

Applicant's likely rebuttal: no single cited reference shows a caching agent performing coherency for an integrated IIO; the DCA references still use a chipset/IOH as an intermediary. Counter: that is a bodily-transfer-of-functions argument the combination defeats, and the Board/PTAB record for IPR2025‑00207 (filed against the family; page notes "Settlement") will be the real test — I do not have the instituted grounds or an institution decision on this page, so I flag that as an open item rather than asserting an outcome.

5. Independent claim 11 — proposed combination

Same primary combination, with US7937534B2 (DCA attributes) supplying the "allocation transaction → direct store into shared cache" core.

Dependent claims 12–15 map almost verbatim onto known DCA/MESI behavior: claim 12 (repeated core access "without sending a transaction to a system memory") ← Huggahalli '027 + US7937534; claim 13 (write-back only on eviction of modified data) ← IBM '283 MESI write-back semantics; claim 14 (store without communicating with system memory) ← US7937534's "before/instead of" memory placement; claim 15 (drop-ownership indication on snoop) ← see §7.

6. Independent claim 16 — proposed combination

Primary combination: Huggahalli '027 (FIG. 6, two processors) + Sistla US20100274975A1 + Intel QPI NPL + Vash, plus US7165131B2 and US7689778B2 for the TOR/posted-entry element.

• Two multicore processors, each with cores, shared cache, IIO, and a caching agent → Huggahalli '027 FIG. 6 (two processors, point-to-point link to IOH) and the Intel QPI NPL (multiprocessor coherent sockets); Sistla for dual-processor system construction.
• TOR with a dedicated entry for a posted transaction → US7165131B2 (per-class virtual channels / separate resources so one transaction class cannot block another) combined with the admitted PCIe™ ordering rule (Background: "posted requests must not be blocked by non-posted requests… otherwise a deadlock concern exists"). Using a dedicated queue entry (a "posted credit") is the predictable hardware implementation of a known ordering requirement.
• Peripheral controller coupled to at least one processor → Huggahalli '027 FIG. 5 (chipset with MCH/ICH and PCI bridge), FIG. 6 (IOH); the '228 FIG. 7's PCH (peripheral controller hub) is not itself claimed with specificity.

Claims 17–19 add nothing beyond the §4/§5 and Vash mappings (allocation transaction direct store; repeated core access without memory transaction; single distributed caching agent with per-core portions, distributed LLC, ring interconnect).

7. Claims 3, 8, 9, 10, 15 — the "drop ownership" limitations

These are the strongest candidates for a non-obviousness argument, so I treat them separately.

• The problem is conceded: the specification states that in a conventional IIO, ownership is prefetched "long prior to when the IIO device is read to retire and meet write ordering," and that two IIOs could each hold non-oldest ownership while both bidding for the oldest transaction, producing deadlock "unless either side relinquishes the ownership."
• The solution is taught in the cited art: IBM '283 (I/O-visible cache lines must be invalidated/snooped in the coherent domain); US7689778B2 (resolving conflicting/system snoop and cross-snoop requests among agents); Dombrowski US20070150664A1 (an agent holding a line in Forward/Exclusive is notified to downgrade its status to shared/invalid when another agent requests the line, and the protocol tracks who owns/forwards the line); US20060053258A1 (tracking which cores hold a line — the "ownership indicator" state information recited in the '228 spec).
• Motivation to combine: PCIe™ ordering compliance and deadlock avoidance are the stated goals, and the Background expressly identifies deadlock as the problem to be solved. Sending a "drop ownership" message to the IIO on a snoop hit is a straightforward application of the known downgrade-on-snoop mechanism to the newly integrated IIO agent.
• Claim 9 ("the IO device prefetched the cache line") and claim 10 ("the another agent is one of the plurality of cores") are express design choices directly supported by Huggahalli '027 (external agent's speculative prefetch of data it may need) and by ordinary core-initiated snoops.

8. Claim 2 / 3 — TOR shared between cores and IIO, dedicated posted entry

Huggahalli '027's directive/attribute handling, US7165131B2's per-class (virtual channel) queues, and the admitted PCIe ordering rule together render claim 2 obvious; claim 3's "at least one dedicated entry" is a predictable, single-entry resource reservation that the '228 specification itself describes as "a single entry of the queue" with no asserted criticality.

9. Secondary considerations

The only arguably objective indicia are the patent's own asserted benefits (fewer caching agents, less snoop traffic, less resource division, faster IO-to-cache path). Under KSR these are the expected, predictable consequences of reducing the number of caching agents — a result the Background frames as the desired outcome before the claimed solution is described. I see no unexpected-result or long-felt-but-unmet-need evidence in the record on this page.

10. Bottom line

• Claims 1, 4, 5, 19 — strongest obviousness posture: Vash US20110153924A1 (US 8,359,436) supplies nearly element-for-element the "single distributed caching agent, one portion per core, LLC slices, ring interconnect" architecture; the IO integration and the reason to consolidate are conceded in the specification.
• Claims 6, 7, 11, 12, 14, 17, 18 — strong: Huggahalli US20060085602A1 (US 7,360,027) + US7937534B2 teach I/O data placed directly into a processor cache and behavior "before/instead of" system memory.
• Claims 2, 3, 13, 16, 17 — strong: US7165131B2 + US7689778B2 + IBM US20040139283A1 + admitted PCIe ordering rules + Sistla/QPI NPL.
• Claims 8, 9, 10, 15 — moderate: the deadlock/scaling problem is admitted; relinquish/downgrade-on-snoop is taught by IBM '283, Dombrowski US20070150664A1 and US7689778B2, but the specific "caching agent → IIO drop-ownership indication" signaling may be where a patentee focuses its defense on secondary-indicia/teaching-away grounds.
• Caveats I cannot close from this page: I do not have the IPR2025‑00207 institution decision, the petitioner's (Arm Ltd. and MediaTek, Inc.) specific ground set, or the W.D. Tex. / E.D. Tex. pleadings; the page records the PTAB case as filed and "Settlement." I also cannot verify from this page whether any single cited reference discloses an IIO physically on the CPU die — the cited DCA references place the IOH/chipset off-die, so the on-die integration limitation rests on the specification's own admission plus the ordinary artisan's knowledge, not on an express reference disclosure.