Invalidity dossier
US 6009488
Added 9/23/2026, 8:18:27 PM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview: US6009488A
Title: Computer having packet-based interconnect channel
Patent number: US6009488A
Application number: US08/965,760
Inventor: Gautam Kavipurapu
Original/Current Assignee: Microlinc LLC
Priority/Filing date: 1997-11-07
Publication (grant) date: 1999-12-28
Legal status (as listed): Expired – Lifetime; anticipated expiration 2017-11-07
Purpose (from the supplied text): The invention "relates to physically non-distributed microprocessor based systems and, more particularly, the communication channel between functional components within a class of computer systems commonly known as personal computers." It addresses limitations of the conventional parallel data/address bus, which the text describes as single-transaction, sequential, generically constrained by dated electrical specifications, slowed by worst-case capacitive loading, dependent on physical handshake signals (READ, WRITE, MEM, I/O, WAIT/READY), and limited by fixed data width. The stated object is "a system with the configuration flexibility of a bus-based PC while reducing the electrical problems," whereby "interfunctional-unit communication speed and flexibility are greatly enhanced."
Plain-language scope (from the supplied text): The invention "applies a point-to-point packetized interconnection str[ucture/ategy]" — i.e., instead of a shared multi-drop parallel bus, functional components communicate over point-to-point links using packets. Classification data in the source places it under bus/loop networks with centralised control (H04L12/403; H04L12/423). The source's prior-art keywords are: packet, node, microprocessor, data, devices. The excerpt references claims concerning bidirectional communication, dependent claims, ring circuit, and communication methods, but does not reproduce claim language.
Source: https://patents.google.com/patent/[US6009488](/patent/US6009488)/en
What the excerpt does not establish: It does not provide the full specification, any complete claim text, the drawings' contents, the identity or contents of cited prior art, claim-by-claim scope, or the outcome/merits of any litigation, ownership transfer, or validity question. It also truncates mid-sentence ("interconnection str—"), so the precise scope of the interconnection structure is not established here. No litigation, validity, or prior-art conclusions are drawn.
Generated 10/1/2026, 9:41:28 PM
Cases on file (0)
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Litigation summary
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Proceedings on file (0)
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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.