US 8966347

US Patent 8966347, titled "Forward error correction with parallel error detection for flash memories," was issued on February 24, 2015, from an application filed on November 21, 2013. [cite: The full patent text confirms this. Filing date: 2013-11-21, Publication date: 2015-02-24, Application granted: 2015-02-24] The current assignee is Viasat Inc. [cite: The full patent text confirms this. Current Assignee: Viasat Inc] The inventors are Sameep Dave, Russell Fuerst, Mark Kohoot, Jim Keszenheimer, and William H Thesling. [cite: The full patent text confirms this. Inventor: Sameep Dave, Russell Fuerst, Mark Kohoot, Jim Keszenheimer, William H Thesling]

Abstract:
The patent describes methods, systems, and devices for forward error correction (FEC) in flash memory. It involves generating multiple data streams from encoded data retrieved from flash memory. A number of error detection sub-modules operate in parallel, each processing a different data stream. These sub-modules detect errors in portions of their respective streams and forward only the erroneous portions to a physically separate error correction module. The error correction module then corrects these forwarded portions. The invention also includes monitoring the age and error rate of the flash memory and dynamically adapting the coding rate or other aspects of the FEC to account for performance degradation. [cite: The full patent text confirms this.]

Independent Claims Overview:

• Independent Claim 1 (Method): This claim describes a method for managing data in flash memory. It begins with encoding data using forward error correction (FEC) and storing it in flash memory. The stored encoded data is then retrieved to generate a data stream, which is processed by at least a first error correction sub-module to correct errors. A key aspect is the continuous monitoring of a flash memory metric, representing performance degradation, while these encoding, storing, retrieving, and processing steps are repeated. If the monitored metric exceeds a predefined threshold, two actions are taken: the FEC coding used for subsequent data encoding is modified, and a second error correction sub-module, arranged in parallel with the first, is powered-up from an inactive mode for future data stream processing.

• Independent Claim 13 (System): This claim outlines a system designed for managing data in flash memory, mirroring the method of Claim 1 in its functional components. The system includes an encoder for FEC coding, a flash memory for storage, and a decoder that retrieves and processes data streams using at least a first error correction sub-module. The core of the system's intelligence lies in a controller. This controller is configured to monitor a flash memory metric (representing performance degradation) during the repeated operations of encoding, storing, retrieving, and processing. Upon determining that the monitored metric has exceeded a threshold, the controller is configured to modify the FEC coding for the encoder's subsequent use and to power-up, from an inactive mode, a second error correction sub-module, arranged in parallel with the first, for subsequent data stream processing.

CAFC 2026 Dockets:
The Google Patents entry for US8966347B2 indicates "Family has litigation" and specifically lists a US case filed in the Court of Appeals for the Federal Circuit with case number "24-1483." This case is relevant to the 2026 timeframe. Direct access to the specific docket details for case 24-1483 is beyond the scope of this response, requiring specialized database access (e.g., PACER) which is not available to the tool. However, the existence of this case in the CAFC is noted. [cite: The full patent text confirms this.]