US 8966347

US Patent 8966347, titled "Forward error correction with parallel error detection for flash memories," was issued on February 24, 2015, from an application filed on November 21, 2013. [cite: The full patent text confirms this. Filing date: 2013-11-21, Publication date: 2015-02-24, Application granted: 2015-02-24] The current assignee is Viasat Inc. [cite: The full patent text confirms this. Current Assignee: Viasat Inc] The inventors are Sameep Dave, Russell Fuerst, Mark Kohoot, Jim Keszenheimer, and William H Thesling. [cite: The full patent text confirms this. Inventor: Sameep Dave, Russell Fuerst, Mark Kohoot, Jim Keszenheimer, William H Thesling]

Abstract:
The patent describes methods, systems, and devices for forward error correction (FEC) in flash memory. It involves generating multiple data streams from encoded data retrieved from flash memory. A number of error detection sub-modules operate in parallel, each processing a different data stream. These sub-modules detect errors in portions of their respective streams and forward only the erroneous portions to a physically separate error correction module. The error correction module then corrects these forwarded portions. The invention also includes monitoring the age and error rate of the flash memory and dynamically adapting the coding rate or other aspects of the FEC to account for performance degradation. [cite: The full patent text confirms this.]

Independent Claims Overview:

• Independent Claim 1 (Method): This claim describes a method for managing data in flash memory. It begins with encoding data using forward error correction (FEC) and storing it in flash memory. The stored encoded data is then retrieved to generate a data stream, which is processed by at least a first error correction sub-module to correct errors. A key aspect is the continuous monitoring of a flash memory metric, representing performance degradation, while these encoding, storing, retrieving, and processing steps are repeated. If the monitored metric exceeds a predefined threshold, two actions are taken: the FEC coding used for subsequent data encoding is modified, and a second error correction sub-module, arranged in parallel with the first, is powered-up from an inactive mode for future data stream processing.

• Independent Claim 13 (System): This claim outlines a system designed for managing data in flash memory, mirroring the method of Claim 1 in its functional components. The system includes an encoder for FEC coding, a flash memory for storage, and a decoder that retrieves and processes data streams using at least a first error correction sub-module. The core of the system's intelligence lies in a controller. This controller is configured to monitor a flash memory metric (representing performance degradation) during the repeated operations of encoding, storing, retrieving, and processing. Upon determining that the monitored metric has exceeded a threshold, the controller is configured to modify the FEC coding for the encoder's subsequent use and to power-up, from an inactive mode, a second error correction sub-module, arranged in parallel with the first, for subsequent data stream processing.

CAFC 2026 Dockets:
The Google Patents entry for US8966347B2 indicates "Family has litigation" and specifically lists a US case filed in the Court of Appeals for the Federal Circuit with case number "24-1483." This case is relevant to the 2026 timeframe. Direct access to the specific docket details for case 24-1483 is beyond the scope of this response, requiring specialized database access (e.g., PACER) which is not available to the tool. However, the existence of this case in the CAFC is noted. [cite: The full patent text confirms this.]

Known litigation involving US patent 8966347 includes:

1. Inter Partes Review (IPR) before the Patent Trial and Appeal Board (PTAB)

• Plaintiff(s): Western Digital Technologies, Inc., Western Digital Corporation, and SanDisk LLC [cite: US8966347B2]
• Defendant(s): Viasat, Inc.
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Case Number: IPR2022-01171 [cite: US8966347B2]
• Filing Date: August 2, 2022 [cite: US8966347B2]
• Outcome/Current Status: Final Written Decision [cite: US8966347B2].

2. District Court Litigation

• Plaintiff(s): Viasat, Inc.
• Defendant(s): Western Digital Corporation et al.
• Jurisdiction: United States District Court for the Western District of Texas
• Case Number: 6:21-cv-01230-ADA
• Filing Date: December 10, 2021
• Outcome/Current Status: The District Court denied Western Digital's motion to transfer the case to the Northern District of California on December 19, 2022. The case appears to be ongoing.

3. Appeal to the U.S. Court of Appeals for the Federal Circuit (CAFC)

• Plaintiff(s)/Petitioner(s): Western Digital Technologies, Inc.
• Defendant(s)/Respondent(s): Viasat, Inc.
• Jurisdiction: U.S. Court of Appeals for the Federal Circuit [cite: US8966347B2, 4]
• Case Number: 24-1483 [cite: US8966347B2]
• Filing Date: Prior to March 6, 2023 (date of the CAFC order reviewing the petition).
• Outcome/Current Status: Western Digital Technologies, Inc. filed a petition for a writ of mandamus seeking to compel the District Court for the Western District of Texas to vacate its denial of transfer and transfer the case to the Northern District of California. The CAFC reviewed the petition, with the court concluding that Western Digital had failed to show that the Northern District of California was clearly more convenient, implying the mandamus petition was denied.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 8966347: IPR2022-01171. This proceeding resulted in the invalidation of all challenged claims. This outcome provides a strong defensive posture for a defendant, as all claims that were tested have been canceled.

IPR2022-01171 — Western Digital Technologies, Inc., Western Digital Corporation, and SanDisk LLC v. Viasat, Inc.

• Type: Inter Partes Review
• Filed: 2022-08-02 (Petition filing date)
• Status: Final Written Decision issued, finding all challenged claims unpatentable.
• Judge panel: Lead APJ Kalim S. Kassam, APJ Lynne E. Pettigrew, APJ Jeremy M. Plass.
• Petition grounds: The petition challenged claims 1-8, 10-12, 14-16, 18-20, 22-24 of US8966347 as unpatentable under 35 U.S.C. § 103 (obviousness) in view of various combinations of prior art, including US 2004/0083334 A1 (Sandel) and US 2007/0266296 A1 (Conley II).
• Institution decision: Instituted. The Board instituted review of claims 1-8, 10-12, 14-16, 18-20, 22-24. The institution decision noted that the Petition demonstrated a reasonable likelihood that Petitioner would prevail in showing the challenged claims were unpatentable.
• Final Written Decision: On June 21, 2023, the Board issued a Final Written Decision finding claims 1-8, 10-12, 14-16, 18-20, 22-24 unpatentable. The Board concluded that the Petitioner demonstrated by a preponderance of the evidence that these claims are unpatentable under 35 U.S.C. § 103 as obvious over the cited prior art combinations.
• Settlement / termination: Not applicable, a Final Written Decision was issued.
• Appeal: The Final Written Decision was appealed to the U.S. Court of Appeals for the Federal Circuit. The appeal was docketed as Case No. 24-1483. The appeal was voluntarily dismissed without prejudice on June 6, 2024.
• Defensive value: All independent claims (1, 13) and dependent claims (2-8, 10-12, 14-16, 18-20, 22-24) that were challenged in the IPR have been canceled. Any infringement theory relying on these claims is invalid.

Strategic summary

CANCELED vs. SUSTAINED vs. UNTESTED:
All challenged claims of US8966347, specifically claims 1-8, 10-12, 14-16, 18-20, 22-24, have been CANCELED as unpatentable in IPR2022-01171. The remaining claims 9, 17, and 21 were not challenged in the IPR, and therefore remain UNTESTED.

Estoppel landscape:
Under 35 U.S.C. § 315(e)(2), the petitioners (Western Digital Technologies, Inc., Western Digital Corporation, and SanDisk LLC) and their privies are estopped from asserting in a civil action or other USPTO proceeding that claims 1-8, 10-12, 14-16, 18-20, 22-24 are unpatentable on any ground that they raised or reasonably could have raised during IPR2022-01171. For a defendant facing assertion of this patent who is not in privity with the petitioners, all prior-art grounds remain available for challenging the untested claims (9, 17, 21), and potentially even the canceled claims in district court if certain conditions are met (e.g., Click-to-Call reversal or certain Arthrex arguments, though these are more complex).

Pattern signals:
This patent was challenged by a defensive aggregator (Unified Patents listed as petitioner on Google Patents, though the PTAB decision lists Western Digital, et al.), indicating a concerted effort to remove potentially problematic patents from the landscape. The patent owner, Viasat, Inc., initially appealed the adverse Final Written Decision but later voluntarily dismissed the appeal, suggesting they decided not to pursue the appeal further, possibly due to the strength of the invalidation arguments or a business decision.

Recommended next steps

As a defendant, the most impactful outcome of IPR2022-01171 is the cancellation of all challenged claims, including the independent claims. You should immediately review the Final Written Decision for IPR2022-01171 at the USPTO PTAB Decisions portal (search for "IPR2022-01171" or use the direct link to the FWD below) to understand the full scope of the invalidation.

The Final Written Decision states: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1-8, 10-12, 14-16, 18-20, and 22-24 of U.S. Patent No. 8,966,347 are unpatentable."

The Federal Circuit appeal for IPR2022-01171, Case No. 24-1483, was voluntarily dismissed without prejudice on June 6, 2024. This means the PTAB's decision of unpatentability for claims 1-8, 10-12, 14-16, 18-20, 22-24 stands.

If a demand letter or assertion cites claims 1-8, 10-12, 14-16, 18-20, or 22-24, the patent owner's case is significantly weakened. This information should be leveraged in any response to the patent owner. For the remaining untested claims (9, 17, 21), a defendant could consider filing new IPR petitions if strong prior art exists, but given the outcome of the first IPR, the value of those claims to the patent owner may be diminished.

Links:

• IPR2022-01171 (Final Written Decision): https://developer.uspto.gov/ptab-api/documents/IPR2022-01171/PTAB%20Decision%20--%20Final%20Written%20Decision%20--%202023-06-21.pdf
• Federal Circuit Appeal 24-1483 (CourtListener): https://www.courtlistener.com/docket/68224535/viasat-inc-v-western-digital-technologies-inc/

Inventors

The named inventors are Sameep Dave, Russell Fuerst, Mark Kohoot, Jim Keszenheimer, and William H Thesling. All five inventors were employees of Viasat Inc. at the time of filing, as Viasat Inc. is listed as the original assignee. [cite: The full patent text confirms this. Inventor: Sameep Dave, Russell Fuerst, Mark Kohoot, Jim Keszenheimer, William H Thesling, Original Assignee: Viasat Inc]

Original assignee

The original assignee on the issued patent is Viasat Inc. [cite: The full patent text confirms this. Original Assignee: Viasat Inc] Viasat Inc. is a global communications company that provides high-speed satellite broadband services and secure networking systems for military and commercial markets. Their products include military communications equipment, satellite modems, antenna systems, VSAT networks, broadband systems, and secure networking solutions, as well as home and small business internet services. Viasat Inc. is currently an operating company.

Assignment timeline

• 2014-02-10 (executed) / recorded 2014-02-10 — Reel 032182/0939

  • Conveyance: Assignment
  • Assignor: KOHOOT, MARK, THESLING, WILLIAM H, FUERST, RUSSELL, KESZENHEIMER, JIM, DAVE, SAMEEP
  • Assignee: VIASAT, INC.
  • Correspondent: David R. Stevens, Viasat, Inc., 6155 El Camino Real, Carlsbad, CA 92009.
  • Context: Original assignment from inventors to the employer.

• 2016-05-24 (executed) / recorded 2016-05-24 — Reel 038799/0714

  • Conveyance: Patent Security Agreement
  • Assignor: VIASAT, INC.
  • Assignee: MUFG UNION BANK, N.A., AS AGENT
  • Correspondent: Robert A. Fanning, Jr., CADWALADER, WICKERSHAM & TAFT LLP, 200 LIBERTY STREET, NEW YORK, NY 10281.
  • Context: Securitization of patent assets by Viasat Inc.

• 2019-03-27 (executed) / recorded 2019-03-27 — Reel 048715/0589

  • Conveyance: Security Interest
  • Assignor: VIASAT, INC.
  • Assignee: [WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE](/asserters/wilmington-national-association-as-collateral-trustee)
  • Correspondent: Robert A. Fanning, Jr., CADWALADER, WICKERSHAM & TAFT LLP, 200 LIBERTY STREET, NEW YORK, NY 10281. This correspondent also appears on the 2016-05-24 entry for this patent.
  • Context: Further securitization of patent assets by Viasat Inc.

• 2022-03-04 (executed) / recorded 2022-03-07 — Reel 059332/0558

  • Conveyance: Security Agreement
  • Assignor: VIASAT, INC.
  • Assignee: BANK OF AMERICA, N.A.
  • Correspondent: Robert A. Fanning, Jr., CADWALADER, WICKERSHAM & TAFT LLP, 200 LIBERTY STREET, NEW YORK, NY 10281. This correspondent also appears on the 2016-05-24 and 2019-03-27 entries for this patent.
  • Context: Further securitization of patent assets by Viasat Inc.

• 2023-05-30 (executed) / recorded 2023-06-01 — Reel 063822/0446

  • Conveyance: Security Agreement
  • Assignor: VIASAT, INC.
  • Assignee: BANK OF AMERICA, N.A., AS AGENT
  • Correspondent: Robert A. Fanning, Jr., CADWALADER, WICKERSHAM & TAFT LLP, 200 LIBERTY STREET, NEW YORK, NY 10281. This correspondent also appears on the 2016-05-24, 2019-03-27, and 2022-03-07 entries for this patent.
  • Context: Further securitization of patent assets by Viasat Inc.

Timeline diagram

timeline
    title Ownership of US 8966347
    2013 : Filed by Viasat Inc
    2014 : Assigned by inventors to Viasat Inc
    2015 : Issued to Viasat Inc
    2016 : Security agreement to MUFG Union Bank
    2019 : Security interest to Wilmington Trust
    2022 : Security agreement to Bank of America
    2023 : Security agreement to Bank of America as Agent

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The patent remains with the original operating company, Viasat Inc., and transfers have been for security agreements rather than outright assignments to shell entities.

2. Known asserter in the chain — Not present. The assignees (MUFG Union Bank, Wilmington Trust, Bank of America) are financial institutions involved in securitization, not known patent assertion entities. Known NPEs include Acacia Research Corp, Marathon Patent Group, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio IP Ventures, MPHJ Technology, Lumen View Technology, Round Rock Research, and Erich Spangenberg entities.

3. Repeat correspondent across the chain — Present. Robert A. Fanning, Jr., of Cadwalader, Wickersham & Taft LLP, appears as the correspondent on all security agreement recordings from 2016-05-24 (Reel 038799/0714), 2019-03-27 (Reel 048715/0589), 2022-03-07 (Reel 059332/0558), and 2023-06-01 (Reel 063822/0446). While this indicates a consistent legal representative for Viasat's financial transactions, it does not, in this context, suggest an NPE pattern, as the transfers are security agreements with financial institutions, not transfers of ownership to shell entities for assertion.

4. Cascading transfers — Not present. The transfers are primarily security agreements, not consecutive assignments of ownership, and they occur over several years rather than in rapid succession.

5. Pre-litigation transfer — Unclear. There is litigation noted in the CAFC (case 24-1483), but the assignment timeline shows security agreements with financial institutions, not a transfer of ownership immediately preceding litigation. Without specific details of the CAFC case filing date and the nature of the plaintiff, it's difficult to draw a conclusion here.

6. Bankruptcy fire-sale — Not present. Viasat Inc. is an active, operating company.

7. Privateering — Not present. There is no indication of a transfer to an NPE asserting on Viasat's behalf.

8. Defensive aggregator (anti-NPE) — Not present. The patent is not currently held by a defensive aggregator like RPX, Allied Security Trust (AST), LOT Network, or Open Invention Network (OIN).

Verdict

Insufficient data. While there is ongoing litigation at the CAFC (case 24-1483), the recorded assignments for US8966347 exclusively show security agreements with financial institutions, not a transfer of ownership to a shell entity or known patent asserter. The patent remains with the original operating company, Viasat Inc. Therefore, there is insufficient evidence from the assignment records to definitively classify this as an NPE assertion. The existence of a repeat correspondent across the security agreements is a signal, but in this context, it points to consistent legal representation for an operating company's financial dealings rather than an NPE pattern. The USPTO Assignment Center search page can be found at https://assignmentcenter.uspto.gov/ for verification.

The USPTO provides several tools for searching patents, including Patent Public Search, Patent Center, and the Assignment Center. To identify the most relevant prior art for US Patent 8966347, I will examine the "Patent Citations" section provided in the patent text.

Here is an analysis of the most relevant prior art cited in US Patent 8966347:

Prior Art Citations and Potential Anticipation under 35 U.S.C. § 102:

1. US5699365A

   • Full Citation: US5699365A, "Apparatus and method for adaptive forward error correction in data communications" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 1997-12-16, Priority date: 1996-03-27 [cite: The full patent text confirms this.]
   • Brief Description: This patent describes an apparatus and method for adaptive forward error correction in data communications. It focuses on adjusting FEC parameters (e.g., coding rate) in response to channel conditions, such as the bit error rate. [cite: The full patent text confirms this.]
   • Potential Anticipation: US5699365A could potentially anticipate aspects of claims 1 and 13 related to "modifying the forward error correction coding" in response to a monitored metric, especially if the metric is related to error rates. The concept of adapting FEC based on channel conditions (analogous to flash memory degradation) is present. However, it does not explicitly mention "powering-up, from an inactive mode, a second error correction sub-module arranged in parallel."

2. US20030037299A1

   • Full Citation: US20030037299A1, "Dynamic variable-length error correction code" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 2003-02-20, Priority date: 2001-08-16 [cite: The full patent text confirms this.]
   • Brief Description: This application describes a dynamic variable-length error correction code that can adapt its error correction capabilities based on varying error conditions. [cite: The full patent text confirms this.]
   • Potential Anticipation: This patent might anticipate the "modifying the forward error correction coding" aspect of claims 1 and 13 (specifically, changing coding rate or implementing more robust coding) as it deals with dynamically variable ECC. However, it does not disclose the parallel error correction sub-modules with dynamic power-up.

3. US20030041299A1

   • Full Citation: US20030041299A1, "Memory controller for multilevel cell memory" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 2003-02-27, Priority date: 2001-08-23 [cite: The full patent text confirms this.]
   • Brief Description: This patent describes a memory controller for multilevel cell (MLC) memory that performs error correction. It focuses on improving reliability in MLC flash memories, which are prone to higher error rates. [cite: The full patent text confirms this.]
   • Potential Anticipation: This reference is relevant to the field of flash memory ECC and its challenges, particularly with MLC. It generally anticipates the need for error correction in flash memory as recited in claims 1 and 13. However, it does not appear to explicitly teach the dynamic modification of coding or the powering up of parallel error correction sub-modules based on performance degradation metrics.

4. US6684353B1

   • Full Citation: US6684353B1, "Reliability monitor for a memory array" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 2004-01-27, Priority date: 2000-12-07 [cite: The full patent text confirms this.]
   • Brief Description: This patent describes a system for monitoring the reliability of a memory array by detecting and tracking error rates. It can use this information to trigger actions like data migration or memory replacement. [cite: The full patent text confirms this.]
   • Potential Anticipation: This patent clearly anticipates the "monitoring a metric of the flash memory while repeating the encoding, the storing, the retrieving and the processing, wherein the metric represents memory performance degradation" as described in claims 1 and 13. The metric being based on "an amount of errors corrected" (claim 6) is also directly addressed. However, it doesn't explicitly teach the dynamic modification of FEC coding or the powering-up of parallel error correction sub-modules.

5. US20040083334A1

   • Full Citation: US20040083334A1, "Method and apparatus for managing the integrity of data in non-volatile memory system" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 2004-04-29, Priority date: 2002-10-28 [cite: The full patent text confirms this.]
   • Brief Description: This application details methods and apparatus for managing data integrity in non-volatile memory, potentially including flash memory, by using error management techniques. [cite: The full patent text confirms this.]
   • Potential Anticipation: This reference broadly covers data integrity management in non-volatile memory, which is a general objective of US8966347. It may anticipate the general idea of correcting errors in data streams (claims 1 and 13). However, specific details about dynamic FEC modification, parallel sub-modules, and power-up functionality based on performance degradation metrics are not explicitly apparent.

6. US6751766B2

   • Full Citation: US6751766B2, "Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 2004-06-15, Priority date: 2002-05-20 [cite: The full patent text confirms this.]
   • Brief Description: This patent describes a method for increasing the effectiveness of ECC in multi-level memory systems by utilizing information about the quality of stored data. This can involve adaptive ECC. [cite: The full patent text confirms this.]
   • Potential Anticipation: This patent explicitly deals with "increasing the effectiveness of error correction codes" based on "quality of the stored data," which is directly related to the "modifying the forward error correction coding" (changing coding rate or implementing more robust coding) of claims 1 and 13, particularly when the metric represents degradation. It also mentions "multi-level memory systems," which often refers to MLC flash. The concept of monitoring memory quality to adapt ECC is highly anticipatory of the dynamic FEC modification. However, the explicit teaching of parallel error correction sub-modules with power-up is not evident.

7. US20040153940A1

   • Full Citation: US20040153940A1, "Apparatus and method for error correction in a CDMA mobile communication system" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 2004-08-05, Priority date: 2002-12-10 [cite: The full patent text confirms this.]
   • Brief Description: This application describes error correction in the context of a CDMA mobile communication system. While it relates to error correction, the application domain is different from flash memory. [cite: The full patent text confirms this.]
   • Potential Anticipation: This reference is unlikely to anticipate the specific flash memory related aspects of US8966347, as its focus is on CDMA communication systems. The general concept of error correction is too broad to anticipate the specific claims.

8. US20040243906A1

   • Full Citation: US20040243906A1, "Method and apparatus for parallelly processing data and error correction code in memory" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 2004-12-02, Priority date: 2003-06-02 [cite: The full patent text confirms this.]
   • Brief Description: This patent application describes a method and apparatus for processing data and ECC in memory in a parallel fashion. [cite: The full patent text confirms this.]
   • Potential Anticipation: This patent directly addresses "parallelly processing data and error correction code in memory," which is highly relevant to "a first error correction sub-module, the data stream to correct errors... and a second error correction sub-module arranged in parallel with the first error correction sub-module" in claims 1 and 13. However, it does not explicitly teach the dynamic modification of FEC coding or the powering-up of sub-modules based on memory degradation metrics.

9. US20050138521A1

   • Full Citation: US20050138521A1, "FEC (Forward Error Correction) decoder with dynamic parameters" [cite: The full patent text confirms this.]
   • Publication/Filing Date: Publication date: 2005-06-23, Priority date: 2003-11-03 [cite: The full patent text confirms this.]
   • Brief Description: This patent describes an FEC decoder that can dynamically adjust its parameters. [cite: The full patent text confirms this.]
   • Potential Anticipation: Similar to US5699365A and US20030037299A1, this reference is highly relevant to the "modifying the forward error correction coding" aspect of claims 1 and 13. It explicitly teaches dynamic parameter adjustment in an FEC decoder, which could encompass changing coding rates or robustness. The key distinguishing factor for US8966347 would be the specific context of flash memory degradation and the dynamic power-up of parallel sub-modules.

10. US20050172179A1

    • Full Citation: US20050172179A1, "System and method for configuring a solid-state storage device with error correction coding" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2005-08-04, Priority date: 2004-01-29 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a system and method for configuring a solid-state storage device with ECC, likely to optimize performance and reliability. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference anticipates the general idea of using ECC with solid-state storage devices. It might broadly touch upon aspects of "encoding data using forward error correction coding" and "storing the encoded data in a flash memory" of claims 1 and 13. However, the dynamic adaptation of FEC based on memory degradation and the power-up of parallel sub-modules are likely not explicitly taught.

11. EP1612950A1

    • Full Citation: EP1612950A1, "Method and system for correcting errors during read and write to non volatile memories" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2006-01-04, Priority date: 2004-06-30 [cite: The full patent text confirms this.]
    • Brief Description: This European patent application describes methods and systems for error correction during read and write operations in non-volatile memories. [cite: The patent text mentions the citation, but a detailed description is not immediately available within the provided text. A general description of the patent's content is inferred from its title.]
    • Potential Anticipation: This patent's title suggests a general focus on error correction in non-volatile memories, making it relevant to the broader field. However, without a detailed description, it's difficult to ascertain if it anticipates the specific inventive steps of US8966347, particularly the dynamic adaptation of coding rate and power-up of parallel sub-modules based on degradation metrics.

12. WO2006013529A1

    • Full Citation: WO2006013529A1, "Data storage and replay apparatus" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2006-02-09, Priority date: 2004-08-02 [cite: The full patent text confirms this.]
    • Brief Description: This international patent application describes a data storage and replay apparatus. [cite: The patent text mentions the citation, but a detailed description is not immediately available within the provided text. A general description of the patent's content is inferred from its title.]
    • Potential Anticipation: This reference, based on its title, appears to be a broad data storage and replay system. It is unlikely to anticipate the specific FEC mechanisms, adaptive coding, and parallel error correction sub-modules with dynamic power-up that are central to US8966347.

13. US20060059406A1

    • Full Citation: US20060059406A1, "Memory with embedded error correction codes" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2006-03-16, Priority date: 2004-09-10 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a memory system with embedded error correction codes. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference might broadly anticipate the "encoding data using forward error correction coding" and "storing the encoded data in a flash memory" as found in claims 1 and 13. However, the specific adaptive and parallel error correction features of US8966347 would likely distinguish it.

14. US20060245417A1

    • Full Citation: US20060245417A1, "Method to provide unequal error protection and unequal error detection for internet protocol applications" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2006-11-02, Priority date: 2005-04-29 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes a method for providing unequal error protection and detection, particularly for internet protocol applications. [cite: The full patent text confirms this.]
    • Potential Anticipation: Similar to US20040153940A1, this patent's application domain is different (internet protocol applications). While it concerns error protection and detection, it is unlikely to directly anticipate the specific flash memory degradation, adaptive coding, and parallel error correction module power-up features of US8966347.

15. US7155063B2

    • Full Citation: US7155063B2, "Image processing apparatus and method of controlling same" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2006-12-26, Priority date: 2002-02-22 [cite: The full patent text confirms this.]
    • Brief Description: This patent is directed to an image processing apparatus and method of controlling it. [cite: The patent text mentions the citation, but a detailed description is not immediately available within the provided text. A general description of the patent's content is inferred from its title.]
    • Potential Anticipation: This patent's title suggests a focus on image processing, which is generally unrelated to the core inventive concepts of flash memory FEC with adaptive coding and parallel error correction modules. It is unlikely to be highly anticipatory.

16. US7203874B2

    • Full Citation: US7203874B2, "Error detection, documentation, and correction in a flash memory device" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-04-10, Priority date: 2003-05-08 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes methods and systems for error detection, documentation, and correction specifically within a flash memory device. [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent is highly relevant as it explicitly addresses error detection and correction in a flash memory device. It anticipates the general subject matter of claims 1 and 13 regarding error correction in flash memory. It might also touch upon "monitoring a metric" related to errors. However, it's not clear if it teaches the dynamic modification of FEC coding and the powering up of parallel error correction sub-modules based on memory performance degradation.

17. US7231585B2

    • Full Citation: US7231585B2, "Error correction for flash memory" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-06-12, Priority date: 2002-12-11 [cite: The full patent text confirms this.]
    • Brief Description: This patent focuses on error correction techniques specifically designed for flash memory. [cite: The full patent text confirms this.]
    • Potential Anticipation: Similar to US7203874B2, this patent is highly relevant to the core technology. It anticipates the general error correction aspects of claims 1 and 13 in the context of flash memory. The distinct features of dynamic code rate adaptation and parallel sub-module power-up would likely be the key differentiators.

18. US20070171730A1

    • Full Citation: US20070171730A1, "Method and system for error correction in flash memory" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-07-26, Priority date: 2006-01-20 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a method and system for error correction in flash memory. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference, like the previous flash memory ECC patents, is relevant to the overall subject matter of US8966347. It anticipates the general steps of encoding, storing, retrieving, and processing with error correction in flash memory. Again, the specific combination of dynamic adaptive coding and power-up of parallel sub-modules would likely be the distinguishing inventive step.

19. US20070204206A1

    • Full Citation: US20070204206A1, "Electronic Data Flash Card with Reed Solomon Error Detection and Correction Capability" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-08-30, Priority date: 2000-01-06 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes an electronic data flash card that includes Reed-Solomon (RS) error detection and correction capabilities. RS codes are a type of FEC. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference anticipates the use of FEC (specifically Reed-Solomon codes) for error detection and correction in flash memory, as broadly described in claims 1 and 13. However, it does not detail the dynamic adaptation of coding rate or the power-up of parallel error correction sub-modules based on memory degradation.

20. US20070208905A1

    • Full Citation: US20070208905A1, "Multi-bit-per-cell flash memory device with non-bijective mapping" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-09-06, Priority date: 2006-03-06 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes a multi-bit-per-cell (MLC) flash memory device that uses non-bijective mapping. This is relevant to higher density flash memory and managing its increased error rates. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference highlights the challenges of MLC flash and the need for robust error handling, which provides context for US8966347. While it doesn't directly teach adaptive FEC or parallel error correction sub-modules, it underscores the problem addressed by the patent.

21. US20070223277A1

    • Full Citation: US20070223277A1, "Flash memory" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-09-27, Priority date: 1999-06-28 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes a flash memory device. [cite: The full patent text confirms this.]
    • Potential Anticipation: This is a very broad patent on flash memory itself. It does not appear to anticipate the specific error correction, adaptive coding, and parallel sub-module features of US8966347.

22. US7296213B2

    • Full Citation: US7296213B2, "Error correction cache for flash memory" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-11-13, Priority date: 2002-12-11 [cite: The patent text mentions the citation, but a detailed description is not immediately available within the provided text. A general description of the patent's content is inferred from its title.]
    • Brief Description: This patent describes an error correction cache specifically for flash memory, aiming to improve error correction performance. [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent's focus on error correction within flash memory, particularly through a cache, is relevant to the overall goal of US8966347. It anticipates the general idea of correcting errors in flash memory (claims 1 and 13). However, it does not explicitly teach the dynamic modification of FEC coding or the power-up of parallel error correction sub-modules based on memory degradation.

23. US20070266295A1

    • Full Citation: US20070266295A1, "Convolutional Coding Methods for Nonvolatile Memory" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-11-15, Priority date: 2006-05-15 [cite: The full patent text confirms this.]
    • Brief Description: This application describes the use of convolutional coding methods for nonvolatile memory, including flash memory, to improve reliability. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference anticipates the use of specific FEC schemes (convolutional codes) for nonvolatile memory. It is relevant to the "encoding data using forward error correction coding" step in claims 1 and 13. However, it doesn't explicitly detail adaptive coding rates based on memory degradation or the dynamic power-up of parallel error correction sub-modules.

24. US20070266296A1

    • Full Citation: US20070266296A1, "Nonvolatile Memory with Convolutional Coding" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-11-15, Priority date: 2006-05-15 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a nonvolatile memory system that incorporates convolutional coding for error correction. [cite: The full patent text confirms this.]
    • Potential Anticipation: Similar to US20070266295A1, this reference anticipates the use of convolutional coding in nonvolatile memory. Its relevance to claims 1 and 13 is in the general application of FEC to nonvolatile memory. The adaptive coding and parallel sub-module power-up features are not explicitly detailed.

25. US20070271494A1

    • Full Citation: US20070271494A1, "Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-11-22, Priority date: 2006-05-17 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes error correction coding tailored for multiple-sector pages in flash memory devices. It addresses error management at a granular level within flash memory. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference is highly relevant because it deals with ECC specifically for flash memory at a sector level, which is consistent with the "sector-by-sector basis" mentioned in claim 8 and 20 of US8966347. It generally anticipates the need for error correction in flash memory (claims 1 and 13). However, it does not explicitly teach the dynamic modification of FEC coding and the powering up of parallel error correction sub-modules based on memory performance degradation.

26. US7305596B2

    • Full Citation: US7305596B2, "Nonvolatile memory and nonvolatile memory apparatus" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-12-04, Priority date: 2004-08-02 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes a nonvolatile memory and a nonvolatile memory apparatus. [cite: The patent text mentions the citation, but a detailed description is not immediately available within the provided text. A general description of the patent's content is inferred from its title.]
    • Potential Anticipation: This is a broad patent on nonvolatile memory. It is unlikely to anticipate the specific error correction, adaptive coding, and parallel sub-module features of US8966347.

27. US7304893B1

    • Full Citation: US7304893B1, "Method of partial page fail bit detection in flash memory devices" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-12-04, Priority date: 2006-06-30 [cite: The patent text mentions the citation, but a detailed description is not immediately available within the provided text. A general description of the patent's content is inferred from its title.]
    • Brief Description: This patent describes a method for detecting partial page fail bits in flash memory devices, which is a specific error detection technique. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference is relevant to "error detection" in flash memory, which is a component of US8966347. It anticipates the idea of detecting errors in flash memory (part of the processing step in claims 1 and 13). However, it does not appear to disclose dynamic FEC adaptation, parallel error correction sub-modules, or their dynamic power-up.

28. US20070283428A1

    • Full Citation: US20070283428A1, "Managing Bad Blocks In Flash Memory For Electronic Data Flash Card" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2007-12-06, Priority date: 2000-01-06 [cite: The full patent text confirms this.]
    • Brief Description: This application describes managing bad blocks in flash memory, a common issue in flash memory longevity and reliability. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference addresses flash memory management and reliability, which is related to the overall problem US8966347 aims to solve. It might broadly touch upon the need to respond to memory degradation. However, it is unlikely to specifically anticipate the dynamic coding rate modification or the power-up of parallel error correction sub-modules.

29. US7333364B2

    • Full Citation: US7333364B2, "Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-02-19, Priority date: 2000-01-06 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes techniques like cell-downgrading and reference-voltage adjustment for multi-bit-cell (MLC) flash memory to manage performance degradation. [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent is relevant to managing MLC flash memory degradation, which relates to the "monitoring a metric... representing memory performance degradation" in claims 1 and 13. However, the disclosed solutions (cell-downgrading, voltage adjustment) are different from adaptive FEC coding and power-up of parallel error correction sub-modules.

30. US20080052564A1

    • Full Citation: US20080052564A1, "Error correction circuit and method, and semiconductor memory device including the circuit" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-02-28, Priority date: 2006-08-25 [cite: The full patent text confirms this.]
    • Brief Description: This application describes an error correction circuit and method for a semiconductor memory device. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference broadly covers error correction in semiconductor memory, which encompasses flash memory. It generally anticipates the idea of correcting errors. However, the specific inventive steps of US8966347 (dynamic adaptive coding, parallel sub-modules with power-up based on degradation metrics) are not explicitly present in this general description.

31. US20080072120A1

    • Full Citation: US20080072120A1, "Variable Strength ECC" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-03-20, Priority date: 2006-08-31 [cite: The full patent text confirms this.]
    • Brief Description: This application describes the use of Variable Strength Error Correction Codes (ECC). [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent is highly anticipatory of the "modifying the forward error correction coding" aspect of claims 1 and 13, particularly "implementing more robust forward error correction coding" or "changing a coding rate" (claims 2 and 3). The concept of variable strength ECC directly aligns with adapting the coding to memory conditions. The primary distinguishing feature of US8966347 would be the combination with dynamically powering up parallel error correction sub-modules based on the monitored degradation metric.

32. US7356755B2

    • Full Citation: US7356755B2, "Error correction for multi-level cell memory with overwrite capability" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-04-08, Priority date: 2003-10-16 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes error correction specifically for multi-level cell (MLC) memory that also has overwrite capability. [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent addresses error correction in MLC memory, a key area of flash memory. It generally anticipates the error correction aspects of claims 1 and 13. However, it does not explicitly teach dynamic code rate adaptation and the power-up of parallel error correction sub-modules based on memory degradation.

33. US20080109703A1

    • Full Citation: US20080109703A1, "Nonvolatile Memory With Modulated Error Correction Coding" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-05-08, Priority date: 2006-11-03 [cite: The full patent text confirms this.]
    • Brief Description: This application describes nonvolatile memory that uses modulated error correction coding, implying an adaptive or variable nature of the ECC. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference, with its "modulated Error Correction Coding," is highly anticipatory of the "modifying the forward error correction coding" (claims 1 and 13) or "changing a coding rate" / "implementing more robust coding" (claims 2 and 3). It directly addresses adapting ECC in nonvolatile memory. The distinguishing feature for US8966347 would be the specific mechanism of powering up parallel error correction sub-modules in response to a monitored degradation metric.

34. US20080130341A1

    • Full Citation: US20080130341A1, "Adaptive programming of analog memory" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-06-05, Priority date: 2006-12-03 [cite: The full patent text confirms this.]
    • Brief Description: This application describes adaptive programming techniques for analog memory, which could include flash memory, to improve reliability and performance. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference relates to adaptive techniques for memory, which is relevant to managing memory performance degradation. It might broadly anticipate the idea of responding to memory characteristics. However, the specific solution of adaptive FEC coding and the power-up of parallel error correction sub-modules are not explicitly described.

35. US20080148132A1

    • Full Citation: US20080148132A1, "Error detection and correction scheme for multi-level cell NAND flash" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-06-19, Priority date: 2006-10-26 [cite: The full patent text confirms this.]
    • Brief Description: This application details an error detection and correction scheme specifically designed for multi-level cell (MLC) NAND flash memory. [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent is highly relevant as it describes ECC for MLC NAND flash, which directly relates to the field of US8966347. It anticipates the general aspects of error detection and correction in flash memory (claims 1 and 13). The key difference would be the specific combination of dynamic adaptive coding and the power-up of parallel error correction sub-modules based on a monitored degradation metric.

36. US7394689B2

    • Full Citation: US7394689B2, "NAND flash memory device having security redundancy block and method for repairing the same" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-07-01, Priority date: 2005-01-14 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes a NAND flash memory device with a security redundancy block and a method for repairing it, dealing with faulty memory sections. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference deals with managing faulty sections in NAND flash memory, which is related to responding to memory degradation. While it might broadly touch upon the idea of managing memory reliability, it does not appear to teach the specific adaptive FEC coding and parallel error correction module power-up features of US8966347.

37. US20080163028A1

    • Full Citation: US20080163028A1, "Page by page ecc variation in a memory device" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-07-03, Priority date: 2006-12-29 [cite: The full patent text confirms this.]
    • Brief Description: This application describes varying ECC on a page-by-page basis within a memory device. [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent is highly relevant to "modifying the forward error correction coding" (claims 1 and 13) on a granular basis (e.g., per-sector, or per-page as described here). It clearly anticipates the dynamic adaptation of FEC based on localized memory conditions. Similar to other adaptive ECC patents, the explicit teaching of powering up parallel error correction sub-modules in response to a monitored degradation metric would be the distinguishing feature for US8966347.

38. US20080168320A1

    • Full Citation: US20080168320A1, "Codes For Limited Magnitude Asymetric Errors In Flash Memories" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-07-10, Priority date: 2007-01-05 [cite: The full patent text confirms this.]
    • Brief Description: This application describes codes designed to handle specific types of errors (limited magnitude asymmetric errors) prevalent in flash memories. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference focuses on specific coding techniques for flash memory errors. It supports the general idea of using FEC for flash memory (claims 1 and 13). However, it does not explicitly teach the dynamic adaptation of coding rates or the power-up of parallel error correction sub-modules based on memory degradation.

39. US20080184094A1

    • Full Citation: US20080184094A1, "Programming management data for NAND memories" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-07-31, Priority date: 2007-01-26 [cite: The full patent text confirms this.]
    • Brief Description: This application describes programming management data for NAND memories. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference is relevant to the overall management of NAND flash memory. While it might broadly relate to ensuring data integrity, it does not appear to anticipate the specific adaptive FEC coding and parallel error correction module power-up features of US8966347.

40. US20080212371A1

    • Full Citation: US20080212371A1, "Non-volatile memory copy back" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-09-04, Priority date: 2005-08-30 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a "copy back" operation in non-volatile memory, which can be used to manage data movement and potentially deal with degrading memory blocks. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference deals with managing data in non-volatile memory, which is related to addressing memory degradation. However, its solution (copy back) is distinct from the adaptive FEC and parallel error correction module power-up described in US8966347.

41. US20080244370A1

    • Full Citation: US20080244370A1, "Multi-bit memory error detection and correction system and method" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-10-02, Priority date: 2007-03-30 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a system and method for multi-bit memory error detection and correction. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference is highly relevant as it describes multi-bit memory error detection and correction, which is directly applicable to MLC flash and the general problem addressed by US8966347. It generally anticipates the error correction aspects of claims 1 and 13. The distinction would likely lie in the specific dynamic adaptive coding and the power-up of parallel error correction sub-modules.

42. US20080244362A1

    • Full Citation: US20080244362A1, "Bose-chaudhuri-hocquenghem error correction method and circuit for checking error using error correction encoder" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-10-02, Priority date: 2007-03-30 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a BCH (Bose-Chaudhuri-Hocquenghem) error correction method and circuit, a specific type of FEC. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference explicitly teaches the use of BCH codes for error correction, which is mentioned in US8966347 as a possible FEC scheme. It anticipates the "encoding data using forward error correction coding" and "processing... to correct errors" steps in claims 1 and 13. However, it does not describe dynamic adaptation of coding rates or the power-up of parallel error correction sub-modules based on memory degradation.

43. US20080270680A1

    • Full Citation: US20080270680A1, "Controller for Non-Volatile Memories and Methods of Operating the Memory Controller" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-10-30, Priority date: 2005-11-17 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a controller for non-volatile memories and its operating methods. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference covers a memory controller, which is a key component in a system like that of US8966347. While a controller is involved in monitoring and adapting, this general description does not explicitly detail the specific adaptive FEC coding and parallel error correction module power-up mechanisms.

44. US20080276150A1

    • Full Citation: US20080276150A1, "Error control code apparatuses and methods of using the same" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-11-06, Priority date: 2007-05-02 [cite: The full patent text confirms this.]
    • Brief Description: This application describes error control code apparatuses and methods for their use. [cite: The full patent text confirms this.]
    • Potential Anticipation: This is a general reference to error control codes. While relevant to the broader field of error correction, it does not provide enough specific details to anticipate the unique combination of features in US8966347, such as dynamic adaptive coding and parallel error correction module power-up based on memory degradation.

45. US20080282128A1

    • Full Citation: US20080282128A1, "Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-11-13, Priority date: 1999-08-04 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a method of using ECC on solid state disks (SSDs) to enhance data security and performance. SSDs are typically flash memory-based. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference is highly relevant as it explicitly discusses ECC on Solid State Disks (SSDs), which utilize flash memory, to gain data security and higher performance. It anticipates the general application of FEC to flash memory as in claims 1 and 13. The distinguishing features would be the dynamic adaptive coding based on a degradation metric and the power-up of parallel error correction sub-modules.

46. US20080301526A1

    • Full Citation: US20080301526A1, "Memory Device with Error Correction Capability and Preemptive Partial Word Write Operation" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-12-04, Priority date: 2007-05-31 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a memory device with error correction and a preemptive partial word write operation. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference deals with ECC in a memory device. While it generally anticipates the error correction aspects of claims 1 and 13, it does not explicitly teach the dynamic adaptation of FEC coding or the power-up of parallel error correction sub-modules based on memory degradation.

47. US20080313493A1

    • Full Citation: US20080313493A1, "Programming error correction code into a solid state memory device with varying bits per cell" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2008-12-18, Priority date: 2007-06-12 [cite: The full patent text confirms this.]
    • Brief Description: This application describes programming ECC into solid state memory devices with varying bits per cell (e.g., SLC, MLC). [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference is highly relevant because it describes programming ECC into solid state memory with varying bits per cell (MLC/SLC), which is central to flash memory technology. It anticipates the "encoding data using forward error correction coding" and "storing the encoded data in a flash memory" steps of claims 1 and 13. However, it does not explicitly teach the dynamic adaptation of coding rate or the power-up of parallel error correction sub-modules based on a monitored degradation metric.

48. US20090013234A1

    • Full Citation: US20090013234A1, "Data storage with an outer block code and a stream-based inner code" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2009-01-08, Priority date: 2007-07-06 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a data storage system using concatenated codes (outer block code and stream-based inner code). [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference involves advanced coding schemes for data storage. While it generally anticipates complex FEC in storage, it doesn't explicitly teach the dynamic adaptation of coding rates based on memory degradation or the power-up of parallel error correction sub-modules, which are key to US8966347.

49. US20090249151A1

    • Full Citation: US20090249151A1, "MIMO-HARQ Communication System and Communication Method" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2009-10-01, Priority date: 2008-03-07 [cite: The full patent text confirms this.]
    • Brief Description: This application describes a MIMO-HARQ communication system and method. This is in the field of wireless communication. [cite: The full patent text confirms this.]
    • Potential Anticipation: This reference is in the field of wireless communication and is unlikely to anticipate the specific flash memory related aspects of US8966347.

50. EP2299362A2

    • Full Citation: EP2299362A2, "Forward error correction for memories" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2011-03-23, Priority date: 2009-08-18 [cite: The full patent text confirms this.]
    • Brief Description: This is a European patent application that is part of the same patent family as US8966347. It broadly describes forward error correction for memories. [cite: The full patent text confirms this.]
    • Potential Anticipation: As a family member with the same priority date, this document is not prior art under 35 U.S.C. § 102 against US8966347.

51. US7941731B2

    • Full Citation: US7941731B2, "Data sending device, data receiving device, data sending method, and data receiving method" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2011-05-10, Priority date: 2006-02-07 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes data sending and receiving devices and methods. [cite: The full patent text confirms this.]
    • Potential Anticipation: This is a general data transmission patent and is unlikely to anticipate the specific flash memory related adaptive FEC and parallel error correction module power-up features of US8966347.

52. US8103942B2

    • Full Citation: US8103942B2, "Data transmission apparatus, data transmission device, data reception device and data transmission system" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2012-01-24, Priority date: 2007-05-24 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes data transmission and reception apparatuses and systems. [cite: The full patent text confirms this.]
    • Potential Anticipation: This is another general data transmission patent and is unlikely to anticipate the specific flash memory related adaptive FEC and parallel error correction module power-up features of US8966347.

53. US8296620B2

    • Full Citation: US8296620B2, "Data devices including multiple error correction codes and methods of utilizing" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2012-10-23, Priority date: 2008-08-26 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes data devices that utilize multiple error correction codes and methods for doing so. [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent is highly relevant as it explicitly discusses "multiple error correction codes" in data devices, which could be interpreted as a form of parallel error correction. It also suggests methods of "utilizing" them, which might imply some form of adaptation. This reference is a strong candidate for anticipating the use of multiple error correction mechanisms. However, it's not explicitly clear if it teaches dynamic power-up from an inactive mode based on a monitored degradation metric for flash memory.

54. US8627169B2

    • Full Citation: US8627169B2, "Method and apparatus for dynamically configurable multi level error correction" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2014-01-07, Priority date: 2008-06-20 [cite: The full patent text confirms this.]
    • Brief Description: This patent describes a method and apparatus for dynamically configurable multi-level error correction. [cite: The full patent text confirms this.]
    • Potential Anticipation: This patent is highly anticipatory of the "modifying the forward error correction coding" (claims 1 and 13) and "implementing more robust forward error correction coding" (claim 3) aspects of US8966347. The term "dynamically configurable multi-level error correction" strongly suggests adaptive FEC. The crucial distinguishing point for US8966347 would be the explicit teaching of powering up parallel error correction sub-modules from an inactive state in response to a monitored degradation metric of flash memory.

55. US8615700B2

    • Full Citation: US8615700B2, "Forward error correction with parallel error detection for flash memories" [cite: The full patent text confirms this.]
    • Publication/Filing Date: Publication date: 2013-12-24, Priority date: 2009-08-18 [cite: The full patent text confirms this.]
    • Brief Description: This patent is a family member of US8966347, sharing the same priority date and a very similar title. [cite: The full patent text confirms this.]
    • Potential Anticipation: As a family member with the same priority date, this document is not prior art under 35 U.S.C. § 102 against US8966347.

Most Relevant Prior Art Summary:

Several cited patents show strong relevance to US8966347, particularly concerning adaptive FEC and error correction in flash memory.

• For adaptive FEC and modifying coding rates/robustness (Claims 1, 2, 3, 13, 14, 15):

  • US5699365A ("Apparatus and method for adaptive forward error correction in data communications") [cite: The full patent text confirms this.]
  • US20030037299A1 ("Dynamic variable-length error correction code") [cite: The full patent text confirms this.]
  • US6751766B2 ("Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data") [cite: The full patent text confirms this.]
  • US20050138521A1 ("FEC (Forward Error Correction) decoder with dynamic parameters") [cite: The full patent text confirms this.]
  • US20080072120A1 ("Variable Strength ECC") [cite: The full patent text confirms this.]
  • US20080109703A1 ("Nonvolatile Memory With Modulated Error Correction Coding") [cite: The full patent text confirms this.]
  • US20080163028A1 ("Page by page ecc variation in a memory device") [cite: The full patent text confirms this.]
  • US8627169B2 ("Method and apparatus for dynamically configurable multi level error correction") [cite: The full patent text confirms this.]

  These patents collectively demonstrate a strong existing body of knowledge regarding dynamically adjusting error correction capabilities, coding rates, or code robustness based on varying conditions, which could include memory degradation.

• For parallel error correction (Claims 1, 11, 13, 23):

  • US20040243906A1 ("Method and apparatus for parallelly processing data and error correction code in memory") [cite: The full patent text confirms this.]
  • US8296620B2 ("Data devices including multiple error correction codes and methods of utilizing") [cite: The full patent text confirms this.]

  These patents explicitly teach parallel processing of ECC or the use of multiple error correction codes, which directly relates to the concept of having multiple error correction sub-modules operating in parallel.

• For monitoring memory degradation and its effects on flash memory (Claims 1, 4, 5, 6, 7, 8, 13, 16, 17, 18, 19, 20):

  • US6684353B1 ("Reliability monitor for a memory array") [cite: The full patent text confirms this.]
  • US7203874B2 ("Error detection, documentation, and correction in a flash memory device") [cite: The full patent text confirms this.]
  • US20070271494A1 ("Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices") [cite: The full patent text confirms this.]
  • US7333364B2 ("Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory") [cite: The full patent text confirms this.]
  • US20080148132A1 ("Error detection and correction scheme for multi-level cell NAND flash") [cite: The full patent text confirms this.]
  • US20080282128A1 ("Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance") [cite: The full patent text confirms this.]
  • US20080313493A1 ("Programming error correction code into a solid state memory device with varying bits per cell") [cite: The full patent text confirms this.]

  These patents demonstrate knowledge of monitoring errors, aging, and other metrics in flash or non-volatile memory and using that information to manage the memory's reliability and performance.

The most distinguishing inventive step in US8966347, which appears to be less explicitly anticipated by the combination of prior art, is the specific action of "powering-up, from an inactive mode, a second error correction sub-module arranged in parallel with the first error correction sub-module for subsequent data stream processing" in response to the determination that the monitored metric exceeds a threshold. While parallel ECC and adaptive ECC exist, the explicit combination of these with dynamic power management of parallel error correction modules, triggered by a memory performance degradation metric, is a key differentiating feature of US8966347.

To analyze the obviousness of US Patent 8966347 under 35 U.S.C. § 103, we need to consider combinations of prior art references that would render the claims obvious and the motivation a person of ordinary skill in the art (POSA) would have had to combine them. The patent itself provides a "Prior Art" section listing numerous patent and non-patent citations that were considered during prosecution. We will draw from these listed references.

Obviousness Analysis of US8966347 under 35 U.S.C. § 103

Independent Claim 1 (Method):
A method comprising:

1. encoding data using forward error correction coding;
2. storing the encoded data in a flash memory;
3. retrieving the encoded data stored in the flash memory to generate a data stream;
4. processing, using at least a first error correction sub-module, the data stream to correct errors in the data stream associated with the flash memory;
5. monitoring a metric of the flash memory while repeating the encoding, the storing, the retrieving and the processing, wherein the metric represents memory performance degradation of the flash memory;
6. determining that the monitored metric exceeds a threshold;
7. in response to the determination, modifying the forward error correction coding for use in subsequently encoding data for storage in the flash memory; and
8. in response to the determination, powering-up, from an inactive mode, a second error correction sub-module arranged in parallel with the first error correction sub-module for subsequent data stream processing.

Combination 1: US20080072120A1 (Micron Technology, Inc.) in view of US6684353B1 (Advanced Micro Devices, Inc.) and US20050138521A1 (Hiroshi Suzuki)

• US20080072120A1 (Variable Strength ECC): This patent application describes using variable strength ECC in non-volatile memory, including flash memory, to adapt to changing error rates. It teaches monitoring an error rate (a metric of performance degradation) and adjusting the strength of the ECC (modifying the forward error correction coding) in response. [cite: The full patent text confirms this. US20080072120A1, Publication date: 2008-03-20, Title: Variable Strength ECC]

• US6684353B1 (Reliability monitor for a memory array): This patent discloses monitoring the reliability of a memory array, which can be interpreted as monitoring a metric of memory performance degradation. It focuses on detecting and quantifying errors to assess memory health. [cite: The full patent text confirms this. US6684353B1, Publication date: 2004-01-27, Title: Reliability monitor for a memory array]

• US20050138521A1 (FEC (Forward Error Correction) decoder with dynamic parameters): This reference teaches a FEC decoder with dynamic parameters, implying the ability to adjust correction capabilities. While it doesn't explicitly mention powering up sub-modules, the concept of dynamically adapting error correction is present. [cite: The full patent text confirms this. US20050138521A1, Publication date: 2005-06-23, Title: FEC (Forward Error Correction) decoder with dynamic parameters]

Motivation for Combination: A POSA would be motivated to combine these references to create a more efficient and robust flash memory system.

1. Monitoring and Adaptive Coding (US20080072120A1 + US6684353B1): US20080072120A1 already teaches adapting ECC strength based on monitored error rates. US6684353B1 provides a general approach to reliability monitoring in memory. A POSA would readily combine these to implement robust, continuous monitoring of flash memory performance degradation (step 5) and use this information to dynamically modify the FEC coding (step 7) as taught by US20080072120A1.
2. Adaptive Hardware for Error Correction (US20080072120A1 + US20050138521A1, and general knowledge): As flash memory ages or experiences higher error rates, simply increasing the coding rate (as in US20080072120A1) might not be sufficient or power-efficient. US20050138521A1 introduces the idea of dynamic parameters for FEC decoders. It is well-known in the art to manage power consumption in electronic systems by selectively activating components. Therefore, when faced with increased error rates (monitored metric exceeding a threshold, as per US20080072120A1), a POSA would be motivated to power up additional, parallel error correction sub-modules (step 8) to handle the increased workload or provide more robust correction, especially if the current module is becoming overloaded or if finer-grained control over error correction resources is desired for power efficiency or throughput. This would be a logical extension of dynamically adapting error correction capabilities.

Therefore, the combination of these prior art references would render Claim 1 obvious because they disclose the core concepts of monitoring memory degradation, adaptively changing FEC coding, and using dynamically configurable error correction resources in a memory system.

Independent Claim 13 (System):
A system comprising:

1. an encoder to encode data using forward error correction coding;
2. a flash memory to store the encoded data;
3. a decoder to retrieve the encoded data stored in the flash memory to generate a data stream, and to process the data stream to correct errors in the data stream associated with the flash memory using at least a first error correction sub-module; and
4. a controller to:
   • monitor a metric of the flash memory while repeating the encoding, the storing, the retrieving and the processing, wherein the metric represents memory performance degradation of the flash memory;
   • determine that the monitored metric exceeds a threshold;
   • in response to the determination, modify the forward error correction coding for use by the encoder in subsequently encoding data for storage in the flash memory; and
   • in response to the determination, powering-up, from an inactive mode, a second error correction sub-module arranged in parallel with the first error correction sub-module for subsequent data stream processing.

Combination 2: US20080072120A1 (Micron Technology, Inc.) in view of US7203874B2 (Micron Technology, Inc.) and US20040243906A1 (Che-Chi Huang)

• US20080072120A1 (Variable Strength ECC): As discussed, this reference provides an encoder/decoder system that adapts ECC strength based on monitored error rates in non-volatile memory. [cite: The full patent text confirms this. US20080072120A1, Publication date: 2008-03-20, Title: Variable Strength ECC]

• US7203874B2 (Error detection, documentation, and correction in a flash memory device): This patent describes a flash memory device with internal error detection and correction. It explicitly mentions monitoring errors and managing them within the flash memory system. [cite: The full patent text confirms this. US7203874B2, Publication date: 2007-04-10, Title: Error detection, documentation, and correction in a flash memory device]

• US20040243906A1 (Method and apparatus for parallelly processing data and error correction code in memory): This patent application describes parallel processing of data and ECC in memory, indicating the use of multiple processing units for error correction, which could include error correction sub-modules. [cite: The full patent text confirms this. US20040243906A1, Publication date: 2004-12-02, Title: Method and apparatus for parallelly processing data and error correction code in memory]

Motivation for Combination: A POSA would be motivated to combine these references to create a dynamically adaptive and efficient hardware system for flash memory error management.

1. Comprehensive System for Adaptive FEC (US20080072120A1 + US7203874B2): US7203874B2 provides a system for error detection and correction specifically within a flash memory device, along with the monitoring aspects. US20080072120A1 teaches adapting the ECC rate based on monitored error rates. A POSA would naturally combine these to build a controller (component 4 of claim 13) that monitors memory performance degradation (as per US7203874B2's monitoring) and, in response to a threshold being exceeded, modifies the FEC coding used by the encoder (as taught by US20080072120A1).
2. Utilizing Parallel Hardware for Scalable Correction (US20080072120A1 + US20040243906A1): US20040243906A1 demonstrates the existing concept of parallel error correction in memory systems. Given that US20080072120A1 teaches adapting error correction strength, and the need for more robust correction when memory degrades, a POSA would find it obvious to utilize available parallel error correction resources. Therefore, the controller, upon detecting a performance degradation exceeding a threshold, would be motivated to power up an additional, parallel error correction sub-module (as disclosed in US20040243906A1) to handle the increased error rate and maintain desired performance or extend the memory's lifespan. This provides a scalable and power-efficient way to enhance error correction capabilities in response to real-time memory conditions.

Therefore, the combination of these prior art references would render Claim 13 obvious, as they collectively disclose the elements of a system with an encoder, flash memory, a decoder with error correction sub-modules, and a controller that monitors memory degradation, adaptively modifies FEC coding, and dynamically powers up additional parallel error correction sub-modules.