US 8458492

I'll run a few targeted searches for this specific patent number before summarizing.

Let me run a couple more targeted checks on litigation and family specifics.

US 8,458,492 B2 — "Crypto-engine for cryptographic processing of data"

Search scope note: I ran targeted searches against Google Patents (full authoritative text supplied), USPTO assignment/PTAB material surfaced by search, and CAFC docket material (CourtListener/PACER/RECAP, Law360, Patexia). I found no CAFC 2026 docket, appeal, or IPR specifically identifying U.S. Patent No. 8,458,492. See "Litigation / docket check" below — this is a negative finding, not a confirmation that none exists.

Bibliographic data

Source: https://patents.google.com/patent/US8458492/en

Abstract (verbatim)

"A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic units are controlled by an arithmetic controller."

Plain-language overview of the independent claims

Claim 1 — Apparatus (the "shared engine" claim). A hardware apparatus with two cooperating parts:

• a modular arithmetic unit (MAU) that performs modular arithmetic operations iteratively; and
• an interface control unit (ICU) coupled to the MAU that performs cryptographic processing using received inputs, where the inputs themselves select which of two different encryption protocols to run (the specification's examples are RSA and ECC).
• Both protocols involve modular arithmetic, and the ICU reuses the same MAU to do that modular arithmetic for both protocols.
• The point of novelty (the limiting element): the modular arithmetic operations include sign inversion operations performed on temporary/intermediate data, and the MAU must contain a dedicated sign inversion unit (SIU) that performs them.

Claim 12 — Method (the mirror-image process claim). A method that:

• receives first inputs for cryptographic processing under a first protocol at an ICU that supports at least the first or a second protocol;
• performs the first-protocol processing with those inputs, including invoking a modular arithmetic unit;
• receives second inputs for a different second protocol, at the same ICU;
• performs the second-protocol processing, including invoking that same modular arithmetic unit;
• wherein invoking the MAU (both times) includes invoking a sign inversion unit of that same MAU to perform sign inversion operations on temporary data of the modular arithmetic operations.

Reading of claim scope: Both independent claims are drafted around the same inventive kernel — a single shared modular-arithmetic engine driven selectively for two different public-key protocols (RSA/ECC), with the sign-inversion unit operating on temporary data as an express, claim-limiting requirement. Claim 1 recites the "iterative" nature of the MAU operations; claim 12 recites the sharing via method steps rather than apparatus. This narrow, sign-inversion-anchored wording is consistent with the file history notes in the record (Office Actions of 2007-02-13, 2007-10-17, 2008-08-21, and a Notice of Allowability of 2009-07-24), i.e., the granted claims were narrowed during prosecution from the broader parent-style language (compare the parent US 7,634,666 and the specification's summary, which claim more generally "a multiplication unit, an addition unit and a sign inversion unit"). I do not have the Office Actions themselves in the supplied text, so the reason for allowance is an inference from the sequence of actions, not a document I verified.

Dependent claims briefly: claim 2 adds the memory unit + multiplication unit + addition unit; claim 3 adds the register/shift-register/FIFO multiplication architecture; claim 4 adds bitwise-segmented multiplier/multiplicand/modulo; claim 5 specifies ~384-byte memory and k≈64-bit SIU; claim 6 feedback of SIU outputs into memory; claim 7 adds the arithmetic controller; claim 8 feedback to the arithmetic controller; claim 9 host-synchronization and faster-than-host operation; claim 10 concatenation/splitter + cryptographic controller with modular opcodes; claim 11 names RSA and ECC. Method dependents 13–18 mirror these.

Litigation / docket check (USPTO + CAFC, 2026)

• The full text carries a "Family has litigation" flag pointing to Darts-IP family ID 34136462 — indicating some family-level litigation activity exists, but that link does not identify a specific case.
• Longhorn Automotive Group LLC (the listed current assignee) is active in 2026 patent litigation and Federal Circuit practice, e.g. In re Volkswagen Group of America, Inc., Fed. Cir. No. 26-123 (mandamus over a PTAB non-institution decision; petitions/responses filed Jan.–Feb. 2026), and Longhorn Automotive Group LLC v. Volvo Group North America, LLC et al (E.D. Tex. No. 2:26-cv-00235, filed March 2026). PTAB matters involving Longhorn in 2025 include IPR2025-01089 (Nissan), IPR2025-01064 and IPR2025-00925 (Volkswagen), IPR2025-00955 (Koito).
• However, I found no authoritative source tying any of those matters, or any CAFC 2026 docket, to US 8,458,492 specifically. The PTAB/IPR and district-court documents I retrieved concern other Longhorn patents (e.g., U.S. 7,513,238 and various headlight/infotainment/data-storage patents). Anyone relying on litigation posture should verify the asserted patents directly from the complaints/IPR petitions rather than inferring from assignee identity.

Uncertainty / caveats

• Google Patents expressly disclaims accuracy of the assignee list and legal status; the "Current Assignee" and "Expired – Lifetime" entries should be confirmed against USPTO Patent Center and the assignment reel/records.
• The full text states claim 7 recites "the arithmetic unit" where "the addition unit" would be expected. Per instructions, I am not auto-correcting this; it may be a drafting inconsistency or a text-extraction artifact.
• I have not verified the 2025-11-02 adjusted expiration date or the 12th-year fee payment (2024-12-30) beyond the supplied record.

Sources: https://patents.google.com/patent/US8458492/en · https://www.courtlistener.com/docket/72143262/in-re-volkswagen-group-of-america-inc/ · https://services.patexia.com/lawsuits/Nissan-Motor-Co-Ltd-v-Longhorn-Automotive-Group-LLC-id-[211619](/patent/211619)/documents/sort_by/created/sort_dir/desc · https://dockets.justia.com/browse/circuit-5/state-texas/court-txedce/noscat-10/nos-830?page=8

I'll run targeted searches for litigation specifically identifying US 8,458,492.

No hits tying US 8,458,492 to any case yet. Let me try more targeted queries, including the assignee names and Unified Patents.

Let me try additional targeted queries.

Litigation Search for U.S. Patent No. 8,458,492

Bottom line: I found no litigation that identifies U.S. Patent No. 8,458,492 ("the '492 patent") as an asserted patent. This is a negative finding from targeted searching, not a certification that none exists. Details and caveats below.

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Search methodology and sources queried

Note on one near-miss: a Justia-reproduced opinion (N.D. Ill. No. 1:13-cv-02082, GeneralPlus) discusses an ex parte reexamination of a "'845 patent." That is a different patent (the string "8,458,492" appears nowhere in it), and I am not treating it as relevant.

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Resulting finding

No known litigation is identified for U.S. Patent No. 8,458,492.

• Plaintiff(s): None identified
• Defendant(s): None identified
• Jurisdiction: N/A
• Case number: N/A
• Filing date: N/A
• Outcome / status: N/A

I am stating this explicitly rather than fabricating a case. Per my operating rules, I do not invent case numbers, courts, or dates.

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Reasons this negative result is plausible (context, not proof)

1. The patent is expired. The '492 patent's term ended 2025-11-02 (adjusted expiration; Google Patents status "Expired – Lifetime"), and its parent US 7,634,666 B2 is likewise expired. Longhorn acquired the family only in 2023–2024, leaving a short enforcement window. That does not preclude past-infringement suits filed during the term, but no such suit naming this patent surfaced.
2. Longhorn's documented 2024–2026 campaigns assert a different portfolio. Longhorn's suits (Volvo Car 2:24-cv-00603; Mazda 2:24-cv-00686; Volkswagen 2:24-cv-00933; Hyundai/Kia; Nissan 2:24-cv-00397) plead U.S. 8,810,803; 7,987,002; 7,513,238; 8,265,353; RE44,331; 7,089,101; and 8,085,192 — not the '492 patent. The 2026 Volvo Group North America complaint likewise asserts '803, '002, '238, and 8,085,192. Separately, the PTAB petitions against Longhorn (IPR2025-00925 VW; IPR2025-01089 Nissan; IPR2025-00955 Koito) target those same automotive patents.
3. The '492 patent doesn't fit Longhorn's automotive-infotainment enforcement theme. It is a cryptographic co-processor patent (RSA/ECC modular-arithmetic engine), originally from CityU Research Limited and assigned to Intellectual Ventures Holding 57 LLC. If ever asserted, it would more likely have been in an IV-style campaign in the 2010s, not Longhorn's automotive campaign — but I found no such record either.

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Caveats — please verify before relying on this

1. The "Family has litigation" flag is unexplained. Google Patents attaches a Darts-IP litigation flag to family ID 34136462, which includes both the '492 patent and the parent US 7,634,666 B2 (and the pre-grant pubs US 2005/0036617 A1 and US 2010/0049945 A1). That flag indicates some family-level litigation activity exists, but the Google Patents text does not identify the case, court, patent, or party. The suit could involve the parent, a foreign counterpart, or the '492 patent itself. This is the single most important item to run down. I could not resolve it from the sources available.
2. I could not query PACER/PTAB dockets exhaustively by patent number. Free docket aggregators (CourtListener/RECAP, Docket Alarm, Justia, Patexia) do not provide a complete patent-number-to-docket cross-index for patents never heavily litigated. A docket naming the '492 patent could exist without appearing in these free indexes.
3. Assignee-identity inference is unreliable. As noted in my earlier summary, many Longhorn/IV matters concern other patents; do not infer that the '492 patent was asserted merely because Longhorn is an active litigant.
4. Recommended next steps to close this out:
   • Pull the Darts-IP family 34136462 record directly (the Google Patents link) to see which family member and which case are flagged.
   • Run a PACER/Docket Navigator "patent number = 8,458,492" search across all district courts and the PTAB.
   • Check IV/Intellectual Ventures historical assertion campaigns (IV has asserted crypto/DRM patents) for any complaint listing 8,458,492 or its parent 7,634,666.

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Sources

• Patent record (authoritative, including the "Family has litigation" flag and legal-events table): https://patents.google.com/patent/US8458492/en
• Longhorn v. Volvo Car (E.D. Tex. 2:24-cv-00603): https://services.patexia.com/lawsuits/Longhorn-Automotive-Group-LLC-v-Volvo-Car-USA-LLC-et-al-id-[201644](/patent/201644)/documents
• Longhorn v. Mazda (E.D. Tex. 2:24-cv-00686): https://services.patexia.com/lawsuits/Longhorn-Automotive-Group-LLC-v-Mazda-Motor-Corporation-This-is-a-consolidated-MEMBER-case-Docketing-is-required-in-the-LEAD-case-id-[202262](/patent/202262)/documents
• Longhorn v. Hyundai/Kia (asserted patents listed; not the '492 patent): https://www.courtlistener.com/opinion/[10678970](/patent/10678970)/longhorn-automotive-group-llc-v-hyundai-motor-company/
• Longhorn v. Volvo Group (2026; asserted patents listed): https://scalejuris.com/news/10841/longhorn-automotive-group-sues-volvo-sub
• Volkswagen v. Longhorn, IPR2025-00925: https://gaeflexstaging-dot-docketupdate.appspot.com/cases/PTAB/IPR2025-00925/Volkswagen_Group_of_America_Inc._v._Longhorn_Automotive_Group_LLC/

If a specific case involving the '492 patent is supplied to me, I will analyze that case rather than rely on this negative finding.

I'll verify the structured "no PTAB proceedings" finding against web sources before writing up.

Let me check the parent patent and the known IV litigation for any related PTAB filings.

Proceedings overview

Zero. The canonical PTAB list from the USPTO Open Data Portal returns no AIA trial proceedings of any kind on US 8,458,492 — 0 active, 0 with claims invalidated, 0 with claims sustained, 0 settled, 0 institution denials. Nothing in my independent web checks contradicts that: I ran searches keyed to the patent number, the title ("Crypto-engine for cryptographic processing of data"), the assignee (Longhorn Automotive Group LLC / Intellectual Ventures Holding 57 LLC), and the parent (7,634,666), and every plausible hit resolved to a different patent — IPR on U.S. 10,523,492 (server consolidation, "Power/Kerr"), U.S. 8,459,492 (a beverage-straw patent), and U.S. 8,180,492 — not this one.

Bottom-line defensive posture for a defendant: there is no IPR to inherit and no claim of the '492 is cancelled. The patent is untested at the Board. That is ordinarily bad news (no free invalidity ruling), but it is heavily offset here because the '492 expired on 2025-11-02 (adjusted expiration, per the record) and today is 2026-09-30 — the patent has been dead for roughly eleven months. There is no injunctive exposure and no forward-looking royalty; any case is a backward-looking damages case under 35 U.S.C. § 286. Note also that the parent patent, U.S. 7,634,666 B2, was IPR'd (IPR2014-00180, FWD issued) — that is the closest thing to PTAB intelligence on this family, and it is set out below even though it is not a proceeding on the '492.

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Non-proceedings — false positives to rule out

For the record, these are not proceedings on this patent, and a demand letter or docket search may conflate them:

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IPR2014-00180 — Petitioner (unverified) v. Patent Owner of U.S. 7,634,666 B2 (parent patent — NOT a proceeding on US 8,458,492)

• Type: Inter Partes Review
• Filed: 2014 (exact filing date not confirmed in the sources I retrieved)
• Status: Final Written Decision issued (the FWD document is publicly available; I retrieved its text via Finnegan's hosted copy). I could not verify from the retrieved excerpt whether claims were cancelled, sustained, or partially sustained.
• Judge panel: not verified in retrieved sources.
• Petition grounds: not verified. The FWD I retrieved reproduces claim 1 of the '666 as illustrative and works through construction of "multiplication unit," "addition unit," and "sign inversion unit" — so the review reached the merits on at least the independent apparatus claim.
• Institution decision: not verified (date/panel reasoning not retrieved).
• Final Written Decision: Disposition not verified — do not assume. The retrieved excerpt shows the Board applying the broadest reasonable construction (citing In re Cuozzo and In re Translogic) and construing the three arithmetic-unit terms; the operative "claims shown unpatentable / not shown unpatentable" table was not in the retrieved text. Pull the FWD directly before relying on any outcome.
• Settlement / termination: no termination for settlement found; an FWD exists, so the trial ran to judgment.
• Appeal: I found no Federal Circuit appeal of IPR2014-00180 in the material retrieved. Unverified.
• Defensive value: two things survive regardless of the verdict. First, the Board's constructions of "multiplication unit / addition unit / sign inversion unit" in the '666 IPR are directly transferable argument material for the '492's claim 1, which recites "a sign inversion unit configured to perform the sign inversion operations." Second, the same three prior-art references cited on the face of the '492 (US 4,894,781 Cylink; US 6,230,179 and US 6,397,241 Motorola; US 7,277,540 Toshiba) plus the '492's own citation of US 7,027,597 (Cisco) and the '666 IPR record give a defendant a running start.

Links: FWD PDF — https://www.finnegan.com/a/web/[115342](/patent/115342)/2G4qSr/ipr2014-00180-final-written-decision-35-usc-c2a7-318a-and-3.pdf · PTAB E2E — https://ptacts.uspto.gov/ptacts/ (search IPR2014-00180)

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Adjacent family-intelligence you should have (not PTAB, but load-bearing)

1. The Darts-IP "family has litigation" flag on the '492 is almost certainly the IV v. JPMC campaign on the parent '666, not a '492 case. Intellectual Ventures II LLC v. JP Morgan Chase & Co., No. 13 Civ. 3777 (AKH) (S.D.N.Y.): IV asserted the '666 against JPMC's IBM 4765 PCIe Cryptographic Coprocessor. IV's other asserted patents in that campaign were withdrawn or held invalid under § 101, leaving the '666 as the last one standing. On 2016-07-21 the court denied JPMC's second summary-judgment motion of non-infringement, but only after rejecting IV's "mere capability" theory. Source: https://www.pbwt.com/content/uploads/2016/09/Patterson_Intellectual-Ventures-v-JPMC.pdf
2. Claim-construction gold for the '492: in that case the parties agreed, and Judge Hellerstein adopted, that "sign inversion unit" means "a unit that changes positive numbers to negative numbers and changes negative numbers to positive numbers." JPMC's winning theme was that the accused SIU accepted only inputs > 0 and therefore did not convert in both directions; the court said JPMC's showing "appeared to be persuasive" and warned IV's contrary position looked like "solely an expert's unsupported conclusion." That construction is a ready-made non-infringement hook for accused hardware whose SIU is one-directional — and the '492's claim 1 makes the SIU a limiting element (unlike the broader parent-language summary in the spec).
3. Unified Patents is already on this family. On 2025-01-14 Unified announced it "found prior art" on U.S. 7,634,666, describing the crypto-engine (RSA + ECC) and noting the '666 "has been asserted against Nissan," and listing the owner as "Longhorn Automotive Group, LLC, an entity of Alpha Alpha Intellectual Partners LLC." https://www.unifiedpatents.com/insights/2025/1/14/longhorn-automotive-crypto-engine-patent-prior-art-found — I could not confirm whether that prior-art effort ripened into a filed IPR, and I found no IPR docketed against the '492. If Unified did file, it would be against the '666, not the '492.
4. Expiry. Adjusted expiration 2025-11-02 (12th-year maintenance fee paid 2024-12-30 with a 11.5-year surcharge). The '492 is expired, and the parent '666 shares the same priority (2003-08-15) and thus a November 2025 expiry as well.

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Strategic summary

Claim status across the '492. All 18 claims (independent 1 and 12; dependents 2–11 and 13–18) are UNTESTED at the PTAB. Zero CANCELED. Zero SUSTAINED. There is no IPR-derived narrowing of this patent, so the "surviving claims" question is the whole claim set — with the important caveat that the claims as issued are already narrow relative to the 2003 parent: both independents are moored to a sign inversion unit acting on temporary data, and claim 1 to a dedicated "sign inversion unit" in the MAU. That limitation is the single most productive non-infringement fulcrum, per the JPMC construction.

Estoppel landscape. Because no IPR was ever instituted on the '492, § 315(e)(2) estoppel is empty as to this patent. A defendant can raise § 102/§ 103 on any reference, including art that was before the examiner. Three limits matter: (a) § 315(b) — a petition must be filed within one year of service of a complaint alleging infringement of the '492, so if you have already been served, calendar it immediately; (b) § 325(d) — the examiner-of-record art on the '492's face (Cylink '781, Motorola '179 and '241, Toshiba '540, Cisco '597, plus WO 00/46954 Qualcomm) invites discretionary denial unless you articulate how the Office materially erred (the Advanced Bionics/§ 325(d) framework) — pairing it with non-cited art (as the parent IPR apparently did) is the safer path; (c) § 315(e)(1) estoppel from the '666 IPR binds only that proceeding's petitioner and its privies and does not bind you. Conversely, if you are a privy/RPI of the '666 petitioner, check IPR2014-00180's ground scope before filing.

Pattern signals. No serial-petitioner pattern on this family's '492 — nobody has filed at all. The patent owner does not appear to be an aggressive PTAB appellant in this family; the family's litigation history is offensive (IV against banks; now Longhorn/Alpha Alpha against automotive OEMs), not defensive. A defensive aggregator is in the chain adjacent to this family — Unified Patents publicly worked the parent '666 in January 2025 — which is a useful tell that the crypto-engine family is being watched by a well-resourced, non-practicing challenger, and a possible partner/amici source. Longhorn's broader PTAB exposure (IPR2025-00925/-00955/-01064/-01089) shows it defends itself, and it won discretionary denials in three of those four (Nissan, Koito, Volkswagen) and settled one (Volkswagen, terminated-settled) — i.e., Longhorn has demonstrated it can keep IPRs off its patents via Fintiv-style discretionary arguments. Expect the same playbook if a '492 petition is filed, though the expired status and any dismissal/joint-dismissal posture (compare the Mazda and Mitsubishi dismissals) weakens the "parallel litigation investment" prong.

The practical bottom line. With the '492 expired on 2025-11-02, a defendant's realistic objectives are (1) defeat any backward-looking damages theory and (2) get out cheaply. An IPR is still available against an expired patent and still worth it where past damages are meaningful, but the cost-benefit is now dominated by non-infringement arguments on the narrow "sign inversion unit"/"temporary data" limitations rather than by validity.

Recommended next steps

• If you are already in suit or have been served: your § 315(b) one-year clock to file an IPR on the '492 is running from service of a complaint alleging infringement of this patent — not from service as to its siblings. Confirm the asserted-claims disclosure names the '492; Longhorn's Rule 3-1 contentions in the automotive campaign (e.g., 2:24-cv-00933-JMD lead case) have disclosed '803, '002, '238, '353 and '192 — the crypto-engine family surfaced separately. If the '492 was never asserted to you, you may be outside the § 315(b) bar entirely.
• Pull the IPR2014-00180 FWD at PTAB E2E / the Finnegan PDF and read the disposition table and the Board's constructions of "multiplication unit," "addition unit," and "sign inversion unit." I have not verified its verdict — do not brief it until you have. If claims of the '666 were cancelled, mine that record for the same art applied to the '492's corresponding limitations.
• Quote and use the claim construction. "Sign inversion unit" = "a unit that changes positive numbers to negative numbers and changes negative numbers to positive numbers" (Intellectual Ventures II LLC v. JP Morgan Chase & Co., No. 13 Civ. 3777 (S.D.N.Y.); Markman Order 2014-03-18, adopted in the 2016-07-21 opinion, https://www.pbwt.com/content/uploads/2016/09/Patterson_Intellectual-Ventures-v-JPMC.pdf). Build your non-infringement case on the accused SIU's input range and directionality.
• Run the expiry math. With an adjusted expiration of 2025-11-02, apply § 286's six-year lookback to whatever damages window a plaintiff can still reach, and check the certificate of correction dated 2014-03-25 for any claim-text change you should mirror in your invalidity charts.
• No PTAB watch items exist to calendar — there is no pending institution deadline, no oral hearing, and no FWD due date, because there is no proceeding. If the USPTO Open Data Portal is stale (it can lag recent filings), re-run PTAB E2E before you file anything, and specifically check for any Unified Patents petition against the '666 or the '492 that post-dates January 2025.

Verification caveats (please do not treat any of the above as a legal conclusion): the '492's PTAB emptiness is a negative finding supported by both the ODP structured data and my searches; the assignee list and "Expired – Lifetime / 2025-11-02" status are Google Patents' own hedged representations and should be confirmed at USPTO Patent Center and the assignment reels. The IPR2014-00180 petitioner identity, institution date, ground list, FWD disposition, and any CAFC appeal are unverified in what I retrieved. Also flagging an internal-consistency note against the earlier generated section: that section correctly reported no PTAB activity but located the "family has litigation" flag only generically — the concrete family litigation is the IV v. JPMC '666 case described above, and the earlier section's list of Longhorn PTAB matters (Nissan/VW/Koito) concerns headlight and imaging patents, not this crypto-engine family.

I'll verify the assignment chain details and check for litigation/asserter signals before writing up the analysis.

Strong leads: the parent patent U.S. 7,634,666 (same crypto-engine family) was asserted by Longhorn against Nissan, and AI-Core appears tied to a broader affiliate network. Let me dig deeper.

I hit the tool-call limit mid-verification, so I'll flag clearly what is sourced vs. what I could not verify. One important update to the prior section: I did find that Longhorn Automotive Group is actively asserting the sibling/parent patent in this family (U.S. 7,634,666) — see below.

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Inventors

Basis: The original assignee of the parent application was City University of Hong Kong (listed as assignee on the sibling U.S. 7,634,666), and the recorded assignor to IV was CityU Research Limited — CityU's technology-transfer vehicle. The inventors are therefore academic/research employees of CityU, not industry engineers.

Unusual-pattern check: The classic red flag — inventors departing a commercial assignee within 12 months — does not apply cleanly here, because the original owner was a university, not an operating company. What is observable is a university-to-aggregator monetization event: CityU Research Limited executed the sale to Intellectual Ventures Holding 57 LLC effective 2009-12-21, roughly one month after the continuation (US 12/589,605) was filed on 2009-10-26. I could not determine individual inventor separation or employment-end dates from the available record — treat that as unknown, not as "no departures."

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Original assignee

• On the face of the issued patent: the "original assignee" listing is Intellectual Ventures Holding 57 LLC (because the '492 continuation was filed 2009-10-26 by the IV entity, after the CityU→IV acquisition was agreed).
• True original owner of the technology: CityU Research Limited, the commercialization/tech-transfer arm of City University of Hong Kong.
  • Primary line of business: university IP management and licensing — it does not make or sell products embodying the claims, and a university tech-transfer office is a licensing entity by design, not a product company.
  • Product embodying the claims: no evidence any assignee ever shipped a crypto-engine product. The specification describes a 0.35 µm ASIC built as a research prototype (15K gates for RSA, 20K for RSA+ECC, k=64) — a lab/benchmark device, not a commercialized part.
  • Current status: no bankruptcy, dissolution, or M&A event found for CityU Research Limited. It was a voluntary sale, not a fire-sale.

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Assignment timeline

All five events below are the post-issuance/post-filing recorded assignments reflected in the Google Patents legal-events feed, which mirrors the USPTO assignment register. Reel/frame strings are reproduced as shown; confirm against USPTO Assignment Center before relying on them.

1. Executed 2009-12-21 / recorded 2010-02-09 — Reel 023918/0288

• Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
• Assignor: CityU Research Limited
• Assignee: Intellectual Ventures Holding 57 LLC (Nevada)
• Correspondent: Not available in the supplied source. The Google Patents legal-events record reproduced in the patent text does not carry the correspondent field. ⚠️ This must be pulled directly from Assignment Center — see "Correspondent gap" below.
• Context: University monetization sale / portfolio acquisition by IV. CityU sold the crypto-engine family to IV while the continuation was being prosecuted.

2. Executed 2013-05-23 / recorded 2013-05-28 — Reel 030494/0239

• Conveyance: Merger
• Assignor: Intellectual Ventures Holding 57 LLC
• Assignee: Intellectual Ventures II LLC (Delaware)
• Correspondent: Not available in the supplied source (same gap).
• Context: Internal corporate reorganization — an IV intra-group merger, no change in beneficial control.

3. Executed 2023-09-25 / recorded 2023-09-25 — Reel 065015/0675

• Conveyance: Assignment
• Assignor: Intellectual Ventures II LLC (Delaware)
• Assignee: Intellectual Ventures Assets 190 LLC (Delaware)
• Correspondent: Not available in the supplied source (same gap).
• Context: Internal IV reorg / staging for divestiture. "Assets 190" is one of IV's numbered asset-transfer shells. (Compare the analogous IV Assets 156 LLC document surfaced in search, whose assignor signatory is Jim Weisfield, "Authorized Person" — the IV-side signature block, not the correspondent of record.)

4. Executed 2023-10-05 / recorded 2023-10-13 — Reel 065227/0107

• Conveyance: Assignment
• Assignor: Intellectual Ventures Assets 190 LLC (Delaware)
• Assignee: AI-Core Technologies, LLC (Texas)
• Correspondent: Not available in the supplied source (same gap).
• Context: Transfer-to-asserter / divestiture to a third-party NPE. AI-Core Technologies, LLC appears in the Stanford NPE Litigation Database as an "Acquired patents" asserter (e.g., AI-Core Technologies, LLC v. Omron Corp., 2:24-cv-00624, E.D. Tex.), and the Databricks v. Weisfield complaint lists AI-Core among a set of affiliated entities that Weisfield and Chummun allegedly caused to file patent infringement suits.

5. Executed 2023-10-06 / recorded 2024-03-26 — Reel 066911/0261

• Conveyance: Assignment
• Assignor: AI-Core Technologies, LLC (Texas)
• Assignee: Longhorn Automotive Group LLC (Texas)
• Correspondent: Not available in the supplied source (same gap).
• Context: Pass-through to the asserting entity. Executed one day after AI-Core received the asset (10-05 → 10-06). Independently corroborated: Volkswagen's motion in the Longhorn E.D. Tex. campaign states Longhorn "acquired the Asserted Patents" before October 6, 2023 — matching this effective date.

Non-assignment register events (for completeness, not conveyances): Certificate of Correction 2014-03-25; maintenance-fee payments 2016-11-28 (4th yr), 2020-09-28 (8th yr), 2024-12-30 (12th yr, with 11.5-yr surcharge).

⚠️ Correspondent gap (important limitation)

You specifically asked me to capture the correspondent of record for each link — the single best "tell." I could not retrieve it. The full patent text I was given reproduces Google Patents' legal-events table, which lists reel/frame, conveyance, parties, and dates but omits the correspondent field entirely. I will not invent an attorney name or firm. To fill this, run each reel/frame at https://assignment.uspto.gov/patent/index.html (search patent number 8458492, open each assignment, read the "Correspondent" block). This is worth doing: if the same attorney/firm appears on reels 065015/0675, 065227/0107 and 066911/0261, that would convert NPE signal #3 from "unclear" to "present."

SEC cross-reference: no 10-K/8-K coverage available — Intellectual Ventures is private, Longhorn Automotive Group LLC and AI-Core Technologies LLC are private LLCs, and CityU Research Limited is a university company. Nothing to pull from EDGAR.

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Timeline diagram

timeline
    title Ownership of US 8458492
    2003 : Parent crypto-engine filed by CityU
    2009 : Continuation filed by IV Holding 57
         : CityU Research assigns to IV
    2010 : Assignment recorded at USPTO
    2013 : Merged into Intellectual Ventures II
    2023 : Moved to IV Assets 190 LLC
         : Passed to AI-Core Technologies
         : Acquired by Longhorn Automotive
    2024 : Longhorn recording hits register

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NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
The patent moves from a non-operating university licensing arm into a chain of named holding shells: Intellectual Ventures Holding 57 LLC → Intellectual Ventures II LLC → Intellectual Ventures Assets 190 LLC (reels 023918/0288, 030494/0239, 065015/0675). The "Holdings / Ventures / Assets" naming and the Delaware incorporation are corroborated by address evidence from the same program (IV Assets 156 LLC lists 251 Little Falls Drive, Wilmington, DE 19808 — a registered-agent service address). The terminal holder, Longhorn Automotive Group LLC, holds no automotive manufacturing assets; per Unified Patents it is "an entity of Alpha Alpha Intellectual Partners LLC."

2. Known asserter in the chain — PRESENT.
Intellectual Ventures (via Holding 57, IV II, and IV Assets 190) is on the public NPE list you supplied — indeed the largest U.S. patent aggregator, with ~1,276 identified shell entities as documented in the Santa Clara "Giants Among Us" study. AI-Core Technologies, LLC appears in the Stanford NPE Litigation Database as an "Acquired patents" asserter. Longhorn Automotive Group LLC is an active, high-volume 2024–2026 plaintiff in E.D. Tex. (Nissan, Hyundai/Kia, Volvo, Mitsubishi, Mazda, Volkswagen cases), and Unified Patents classifies the patent owner as "NPE (Patent Assertion Entity)" in IPR2025-01089.

3. Repeat correspondent across the chain — UNCLEAR (not verifiable here).
Cannot be scored: the correspondent field is absent from the supplied record (see gap above). Do not treat the absence as a negative — it is simply unretrieved. Note as a related (imperfect) proxy: the Databricks v. Weisfield complaint alleges that Jim Weisfield and Chummun "caused AI-Core to file at least one patent infringement lawsuit," and Jim Weisfield signed as "Authorized Person" on the analogous IV Assets 156 assignment — i.e., continuity of principals, which is suggestive but is not the correspondent evidence you asked for.

4. Cascading transfers — PRESENT (strong).
Three assignments cleared within 11 days: IV II → IV Assets 190 (eff. 2023-09-25, reel 065015/0675) → AI-Core (eff. 2023-10-05, reel 065227/0107) → Longhorn (eff. 2023-10-06, reel 066911/0261). AI-Core held title for one day before passing it on. This is a text-book staging-and-passthrough structure, not an arm's-length commercial sale.

5. Pre-litigation transfer — PRESENT for the family; UNCONFIRMED for the '492 itself.
Longhorn took title via reel 066911/0261 effective 2023-10-06, then sued Nissan on 2024-05-31 (Longhorn Auto. Grp. v. Nissan Motor Co., 2:24-cv-00397, E.D. Tex.), asserting U.S. 7,634,666 — the parent of the '492 in this same crypto-engine family. That gap is ~7.5 months (slightly outside a strict 6-month window). I did not find any complaint, IPR, or PTAB paper naming US 8,458,492 itself. Longhorn's 2024–2026 campaigns I could source involve other patents (7,513,238; 8,265,353; 8,810,803; 7,987,002; and the '666). This is a genuine limitation: the family has been asserted; the '492 specifically has not been confirmed as asserted. (Note also that the '492 is shown as Expired – Lifetime, adjusted expiration 2025-11-02, which reduces its forward assertion value relative to the still-live sibling.)

6. Bankruptcy fire-sale — NOT PRESENT.
No Chapter 7/11 record for CityU Research Limited, IV, AI-Core, or Longhorn Automotive Group. The CityU→IV transfer was a voluntary university monetization sale; the IV→AI-Core→Longhorn leg was a portfolio divestiture. No court-supervised sale found.

7. Privateering — NOT PRESENT (in the strict sense).
True privateering is an operating company transferring to an NPE to assert against its competitors. Here the original owner was a university, not an operating company, and there is no evidence CityU is directing or benefiting from assertion against rivals. The IV→NPE-to-asserter structure is standard aggregator divestiture, not privateering.

8. Defensive aggregator — NOT PRESENT.
The chain terminates at an asserting entity, not at RPX / AST / LOT / Unified Patents / OIN. In fact Unified Patents is adverse here: it ran a public prior-art bounty against sibling patent US 7,634,666, and its portal classifies the Longhorn-owned patent as an "NPE." That is a challenge to this family, not neutralization of it.

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Verdict

NPE — high confidence.

Four strong signals converge with concrete reel/frame support: (i) shell-entity transfer out of a non-operating university arm into IV holding shells (reels 023918/0288, 030494/0239, 065015/0675); (ii) known asserters at every downstream link — IV, then AI-Core Technologies, LLC (Stanford NPE database; reel 065227/0107), then Longhorn Automotive Group LLC, classified "NPE" by Unified Patents (reel 066911/0261); (iii) three cascading transfers in 11 days, including a one-day AI-Core hold (eff. 2023-09-25 → 2023-10-05 → 2023-10-06); and (iv) active assertion of the sibling patent US 7,634,666 by Longhorn against Nissan (2:24-cv-00397, filed 2024-05-31), roughly 7.5 months after Longhorn took title. The one thing I could not do is tie the '492 itself to a filed complaint or IPR, and I could not retrieve the correspondent of record — both are open verification items, not counter-evidence.

Verify at: https://assignment.uspto.gov/patent/index.html — search patent number 8458492 (legacy Assignment Search); the current portal is https://assignmentcenter.uspto.gov/. Cross-check the correspondent on reels 065015/0675, 065227/0107 and 066911/0261, and confirm the 2025-11-02 adjusted-expiration status via USPTO Patent Center.

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Sources

• https://patents.google.com/patent/US8458492/en (full text + legal events used for all reel/frame data)
• https://portal.unifiedpatents.com/ptab/case/IPR2025-01089 (patent owner classified "NPE"; Longhorn Automotive Group)
• https://patroll.unifiedpatents.com/contests/v4BnWmDzYWwnHPnbG (prior-art bounty on US 7,634,666; "Longhorn Automotive Group, LLC, an entity of Alpha Alpha Intellectual Partners LLC")
• https://npe.law.stanford.edu/patent/[9338217](/patent/9338217) (AI-Core Technologies, LLC as "Acquired patents" asserter; AI-Core v. Omron, 2:24-cv-00624)
• https://fingfx.thomsonreuters.com/gfx/legaldocs/mopaqgekapa/Databricks%20v%20Weisfield%20et%20al%20-%2020240906.pdf (AI-Core among Weisfield/Chummun affiliate network)
• https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1557967](/patent/1557967)/... (Longhorn v. Nissan, 2:24-cv-00397, asserting US 7,634,666)
• https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1557805](/patent/1557805)/... (Volkswagen motion: Longhorn "acquired the Asserted Patents" before October 6, 2023)
• https://law.scu.edu/wp-content/uploads/hightech/The%20Giants%20Among%20Us%20(2011-10-07)1.pdf (IV shell-entity structure, ~1,276 shells)

I'll verify the exact patent record and each cited reference against USPTO/live sources before analyzing.

Let me verify the remaining cited references and the parent patent record.

Prior-Art Analysis — U.S. Patent No. 8,458,492 B2

0. Scope note and methodology

Per your instruction, I limited the search to patent number 8,458,492 and did not return results for similar numbers. I used the authoritative full text (which contains the complete face-of-patent citation tables) and verified individual references against Google Patents, Justia, USPTO-report, Unified Patents Portal, and patent-image PDFs.

A precision point on your request: there is no verified record that any of these references was actually applied to reject a claim. The '492 patent issued with all 18 claims, and the citation tables are simply the references listed on the face of the patent (struck as "cited by examiner" or "cited by third party"). I therefore analyze them as candidate § 102/§ 103 art and flag explicitly where the analysis can only support § 103, not § 102. I do not have the Office Actions in the supplied text, so I cannot state which reference the examiner relied on.

Statutory framework: the '492 patent carries a priority date of 2003-08-15 (continuation of Ser. No. 10/641,869). Applications with pre-March-16-2013 priority are governed by pre-AIA 35 U.S.C. §§ 102/103. That matters for the analysis: under pre-AIA § 102(e), a U.S. patent/publication is prior art as of its filing date, not its publication date. I give both dates below.

The decisive limitation. Both independent claims turn on one narrow element that is absent from the specification's generic summary and was apparently added to survive prosecution:

• Claim 1: "…wherein the modular arithmetic operations include sign inversion operations on temporary data of the modular arithmetic operations, and the modular arithmetic unit includes a sign inversion unit configured to perform the sign inversion operations."
• Claim 12: "…wherein invoking a modular arithmetic unit … comprises invoking a sign inversion unit of the same modular arithmetic unit to perform sign inversion operations on temporary data…"

None of the ten cited references, as described in the record and the sources I retrieved, discloses a dedicated sign-inversion unit operating on temporary data internal to the modular arithmetic operations. That element is the reason the claim set survived, and it is the element that simultaneously defeats most of the candidate art on § 102 and pushes it into § 103 territory. I state this as an analytical conclusion from the reference disclosures, not from a document I verified.

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1. Reference-by-reference analysis

1.1 US 7,277,540 B1 — the single most relevant reference

• Full citation: Shiba, Masue; Kawamura, Shinichi. "Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography." Kabushiki Kaisha Toshiba. US 7,277,540 B1.
• Dates: Filed 2000-01-19; issued 2007-10-02.
• Description: A coprocessor with a "long product-sum" multiply unit that executes both integer-based (RSA) arithmetic and finite-field GF(2^m)-based (elliptic curve) arithmetic, switchable by a carry-propagation selection circuit. Includes an arithmetic unit, controller unit, memory, and buffers (data X/Y/Z/R) on a shared data bus.
• Relevance / claims potentially affected: This is the closest art to the architectural kernel of claims 1 and 12 (a single arithmetic apparatus driving two different public-key protocols, shared by both), and to claims 11/16 (RSA + ECC named). It also touches claims 2, 7 (memory + controller).
• § 102 assessment: Unlikely to anticipate claims 1 or 12 as issued, because (a) its ECC field is GF(2^m), not the prime-field GF(p) modular arithmetic emphasized by the '492 specification, and (b) it discloses no sign-inversion unit on temporary data. It is instead the strongest § 103 candidate against claims 1, 11, 12, 16 if combined with a modular-arithmetic reference such as Shiba's own or Cylink's.
• Source: https://patents.google.com/patent/US7277540 (record); US7277540B1 PDF.

1.2 US 6,230,179 B1 — dual-protocol shared arithmetic processor

• Full citation: Vanstone, Scott A.; Vadekar, Ashok; Lambert, Robert J.; Glaser, P. Michael; Dworkin, James D.; Torla, Michael J. "Finite field multiplier with intrinsic modular reduction." Certicom Corp. (listed in the '492 record as Motorola). US 6,230,179 B1.
• Dates: Priority 1997-04-18; filed 1997-12-23; issued 2001-05-08.
• Description: An arithmetic processor performing both finite-field and integer arithmetic with shared arithmetic circuits, registers, and a mode-selection control that selectively enables one or the other — expressly motivated by the RSA→ECC transition ("a need for an arithmetic processor that supports both these operations"). Also recites an interface unit translating an n-bit data path to an m-bit data path.
• Relevance / claims potentially affected: Directly relevant to claims 1 and 12 (shared engine for two protocols), claim 2 (memory + ALU), claim 10 (interface/data-width handling), and claims 11/16 (RSA + ECC).
• § 102 assessment: Strong candidate for a § 103 combination, but weak as § 102(a)/(e) anticipation of claims 1/12 because it recites no sign-inversion unit and the '492 claim additionally requires the operations be performed "iteratively" with sign inversion on temporary data. Note the family/assignee discrepancy (record lists Motorola; the PDF lists Certicom) — flagging, not correcting.
• Sources: https://patents.google.com/patent/[US6230179B1](/patent/US6230179B1)/en ; https://portal.unifiedpatents.com/patents/patent/US-[6230179](/patent/6230179)-B1

1.3 US 4,891,781 A — modulo arithmetic processor chip (prime field GF(p))

• Full citation: Omura, Jimmy K. "Modulo arithmetic processor chip." Cylink Corporation. US 4,891,781 A.
• Dates: Priority 1987-03-04 (record); Unified Patents lists priority 1987-03-03, application 1988-12-21; issued 1990-01-02 (Unified lists grant 1990-01-01). Two minor date discrepancies between sources — stated as-is, not reconciled.
• Description: A processor chip computing addition, multiplication, and exponentiation in GF(p) modulo a prime, including registers, a full adder, a feedback register generating a two's-complement feedback number from p, and explicit statement that it can compute exponentiation "in the ring of integers modulo a composite number … such as in the RSA public key cryptographic scheme."
• Relevance / claims potentially affected: Relevant to claim 1 (iterative modular arithmetic), claim 2 (memory + multiply/add units), claim 4 (modulo value driving modular multiplication). The two's-complement feedback number is conceptually adjacent to the '492 sign-inversion concept but is not a sign-inversion unit on temporary data — a distinction worth flagging for any validity/§ 102 comparison.
• § 102 assessment: Does not anticipate claims 1/12 (no dual-protocol ICU, no sign-inversion unit). Useful § 103 building block for the modular-arithmetic-unit element.
• Sources: US4891781 PDF; https://patents.google.com/patent/US4891781

1.4 US 7,027,597 B1 — modular multiplication/exponentiation for multiple protocols

• Full citation: Stojancic, Mihailo M.; Tomei, Kenneth J.; Maddury, Mahesh S. "Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits." Cisco Technology, Inc. US 7,027,597 B1.
• Dates: Filed 2001-09-18; issued 2006-04-11.
• Description: Modular multiplication/exponentiation via dual-pass Montgomery with pre-computed constants; expressly supporting RSA, Diffie-Hellman, and DSA; register files, an array of multiplier circuits and an array of modular reduction circuits.
• Relevance / claims potentially affected: Relevant to claims 1, 2, 12 (modular multiply architecture and modular operations for cryptographic protocols); claims 3/4 (multiplier array / segmented multiply) at a generic level; the "selectable protocol" theme touches claims 1, 11, 16. Note it is a method/architecture reference and does not recite an ICU/MAU split or a sign-inversion unit.
• § 102 assessment: Not an anticipation of claims 1/12; § 103 candidate at best. (Related sibling: US 7,027,598 B1, same family.)
• Source: https://patents.google.com/patent/US7027597

1.5 US 6,397,241 B1 and US 6,671,709 B2 — multiplier cell (same family)

• Full citation (a): "Multiplier cell and method of computing." Motorola, Inc. US 6,397,241 B1. Filed/priority 1998-12-18; issued 2002-05-28.
• Full citation (b): "Multiplier cell and method of computing." Motorola, Inc. US 6,671,709 B2. Priority 1998-12-18; issued 2003-12-30. (Appears in the "Patent Citations (10)" table; not in the "Citations (9)" table.)
• Description: A multiplier cell and its computing method — i.e., the bit-slice building block for modular/multiplication hardware, not a full crypto-engine.
• Relevance / claims potentially affected: Relevant to claim 4 (bitwise-segmented multiplier/multiplicand/modulo) and claim 3 (multiplication-element architecture). Not relevant to the independent claims' dual-protocol/ICU or sign-inversion elements.
• § 102 assessment: Cannot anticipate claims 1/12. May be relevant to the multiplier-element dependents as § 102/§ 103 art.
• Verification caveat: I could not complete independent retrieval of US 6,397,241 within this session (tool step limit), so the description above is based on the citation record and the title/assignee metadata, not a page-level read. Treat with corresponding caution.
• Source: '492 citation tables; US6671709B2 record (same title/assignee/priority).

1.6 US 6,397,241 — see 1.5 above (grouped to avoid double-counting).

1.7 US 4,316,055 A — stream/block cipher system (background only)

• Full citation: "Stream/block cipher cryptographic system." International Business Machines Corporation. US 4,316,055 A.
• Dates: Filed/priority 1976-12-30; issued 1982-02-16.
• Description: A symmetric stream/block cipher system.
• Relevance / claims potentially affected: General cryptographic background only. It is a symmetric cipher reference and discloses nothing about public-key modular arithmetic, RSA/ECC selection, or sign inversion.
• § 102 assessment: Does not anticipate any claim of the '492 patent. Background art under the "Definitions" keyword list ("bit, data, operations") at most.

1.8 US 4,484,301 A — array multiplier (one's complement)

• Full citation: "Array multiplier operating in one's complement format." Sperry Corporation. US 4,484,301 A.
• Dates: Filed/priority 1981-03-10; issued 1984-11-20.
• Description: Hardware array multiplier using one's-complement format.
• Relevance / claims potentially affected: Only to the multiplier-hardware dependents (claims 3, 4), and only at a generic level (it is not a modular multiplier for cryptography).
• § 102 assessment: Does not anticipate claims 1/12; marginal relevance even to claim 4.

1.9 WO 2000/046954 A1 — encryption stream ciphers (background only)

• Full citation: "Method and apparatus for generating encryption stream ciphers." Qualcomm Incorporated. WO 2000/046954 A1.
• Dates: Filed/priority 1999-02-08; published 2000-08-10.
• Description: Generation of symmetric encryption stream ciphers.
• Relevance / claims potentially affected: General cryptographic background. No modular arithmetic, no dual public-key protocol selection, no sign inversion.
• § 102 assessment: Does not anticipate any claim of the '492 patent.

1.10 US 2002/0191791 A1 — hash processing system (background only)

• Full citation: Anand, Satish N. "Apparatus and method for a hash processing system using multiple hash storage areas." US 2002/0191791 A1.
• Dates: Filed/priority 2001-06-13; published 2002-12-19.
• Description: A hashing system with multiple hash storage areas.
• Relevance / claims potentially affected: Memory/"multiple storage areas" architecture is tangentially analogous to the '492 SRAM-Block memory unit (claims 2, 5), but hashing is not modular arithmetic and the reference discloses no ICU/MAU or sign-inversion unit.
• § 102 assessment: Does not anticipate claims 1/12; only weak § 103 color against the memory-unit dependent claims, if any.

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2. Ranking of the cited art by relevance to the '492 claims

No cited reference individually anticipates independent claim 1 or claim 12. Each of the two most relevant (Toshiba '540 and Certicom '179) covers the "one engine, two public-key protocols" idea but lacks the sign-inversion unit on temporary data that both independent claims require, and the Toshiba reference uses GF(2^m) rather than GF(p). The combination of Toshiba '540 (or Certicom '179) with Cylink '781 (prime-field modular arithmetic with a two's-complement feedback register) is the most plausible § 103 attack the record supports — but even that combination would need an additional teaching for the dedicated sign-inversion unit on temporary data to reach the issued claims. This is the reason the sign-inversion limitation appears to be the claim's load-bearing element.

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3. Related / nearby material (not § 102 art on the face of the patent)

• Parent US 7,634,666 B2 ("Crypto-engine for cryptographic processing of data," Ser. No. 10/641,869) — same family, not prior art to the '492 patent; but it is the direct comparison point for how the claims narrowed (the parent-style summary recites a generic "multiplication unit, an addition unit and a sign inversion unit" without the temporary data limitation). A validity analysis should read the two claim sets side-by-side.
• CN 101212292 A ("ECC/RSA encryption/decryption coprocessor") appears in the "Similar Documents" list, not the citation table. It is thematically on point (dual RSA/ECC coprocessor) but is not art cited against the '492 patent and, on the dates shown (2008), post-dates the 2003 priority and could only be § 102(a)/(e)/§ 103 art depending on proof of date. Flagged for completeness.
• Non-patent citations in the record are not prior-art references — they are the prosecution papers for the parent application (Office Actions of 2007-02-13, 2007-10-17, 2008-08-21; Notice of Allowability 2009-07-24). I did not retrieve their contents, so I cannot state which reference the examiner actually used.

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4. Caveats (stated openly)

1. I did not retrieve the actual rejections. My § 102/§ 103 characterizations are reasoned from the reference disclosures, titles, and abstracts I retrieved — not from the Office Actions, which are not in the supplied text. Any statement that a reference "anticipates" or "does not anticipate" is my analytical judgment, not a record citation.
2. Anticipation is element-by-element. For a clean § 102 anticipation, one reference must disclose every limitation. None of the ten references does so for claims 1 or 12, chiefly because of the sign-inversion-unit-on-temporary-data element. Accordingly I have classified most of them as § 103 candidates rather than § 102 anticipators, and said so per reference.
3. Unverified reference: US 6,397,241 B1. Retrieval did not complete in this session; the entry above is based on the citation record plus title/assignee/priority metadata.
4. Date discrepancies (stated literally, not auto-corrected): US 4,891,781 priority is 1987-03-04 in the '492 record but 1987-03-03 at Unified Patents (grant 1990-01-02 vs 1990-01-01). US 6,230,179 lists Motorola as assignee in the '492 record but Certicom Corp in the patent PDF.
5. § 102 subsection matters under pre-AIA. Given the 2003 priority, US patents/published applications from these references qualify under § 102(e) as of their filing dates. Publication dates shown above are the issue/publication dates and are used for readability; the earlier filing/priority dates control the § 102(e) analysis.
6. No litigation is tied to this patent. Consistent with the earlier-generated sections, I found no case, IPR, or appeal identifying US 8,458,492; the "Family has litigation" Darts-IP flag (family ID 34136462) remains unexplained in the Google Patents text.

5. Bottom line

The most relevant prior art to US 8,458,492 is US 7,277,540 B1 (Toshiba) and US 6,230,179 B1 (Certicom/Motorola) — both disclose a single arithmetic processor supporting two public-key cryptosystems (RSA and elliptic-curve), which maps to the shared ICU/MAU kernel of claims 1 and 12. They are supported by US 4,891,781 (Cylink) and US 7,027,597 (Cisco) for the prime-field modular arithmetic unit, and by US 6,397,241 / 6,671,709 (Motorola) for the multiplier-cell dependents. None anticipates the issued independent claims on its own, because none discloses the claimed sign-inversion unit performing sign inversion operations on temporary data — the limitation that appears to define the patented contribution. The remaining cited references (IBM '6055, Sperry '4301, Qualcomm WO'954, Anand '1791) are cryptographic/hardware background and do not reach the modular-arithmetic claims.

Sources: https://patents.google.com/patent/US8458492/en (authoritative full text & citation tables) • https://patents.google.com/patent/US7277540 • https://patents.google.com/patent/US6230179B1/en • https://portal.unifiedpatents.com/patents/patent/US-6230179-B1 • https://patents.google.com/patent/US4891781 • https://portal.unifiedpatents.com/patents/patent/US-[4891781](/patent/4891781)-A • https://patents.google.com/patent/US7027597 • https://uspto.report/patent/grant/[7,027,597](/patent/7027597) • https://uspto.report/patent/grant/[7277540](/patent/7277540)

I'll ground this obviousness analysis in the references actually listed in the patent's Prior Art / citations sections, and verify a few of them.

Let me verify two references that surfaced and that are relevant to the shared-engine and sign-handling elements.

Obviousness Analysis — U.S. Patent No. 8,458,492 B2

("Crypto-engine for cryptographic processing of data") under 35 U.S.C. § 103

Analyst note on scope. Per instructions I build on the previously generated summary and litigation sections rather than repeating them. This analysis is grounded in the Prior Art section of the patent page — i.e., the examiner-cited "Citations (9)/(10)" table, the "Similar Documents," and the "Families Citing"/non-patent citations — plus two supplementary references I located by search (flagged as such). I do not have the actual Office Actions (only their dates: 2007‑02‑13, 2007‑10‑17, 2008‑08‑21, Notice of Allowability 2009‑07‑24), so every element-by-element mapping below is my own reconstruction, not a verified examiner position.

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1. Governing framework

Level of ordinary skill. A person having ordinary skill (POSITA) here is a hardware/VLSI engineer with a bachelor's degree (or equivalent) in EE/CS and 3–5 years of experience, or a graduate degree plus 1–2 years, in the design of finite-field / modular-arithmetic coprocessors for public-key cryptography. This level is consistent with the patent's own disclosure (0.35 µm implementation, ~15K–20K gate counts, 64‑bit datapath) and with the sophistication of the cited art.

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2. The prior-art universe from the patent page, with qualification

2a. Examiner-cited references ("Citations" table)

Non-patent citations (the parent's four pre-grant Office Actions / Notice of Allowability) are prosecution documents, not prior art, but they confirm the '492 claims were narrowed during prosecution of the parent — consistent with the sign-inversion limitation being the allowance hook.

2b. "Similar Documents" of potential use

2c. "Families citing" — all post-date the priority date

US 2007/0101401 A1; US 7,870,399 B2; US 9,860,055 B2; EP 2 978 158 A1; CN 104536913 B; US 9,948,460 B2; CN 106921638 B; CN 110113147 A — all 2007 or later; none is § 103 art for a 2003 priority date. They are excluded.

2d. Supplementary reference (found by search; NOT on the patent page)

EP 1 293 891 A2/B1/B2 — "Arithmetic processor accommodating different finite field size" (Google Patents EP1293891A2, EP1293891B1, EP1293891B2). Disclosure: an ALU "includes shared finite field and integer arithmetic circuitry"; "a mode selection control 10 is provided to select between either finite field computations or modular integer computations"; a controller that "provides the appropriate arithmetic mode and operation to the ALU"; and a host bus interface ("receives control signals from the host system and communicates data to the host data bus"). Its background expressly states the motivation: "with the advent of superior and more secure EC cryptography the need for processors that perform modular exponentiation exclusively is becoming less imperative. However, while users are in transition from RSA cryptography to EC cryptography there is a need for an arithmetic processor that supports both these operations, with little or no penalty in performance and cost."

⚠️ Caveat: I retrieved this from Google Patents and did not independently verify its filing/priority date from an authoritative register. Its A2 publication and the cited public debate (references to EP‑A 0 267 836 and De Win et al. 1996) indicate the 2002–2003 window; confirm the priority date before relying on it as § 102 art. Also note it is not in the '492 record's citation list, so it was apparently not before the examiner.

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3. Claim 1 — element-by-element mapping

Assessment: claim 1 is likely obvious over US 7,277,540 in view of US 4,891,781 (and optionally US 4,484,301 / EP 1 293 891). Element (d) is the only element not squarely met by the Toshiba reference alone, and it is met by Cylink as an analogous-art modular-arithmetic chip.

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4. Identified § 103 combinations

Combination 1 (primary): US 7,277,540 (Toshiba) + US 4,891,781 (Cylink)

Why Toshiba is the natural starting point. Toshiba states the identical problem the '492 patent identifies. The '492 Background concedes: "in known hardware architectures resources cannot be shared by the algorithms and reused." Toshiba answers exactly that: "As is obvious from the comparison between the circuits shown in FIGS. 24 and 26, an integer based multiply operation and finite field GF(2^m) arithmetic operation … totally differ in their architectures … Attempts have therefore been made to form different hardware arrangements for the respective cryptosystems." Toshiba then teaches unifying them (selector 13 + shared adder 14/15 + carry holder 16 + buffers).

Why a POSITA would add Cylink's sign-inversion/reduction hardware. Toshiba's unified engine already buffers "interim result data" and a "carry" (claim 2's memory unit / claim 6's feedback). Cylink contributes the one missing functional block — a hardware generator of the additive inverse (two's complement) used with an overflow register to add/subtract and conditionally reduce interim values with minimal gate cost. A POSITA implementing GF(p) ECC on Toshiba's engine would necessarily need modular subtraction/negation (EC point arithmetic flips the y‑coordinate sign; and, as the search results confirm for the field generally, "negative values can be generated by subtractions" in modular-inversion loops — standard knowledge). Adding a dedicated inversion unit is a predictable, low-risk use of a known technique to improve a similar device in the same way (KSR).

Motivation factors (KSR/Graham):

• Same field of endeavor (public-key crypto coprocessors for smart cards / IC cards); both expressly address RSA and GF(p)/EC arithmetic, so Cylink is analogous art.
• Express design incentive: chip area and gate count. Toshiba's own IC‑card LSI context and the '492 patent's own stated gate-count goal (15K RSA / 20K RSA+ECC) show a strong, documented motivation to share logic rather than add separate units.
• Finite number of identified approaches: to perform modular subtraction/sign handling in hardware, one either (i) adds the two's complement of the modulus, or (ii) conditionally subtracts the modulus. Both are disclosed in Cylink; both are the predictable solutions, not an inventive leap.

Combination 2 (strongest, but uses non-record art): US 7,277,540 + EP 1 293 891 + US 4,891,781

Toshiba selects between two distinct multiplier circuits; EP 1 293 891 goes further and discloses an ALU that is literally "shared finite field and integer arithmetic circuitry" with a mode selection control. Combined with Cylink's sign-inversion/reduction block, this combination maps every claim-1 limitation — including the "use the same modular arithmetic unit for both protocols" requirement, which is Toshiba's weakest point and EP 1 293 891's strongest. EP 1 293 891 also supplies the express motivtion sentence quoted in § 2d. Limitation: EP 1 293 891 is not in the '492 citation list and its date needs verification.

Combination 3 (dependent claims): + US 6,230,179 and US 6,397,241 / US 6,671,709 (Motorola), US 7,027,597 (Cisco), US 2002/0191791 A1 (Anand)

Conclusion on the dependent claims: claims 2, 3, 4, 6, 7, 9, 10, 11, 13–16 are each obvious over Combinations 1–3; claims 5, 8 are the weakest (pure design choice / routine feedback), which makes them more vulnerable to § 103, not less.

The method claims (12–18)

Claim 12 is the apparatus claim restated as steps and adds nothing beyond Toshiba's operation of the coprocessor for RSA and then for EC, plus Cylink's inversion step. Toshiba's specification describes operating the same coprocessor to execute "a long integer multiply operation or finite field GF(2^m) based multiply operation" under host control — i.e., the recited "receiving first inputs … performing … receiving second inputs … performing" sequence. Claim 12 is obvious for the same reasons as claim 1. The mirror-image dependents 13–18 fall with their apparatus counterparts.

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5. Motivation-to-combine narrative (for an obviousness rejection)

A POSITA reading US 7,277,540 would understand that:

1. RSA (integer modular) and ECC (finite-field/modular) coprocessors had historically been built as separate hardware, and that this duplication is wasteful for area- and cost-constrained IC-card/smart-card LSIs (Toshiba's own stated problem).
2. The remedy — a shared arithmetic datapath selected by mode — was known and desired before 2003, as both Toshiba (selector 13 + shared adder/carry holder) and EP 1 293 891 ("shared finite field and integer arithmetic circuitry" + mode selection) demonstrate, and as the '492 specification itself admits.
3. Implementing GF(p) ECC and RSA on one modular engine requires modular subtraction/negation on intermediate values (EC point negation; Montgomery/modular reduction loops). The predictable hardware answer — a two's-complement/additive-inverse generator used with an overflow register and conditional reduction — was already disclosed in US 4,891,781 in the same field and for the same purpose (exponentiation "in the ring of integers modulo a composite number … such as in the RSA public key cryptographic scheme"), and one's-complement sign handling in a multiplier was old (US 4,484,301).
4. Combining these teachings yields nothing more than the predictable aggregation of known elements, each performing its known function (Claim 1's MAU + ICU + SIU), with a reasonable expectation of success — a shared datapath had already been demonstrated by Toshiba itself.

Under KSR, this is a textbook "combination of familiar elements according to known methods … yields predictable results," and, alternatively, a "use of a known technique to improve a similar device in the same way."

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6. Where the patent may resist (and where it does not)

Likely to survive: nothing in the granted independent claims is architecturally specific. If § 103 is contested, expect the patentee to argue (a) that Toshiba's ECC is over GF(2^m) (polynomial basis), not GF(p) modular arithmetic, so it does not teach "modular arithmetic" for the second protocol, and (b) that no record reference teaches a dedicated sign inversion unit as opposed to an adder/carry datapath. Both are rebuttable: the '492 specification repeatedly ties ECC to GF(p) with "modular multiplication" as the shared operation, and Cylink supplies exactly the negation/reduction block; ECC over GF(p) additionally requires subtraction (EP 1 293 891's own background says so).

Notably absent: no secondary considerations of nonobviousness are apparent. There is no known litigation, licensing campaign, or commercial-success evidence tying the '492 patent to any product (see the prior litigation section — the negative finding stands). With no nexus evidence, there is no rebuttal to a prima facie § 103 case.

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7. Explicit caveats and contradictions to flag

1. File history is inferred, not verified. I have only the dates of the parent's Office Actions and Notice of Allowability. My inference that the sign-inversion limitation was the allowance hook is reasoning from the record's shape, not a document I read. If the actual Office Actions relied on US 7,277,540 and/or US 7,027,597 (both examiner-cited), a re-analysis should address the examiner's own reasoning.
2. EP 1 293 891 and the Wolkerstorfer "Dual-Field Arithmetic Unit" line of art are not on the patent page. EP 1 293 891 is the strongest single piece for the "shared engine" limitation, but its priority/filing date must be verified before asserting it as § 102/§ 103 art. Treat it as the top item to run down.
3. CN 101212292 A ("ECC/RSA coprocessor", 2008) is NOT prior art to a 2003 priority date despite describing the same architecture (RSA/ECC switch, modular multiply/add/subtract). Do not cite it in a § 103 rejection; it is only evidence that the concept was conventional by the mid-2000s.
4. Contradiction with the earlier-generated summary re: claim 7. The earlier section flagged that claim 7 recites "the arithmetic unit" where "the addition unit" would be expected. The record shows a Certificate of Correction dated 2014‑03‑25, which may have corrected exactly this. I am not auto‑correcting the claim text; flagging only that the printed claim and the corrected claim should be compared before relying on the literal wording.
5. Assignee/status data (Google Patents disclaims accuracy) and the 2025‑11‑02 adjusted expiration are as-listed and unverified beyond the supplied record. Expiry of a patent does not affect the § 103 analysis but does explain the absence of enforcement.
6. The patent spells the elliptic-curve cryptosystem "EEC" in two places in the Background (the "ECC" spelling is used elsewhere). I have not auto-corrected this; it is a drafting inconsistency only and has no § 103 effect.

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Sources

• US 7,277,540 B1 (Shiba/Toshiba) — abstract and specification: https://patentimages.storage.googleapis.com/3d/1c/1f/c8d7ca0417afc2/[US7277540B1](/patent/US7277540B1).pdf · https://uspto.report/patent/grant/7277540
• US 4,891,781 (Omura/Cylink) — abstract, two's-complement feedback, overflow/reduction means: https://patents.google.com/patent/US4891781 · https://patentimages.storage.googleapis.com/bb/29/58/849243e0052fb5/US4891781.pdf
• EP 1 293 891 A2/B1/B2 — "shared finite field and integer arithmetic circuitry," mode selection control: https://patents.google.com/patent/EP1293891A2/en · https://patents.google.com/patent/EP1293891B2
• US 4,484,301 — one's-complement array multiplier (per the patent's citation table): https://patents.google.com/patent/[US8458492](/patent/US8458492)/en
• CN 101212292 A — ECC/RSA coprocessor (post-dates priority; context only): https://www.zhangqiaokeyan.com/patent-detail/06120105417101.html
• Full patent text and citation tables: https://patents.google.com/patent/US8458492/en

Bottom line: Claims 1 and 12 (and their dependents) are, on this record, obvious under § 103 over US 7,277,540 in view of US 4,891,781, with US 4,484,301 and US 6,230,179 / US 6,397,241 / US 6,671,709 supplying the sign-handling and bitwise-segmented-multiplier limitations of the dependents. The combination is materially strengthened if EP 1 293 891 is confirmed as § 102 art, because only that reference squarely teaches the shared (rather than merely selectable) finite-field/integer arithmetic circuitry that claim 1's third clause requires.