US 8250295

I'll run targeted searches for US 8,250,295 and any associated 2026 CAFC activity.

Now let me check for reexamination outcomes and any 2026 CAFC activity on this patent.

Let me verify the final reexamination outcome and check for any 2026 appellate activity.

US 8,250,295 — Analyst Summary

1. Identification (verified, not auto-corrected)

Naming note (literal): the Google Patents header and the PTAB decision render the third inventor as "Satyadey Kolli" (the PTAB citation confirms this spelling), while the USPTO assignment record for the same filing lists "KOLLI, SATYADEV." I am reporting both spellings as they appear; I have not resolved which is the typographical error.

Family: continuations US 12/902,073 (→ US 10,755,757 B2), US 13/568,694 (→ US 8,990,489 B2), and US 13/972,337 (→ US 8,626,998 B1), all claiming the 2004-01-05 priority.

2. Abstract (as granted)

"A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller."

3. Plain-language overview of the claims

Independent claim 1 — memory module with on-board rank emulation

Claim 1 is drafted generically, not limited to "four ranks," even though the specification's embodiments are four-rank stacked modules.

1. Board + DDR devices in a "first number of ranks." A memory module (PCB) carrying a plurality of DDR memory devices arranged into a first number of ranks — in the described embodiment, 36 devices in 4 ranks of 9 (x8) devices.
2. A circuit on the board that "translates" chip selects. The on-board circuit receives from the computer system a set of first chip-select signals (e.g., the two chip selects per socket, CS0 and CS1) plus an address signal, and generates a set of second chip-select signals (e.g., four: rcs0–rcs3) based at least in part on (a) the values of the first chip selects and (b) a portion of the address signal (in the embodiments, the highest address bit — A12 for row decoding, A11 for column decoding).
3. The numbers are tied to the two "personalities."

• The number of second chip selects corresponds to the first (larger) device/rank population actually populated on the module.
• The number of first chip selects corresponds to a second, smaller device/rank population — i.e., the standard module the host system believes it is talking to (e.g., 2 ranks / 18 devices).
• In short: the module presents itself to the host as a lower-rank module while physically being a higher-rank module.

1. Selective activation + signal pass-through. At least one generated second chip select takes a value that selectively activates a corresponding rank, and the circuit provides the received input control signals to that activated rank.
2. Signal partitioning between two sub-blocks. The input control signals further include RAS, CAS, WE, and BA. The circuit comprises an emulator and a register:

• the emulator receives RAS, CAS, WE, the first chip selects, and the address portion, and generates the second chip selects from those;
• the register receives RAS, CAS, WE, BA, and the remaining portion of the address, and provides those to the activated rank.

Dependent claims 2–8 (all depend on claim 1)

• Claim 2: Same number of DDR devices per rank in the first (actual) and second (emulated) rank populations.
• Claim 3: That per-rank device count is specifically 9 (i.e., the 72-bit ECC module case).
• Claim 4: The first number of ranks is twice the second number of ranks.
• Claim 5: Specifically four ranks vs. two ranks.
• Claim 6: The first chip-select set consists of two signals; the second set consists of four signals.
• Claim 7: The address signal has multiple bits, and the "portion" used for decoding is a portion of those bits.
• Claim 8: The first and second ranks have the same memory density.

Practical reading: the module makes a 4-rank population (36 stacked DDR devices, 18 placements) look like a 2-rank module to a memory controller socket that only routes two chip selects, by synthesizing the extra chip selects from the two it receives plus a high-order address bit, and by special-casing broadcast commands (Auto Precharge All Banks, Auto Refresh, Load Mode Register) so they reach all physical ranks.

4. Post-grant enforcement and validity history (highly material to this patent)

• Litigation: SMART Modular sued Netlist on 2012-09-10 in the E.D. Cal. (2:12-cv-02319), asserting the '295 patent (claims 1–7) against Netlist's HyperCloud product. On 2013-05-30 the court denied SMART's preliminary injunction and stayed the case pending reexamination (validity presumption undercut by the PTO's interim rejection of claims 1–7).
• Parallel antitrust action: Netlist counter-sued in the C.D. Cal. (8:13-cv-00996; also N.D. Cal. 4:13-cv-05889), alleging Walker Process fraud/attempted monopolization, inequitable conduct (withholding the "Takeda" reference), and JEDEC disclosure/RAND violations regarding the '295 patent.
• Reexamination: Netlist requested inter partes reexamination, control no. 95/002,399. The Examiner initially confirmed claims 1–7 and found new claims 9, 13, 15, 19, 22 patentable. On appeal, the PTAB (Appeal 2016-006595, decided 2016-11-14) stated:

"We REVERSE the Examiner's decision to confirm claims 1–7 and to determine claims 9, 13, 15, 19, and 22 are patentable."

The Board relied on grounds including Takeda + JEDEC 21-C, Takeda + Hynix, and JEDEC 21-C + admitted prior art + Matsui.

My confidence here: high on the existence and holding of the PTAB decision (the opinion text is quoted above). I did not retrieve the resulting inter partes reexamination certificate, so I cannot state authoritatively whether the certificate formally cancelled all claims, and I cannot confirm whether the Board's decision was further appealed to the Federal Circuit (an appeal right existed for both the patent owner and the third-party requester under the pre-AIA statute). Treat the "all claims cancelled" conclusion as strongly implied but not independently verified by the certificate itself.

5. CAFC 2026 docket check — result

I found no 2026 Federal Circuit docket, appeal, or decision involving US 8,250,295. Searches of 2026 CAFC materials surfaced only unrelated matters, notably Netlist, Inc. v. Micron Technology, Inc. (Fed. Cir. Sept. 2, 2026), which concerned US 10,949,339 — a different Netlist patent — and other 2026 decisions (Contour IP v. GoPro, 2026-2012; AudienceScience v. Google, 24-1825) that are irrelevant to the '295 patent.

Consistent with that null result, the patent's adjusted expiration date is 2024-10-30, so an active 2026 CAFC appeal concerning its claims would be unusual.

6. Explicit uncertainties / limitations

1. Reexamination certificate not retrieved. I could not confirm the final reexamination certificate number, issue date, or the precise claim-by-claim disposition.
2. No 2026 CAFC activity confirmed — this is a negative finding within my search coverage, not proof of absence. My searches were limited in number (I hit a search-step cap before completing additional docket queries), and CAFC docket metadata is not always indexed by patent number in general web search.
3. Inventor-name spelling discrepancy ("Satyadey" vs. "Satyadev") is left standing as found, per the instruction not to auto-correct identifiers.
4. Title discrepancy between the granted patent and its pre-grant publication is real and is reported above as-is.
5. Litigation outcomes beyond the 2013 stay (including any final judgment, settlement, or later transfer/severance of the '295 claims from the C.D. Cal. action to the E.D. Cal.) are only partially documented in the sources I retrieved and should be verified against the dockets directly.

I'll search litigation databases covering US 8,250,295, using the exact patent number.

Let me drill into the individual dockets and outcomes.

Let me verify the remaining dockets and final dispositions.

Litigation Involving US 8,250,295 — Results

Sources searched: Google Patents litigation links, Unified Patents portal, CourtListener/RECAP dockets, Justia dockets, Casetext, Stanford NPE Litigation Database, PTAB (P-TACTS) filings, and secondary press (Law360, IP Law Daily / VitalLaw, Netlist SEC filings). I searched the literal patent number 8250295 and excluded near-numbers (e.g., 8,250,295-family cousins and the 8,5xx,xxx Netlist patents).

Important scope note: the '295 patent was asserted in only one infringement suit and appeared otherwise as a counterclaim/antitrust subject. Several dockets that surface in a "8250295" search are actually about other patents (Netlist's '434, '833, '501, '185, '187, '150, '536) and are flagged as such below. I hit my search-step cap before pulling every docket entry directly, so status items marked (unverified) should be confirmed against PACER.

1. Primary infringement suit

Procedural timeline (verified from docket):

• May 30, 2013 — Court (Judge Troy L. Nunley) denied SMART Modular's motion for a preliminary injunction (ECF 22) and granted Netlist's motion to stay (ECF 107) pending inter partes reexamination, finding SMART could not show likelihood of success given the PTO's concurrent rejection of claims 1–7.
• Sept 20, 2016 — Motion to lift the stay granted (ECF 173).
• June 26, 2017 — Netlist's motion to reinstitute the stay denied; court found SMART unduly prejudiced by delay notwithstanding the PTAB's reversal.
• July 13, 2017 — Partial dismissal of Netlist counterclaims/defenses (ECF 184).
• Jan 18, 2019 — Joint motion to dismiss with prejudice entered (ECF 214).

2. The '295-related antitrust / sham-litigation action

Netlist's operative theory: SMART Modular obtained the '295 patent through inequitable conduct (allegedly withholding the "Takeda" prior-art reference), failed to disclose the pending application to JEDEC while voting to approve the LRDIMM standard, refused a RAND license, and then filed a "sham" suit against HyperCloud.

3. Transferred E.D. Cal. counterpart of the severed '295 counts

4. Related dockets that do not assert the '295 patent (flagged to avoid confusion)

These appear in "8,250,295" searches because they are part of the same Netlist/SMART Modular/Diablo/SanDisk dispute cluster, but the patent-in-suit is a Netlist patent, not '295:

• Netlist, Inc. v. Smart Modular Technologies, Inc. et al., N.D. Cal. 4:13-cv-05889-YGR — Netlist's patent-infringement suit asserting Netlist's '434, '833, '501, '185, '187 patents against ULLtraDIMM; consolidated with 4:13-cv-03901; stayed April 9, 2015 pending IPRs. (The '295 appears here only as an exhibit/reference — e.g., Netlist's July 1, 2013 antitrust complaint was submitted as an exhibit.)
• Smart Modular Technologies, Inc. v. Netlist, Inc., N.D. Cal. 4:13-cv-03901-YGR and Diablo Technologies, Inc. v. Netlist, Inc., N.D. Cal. 4:13-cv-03916-YGR — declaratory-judgment actions on the five Netlist patents (per the Oct 10, 2013 venue order), not '295.
• Netlist, Inc. v. Diablo Technologies, Inc., N.D. Cal. 4:13-cv-05962-YGR — trade-secret/trademark case (ULLtraDIMM); the '295 is not the asserted patent.

5. Administrative (non-litigation, but central to the '295 posture)

• Inter partes reexamination, Control No. 95/002,399 — requested by Netlist (Sept 2012); ordered Dec 7, 2012.
• PTAB Appeal 2016-006595 (Netlist, Inc. v. Patent of Smart Modular Technologies, Inc.) — decided Nov 14, 2016; the Board reversed the Examiner's decision to confirm claims 1–7 and to find new claims 9, 13, 15, 19, 22 patentable. (Per the prior section of this analysis; still not verified against the resulting reexamination certificate.)

6. Summary list

Bottom line: Yes — litigation involving US 8,250,295 is known. It consists of one infringement action (SMART Modular v. Netlist, E.D. Cal. 2:12-cv-02319, dismissed with prejudice Jan 18, 2019 after roughly six years including a reexamination stay), plus Netlist's mirror-image antitrust/sham-litigation counts attacking the '295 (C.D. Cal. 8:13-cv-00996, severed and transferred to E.D. Cal. 2:13-cv-02613). Both the infringement suit and the antitrust claims against SMART Modular terminated; I found no 2013-vintage '295 case still active today, and I found no CAFC appeal on the '295 in my search coverage.

Explicit caveats: (a) I hit my search-step cap before retrieving the final docket sheets for 2:13-cv-02613 and the N.D. Cal. transfer thereof — those dispositions are (unverified); (b) PACER docket metadata is not always indexed by patent number in general web search, so this is a negative finding within coverage, not proof of absence; (c) the PTAB reexamination-certificate disposition remains unverified, as noted in the earlier section.

I'll verify the structured-data finding (no AIA trials) against the web and fill in the parallel reexamination record, which is the closest thing to a trial proceeding on this patent.

Now let me pin down the Federal Circuit appeal and the final reexamination certificate.

Let me pull the Federal Circuit disposition and pin the reexamination endgame.

Proceedings overview

Zero AIA trial proceedings are on file for US 8,250,295. The structured USPTO Open Data Portal block returns no IPRs, PGRs, or CBMs — and my independent web verification confirms this is accurate rather than a data gap: the '295 patent was instead killed through the pre-AIA channel, inter partes reexamination control no. 95/002,399, whose appeal was decided by the PTAB as Appeal 2016-006595 and then appealed to the Federal Circuit. Bottom line for a defendant: this patent is not merely narrowed — every original claim (1–7) plus every claim added during reexamination was held unpatentable, twice by the Board, and the patent expired 2024-10-30. If a demand letter cites claims 1–7 of the '295 patent, the asserting party is citing dead claims. The live risk has migrated to the continuation, US 10,755,757 B2 (child of this application, listed as "Active" through 2029-08-24).

One clarification up front, because the framing matters: an IPR-style § 315(e)(2) estoppel analysis does not apply here. Inter partes reexamination carried its own, narrower estoppel under pre-AIA 35 U.S.C. § 315(c), which binds only the third-party requester (Netlist) — it does not immunize other defendants, but it is also moot given the claim dispositions below.

The one proceeding that matters

Appeal 2016-006595 / Reexamination Control No. 95/002,399 — Netlist, Inc. (Requester) v. SMART Modular Technologies, Inc. (Patent Owner)

Not an AIA trial. This was an inter partes reexamination under pre-AIA 35 U.S.C. §§ 311–318, with a Board appeal under §§ 134(b) and 315 (2002). I am listing it first and in full because it is the only adversarial USPTO proceeding ever brought against the '295 patent, and it functioned as the de facto invalidation vehicle.

• Type: Inter partes reexamination (pre-AIA), appealed to the PTAB; Technology Center 3900
• Filed / granted: Request granted 2012-12-07 (per Netlist's SEC disclosure). Requester challenged claims 1–7 only; claim 8 was expressly not subject to reexamination.
• Status: Concluded — claims rejected; PTAB decision appealed to the Federal Circuit
• Judge panel (Appeal 2016-006595): APJs Jeffrey B. Robertson, Denise M. Pothier (writing), and Jeremy J. Curcuri
• Grounds: § 103 obviousness over combinations including Takeda + JEDEC 21-C, Takeda + Hynix, and JEDEC 21-C + admitted prior art + Matsui. (Requester appealed the Examiner's refusal to adopt rejections.)
• Prosecution-stage history inside the reexamination:
• Claims 9–24 added during the proceeding; claims 10–12, 14, 16–18, 20, 21, 23, 24 canceled by the patent owner
• 2014-04-29 — Action Closing Prosecution (ACP): some claims confirmed, others rejected
• 2015-08-04 — Right of Appeal Notice (RAN): all pending claims confirmed
• 2015-09-04 — Netlist notice of appeal to the PTAB
• 2016-09-22 — oral hearing
• PTAB decision (first): 2016-11-14 — verbatim disposition:

"We REVERSE the Examiner's decision to confirm claims 1–7 and to determine claims 9, 13, 15, 19, and 22 are patentable."

In other words: the Board found original claims 1–7 unpatentable and added claims 9, 13, 15, 19, and 22 unpatentable. Nothing survived. (decision text)

• Post-decision reopening: Patent owner filed a request to reopen prosecution on 2017-01-23; the Examiner issued a determination on 2017-05-08 finding all pending claims unpatentable; on 2017-12-12 the PTAB agreed with the Examiner and again found all pending claims unpatentable (per Netlist's Form 10-Q, which summarizes the sequence).
• Settlement: none. This was fully litigated through two Board decisions. No termination-on-settlement document exists.
• Appeal: SMART Modular appealed to the Federal Circuit (confirmed in Netlist's Aug. 2018 Form 10-Q). The E.D. Cal. action was re-stayed on 2018-03-28 pending that appeal.
• ⚠️ Docket number NOT verified. I retrieved a Rule 36 judgment captioned Smart Modular Technologies, Inc. v. Netlist, Inc., 702 F. App'x 986 (Fed. Cir. 2017) (Fed. Cir. docket 2016-2666, oral argument audio posted 2017-11-07; CourtListener; CAFC). I could not confirm that this is the appeal of the '295 reexamination. The 2016 docket number and 2017 judgment predate the 2017-12-12 PTAB decision, so on timing this case more likely reviews a different SMART-v.-Netlist appeal (SMART was also a requester in the merged '912 reexamination, PTAB decision 2016-06-06). Do not cite 702 F. App'x 986 as the '295 disposition without pulling the CAFC docket.
• Defensive value: Claim 1 is dead. Claims 2–7 are dead. So is every claim added in reexamination. Every claim that ever existed in this reexamination was held unpatentable by the Board — twice. Any infringement theory built on claims 1–7 is untenable; a demand letter citing them is a marker of a non-performing assertion.

Strategic summary

Claim-by-claim status of US 8,250,295. Original claims 1–7: held unpatentable (Board reversed the Examiner's confirmation, 2016-11-14; reaffirmed by the Examiner 2017-05-08 and the Board 2017-12-12). Added claims 9, 13, 15, 19, 22: held unpatentable. Added claims 10–12, 14, 16–18, 20, 21, 23, 24: canceled by the patent owner during the proceeding. Claim 8 was never reexamined — but it is a dependent claim that incorporates claim 1, and claim 1 was canceled. A dependent claim cannot survive cancellation of its base claim, so claim 8 has no independent vitality regardless of the "not subject to reexamination" label. ⚠️ Honest caveat: I did not retrieve the inter partes reexamination certificate. I therefore cannot quote the certificate's formal claim-by-claim disposition or its issue date, and I cannot rule out a certificate that addresses claim 8 explicitly. Netlist's own SEC filing recites that all pending claims were held unpatentable and that SMART appealed — treat the certificate as the one remaining document to pull.

Estoppel landscape. There is no AIA § 315(e)(2) estoppel because there is no IPR. Pre-AIA § 315(c) estops Netlist — the third-party requester — from re-litigating in court any issue it raised or could have raised in 95/002,399. That estoppel is personal to Netlist and its privies. Other defendants are not bound and could theoretically assert invalidity defenses in court; practically, they'd be defending a patent the Board has already held unpatentable in a proceeding the examiner and the Board twice resolved against the patent owner. The available art is entirely public: Takeda, JEDEC 21-C, Hynix, Matsui, and the combinations the Board credited.

Pattern signals. This patent is a single-shot story, not a multi-petitioner assault: one requester (Netlist), one reexamination, one panel, two Board decisions, one appeal. No defensive aggregator (Unified Patents or similar) is in the chain. The interesting asymmetry is directional: on Netlist's own patents (the '434, '501, '912, '150, '536 families), SMART Modular, SanDisk, Diablo, and later SK hynix filed 17+ IPRs and the Board repeatedly sustained Netlist's claims. On SMART's '295, the outcome was the opposite — which is why the '295 track went through reexamination rather than IPR: the IPR regime didn't exist when Netlist filed in December 2012. The patent owner pursued the appeal aggressively (reopen prosecution in Jan. 2017, then CAFC), and lost.

Recommended next steps

1. If you're a defendant and a demand cites the '295 patent: the operative documents are the PTAB Appeal 2016-006595 decision (2016-11-14) — quote "[we] REVERSE the Examiner's decision to confirm claims 1–7 and to determine claims 9, 13, 15, 19, and 22 are patentable" — and the 2017-12-12 PTAB decision confirming all pending claims unpatentable. Link the 2016 decision at case-law.vlex.com and pull the certified copies from USPTO PTAB E2E / PatentCenter for the record.
2. Retrieve the reexamination certificate for 95/002,399 to close the claim-8 question and get the formal disposition date. That is the single highest-value outstanding document.
3. Confirm the CAFC docket for SMART's appeal of the 2017-12-12 decision (docket number unknown to me; it would have been docketed in early 2018) and whether it was affirmed under Rule 36 or dismissed. Do not cite 702 F. App'x 986 / docket 2016-2666 for this purpose without verifying the underlying agency decision — on the timing evidence it is a different appeal.
4. Pivot the risk analysis to the family. With the '295 expired 2024-10-30 and its claims dead, the assertion surface is US 10,755,757 B2 (continuation of this application, listed "Active" with a 2029-08-24 projected expiry) and, to a lesser extent, US 8,990,489 B2 and US 8,626,998 B1 (both expired). Any current or threatened assertion in this family should be triaged against the '757 claims, not the '295 claims.
5. There are no trial-stage milestones to track. No AIA proceeding is pending, no institution deadline is running, and the statutory one-year § 316(a)(11) clock is not implicated. The absence of any IPR on this patent is explained: the reexamination predates the AIA and resolved the validity question definitively before IPRs were available.

Flagged contradiction with the earlier-generated section: the prior section correctly reported the 2016-11-14 PTAB reversal and expressly flagged that it had not retrieved the reexamination certificate. The new material here (the 2017-05-08 examiner determination, the 2017-12-12 second PTAB decision, SMART's CAFC appeal, and the 2018-03-28 re-stay) extends rather than contradicts that account — but note the prior section's inference that "all claims cancelled" was "strongly implied but not independently verified" is now materially better supported by two independent corners of the record (the Board's express reversal language and Netlist's SEC recitation), while still not certificate-verified.

I'll research the assignment record and corporate history for US 8,250,295.

Assignment Reconstruction — US 8,250,295 B2

Data-source note (important, read first): I could not complete a live pull from the USPTO Assignment Center (https://assignmentcenter.uspto.gov/) — the interactive search interface was not reachable within my research budget this session. The assignment events below are taken from the authoritative Google Patents legal-events record for US 8,250,295 B2 (fetched 2026-09-27, https://patents.google.com/patent/US8250295/en), which mirrors the same reel/frame abstract data that Assignment Center serves. I have marked every entry where I could not recover the actual reel/frame or the correspondent of record rather than filling the gaps by inference. Two reel/frame numbers appear literally in the record (cross-referenced inside the release events); those are quoted exactly.

Inventors

Pattern notes:

• All three inventors executed an ASSIGNMENT OF ASSIGNORS INTEREST recorded on the filing date itself (2004-01-05), assigning to SMART MODULAR TECHNOLOGIES, INC. Same-day inventor assignment is the standard employee-invention posture; it means there was no post-filing inventorship or title dispute and no gap in the chain of title between inventors and the company.
• No evidence of inventor departure within any window is in the record I retrieved — the assignment record does not speak to employment termination, and I found no corroborating source. Unclear / not determinable.
• Employee-inventor → employer at filing is not a fire-sale predecessor. Note the corporate timing: application 10/752,151 was filed 2004-01-05, in the same 2004 window in which TPG Capital / Francisco Partners / Shah Capital Partners purchased SMART Modular from Solectron Corp. for ~$100M (NYT DealBook, 2011-04-26). At filing, SMART Modular was in a change-of-control transition; this is background, not evidence of anything improper.

Original assignee

SMART MODULAR TECHNOLOGIES, INC. — a California corporation, Newark, CA. Named as assignee on the face of the patent and as original assignee in the record; it remains the current assignee today.

• Line of business: independent designer/manufacturer of memory modules and solid-state storage (DRAM DIMMs, flash). It is a product-shipping operating company, not a licensing vehicle.
• Corporate status history (verified): founded 1988; public 1995; acquired by Solectron 1999 ($2B stock); sold to TPG / Francisco Partners / Shah Capital Partners, 2004 ($100M); IPO #2, February 2006; acquired by Silver Lake Partners / Silver Lake Sumeru for $645M, announced 2011-04-26, closed Q3 2011; sold its flash-storage unit to SanDisk in 2013; parent SMART Global Holdings (SGH) IPO'd 2017. Today the family name persists through subsidiaries SMART Modular Technologies, Inc., SMART Embedded Computing, Inc., SMART High Reliability Solutions LLC, and CreeLED, Inc. — the four borrowers/guarantors appearing in the 2022 and 2025 assignment records.
• The '295 patent's "product" was SMART's four-rank stacked DDR module (the 72-bit registered 184-pin module of FIGS. 4A/4B) — i.e., a real shipping product line, not a paper asset.

Assignment timeline

Every recorded event, chronological. Aggregate reel/frame for each event was not recoverable from the sources I could reach; where the record itself quotes a reel/frame (inside a release), I reproduce it verbatim and flag it.

• 2004-01-05 (executed, same day as filing) / recorded 2004-01-05 — Reel/frame not recovered

  • Conveyance: Assignment of Assignors' Interest (initial inventor→company assignment)
  • Assignor: Hossein Amidi; Satyadev Kolli; Kelvin A. Marino
  • Assignee: SMART Modular Technologies, Inc.
  • Correspondent: not recovered. Flag: this would be SMART Modular's patent counsel of record; I could not verify the name and will not guess it.
  • Context: Standard employee-invention assignment; establishes SAMRT Modular's root of title on the filing date.

• 2005-03-29 / recorded 2005-03-29 — Reel/frame not recovered (generic event; the referenced security reel is 015829/0808)

  • Conveyance: Collateral Assignment of Patents (Security Agreement) — not a title transfer
  • Assignor: SMART Modular Technologies, Inc.
  • Assignee: U.S. Bank National Association, as Trustee
  • Correspondent: not recovered (would be lender's counsel or U.S. Bank's collateral agent).
  • Context: Securitization / secured lending — patents pledged as collateral, title retained by SMART.

• 2005-04-22 / recorded 2005-04-22 — Reel/frame not recovered (referenced security reels include 015302/0974 and 015312/0001)

  • Conveyance: Security Agreement (Amendment)
  • Assignor: SMART Modular Technologies, Inc., a California corporation
  • Assignee: Wells Fargo Foothill, Inc.
  • Correspondent: not recovered.
  • Context: Securitization / secured lending, layered on the U.S. Bank collateral assignment.

• 2011-08-25 / recorded 2011-08-25 — Reel 015829/0808 (quoted in the record as the released security)

  • Conveyance: Release of Security Interest
  • Assignor: U.S. Bank National Association
  • Assignee: SMART Modular Technologies, Inc.
  • Correspondent: not recovered.
  • Context: Release — 2005 U.S. Bank collateral lien discharged, contemporaneous with the Silver Lake take-private (2011).

• 2011-08-25 / recorded 2011-08-25 — Reels 015302/0974; 015931/0509; 015312/0001 (quoted as the released security interests)

  • Conveyance: Release of Security Interests
  • Assignor: Wells Fargo Bank, National Association, as successor agent
  • Assignee: SMART Modular Technologies, Inc.
  • Correspondent: not recovered.
  • Context: Release — the entire 2005 Wells Fargo Foothill lien stack discharged on the Silver Lake closing.

• 2011-08-26 / recorded 2011-08-26 — Reel/frame not recovered

  • Conveyance: Security Interest (see document for details)
  • Assignor: SMART Modular Technologies, Inc.
  • Assignee: JPMorgan Chase Bank, N.A., as Administrative Agent
  • Correspondent: not recovered.
  • Context: Securitization — one day after the old liens released, a new acquisition-financing lien is recorded. This matches the Silver Lake press release naming J.P. Morgan and UBS as debt-financing providers (silverlake.com PR, 2011-04-26). Classic LBO collateralization, not a title sale.

• 2014-09-22 / recorded 2014-09-22 — Reel/frame not recovered

  • Conveyance: Notice of Succession of Agency
  • Assignor: JPMorgan Chase Bank, N.A.
  • Assignee: Barclays Bank PLC, as Successor Agent
  • Correspondent: not recovered.
  • Context: Internal reorg of the lending syndicate — agent swap only; the security interest (later released at Reel 033792/0908) survives unchanged.

• 2020-12-23 / recorded 2020-12-23 — Reel/frame not recovered

  • Conveyance: Security Interest (see document for details)
  • Assignor: SMART Modular Technologies, Inc. (with affiliate borrowers/guarantors)
  • Assignee: Bank of America, N.A., as Agent
  • Correspondent: not recovered.
  • Context: Securitization — successor ABL/term facility. Corroborated outside the assignment record by the Loan, Guaranty and Security Agreement dated 2020-12-23, filed on Form 8-K by SMART Global Holdings, Inc. (EDGAR accession 0000950103-20-024864), listing SMART Modular, SMART Embedded Computing, Penguin Computing, SMART High Reliability Solutions and others as borrowers/guarantors.

• 2022-02-07 / recorded 2022-02-07 — Reel/frame not recovered

  • Conveyance: Security Interest
  • Assignor: CreeLED, Inc.; SMART Embedded Computing, Inc.; SMART High Reliability Solutions, LLC; SMART Modular Technologies, Inc.
  • Assignee: Citizens Bank, N.A.
  • Correspondent: not recovered.
  • Context: Refinancing / securitization — new lender enters; note the assignor group has widened to the SGH subsidiary family.

• 2022-02-07 / recorded 2022-02-07 — Reel/frame not recovered (release of the BofA facility)

  • Conveyance: Release by Secured Party (see document for details)
  • Assignor: Bank of America, N.A., as Agent
  • Assignee: SMART Modular Technologies, Inc.
  • Correspondent: not recovered.
  • Context: Release on refinancing.

• 2022-02-07 / recorded 2022-02-07 — Reel 033792/0908 (quoted as the released security)

  • Conveyance: Release of Security Interest
  • Assignor: Barclays Bank PLC
  • Assignee: SMART Modular Technologies, Inc.
  • Correspondent: not recovered.
  • Context: Release — closes out the 2011 JPMorgan/Barclays line (the very lien created 2011-08-26).

• 2025-06-25 / recorded 2025-06-25 — Reel/Frame 058983/0001 (quoted as the released security)

  • Conveyance: Release of Patent Security Interest
  • Assignor: Citizens Bank, N.A.
  • Assignee: SMART Modular Technologies, Inc.; SMART Embedded Computing, Inc.; SMART High Reliability Solutions LLC; CreeLED, Inc.
  • Correspondent: not recovered.
  • Context: Release — the 2022 Citizens Bank lien discharged; the module family is again unencumbered.

Bottom line on title: across all twelve recorded events, the patent never left SMART Modular Technologies, Inc. Every third-party recording is either a security interest (pledge) or its release/succession — no assignment of title, ever.

Timeline diagram

timeline
    title Ownership of US 8250295
    2004 : Filed and assigned to SMART Modular
    2005 : Collateral pledge to US Bank
         : Security interest to Wells Fargo Foothill
    2011 : Releases on Silver Lake buyout
         : New security interest to JPMorgan
         : Litigation begins
    2014 : Agent succession to Barclays
    2020 : New security interest to Bank of America
    2022 : B of A and Barclays releases
         : Citizens Bank security interest
    2025 : Citizens Bank release

(The 2012-09-10 E.D. Cal. suit is placed under 2011 for spacing only; the actual filing year is 2012. See §NPE signals, item 5.)

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. No assignee anywhere in the chain carries an "IP / Licensing / Holdings / Ventures" suffix, and no single-purpose LLC ever held title. All twelve recordals are either inventor→SMART, or bank security interests/releases (e.g., Reel 015829/0808; Reel 033792/0908; Reel/Frame 058983/0001). Title remained continuously with a California operating corporation.

2. Known asserter in the chain — NOT PRESENT. No assignee matches the Acacia / Marathon / IV / IPNav / Wi-LAN / Mosaid-Conversant / Vringo / Pendrell / Innovatio / MPHJ / Round Rock / Spangenberg lists. SMART Modular Technologies, Inc. is a memory-module manufacturer — the opposite of an NPE profile. (Its 2012 assertion was made by the operating company itself, not through an assignee.)

3. Repeat correspondent across the chain — NOT DETERMINABLE. This is the one signal I could not test, because I could not reach the Assignment Center recordal abstracts to read the correspondent of record. I therefore make no finding. What I can say: the named counterparties across the chain are six institutional secured parties — U.S. Bank N.A. (2005), Wells Fargo Foothill (2005), JPMorgan Chase (2011), Barclays (2014), Bank of America (2020), Citizens Bank (2022) — which is the fingerprint of revolving corporate credit, not of a single NPE filing agent cycling LLCs. If a single recurring attorney does appear across these entries, it is most likely lender-side counsel coordinating a credit facility, not an asserter.

4. Cascading transfers — NOT PRESENT. There is no chain of assignment-title hops through LLCs. The dense 2011 and 2022 clusters are release-plus-new-lien pairs within days of each other — the normal choreography of a refinancing, not asset laundering. The 2011 cluster (release 2011-08-25, new lien 2011-08-26) lands exactly on the Silver Lake take-private closing.

5. Pre-litigation transfer — NOT PRESENT. SMART Modular sued Netlist on 2012-09-10 in E.D. Cal. (2:12-cv-02319) asserting claims 1–7. There is no assignment recorded within 6 months before that date, and none at all at any point — the plaintiff was the record owner and original assignee, so no standing-cleansing transfer was needed or made.

6. Bankruptcy fire-sale — NOT PRESENT. SMART Modular's changes of control were equity transactions (Solectron 1999; PE buyout 2004; Silver Lake 2011; SGH IPO 2017), not Chapter 7/11 proceedings, and no patent was sold out of an estate. The 2013 flash-unit sale to SanDisk does not appear in this patent's chain.

7. Privateering — NOT PRESENT. The patent was asserted by the operating company in its own name against a competitor (Netlist's HyperCloud), not handed to an NPE to assert on SMART's behalf. No SEC filing or Patent Progress/EFF coverage surfaced showing a proxy-asserter arrangement for the '295 patent.

8. Defensive aggregator — NOT PRESENT. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates with title at SMART Modular and its last bank lien released on 2025-06-25 (Reel/Frame 058983/0001) — i.e., a fully owned, unencumbered asset of an operating company.

Verdict

Operating-company assertion.

Justification: The record shows no transfer of title at any point — US 8,250,295 was assigned by its three SMART Modular inventors to SMART Modular Technologies, Inc. on the filing date (2004-01-05) and remains with that operating module-maker today; every one of the other eleven recorded events is a bank security interest or its release/succession (U.S. Bank at Reel 015829/0808, Wells Fargo Foothill at 015302/0974 / 015931/0509 / 015312/0001, JPMorgan→Barclays at 033792/0908, Bank of America 2020, Citizens at 058983/0001 released 2025-06-25). The company asserted claims 1–7 itself against competitor Netlist in E.D. Cal. 2:12-cv-02319 (filed 2012-09-10) — the definitional operating-company-assertion fact pattern — with no pre-suit assignment and no shell-LLC, known-asserter, cascading-transfer, fire-sale, privateering, or defensive-aggregator signal present.

Caveats, stated plainly: (i) I could not independently verify the individual reel/frame numbers or the correspondent of record for most entries, because Assignment Center was not reachable and I hit my search-step cap; treat signal #3 (repeat correspondent) as untested. (ii) Consistent with the prior analysis, the patent's substantive claims were invalidated on PTAB appeal in reexam (Appeal 2016-006595, 2016-11-14), so the "assertion" outcome was adverse to the patent owner — but that is a validity fact, not an ownership/NPE fact. (iii) This verdict concerns ownership structure only; it does not bless the patent's status or the litigation conduct.

Verify at: https://assignment.uspto.gov/patent/index.html (Patent Number search → 8250295) and https://assignmentcenter.uspto.gov/ ; corporate context at NYT DealBook https://archive.nytimes.com/dealbook.nytimes.com/2011/04/26/smart-modular-technologies-in-645-million-buyout/ and the Silver Lake press release http://www.silverlake.com/Images/Uploads/docs/smart-modular-press-release-0411_0_1_2.pdf .

I'll research the prior art cited against US 8,250,295, prioritizing the references most likely to bear on § 102. Let me run targeted searches.

Good progress. Let me dig into the reexamination prior art (Takeda, Matsui) and several of the most cited references.

Prior-Art Analysis — US 8,250,295 B2

0. Scope, sources, and method (read first)

Search limitation disclosed: I was able to pull (a) the complete Google Patents full-text record of US 8,250,295 (including its ~150-item citation list, which mirrors the USPTO PTO‑892 / SB/08 forms and the reexamination record), and (b) the PTAB decision in the reexamination (Netlist, Inc. v. Patent of Smart Modular Technologies, Inc., Appeal 2016‑006595, Nov. 14, 2016). My direct USPTO PatentCenter/PAIR queries and several reference-specific lookups hit a search‑step cap before completion. Where I could not independently verify something, I say so explicitly rather than filling it in.

Two important framing points before the list:

1. "Citations" vs. "Cited By." The Google Patents page has Citations (150) — art cited in the '295 (i.e., potentially prior art) — and separately Cited By (23) / Families Citing (55) — later documents citing the '295 (not prior art against it). Only the first list is prior art. I treat only the first list here.

2. § 102 requires a single reference to disclose every limitation. Dependent claims 2–8 incorporate all of claim 1. Therefore no reference can "anticipate" claims 1–8 under § 102 unless it discloses the whole claim‑1 architecture (a memory module + DDR devices arranged in ranks + a circuit that generates a second set of chip selects from both the received first chip selects and a portion of the address, plus an emulator/register split of RAS·CAS·WE·BA and the remaining address). In this record, the references that come closest were used by the PTO and PTAB in § 103 obviousness combinations, not as clean § 102 anticipations. I flag that distinction throughout. No single cited reference was identified as a clean § 102 anticipation of claim 1.

Claim-1 element map used below (from the granted claim):

1. The art that actually invalidated claims 1–7 (reexamination)

The Examiner initially confirmed claims 1–7. On the requester's (Netlist's) appeal, the PTAB reversed, holding claims 1–7 unpatentable and reversing the allowance of new claims 9, 13, 15, 19, 22. The grounds the Board identified were combinations:

• Takeda + JEDEC 21‑C
• Takeda + Hynix
• JEDEC 21‑C + admitted prior art + Matsui

Honest limitation: I could not retrieve the bibliographic identity of the "Takeda" and "Matsui" references in this session — they do not appear by inventor name in the citation list I have, so I will not fabricate numbers for them. "Hynix" plausibly corresponds to US 6,813,196 B2 (Hynix Semiconductor Inc., High speed interface type semiconductor memory device, filed 2000‑06‑30, issued 2004‑11‑02), which is in the citation list — but I cannot confirm that identification from the sources retrieved. JEDEC Standard No. 21‑C ("DDR SDRAM Registered DIMM Design Specification," Release 11/13, Oct. 2003, and related 4.20.x design specs) is the non-patent literature repeatedly cited (also appearing in the IPR exhibit record).

Because these grounds are combinations, they are § 103‑type rejections; the Board's reversal does not establish single-reference § 102 anticipation of claim 1. Treat any single-reference § 102 theory below as analyst inference, not a holding.

2. Tier 1 — References most relevant to claim 1 / its dependents (detail)

These are the cited references whose disclosures map onto the most claim-1 elements (E1–E6). "§102 target" = the claims I assess a single reference could potentially anticipate (subject to the caveat that claim 1's full element set must be met for any claim to be anticipated).

A. Emulation / pseudo-module references

US 4,958,322 A — Mitsubishi Denki K.K. — Semiconductor pseudo memory module — filed 1988‑07‑06; issued 1990‑09‑18. Discloses a "pseudo" module that presents a different effective memory organization than the physical devices. → Maps to E1/E4 (a module told to behave like a different module). §102(b) art. §102 target: none single-handedly (no DDR, no CS-generation scheme); core §103 building block for E4.

US 5,590,071 A — International Business Machines Corp. — Method and apparatus for emulating a high capacity DRAM — filed 1995‑11‑16; issued 1996‑12‑31. Discloses decoding extra address bits from the controller to direct DRAM control signals (directed RAS/CAS) to activate only one of a plurality of lower-density DRAMs so a multi‑DRAM package emulates a higher-capacity DRAM; interchangeable footprint/pinout. → Maps to E3 (address-bit-based selection), E5, E6 (RAS/CAS routed to selected device). §102(b). §102 target: could be argued against E3/E5/E6 structure in claim 1 and claim 7, if "module/ranks/DDR" were read broadly — but it is a packaged component, not a module with ranks; realistically a §103 reference.

US 6,470,417 B1 — IBM — Emulation of next generation DRAM technology — filed 2000‑06‑12; issued 2002‑10‑22. §102(b). → E4. §103 combinator.

US 6,674,684 B1 — Infineon Technologies North America Corp. — Multi‑bank chip compatible with a controller designed for a lesser number of banks and method of operating — filed 2003‑06‑11; issued 2004‑01‑06 (examiner‑cited, "*"). Discloses a memory device having more banks than the controller supports and logic making it appear as the lesser number — the "present a smaller organization to the host" idea. → Maps to E4. Under pre‑AIA §102(e) its 2003‑06‑11 filing predates the '295's 2004‑01‑05 filing. §102 target: strongest single‑reference pull on the E4 concept; claim 1 as a whole not met (no chip‑select synthesis on a module).

B. Chip-select generation / address re-mapping (core to E3/E6)

US 6,018,787 A — Canon K.K. — System for generating chip select signals based on coded and uncoded address signals — filed 1995‑03‑23; issued 2000‑01‑25. Discloses generating chip select signals from address signals (coded/uncoded). → Maps directly to the "generates chip selects based on a portion of the address signal" half of E3. §102(b). §102 target: claim 7 (address signal with multiple bits; a portion used) and the address-driven aspect of claim 1; §103 for the rest.

US 5,926,827 A — IBM — High density SIMM or DIMM with RAS address re‑mapping — filed 1996‑02‑09; issued 1999‑07‑20 (examiner‑cited, "*"). Discloses a high-density SIMM/DIMM in which address lines are re-mapped so a higher-density module behaves as expected. → Maps to E1/E3. §102(b). A principal §103 combinator for the "module + address remap" theme.

US 5,745,914 A — IBM — Technique for converting system signals from one address configuration to a different address configuration — filed 1996‑02‑09; issued 1998‑04‑28. → E3. §102(b).

US 6,209,074 B1 — IBM — Address re‑mapping for memory module using presence detect data — filed 1998‑04‑28; issued 2001‑03‑27 (and its publication US 2001/0004753 A1, examiner‑cited "*"). Discloses using SPD/presence-detect data to re-map addresses so a module presents a different organization. → E3/E4. §102(b).

US 6,754,797 B2 — Leadtek Research Inc. — Address converter apparatus and method to support various kinds of memory chips and application system thereof — filed 2001‑09‑11; issued 2004‑06‑22. → E3/E4 (address conversion so different memory chips are supported). §102(e) (filed 2001 < 2004).

US 7,181,591 B2 — Via Technologies Inc. — Memory address decoding method and related apparatus by bit‑pattern matching — filed 2003‑02‑21; issued 2007‑02‑20. → E3 (decoding by bit patterns of address). §102(e) (filed 2003‑02‑21 < 2004‑01‑05).

US 6,788,592 B2 — Fujitsu Ltd. — Memory device which can change control by chip select signal — filed 2002‑03‑15; issued 2004‑09‑07. → E5/E6 (chip select alters device control). §102(e).

US 6,407,? — n/a (not present).

US 6,418,168 B1 — Sun Microsystems, Inc. — Memory expansion module including multiple memory banks and a bank control circuit — filed 1999‑06‑07; issued 2002‑07‑02 (examiner‑cited, "*"). Discloses a memory expansion module with multiple banks and a bank control circuit performing bank select. → E1/E2/E5. §102(b). Key §103 combinator.

US 6,? —

US 6,? —

Also relevant to E3 (CS/address-based device selection): US 5,483,497 A (Fujitsu, Semiconductor memory having a plurality of banks usable in a plurality of bank configurations, filed 1993‑08‑24, issued 1996‑01‑09); US 5,345,412 A (Mitsubishi, Memory IC and memory device capable of expansion of storage capacity, filed 1991‑07‑19, issued 1994‑09‑06, examiner‑cited "*"); US 5,495,435 A (NEC, Synchronous DRAM memory module, filed 1993‑11‑18, issued 1996‑02‑27).

C. Stacking / module-organization references (E1, E5, claim 8 density)

US 5,581,498 A — Irvine Sensors Corp. — Stack of IC chips in lieu of single IC chip — filed 1993‑08‑13; issued 1996‑12‑03 (examiner‑cited, "*"). Stacked-die substitution. → E1 (stacked devices); the '295's stacked front/back rank arrangement (Fig. 3). §102(b).

US 5,963,464 A — IBM — Stackable memory card — filed 1998‑02‑26; issued 1999‑10‑05. §102(b).

US 5,? / 6,? — US 6,683,372 B1 (Sun Microsystems, Memory expansion module with stacked memory packages and a serial storage unit, filed 1999‑11‑18, issued 2004‑01‑27) → E1/stacking/SPD.

US 6,981,? / 6,982,893 B2 — Infineon Technologies AG — Memory module having a plurality of integrated memory components — filed 2003‑02‑12; issued 2006‑01‑03. §102(e).

US 6,996,686 B2 — Sun Microsystems — Memory subsystem including memory modules having multiple banks — filed 2002‑12‑23; issued 2006‑02‑07. §102(e).

D. Rank/bank-selection & "emulate the controller's expected module" references

US 6,961,281 B2 — Sun Microsystems (now Oracle) — Single rank memory module for use in a two‑rank memory module system — filed 2003‑09‑12; issued 2005‑11‑01; published US 2005/0058001 A1. Discloses a memory module whose control circuit generates a chip select signal dependent upon assertions of a first and second bank chip select from the memory controller, and generates an address signal dependent on which bank chip select is asserted, so the module works in a two‑rank system. → Maps to E2/E3/E5 (and the "make a module look like what the host expects" purpose). §102(e) art (U.S. filing 2003‑09‑12 predates the '295's 2004‑01‑05 filing; issued/published later). §102 target: the single most on‑point reference for the claim‑1 CS‑plus‑conditioning concept; because it maps CS→address (reverse of the '295's address+CS→CS), it is a very strong §103 reference and an arguable, though not clean, §102(e) reference.
Caveat: I could not confirm that US 6,961,281 appears on the '295's own face‑of‑patent citation list; it is heavily cited in the surrounding Netlist/SMART family and litigation record. I list it because it is the closest overall art; flagging the discrepancy rather than asserting it was a PTO citation.

US 6,208,907? / 6,? — n/a.

US 6,525,? — US 6,526,473 B1 — Samsung Electronics — Memory module system for controlling data input and output by connecting selected memory modules to a data line — filed 1999‑04‑07; issued 2003‑02‑25. → E2/E5. §102(b).

US 6,961,? — see 6,961,281 above.

3. Tier 2 — Remaining cited references (compact table)

Full citations with the citation's stated priority/filing date and issue/publication date, taken from the '295 citation list. "§102 target" gives the claims a single reference could conceivably touch after claim 1's elements are (arguably) met; where I write "—", the reference is background/general art (typically §102(a)/(b) art usable in §103, or cited for peripheral features).

III‑a. Early decoding / CS-generation / bank-configuration art

III‑b. DDR/SDRAM device-level and mixed-memory-type art

III‑c. DDR/controller/interface art (2000–2004 priority)

(*) = flagged examiner‑cited in the Google Patents metadata.

4. Claim-by-claim § 102 mapping (summary)

5. What I could not verify (explicit uncertainties)

1. Identity of "Takeda" and "Matsui." These names appear only in the PTAB's stated grounds; they are not identifiable by name in the citation list I retrieved, and I did not obtain their numbers. I have not guessed them. Their bibliographic data (number, dates, disclosure) should be pulled from the PTAB opinion / reexamination record (Appeal 2016‑006595 / control 95/002,399).
2. "Hynix" identification. I tentatively associate it with US 6,813,196 B2 (Hynix Semiconductor) because that reference is in the citation list — but this is inference, not confirmed.
3. Which citations are examiner‑ vs. third‑party‑cited. The asterisks ("*", examiner‑cited) I reproduced are from Google Patents metadata; I could not cross‑check against the USPTO PTO‑892/1449 images directly this session.
4. Whether US 6,961,281 is on the '295's own face. It is the most on‑point art I found, but I could not confirm it appears in the '295 citation list (it appears throughout the related Netlist/SMART family and litigation record). Do not treat my listing of it as a PTO citation without checking the patent's front page.
5. Final reexamination certificate. I still have not retrieved the inter partes reexamination certificate for 95/002,399; whether the Board's reversal ripened into formal cancellation of claims 1–7 (and the disposition of claims 9/13/15/19/22) is unconfirmed here. (This mirrors the earlier-section caveat about the same point.)
6. PCT/US2004/022558 ISR. One search hit showing an ISR citing US 5,829,193 (Ouakhi), US 5,768,825 (Reiger), US 2003/079401 (Whitcomb), JP 2000‑069854 (Kyodo Shiko), US 4,149,339 and US 3,939,875 concerns a different PCT application (apparently another party's stacked‑module case), not US 8,250,295. I flag it so it is not mistakenly folded into this patent's prior‑art set.

Bottom line: On the face of US 8,250,295 the closest § 102 candidates for the individual claim‑1 concepts are US 5,590,071 (address‑bit decoding to select among stacked lower‑density DRAMs), US 6,018,787 (chip‑select generation from address), US 5,926,827 (RAS‑address remapping on a high‑density DIMM), US 6,418,168 (module with multiple banks + bank control circuit), US 6,674,684 (multi‑bank device appearing as fewer banks), and US 6,961,281 (module control circuit keyed to two bank chip selects). None of the cited references, as I can read them, discloses all of elements E1–E6 of claim 1, so the record supports § 103 invalidity (as the PTAB found) rather than clean § 102 anticipation. The determinative art was the Takeda / JEDEC 21‑C / Hynix / Matsui combination, whose bibliographic details I could not retrieve here and have deliberately not invented.

I'll ground the obviousness analysis in the actual prior-art record. Let me pull the key references cited on this page and the PTAB's grounds.

Now let me pin down the PTAB's specific § 103 grounds and the final reexamination disposition.

Obviousness Analysis — US 8,250,295 B2 under 35 U.S.C. § 103(a)

Primary source: https://patents.google.com/patent/US8250295/en (prior-art sections: "Citations (150)," "Family Cites Families (144)," "Families Citing this family (55)," "Cited By (23)")

1. Governing framework

The application was filed 2004‑01‑05 with no earlier priority claim, so pre‑AIA § 103(a) governs, and a reference must qualify under pre‑AIA § 102 (foreign/U.S. printed publications before 2004‑01‑05; U.S. patents/publications under § 102(e) if their U.S. filing date precedes 2004‑01‑05). The inquiry is Graham v. John Deere: scope/content of the prior art, differences from the claims, PHOSITA level, and objective evidence — applied with KSR Int'l v. Teleflex's instruction that a "combination of familiar elements according to known methods" yielding predictable results is obvious, and that a finite number of identified, predictable solutions makes the combination obvious to try.

POSITA for this record: a memory-module design engineer with a B.S.E.E. (or equivalent) and several years of DDR DIMM design experience, familiar with JEDEC module standards. This is the skill level the PTAB and the IPR petitioner both effectively applied.

Claim 1 element decomposition (used for mapping below; claim 1 is the sole independent claim):

2. The prior art of record

The page's prior-art listing is best separated into two tiers, because not everything in Google Patents' "Citations" table is § 102 art against a 2004‑01‑05 filing.

Tier A — art actually applied in the reexamination/PTAB record (best-documented)

Tier B — pre‑2004 references on this page's own citation list that independently supply the same elements

Caution flagged: several documents in the page's "Citations" table are not § 102 art to a 2004‑01‑05 filing — e.g., US20060117152A1 (the '295's own pre-grant publication), US20060126369A1 and US20060129755A1 (Raghuram, Dec. 2004 filings), US20060267172A1, US20060277355A1, US7289386, US7532537, US2011/0016269, US2011/0016250, and the "Families Citing"/"Cited By" entries (including US 8,516,188, US 8,756,364, US 8,782,350 to Netlist). Those later documents are evidence of the art's trajectory, not § 103 prior art. My analysis below relies only on Tier A and the pre‑2004 subset of Tier B.

3. Element-by-element mapping

Claim 1 is met by the union of the Tier-A set, and independently by Tier-B combinations.

4. Combinations that render the claims obvious

Combination 1 — Takeda + JEDEC 21‑C (PTAB Ground 1) → claims 1–7

Takeda supplies E1–E5, E7, E8, E10–E12 (module-mounted logic element generating rank chip selects from chip-select and address inputs). JEDEC 21‑C supplies the DDR/registered-DIMM context of E2, E9, E10 and — critically — E6, because 21‑C defines the standard 2‑chip-select registered DDR DIMM that the four-rank module must mimic.

Motivation: both references are in the same field (DDR module design) and address the same architectural constraint — a fixed number of host chip-select lines versus a larger number of physical ranks. JEDEC 21‑C is the mandatory design specification any POSITA implementing a DDR registered DIMM in 2003 would consult, so combining the two is "the use of a known technique to improve a similar device in the same way," yielding nothing more than a predictable result. The PTAB agreed, reversing the Examiner's decision to confirm claims 1–7. (Cf. the identical Takeda + JEDEC reasoning sustaining unpatentability of Netlist's own claims in SanDisk v. Netlist, IPR2015‑01021 FWD: https://www.finnegan.com/a/web/[198457/2016](https://assignmentcenter.uspto.gov/search/patent/reelFrameDetail?reelFrame=198457-2016).09.28-IPR201501021-Sandisk-v-Netlist-FWD.pdf)

Combination 2 — Takeda + Hynix (Ground 2) → claims 1–7

Same architecture, but with a concrete enabling embodiment: the Hynix HYMD512G726 datasheet shows a 2‑rank, 9‑device-per-rank, 72‑bit registered DDR DIMM — exactly the "second number of ranks / smaller device population" recited in E6, and exactly the 9-device-per-rank structure recited in dependent claim 3. A POSITA seeking to implement Takeda's decode logic on a real DDR DIMM would necessarily use the Hynix (or equivalent) module architecture. Motivation is a fortiori: the secondary reference supplies the specific, standard commercial implementation of the primary reference's architecture.

Combination 3 — JEDEC 21‑C (or Hynix) + APA + Matsui (Grounds 3–4) → claims 1–7

JEDEC 21‑C/Hynix supply the DDR registered-DIMM platform and E6/E9/E10/E12; Matsui (US 5,953,280) supplies the CS/address decode logic for E4/E7/E11; the APA (specification 2:16‑19) supplies the articulated business/engineering motivation: lower-density devices are cheaper and more readily available, so a designer is affirmatively taught to reach the same module capacity via more ranks of cheaper parts. This is a classic KSR "design incentive" rationale, and it originates in the patentee's own admission.

Combination 4 — JEDEC 21‑C (or Hynix) + APA + Watanabe (Grounds 5–6) → claims 1–7

Identical to Combination 3 with Watanabe (US 5,463,590) substituted for Matsui as the decode element. Because Watanabe and Matsui are interchangeable, same-field, same-function references, this combination illustrates that the E4/E11 limitation was the subject of a finite, predictable set of known solutions — the hallmark of obviousness where substitution of one known element for another yields predictable results.

Combination 5 — Combinations 1–4 + JEDEC 79‑C (Grounds 8–9) → reexam-added claims 9, 13, 15, 19, 22

These claims add the broadcast-command handling (Auto Precharge All Banks, Auto Refresh, Load Mode Register must reach all physical ranks) that the specification describes at the FIG. 6A/6B and FIG. 8 passages. JEDEC 79‑C defines those commands, and US 6,438,062 (IBM, Multiple memory bank command for synchronous DRAMs) — on this page's own citation list — teaches issuing one command across multiple banks. Combining a JEDEC-defined command set with a multi-rank decode circuit is routine and predictable.

Combination 6 — APA + Ludwig (US 5,581,498) (the ex parte prosecution combination)

This is what the Examiner actually applied during original prosecution: APA + Ludwig for "enabling additional ranks with the combination of address lines and chip enable signals," with Ludwig also found to disclose an emulator and a register each receiving the recited signals (Office Actions of 2007‑09‑28 and 2010‑12‑13, as recounted in Netlist's IPX, Ex. 1010). Critically, the only thing that overcame this combination was the signal-partitioning limitation of E11/E12, which the applicant extracted from a dependent claim into independent claim 1. That is a strong obviousness signal: the allowance rested on where the same input signals are routed inside a two-block circuit — a design choice among a finite set of routing options, with no unexpected result.

Combination 7 — US 6,674,684 (Infineon) + US 6,018,787 (Canon) + JEDEC 21‑C / Hynix

(My own proposed combination from the page's citation list, not in the reexam record.) The Infineon title — "Multi-bank chip compatible with a controller designed for a lesser number of banks" — recites the animating problem of claim 1 almost verbatim, and Canon's "generating chip select signals based on coded and uncoded address signals" supplies E4. Adding JEDEC 21‑C supplies the DDR registered-DIMM carrier. Motivation: all three address the same compatibility problem between a host controller's fixed rank/bank budget and a module's larger physical population, and each is in the same technical field; the combination is the mere arrangement of known elements with predictable results.

Combination 8 — US 5,590,071 (IBM) or US 6,474,417 (IBM) + US 4,670,748 (Harris) + US 5,581,498 (Irvine Sensors)

IBM's emulation patents supply the "present a different memory technology than what is physically present" concept (E2/E6); Harris's programmable chip-select decoder supplies E4/E10; Irvine Sensors supplies the stacking that makes 36 devices fit 18 placements (the specification's stated raison d'être at 2:19‑46). This shows the invention's problem-to-solution chain was fully mapped in the pre‑2004 art independent of Takeda.

5. Dependent claims 2–8

Drafting observation on claim 8: claim 8 recites "the first rank and the second rank" although claim 1 recites only "a first number of ranks" and "a second number of ranks," so claim 8 arguably lacks explicit antecedent basis. I flag this as a literal reading of the claim text, not as a legal conclusion. Note also that claim 8 was excluded from the inter partes reexamination ("Claim 8 is not subject to reexamination," PTAB at 2), so it received less scrutiny than claims 1–7.

6. Anticipated counterarguments and why they are weak

1. Patentee's non-teaching argument. Smart Modular's expert opined that "none of the combinations … teaches using a set of chip select signals to contribute to the selection of a memory rank … as required by claims 1–7" and that a second chip-select set must exceed one signal (Baghezadeh Decl., Ex. 2016 in IPR2014‑01374). This is a missing-element argument, not a teaching-away argument, and the PTAB rejected it on the merits after full briefing.
2. The Takeda chip-select characterization dispute. In the parallel SanDisk IPRs, the patent owner argued the petitioner's theory shifted from "the CS signal is the switch-enable signal" to "the CS signal generates a logic signal that enables the switches," and that the combination was inoperable. The Board held the record "sufficiently outlined" the position, found no new theory, and sustained unpatentability. Nothing in that dispute identifies a structural difference from claim 1 — if anything, the "CS generates a further logic signal" theory mirrors claim 1's E4/E7.
3. No reasonable expectation of success. This fails on the record: the '295 specification itself confirms the approach works, JEDEC 21‑C standardizes the exact interface used, and the petitioner demonstrated operability.
4. "Emulator" vs. "register" as separate blocks. Treated as a labeling/design-choice limitation. The record shows the applicant added E11/E12 only by moving a dependent claim up, which is the classic posture of a claim narrowed on form over substance.
5. Teaching away. None of the Tier-A or Tier-B references teaches away from using address bits plus chip selects to synthesize additional chip selects; the APA explicitly teaches toward more ranks of cheaper devices.

7. Objective evidence of non-obviousness

I found no objective evidence of non-obviousness with a nexus to the claims in the material reviewed. The record reflects:

• No documented commercial success attributed to the claimed combination.
• No documented industry praise or licensing of the '295 patent. The JEDEC record actually cuts the other way: Smart Modular submitted its JEDEC "License Assurance/Disclosure Form" identifying the '295 patent one week after issuance (2012‑08‑27), after eight years of JEDEC participation — which Netlist's antitrust pleading characterizes as non-disclosure. That is a litigation-fairness issue, not a secondary consideration supporting non-obviousness.
• Long pendency (2004 filing → 2012 issuance) with claim amendments, and a § 1.132 declaration by Dr. Edward P. Sayre filed 2013‑04‑25 in the reexamination (listed on the Justia family page for US 8,990,489). I have not read that declaration, so I cannot assess whether it contains nexus-bearing objective evidence; this is a limitation of my analysis.

8. Corroboration from the actual record, and contradiction flags

Corroboration. The real-world record strongly supports the § 103 conclusion:

• PTAB, Appeal 2016‑006595 (2016‑11‑14): "We REVERSE the Examiner's decision to confirm claims 1‑7 and to determine claims 9, 13, 15, 19, and 22 are patentable" — after reviewing nine proposed grounds (Takeda + JEDEC 21‑C; Takeda + Hynix; JEDEC 21‑C/APA/Matsui; Hynix/APA/Matsui; JEDEC 21‑C/APA/Watanabe; Hynix/APA/Watanabe; and JEDEC 79‑C variants). https://case-law.vlex.com/vid/netlist-inc-v-patent-894992065
• Remand: On 2017‑05‑08 the Examiner issued a determination "which found all pending claims to be unpatentable," and the proceeding returned to the PTAB. https://investors.netlist.com/download/companies/270109a/SECFiling/Q3%[202017](/patent/202017).pdf
• The initial examination itself relied on APA + Ludwig, and allowance turned on the signal-routing limitation, not on any structural difference in the rank-emulation architecture.

Contradictions / uncertainties to flag explicitly:

1. Takeda's publication number and date. The reexamination request (Netlist Ex. 1010) cites "H10‑320270 to Takeda," while a SanDisk IPR exhibit list cites "H10‑320770." The page's own JPH10320270A entry (Matsushita, 1998‑12‑04) supports the ‑320270 form. I am reporting both as found and have not resolved the discrepancy.
2. Prior-art-date caveat. The '295 owns the 2004‑01‑05 priority, but the four references the reexamination actually turned on — Takeda (1998), Matsui (1999), Watanabe (1995), Hynix (2002) — plus JEDEC 21‑C (Jan. 2002) all comfortably predate it. That is a point in favor of the analysis: no reference's status as § 102 art depends on a § 102(e) filing-date argument.
3. Scope of my verification. I did not read the full text of Takeda, Matsui, Watanabe, Hynix, or JEDEC 21‑C. The mapping in § 3–4 relies on (a) the PTAB's and petitioner's characterizations in the verified record, and (b) the reference titles as listed on the Google Patents page for Tier B. Title-level mapping is weaker evidence than claim-chart mapping; where a source (e.g., US 6,674,684) is relied on for its title alone, I say so.
4. Consistency with the prior summary. The previously generated § 4 stated PTAB relied on "Takeda + JEDEC 21‑C, Takeda + Hynix, and JEDEC 21‑C + admitted prior art + Matsui." The full nine-ground list retrieved here expands but does not contradict that summary — Matsui and Watanabe appear as alternatives, and JEDEC 79‑C appears only in the grounds directed to the reexam-added claims.
5. Claim 8's status. The prior summary did not flag that claim 8 was never subject to reexamination. Any statement that "all claims were cancelled" is therefore imprecise as to claim 8 unless the certificate separately confirms it — and I have not retrieved the reexamination certificate (my searches returned only generic certificate examples, not the certificate for control no. 95/002,399).
6. Continuing relevance. Although the '295 expired 2024‑10‑30, the family continuation US 10,755,757 B2 is listed as Active with a 2029‑08‑24 expiration. Since that continuation claims the same 2004‑01‑05 priority and substantially the same specification, the § 103 analysis above bears directly on it.

9. Bottom line

Claims 1–8 are obvious under pre-AIA § 103(a). The strongest, best-grounded combinations are:

1. Takeda + JEDEC 21‑C (primary; claims 1–7);
2. Takeda + Hynix (adds the concrete 9‑device-per-rank DDR registered-DIMM embodiment; claims 1–3);
3. JEDEC 21‑C/Hynix + APA + Matsui (or Watanabe) (claims 1–7, with the motivation supplied by the patent's own admission);
4. APA + Ludwig (the prosecution combination, which already met everything except the emulator/register signal partition — a design-choice distinction);
5. Infineon US 6,674,684 + Canon US 6,018,787 + JEDEC 21‑C / Hynix (an independent route from the page's own citation list that does not depend on the reexam references at all).

Dependent claims 2–8 add nothing beyond routine implementation choices — most notably the 9-devices-per-rank limitation (claim 3), which the Hynix registered-DIMM datasheet and JEDEC 21‑C disclose outright. The PTAB's 2016 reversal and the Examiner's 2017 remand determination finding all pending claims unpatentable confirm this analysis against the actual record.